Organic light emitting display panel and organic light emitting display device

Abstract

An organic light emitting display panel and an organic light emitting display device. The present disclosure relates to an organic light emitting display panel and an organic light emitting display device including the same, the display panel including: a buffer layer disposed on a first conductive layer and including a first contact hole overlapping a portion of the first conductive layer; an active layer disposed on the buffer layer; a first insulating film disposed on the active layer and the buffer layer and including a second contact hole overlapping the first contact hole; a second insulating film disposed on the first insulating film and including a third contact hole overlapping a portion of each of the first contact hole and the second contact hole; and a third conductive layer disposed on the second insulating film and contacting a portion of a second conductive layer via the second contact hole. The third contact hole does not overlap the active layer. An organic light emitting display panel including a high-capacity storage capacitor and an organic light emitting display device including the same can be provided.

Description

Technical Field

[0001] This disclosure relates to an organic light-emitting display panel and an organic light-emitting display device including the display panel. Background Technology

[0002] Organic light-emitting display devices include one or more thin-film transistors (TFTs), storage capacitors, and multiple lines.

[0003] One or more thin-film transistors, capacitors, and one or more lines are sometimes implemented as fine patterns on a substrate included in an organic light-emitting display device, and the display device can operate based on complex connections between one or more thin-film transistors, at least one capacitor, and one or more lines.

[0004] Recently, there has been an increasing demand for organic light-emitting display devices with high brightness and high resolution. In order to meet this demand, it is desirable to achieve efficient spatial arrangement, and the connection structure between the components included in the organic light-emitting display device is under investigation. Summary of the Invention

[0005] Embodiments of this disclosure relate to an organic light-emitting display panel that has high light-emitting characteristics by increasing the area of ​​the light-emitting region without reducing the area of ​​the storage capacitor disposed in the non-light-emitting region, and an organic light-emitting display device including the display panel.

[0006] Furthermore, embodiments of the present invention relate to an organic light-emitting display panel that has high brightness and high resolution by increasing the capacity of the storage capacitor without reducing the area of ​​the light-emitting region, and an organic light-emitting display device including the display panel.

[0007] Furthermore, embodiments of the present invention relate to an organic light-emitting display panel that can easily drive sub-pixels by including an active layer with active patterns and conductive patterns, and an organic light-emitting display device including the display panel.

[0008] Furthermore, embodiments of the present invention relate to an organic light-emitting display panel having the following structure and an organic light-emitting display device including the display panel, which prevents damage to the active layer or buffer layer in related processes by setting the active layer to not overlap with a portion of the formation area of ​​a plurality of contact holes.

[0009] According to one aspect of this disclosure, an organic light-emitting display panel and an organic light-emitting display device including the display panel are disclosed. The display panel includes: a substrate; a first conductive layer disposed on the substrate; a buffer layer disposed on the first conductive layer and including a first contact hole overlapping a portion of the first conductive layer; an active layer disposed on or above the buffer layer; a first insulating film disposed on or above the active layer and the buffer layer, and including a second contact hole overlapping the first contact hole; a second conductive layer disposed on the first insulating film and contacting a portion of the first conductive layer and a portion of the active layer via the first and second contact holes; a second insulating film disposed on the second conductive layer and including a third contact hole overlapping a portion of each of the first and second contact holes; and a third conductive layer disposed on the second insulating film and contacting a portion of the second conductive layer via the second contact hole. The third contact hole does not overlap with the active layer.

[0010] According to another aspect of this disclosure, an organic light-emitting display panel and an organic light-emitting display device including the display panel are disclosed. The display panel includes: a substrate; a first conductive layer disposed on the substrate; a buffer layer disposed on the first conductive layer and including a first contact hole overlapping a portion of the first conductive layer; an active layer including an active pattern disposed on the buffer layer and a conductive pattern disposed on the active pattern; a first insulating film disposed on or above the active layer and the buffer layer, and including a second contact hole overlapping the first contact hole; a second conductive layer disposed on the first insulating film and contacting a portion of the first conductive layer and a portion of the active layer via the first and second contact holes; and a plate disposed in the same layer as the second conductive layer and spaced apart from the second conductive layer. A third contact hole does not overlap with the active layer, and one or more of the first conductive layer, the active layer, and the plate form a storage capacitor.

[0011] According to aspects of this disclosure, since the plurality of contact holes disposed in the region where the second node of the driving transistor is located are configured to overlap, and thereby the size of the conductive layer overlapping with the plurality of contact holes can be reduced, an organic light-emitting display panel with high brightness characteristics and an organic light-emitting display device including the display panel can be provided by making it possible to reduce the area of ​​the non-light-emitting area without reducing the area of ​​the storage capacitor, and to increase the area of ​​the light-emitting area relative to the area of ​​the non-light-emitting area.

[0012] Furthermore, according to aspects of this disclosure, since the multiple contact holes disposed in the region where the second node of the driving transistor is located overlap, and thus the size of the conductive layer overlapping with the multiple contact holes can be reduced, the size or capacity of the storage capacitor can be increased without reducing the area of ​​the light-emitting region, and thus an organic light-emitting display panel with high brightness and high resolution and an organic light-emitting display device including the display panel can be provided.

[0013] Furthermore, according to aspects of this disclosure, since the active layer includes an active pattern and a conductive pattern disposed on the active pattern, an organic light-emitting display panel capable of easily driving sub-pixels and an organic light-emitting display device including the display panel can be provided.

[0014] Furthermore, according to aspects of this disclosure, since the active layer does not overlap with a portion of the formation area of ​​the plurality of contact holes, an organic light-emitting display panel having a structure capable of preventing damage to the active layer or buffer layer during the relevant process, and an organic light-emitting display device including the display panel, can be provided. Attached Figure Description

[0015] Figure 1 The system structure of an organic light-emitting display device according to various aspects of the present disclosure is illustrated schematically.

[0016] Figure 2 Examples of subpixel structures are illustrated when an organic light-emitting display panel including an organic light-emitting diode (OLED) is used in a display device, according to various aspects of this disclosure.

[0017] Figure 3 This is a plan view illustrating a partial region of a sub-pixel disposed in the display area of ​​an organic light-emitting display device according to various aspects of the present disclosure.

[0018] Figure 4 Examples illustrate variations in the area of ​​the storage capacitor or the ratio of the light-emitting region in a sub-pixel in an organic light-emitting display device according to various aspects of this disclosure.

[0019] Figure 5 It is along one embodiment of various aspects of this disclosure. Figure 3 The cross-sectional view taken from line AB.

[0020] Figure 6 This illustrates another embodiment of the process along various aspects of this disclosure. Figure 3 A cross-sectional view of the region intercepted by line AB.

[0021] Figure 7 This is an example of another embodiment of various aspects of this disclosure. Figure 3 A cross-sectional view of the region intercepted by line AB.

[0022] Figures 8 to 10 Various embodiments of the arrangement of the buffer layer, the first active layer, the first insulating film, and the second conductive layer in an organic light-emitting display device according to various aspects of the present disclosure are illustrated.

[0023] Figure 11 It is based on all aspects of this disclosure. Figure 3 A cross-sectional view taken from the CD line.

[0024] Figure 12 It is based on all aspects of this disclosure. Figure 3 The cross-sectional view taken from line EF. Detailed Implementation

[0025] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, which illustrate specific examples or embodiments that can be implemented by way of example, and the same reference numerals may be used in the drawings to refer to the same or similar components, even if these components are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein will be omitted where it is determined that such descriptions may obscure the subject matter of some embodiments of the invention. Terms such as “comprising,” “having,” “including,” “constituting,” “forming,” and “form” as used herein are generally intended to allow for the addition of additional components, unless the term is used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0026] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not used to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0027] When referring to the first element and the second element as "connected or linked," "in contact or overlapping," etc., it should be interpreted as meaning that not only can the first element be "directly connected or linked" or "directly in contact or overlapping" with the second element, but a third element can also be "intermediate" between the first and second elements, or the first and second elements can be "connected or linked," "in contact or overlapping," etc., with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected or linked," "in contact or overlapping," etc., with each other.

[0028] When using time-related terms such as “after,” “next,” “before,” etc., to describe a process or operation of an element or structure, or a flow or step in an operation, process, or manufacturing method, these terms may be used to describe discontinuous or non-sequential processes or operations unless they are used together “directly” or “immediately.”

[0029] Additionally, when referring to any size, relative size, etc., even if no specific description is specified, the numerical value or corresponding information of the component or feature (e.g., level, range, etc.) should be considered, including tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.). Furthermore, the term "can" fully encompasses all the meanings of the term "able to".

[0030] Figure 1 The system structure of the organic light-emitting display device according to this disclosure is illustrated schematically.

[0031] The organic light-emitting display device according to this disclosure may include an organic light-emitting display device 100, an illumination device, a light-emitting device, etc. Hereinafter, for ease of description, the organic light-emitting display device according to this disclosure will be described with reference to the organic light-emitting display device 100. However, it should be understood that the embodiments described herein can be applied to various organic light-emitting display devices, such as illumination devices, light-emitting devices, etc., as well as the organic light-emitting display device 100, as long as they include transistors.

[0032] An organic light-emitting display device 100 according to the embodiments described herein includes an organic light-emitting display panel PNL for displaying images or emitting light, and a driving circuit for driving the organic light-emitting display panel PNL.

[0033] The organic light-emitting display device 100 according to the embodiments described herein may be based on a bottom-emitting type in which light is emitted from an organic light-emitting element toward a substrate on which the organic light-emitting element is disposed; however, the embodiments disclosed herein are not limited thereto. In some embodiments, the organic light-emitting display device 100 according to the embodiments described herein may be based on a top-emitting type in which light is emitted from an organic light-emitting element toward a surface opposite to the substrate on which the organic light-emitting element is disposed, or based on a double-sided-emitting type in which light is emitted from an organic light-emitting element toward both the substrate and the surface opposite to the substrate.

[0034] An organic light-emitting display panel (PNL) may include multiple data lines (DL) and multiple gate lines (GL), as well as multiple sub-pixels (SP) defined by the multiple data lines (DL) and multiple gate lines (GL) and arranged in a matrix pattern.

[0035] Multiple data lines (DL) and multiple gating lines (GL) can be arranged to intersect each other in an organic light-emitting display panel (PNL). For example, the multiple gating lines (GL) can be arranged in rows or columns, and the multiple data lines (DL) can be arranged in columns or rows. In the following text, for ease of description and understanding, it is assumed that the multiple gating lines (GL) are arranged in rows and the multiple data lines (DL) are arranged in columns.

[0036] In addition to multiple data lines (DL) and multiple gate lines (GL), one or more other types of signal lines can be arranged in an organic light-emitting diode (PNL) display panel, depending on the sub-pixel structure. Driving voltage lines, reference voltage lines, or common voltage lines can be further configured.

[0037] The type of signal lines disposed on an organic light-emitting display panel (PNL) can vary depending on the sub-pixel structure, etc. Furthermore, all or some of the signal lines of each type described herein may include all or at least a portion of the electrodes to which the signal is applied.

[0038] An organic light-emitting display panel (PNL) may include a display area A / A on which an image is displayed and a non-display area N / A, which is the outer edge of which no image is displayed. Here, the non-display area N / A is sometimes referred to as the border area.

[0039] Multiple subpixels SP used for image display are arranged in the display area A / A.

[0040] In the non-display area N / A, a pad portion including one or more conductive pads can be provided for electrical connection with the data driver DDR, and multiple data link lines can be provided in the non-display area N / A for electrical connection between the pad portion and multiple data lines DL. Here, the multiple data link lines can be portions of the multiple data lines DL extending to the non-display area N / A (e.g., from the display area A / A), or they can be separate patterns electrically connected to the multiple data lines DL.

[0041] Furthermore, lines related to the gating drive can be arranged in the non-display area N / A to transmit the voltage (signals) required for the gating drive to the gating driver GDR via the pad portion electrically connected to the data driver DDR. For example, lines related to the gating drive may include: clock lines for carrying clock signals; gating voltage lines for transmitting gating voltages (VGH, VGL); and gating drive control signal lines for carrying various types of control signals required to generate scan signals. Unlike the gating lines GL located in the display area A / A, these lines related to the gating drive can be arranged in the non-display area N / A.

[0042] The driving circuit may include: a data driver DDR that drives multiple data lines DL; a gating driver GDR that drives multiple gating lines GL; and a controller CTR that controls the data driver DDR and the gating driver GDR.

[0043] The data driver DDR can drive multiple data lines DL by applying data voltage to them.

[0044] The gating driver GDR can drive multiple gating lines GL by providing scan signals to multiple gating lines GL.

[0045] The controller CT can control the operation of the data driver DDR and the gating driver GDR by providing various types of control signals (DCS, GCS) required for their operation. Furthermore, the controller CTR can provide image data DATA to the data driver DDR.

[0046] The controller CTR begins scanning pixels according to the timing processed in each frame, converting image data input from external sources (e.g., host system, other devices, or other image sources) into a data signal form suitable for use in the data driver DDR, and then outputs the converted image data DATA, thereby enabling the data to be written to pixels at pre-configured times according to the scan.

[0047] To control the data driver DDR and the gating driver GDR, the controller CTR can receive timing signals (such as vertical sync signal Vsync, horizontal sync signal Hsync, input data enable signal, clock signal, etc.) from external sources (e.g., host system, other devices, or other image sources). The controller CTR can use the received signals to generate various types of control signals and provide the generated signals to the data driver DDR and the gating driver GDR.

[0048] For example, in order to control the gating driver GDR, the controller CTR can output various types of gating control signals GCS, including gating start pulse GSP, gating shift clock GSC, gating output enable signal GOE, etc.

[0049] In addition, in order to control the data driver DDR, the controller CTR can output various types of data control signals DCS, including source start pulse SSP, source sampling clock SSC, and source output enable signal SOE.

[0050] The controller CTR can be a timing controller used in typical display technologies, or a control device / apparatus that can additionally perform other control functions in addition to the typical functions of a timing controller.

[0051] The controller CTR can be implemented as a component separate from the data driver DDR, or it can be implemented as an integrated circuit integrated with the data driver DDR.

[0052] The data driver DDR can drive multiple data lines DL by providing data voltage to multiple data lines DL after receiving image data DATA from the controller CTR. Here, the data driver DDR is sometimes referred to as a source driver circuit or source driver.

[0053] The data driver DDR can send various signals to or receive various signals from the controller CTR through various interfaces.

[0054] A gating driver (GDR) can sequentially drive multiple gating lines GL by providing scan signals sequentially to them. Here, the gating driver (GDR) is sometimes referred to as a scan drive circuit or scan driver.

[0055] Under the control of the controller CTR, the gating driver GDR can sequentially provide scan signals representing the on or off voltage to multiple gating lines GL.

[0056] When a specific gate line is asserted by a scan signal from the gate driver GDR, the data driver DDR can convert the image data DATA received from the controller CTR into an analog data voltage and provide the obtained data voltage to multiple data lines DL.

[0057] Depending on the driving scheme, display panel design, etc., the data driver DDR may be located on, but is not limited to, only one side of the display panel PNL (e.g., the top or bottom side), or in some embodiments, it may be located on both sides of the display panel PNL (e.g., the top and bottom sides).

[0058] Depending on the driving scheme, the design scheme of the display panel, etc., the gate driver GDR may be located on only one side of the display panel PNL (e.g., the left or right side), or in some embodiments, it may be located on both sides of the display panel PNL (e.g., the left and right sides).

[0059] Data drivers (DDR) can be implemented using SDICs that include one or more source driver integrated circuits.

[0060] Each source driver integrated circuit (SDIC) may include a shift register, latch circuitry, a digital-to-analog converter (DAC), an output buffer, etc. In some implementations, the data driver (DDR) may further include one or more analog-to-digital converters (ADCs).

[0061] Each source driver integrated circuit (SDIC) can be connected to conductive pads, such as bonding pads, of the organic light-emitting display panel (PNL) using either a tape-on-board (TAB) or chip-on-glass (COG) type, or directly disposed on the display panel 110. In some embodiments, each source driver integrated circuit (SDIC) can be integrated into the organic light-emitting display panel (PNL). In some embodiments, each source driver integrated circuit (SDIC) can be implemented as a chip-on-film (COF) type. In this case, each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data line DL in the organic light-emitting display panel (PNL) through the circuit film.

[0062] A gating driver GDR may include multiple gating driver circuits GDC. Each of the multiple gating driver circuits GDC may correspond to a different gating line GL.

[0063] Each gating drive circuit (GDC) may include a shift register, a level shifter, etc.

[0064] Each gate drive circuit GDC can be connected to conductive pads, such as bonding pads, of the organic light-emitting display panel PNL in either a tape-on-board (TAB) or chip-on-glass (COG) manner. In some embodiments, each gate drive circuit GDC can be implemented as a chip-on-film (COF) type. In this case, each gate drive circuit GDC can be mounted on a circuit film and electrically connected to the gate line GL in the organic light-emitting display panel PNL via the circuit film. Furthermore, each gate drive circuit GDC can be implemented as a gate-in-panel (GIP) type and can be embedded within the organic light-emitting display panel PNL. That is, each gate drive circuit GDC can be directly formed in the organic light-emitting display panel PNL.

[0065] Figure 2 An example is illustrated when an organic light-emitting display panel (PNL) including organic light-emitting elements (such as organic light-emitting diodes (OLEDs)) is used in a display device according to this disclosure.

[0066] Reference Figure 2 Each sub-pixel SP in an organic light-emitting display panel PNL including organic light-emitting elements may include: a second transistor T2 that transmits a data voltage Vdata to a first node N1 corresponding to the gate node of a driving transistor T1; and a storage capacitor Cst that holds the data voltage Vdata or a voltage corresponding to the image signal voltage during a frame time.

[0067] An organic light-emitting element (OLED) may include a first electrode (anode or cathode), an organic layer including at least one light-emitting layer, and a second electrode (cathode or anode).

[0068] In one implementation, a base voltage EVSS, such as a low-level voltage, can be applied to the second electrode of the organic light-emitting element (OLED).

[0069] The driving transistor T1 can drive the organic light-emitting diode (OLED) by providing driving current to the OLED.

[0070] The driving transistor T1 can have a first node N1, a second node N2, and a third node N3.

[0071] The “nodes” of the first to the third nodes N1, N2 and N3 can represent points with equal electrical states, one or more electrodes, or one or more lines.

[0072] Each of the first node N1, the second node N2, and the third node N3 can consist of one or more electrodes.

[0073] The first node N1 of the driving transistor T1 can be the node corresponding to its gate node, and can be electrically connected to the source node or drain node of the second transistor T2.

[0074] The second node N2 of the driving transistor T1 can be electrically connected to the first electrode of the organic light-emitting element OLED, and can be either the source node or the drain node.

[0075] The third node N3 of the driving transistor T1 can be the drain node or the source node, which is the node to which the driving voltage EVDD is applied, and can be electrically connected to the driving voltage line DVL used to transmit the driving voltage EVDD.

[0076] The driving transistor T1 and the second transistor T2 can be either n-type transistors or p-type transistors.

[0077] The second transistor T2 can be electrically connected between the data line DL and the first node N1 of the drive transistor T1, and can be controlled by the scan signal SCAN transmitted through the gate line and applied to the gate node of the first transistor T1.

[0078] The second transistor T2 can be turned on by the scan signal SCAN, and the data voltage Vdata through the data line DL is applied to the first node N1 of the driving transistor T1.

[0079] The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2 of the driving transistor T1.

[0080] The storage capacitor Cst is intentionally designed to be an external capacitor located outside the driving transistor T1, rather than an internal capacitor such as a parasitic capacitor (Cgs, Cgd) existing between the first node N1 and the second node N2 of the driving transistor T1.

[0081] The third transistor T3 can be electrically connected between the second node N2 of the driving transistor T1 and the reference voltage line RVL. The on-off operation of the third transistor T3 can be controlled by the second scan signal SCAN2 applied to the gate node of the third transistor T3.

[0082] The drain or source node of the third transistor T3 can be electrically connected to the reference voltage line RVL, and the source or drain node of the third transistor T3 can be electrically connected to the source node of the driving transistor T1.

[0083] For example, the third transistor T3 can be turned on during the period of performing display driving, and also during the period of performing sensing driving for sensing the characteristic value of the driving transistor T1 or the characteristic value of the organic light-emitting diode (OLED).

[0084] The third transistor T3 can be turned on by the second scan signal SCAN2, and according to the corresponding drive timing (e.g., display drive timing or initial timing within the sensing drive period), the reference voltage Vref applied to the reference voltage line RVL is transmitted to the second node N2 of the drive transistor T1.

[0085] The third transistor T3 can be turned on by the second scan signal SCAN2, and according to the corresponding drive timing (e.g., the sampling timing during the sensing drive period), the voltage at the second node N2 of the drive transistor T1 is transmitted to the reference voltage line RVL.

[0086] In other words, the third transistor T3 can control the voltage state at the second node N2 of the driving transistor T1, or transmit the voltage at the second node N2 of the driving transistor T1 to the reference voltage line RVL.

[0087] The reference voltage line RVL can be electrically connected to an analog-to-digital converter (ADC) that senses the voltage of the reference voltage line RVL, converts the sensed voltage into a digital value, and then outputs sensed data including that digital value.

[0088] The analog-to-digital converter can be included in the source driver integrated circuit SDIC that implements the data driver DDR.

[0089] The sensing data output from the analog-to-digital converter can be used to sense characteristic values ​​of the driving transistor T1 (e.g., threshold voltage, mobility, etc.) or characteristic values ​​of the organic light-emitting diode (OLED) (e.g., threshold voltage, etc.).

[0090] Each of the driving transistor T1, the second transistor T2, and the third transistor T3 can be an n-type transistor or a p-type transistor.

[0091] Meanwhile, the first scan signal SCAN1 and the second scan signal SCAN2 can be separate gating signals. In this case, the first scan signal SCAN1 and the second scan signal SCAN2 can be applied to the gate node of the second transistor T2 and the gate node of the third transistor T3 respectively through different gating lines.

[0092] In some implementations, the first scan signal SCAN1 and the second scan signal SCAN2 can be the same gating signal. In this case, the first scan signal SCAN1 and the second scan signal SCAN2 can be applied together to the gate node of the second transistor T2 and the gate node of the third transistor T3 through the same gating line.

[0093] It should be understood that, for the sake of discussion, Figure 3 The subpixel structure shown with three transistors (3T) and one capacitor (1C) is merely one example of possible subpixel structures, and embodiments of this disclosure can be implemented as various structures as needed. For example, a subpixel may further include at least one transistor and / or at least one capacitor.

[0094] In some implementations, each of the multiple sub-pixels may have the same structure, or some of the multiple sub-pixels may have different structures.

[0095] Figure 3 This is a plan view illustrating a partial region of a sub-pixel disposed in the display area of ​​an organic light-emitting display device according to various aspects of the present disclosure.

[0096] Reference Figure 3 At least one sub-pixel of the organic light-emitting display device 100 according to various aspects of the present disclosure may include a light-emitting region EA and a non-light-emitting region defined by the embankment 370.

[0097] The luminescent area EA can be an area that does not overlap with the embankment 370, and the non-luminescent area EA can be an area that overlaps with the embankment 370.

[0098] An organic light-emitting element (OLED), including a first electrode, an organic layer, and a second electrode, can be disposed in the light-emitting region EA. Furthermore, a color filter 380 can be disposed on the organic light-emitting element OLED; however, embodiments of this disclosure are not limited thereto. For example, the color filter 380 may be disposed only in some of the multiple sub-pixels included in the organic light-emitting display device 100, or the color filter may not be applied to all the sub-pixels included in the organic light-emitting display device 100.

[0099] like Figure 3 As shown, the color filter 380 can be configured to overlap with the entire luminous area EA and a portion of the non-luminous area.

[0100] The non-light-emitting area may include a first conductive layer 310, a first active layer 320, a second conductive layer 330, and a plate 340 disposed on or above the substrate 300.

[0101] In addition, the non-light-emitting area may also include: a second active layer 325, which is disposed in the same layer as the first active layer 320; and a third conductive layer 360, which is the anode (or cathode) of the organic light-emitting element disposed on or above the second conductive layer 330 and the plate 340.

[0102] Specifically, the first conductive layer 310 can be disposed on the substrate 300.

[0103] Furthermore, the first signal line 301 and the second signal line 302 may be disposed in the same layer as the first conductive layer 310 and extend along a first direction on or above the substrate 300. The first signal line 301 may be a driving voltage line ( Figure 2 (in DVL), and the second signal line 302 can be a data line ( Figure 1 and Figure 2 (DL in the text); however, embodiments of this disclosure are not limited thereto. For example, each of the first signal line 301 and the second signal line 302 may be a data line.

[0104] For ease of explanation, the following discussion will focus on the structure where the first signal line 301 is a driving voltage line and the second signal line 302 is a data line.

[0105] The first active layer 320 can be disposed on or above the first conductive layer 310.

[0106] Here, a portion of the first active layer 320 may overlap with a portion of the first conductive layer 310.

[0107] Furthermore, a second active layer 325, which is disposed in the same layer as the first active layer 320 and spaced apart from the first active layer 320, may be disposed on or above the substrate 300.

[0108] The second conductive layer 330, the fourth conductive layer 335, the plate 340, the third signal line 303, and the fourth signal line 304 can be arranged above the substrate 300 on which the first active layer 320 and the second active layer 325 are disposed.

[0109] Each of the second conductive layer 330, the fourth conductive layer 335, the plate 340, and the third signal line 303 can be configured to be spaced apart from each other.

[0110] A portion of the second conductive layer 330 may overlap with a portion of the first active layer 320.

[0111] A portion of the fourth conductive layer 335 may overlap with a portion of the second active layer 325.

[0112] A portion of plate 340 may overlap with a portion of the first active layer 320 and a portion of the second active layer 325.

[0113] A portion of the third signal line 303 may overlap with a portion of the first active layer 320 and a portion of the second active layer 325.

[0114] The fourth signal line 304 may overlap with a portion of the first signal line 301.

[0115] Despite Figure 3 Although not shown, a buffer layer may be provided between the first conductive layer 310 and the first active layer 320, and a first insulating film may be provided between the first active layer 320 and the second conductive layer 330.

[0116] The buffer layer may overlap with the first conductive layer 310 and the second conductive layer 330, and includes a first contact hole CH1 in the region where the second conductive layer 330 does not overlap with the first active layer 320. Furthermore, the first insulating film may include a second contact hole CH2, which overlaps with the first contact hole CH1 and with the region where the second conductive layer 330 overlaps with the first active layer 320.

[0117] That is, the first contact hole CH1 may not overlap with the first active layer 320.

[0118] A portion of the top surface of the first conductive layer 310 can be exposed through the first contact hole CH1 and the second contact hole CH2, and a portion of the top surface of the first active layer 320 can be exposed through the second contact hole CH2.

[0119] The second conductive layer 330 can contact a portion of the top surface of the first conductive layer 310 through the first contact hole CH1 and the second contact hole CH2. Additionally, the second conductive layer 330 can contact a portion of the top surface of the first active layer 320 through the second contact hole CH2.

[0120] In the plan view, the area of ​​the first contact hole CH1 can be smaller than the area of ​​the second contact hole CH2.

[0121] although Figure 3 Not shown, however, the first active layer 320 may be electrically connected to Figure 2 The reference voltage line is shown.

[0122] In other words, in relation to Figure 2 The region corresponding to the second node N2 of the driving transistor T1 may include the region where the second conductive layer 330 contacts the first conductive layer 310 and the region where the second conductive layer 330 contacts the first active layer 320.

[0123] The fourth conductive layer 335 can be electrically connected to the data line 302 through contact holes 335a formed in the buffer layer by contacting each other, and can be electrically connected to the second active layer 325 through contact holes 335b formed in the first insulating film by contacting each other.

[0124] Here, the contact hole 335a formed in the buffer layer and the contact hole 335b formed in the first insulating film can overlap, and the area of ​​the contact hole 335a formed in the buffer layer in the plan view can be smaller than the area of ​​the contact hole 335b formed in the insulating film. The contact hole 335a formed in the buffer layer may not overlap with the second active layer 325.

[0125] A portion of plate 340 may overlap with a portion of the first active layer 320 and a portion of the first conductive layer 310.

[0126] Each of the first conductive layer 310, the first active layer 320, and the plate 340 can be used as an electrode of the storage capacitor Cst. The portion of the first active layer 320 that overlaps with the plate 340 and the first conductive layer 310 can be a conductive region or a region in which a conductive pattern is formed.

[0127] A portion of plate 340 can be electrically connected to a portion of the second active layer 325 via contact holes 337 formed in the buffer layer through contact with each other.

[0128] The area where plate 340 contacts a portion of the second active layer 325 via contact hole 337 may include the area in contact with... Figure 2 The region corresponding to the first node N1 of the driving transistor T1.

[0129] The plate 340 may include at least one first extension 345 protruding from one side of the plate 340.

[0130] A portion of the first extension 345 may overlap with a portion of the first active layer 320. The first extension 345 may be used as Figure 2 The gate of the driving transistor T1 is shown. The first active layer 320 can be used as the active layer of the driving transistor T1.

[0131] The third signal line 303 may be disposed on or above the first signal line 301 and the second signal line 302, and may extend in a second direction, which is a direction that intersects with the first direction, the first direction being the direction in which the first signal line 301 and the second signal line 302 extend.

[0132] The third signal line 303 may overlap with a portion of the first signal line 301 and also with a portion of the second signal line 302. Furthermore, as described above, the third signal line 303 may also overlap with a portion of the first active layer 320 and a portion of the second active layer 325.

[0133] The area where the third signal line 303 overlaps with the first active layer 320 can be... Figure 2 The region corresponding to the third transistor T3. The region where the third signal line 303 overlaps with the second active layer 325 can be the same as... Figure 2 The region corresponding to the second transistor T2.

[0134] The fourth signal line 304 can be configured to overlap a portion of the first signal line 301. Furthermore, the fourth signal line 304 and the first signal line 301 can be electrically connected to the second signal line 302 via a plurality of contact holes 339 formed in the buffer layer and the insulating film. This reduces the resistance of the signal lines.

[0135] Furthermore, the fourth signal line 304 may include a second extension 305 extending from the fourth signal line 304. A sub-pixel can receive a driving voltage through the second extension 305; however, embodiments of this disclosure are not limited thereto. For example, when the first signal line 301 is a data line, the fourth signal line 304 may not be provided on the first signal line 301.

[0136] The third conductive layer 360 can be disposed on or above a substrate 300 on which the second conductive layer 330, the fourth conductive layer 335, the plate 340, the third signal line 303 and the fourth signal line 304 are disposed.

[0137] The third conductive layer 360 can be the anode or cathode of an organic light-emitting element.

[0138] The third conductive layer 360 can contact a portion of the top surface of the second conductive layer 330 via a contact hole 342 formed in at least one insulating film disposed between the second conductive layer 330 and the third conductive layer 360. Therefore, the third conductive layer 360 can be electrically connected to the second conductive layer 330.

[0139] As described above, the third conductive layer 360 can be electrically connected to the second conductive layer 330, and the second conductive layer 330 can be electrically connected to the first active layer 320 and the first conductive layer 310. Here, the regions where the first conductive layer 310, the first active layer 320, and the second conductive layer 330 contact, and the regions where the second conductive layer 330 and the third conductive layer 360 contact, can be... Figure 2 The region corresponding to the second node N2.

[0140] The first contact hole CH1 for electrically connecting the first conductive layer 310 and the second conductive layer 330, the second contact hole CH2 for electrically connecting the first active layer 320 and the second conductive layer 330, and the contact hole 342 for electrically connecting the second conductive layer 330 and the third conductive layer 360 may overlap each other.

[0141] Specifically, the entire first contact hole CH1 may overlap with a portion of the second contact hole CH2. The width of the first contact hole CH1 in the second direction (the direction in which the third signal line extends) may be smaller than the width of the second contact hole CH2 in the second direction.

[0142] In addition, a portion of the first contact hole CH1 and a portion of the second contact hole CH1 may overlap with a portion of the contact hole 342 of at least one insulating film disposed between the second conductive layer 330 and the third conductive layer 360.

[0143] When the first contact hole CH1, the second contact hole CH2, and the contact hole 342 are spaced apart from each other, the non-light-emitting area of ​​the sub-pixel needs to include the area occupied by the first contact hole CH1, the area occupied by the second contact hole CH2, and the area occupied by the contact hole 342.

[0144] Conversely, in the organic light-emitting display device 100 according to the embodiments described herein, since the entire first contact hole CH1 overlaps with the second contact hole CH2, and a portion of the first contact hole CH1 and a portion of the second contact hole CH2 overlap with a portion of the contact hole 342 of at least one insulating film disposed between the second conductive layer 330 and the third conductive layer 360, the overlap with the contact hole 342 can be reduced. Figure 2 The area occupied by the point corresponding to the second node N2 of the driving transistor T1.

[0145] In this way, by reducing the area of ​​the point corresponding to the second node N2 of the driving transistor T1, even if the area of ​​the light-emitting region EA of the organic light-emitting display device 100 is not reduced, the area of ​​the storage capacitor Cst can be increased, or the area occupied by the non-light-emitting region can be reduced. Thus, the area of ​​the light-emitting region EA can be increased.

[0146] Reference Figure 4 Let's discuss the above description in detail.

[0147] Figure 4 Examples illustrate variations in the area of ​​the storage capacitor or the ratio of the light-emitting regions in a sub-pixel in an organic light-emitting display device according to various aspects of this disclosure.

[0148] In the following description, for ease of description, some structures, effects, etc. of the embodiments or examples discussed above may be described without repetition. Furthermore, in the following description, similar reference numerals will be used for the same structures or elements as those in the embodiments or examples described above.

[0149] Reference Figure 4 The sub-pixels Y and Z, as shown in the reference Figure 3 As described, by having the following structure, compared with a structure in which contact holes CH1, CH2 and 342 do not overlap, the size of the region corresponding to the second node N2 of the driving transistor T1 can be reduced, the structure being as follows: the entire first contact hole CH1 located in the region corresponding to the second node N2 of the driving transistor T1 overlaps with the second contact hole CH2, and a portion of the first contact hole CH1 and a portion of the second contact hole CH2 overlaps with a portion of the contact hole 342 of at least one insulating film disposed between the second conductive layer 330 and the third conductive layer 360.

[0150] Furthermore, as the area occupied by contact holes CH1, CH2 and 342 in the non-light-emitting region decreases, the area where the second conductive layer 330 overlaps with contact holes CH1, CH2 and 342 can also be reduced.

[0151] Conversely, refer to Figure 4 The X sub-pixel can increase the area occupied by each contact hole 435 and 442 when the first contact hole and the second contact hole 435 do not overlap with the contact hole 442 of at least one insulating film disposed between the second conductive layer 330 and the third conductive layer 360. Therefore, it can increase the area in the second conductive layer 430 that is configured to overlap with the contact holes 435 and 442.

[0152] Meanwhile, since the second conductive layers 330 and 430 are disposed in the same layer as the plate 340 which serves as the electrode for the storage capacitor Cst, the second conductive layers 330 and 430 and the plate 340 need to be spaced apart from each other to prevent short circuits between the second conductive layers 330 and 430 and the plate 340.

[0153] Therefore, as Figure 4 As shown in sub-pixel X, when the area of ​​the second conductive layer 430 increases, it becomes difficult to increase the area of ​​the plate 340 adjacent to the second conductive layer 430.

[0154] On the contrary, such as Figure 4 As shown in the Y sub-pixel, the size of the second conductive layer 330 overlapping with contact holes (CH1, CH2 and 342) can be reduced by having the following structure: the entire first contact hole CH1 overlaps with the second contact hole CH2 and a portion of the first contact hole CH1 and a portion of the second contact hole CH2 overlaps with a portion of the contact hole 342 of at least one insulating film disposed between the second conductive layer 330 and the third conductive layer 360.

[0155] When the size of the second conductive layer 330 decreases, the distance between the second conductive layer 330 and the plate 440 can also be increased. In this case, even when... Figure 4 When the area of ​​plate 440 is increased as shown, since it can be separated from the second conductive layer 330, an organic light-emitting display device 100 including a high-capacity storage capacitor can also be realized.

[0156] In addition, such as Figure 4 As shown in the Y sub-pixel, when the extension (region K) of plate 340 overlaps with the first active layer 320 and the first conductive layer 310, which are the other electrodes of the storage capacitor Cst, the capacity of the storage capacitor Cst can be increased.

[0157] Specifically, when the organic light-emitting display device 100 has a high resolution, a high-capacity storage capacitor (Cst) is required, and in order to achieve such a high-capacity storage capacitor (Cst), the area of ​​the storage capacitor (Cst) disposed in the sub-pixel needs to be increased.

[0158] The area of ​​each subpixel is finite, and if the area of ​​one or more electrodes of the storage capacitor (Cst) located in the non-light-emitting area is increased, the area of ​​the light-emitting area included in the subpixel can be reduced. This can lead to a decrease in the brightness of the subpixel and the appearance of afterimages when driving the associated panel.

[0159] On the contrary, such as Figure 4As shown in the Y sub-pixel, since the entire first contact hole CH1 disposed in the non-light-emitting area overlaps with a portion of the second contact hole CH2, and a portion of the first contact hole CH1 and a portion of the second contact hole CH2 overlap with a portion of the contact hole 342 of at least one insulating film disposed between the second conductive layer 330 and the third conductive layer 360, the corresponding area occupied by the contact holes (CH1, CH2 and 342) can be reduced. Therefore, the area of ​​the second conductive layer 330 overlapping with the contact holes (CH1, CH2 and 342) can be reduced.

[0160] Therefore, by reducing the area occupied by the second node N2 of the driving transistor T1, the area of ​​at least one electrode of the storage capacitor Cst (e.g., the area of ​​the plate that serves as the electrode of the storage capacitor) can be increased. In other words, because the area of ​​the electrode of the storage capacitor Cst can be increased without reducing the area of ​​the light-emitting region, an organic light-emitting display device 100 with high brightness and high resolution characteristics and preventing afterimages can be realized.

[0161] Therefore, when comparing the X and Y sub-pixels, it can be seen that as the area of ​​the plate increases (i.e., when plate 440 is used instead of plate 340), the capacitance of the storage capacitor Cst increases from 247 fF to 348 fF. Furthermore, it can be seen that even with the increase in the area of ​​the storage capacitor Cst corresponding to plate 340 or 440 located in the non-light-emitting area, the ratio of the area occupied by the light-emitting region EA in the sub-pixel does not change.

[0162] As described above, according to the embodiments described herein, by increasing the area of ​​the plate 340 disposed in the non-light-emitting area of ​​the organic light-emitting display device 100, the capacity of the storage capacitor Cst can be increased. In another embodiment, as shown by the Z sub-pixel, instead of increasing the area of ​​the plate 340, the area of ​​the light-emitting region EA can be increased relative to the reduction of the area occupied by the second node N2 of the driving transistor T1.

[0163] Specifically, when the organic light-emitting display device 100 needs to provide high brightness, it is necessary to increase the area of ​​the light-emitting region EA.

[0164] Reference Figure 4 In the structure of the Z sub-pixels, as the size of the second conductive layer 330 decreases, the position of the plate 340 can be arranged away from the light-emitting area, while maintaining the distance between the plate 340 and the second conductive layer 330 and the capacitance of the storage capacitor Cst. As a result, since the area of ​​the non-light-emitting area can be reduced, an organic light-emitting display device 100 with high brightness can be realized by designing the light-emitting area to have an increased area relative to the non-light-emitting area.

[0165] Therefore, when comparing the X sub-pixel and the Z sub-pixel, it can be seen that as the plate 340 moves away from the light-emitting region EA, the ratio of the area occupied by the light-emitting region EA in the sub-pixel increases from 47% to 50% without changing the capacity of the storage capacitor Cst.

[0166] As described above, the detailed structure of the region included in the second node N2 of the driving transistor T1 of the organic light-emitting display device 100, which is capable of achieving high brightness and high resolution according to the embodiments described herein, is as follows.

[0167] Figure 5 In one embodiment according to various aspects of this disclosure, along Figure 3 The cross-sectional view taken from line AB.

[0168] In the following description, for ease of description, some structures, effects, etc. of the embodiments or examples discussed above may be described without repetition. Furthermore, in the following description, similar reference numerals will be used for the same structures or elements as those in the embodiments or examples described above.

[0169] Reference Figure 5 The first conductive layer 310 can be disposed on the substrate 300.

[0170] The first conductive layer 310 may include a conductive material capable of absorbing or reflecting light. For example, the first conductive layer 310 may include any metal or alloy thereof, such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti); however, embodiments of this disclosure are not limited thereto.

[0171] The first conductive layer 310 may be disposed below the first active layer 520 and used to protect the first active layer 520 from external factors (e.g., light), or used as an electrode of the storage capacitor Cst.

[0172] exist Figure 5 In this embodiment, the first conductive layer 310 is shown as a single-layer structure; however, the embodiments of this disclosure are not limited thereto. For example, the first conductive layer 310 may have a multi-layer structure.

[0173] The buffer layer 511 can be disposed above the substrate on which the first conductive layer 310 is disposed.

[0174] The buffer layer 511 may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON); however, embodiments of this disclosure are not limited thereto.

[0175] exist Figure 5In this embodiment, buffer layer 511 is represented as a single-layer structure; however, embodiments of this disclosure are not limited thereto. For example, buffer layer 511 may have a multi-layer structure.

[0176] The buffer layer 511 may include a first contact hole CH1 that exposes a portion of the top surface of the first conductive layer 310.

[0177] The first active layer 520 may be disposed on a portion of the top surface of the buffer layer 511.

[0178] like Figure 5 As shown, the first active layer 520 disposed on the sub-pixels of the organic light-emitting display device 100 according to the embodiments described herein may have a single layer.

[0179] The first active layer 520 can be any type of semiconductor layer.

[0180] The first active layer 520 may be formed of an oxide semiconductor. The material included in the first active layer 320 may be a metal oxide semiconductor and may be formed of the following materials: i) oxides of metals such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti); or ii) combinations of metals such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) with oxides of molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti).

[0181] For example, the first active layer 520 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO); however, the embodiments of this disclosure are not limited thereto.

[0182] The first active layer 520 may include conductive and non-conductive regions. Furthermore, the first insulating film 512 may be disposed on the non-conductive region of the first active layer 520, and the conductive region of the first active layer 520 may be a region that does not overlap with the first insulating film 512.

[0183] The first insulating film 512 can be disposed on the first active layer 520.

[0184] The first insulating film 512 may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON); however, embodiments of this disclosure are not limited thereto.

[0185] The first insulating film 512 may include a second contact hole CH2 that overlaps with the first contact hole CH1 disposed in the buffer layer 511.

[0186] Therefore, the first insulating film 512 can also expose a portion of the top surface of the first conductive layer 310 through the second contact hole CH2. Furthermore, the second contact hole CH2 of the first insulating film 512 can expose a portion of the top surface of the first active layer 520.

[0187] The entire first contact hole CH1 of the buffer layer 511 may overlap with a portion of the second contact hole CH2 of the first insulating film 512. The first contact hole CH1 of the buffer layer 511 may not overlap with the first active layer 520.

[0188] The first contact hole CH1 of the buffer layer 511 and the second contact hole CH2 of the first insulating film 512 can be formed by the same process. In this way, the number of masks required to form the buffer layer 511 and the first insulating film 512 can be reduced.

[0189] Specifically, the material of the buffer layer 511 can be deposited on the substrate 300, and the material of the first active layer 520 can be deposited on the buffer layer 511. After the material of the first active layer 520 is patterned, the material of the first insulating film 512 can be deposited on the substrate 300.

[0190] Subsequently, a process for forming contact holes in each of the first insulating film 512 and the buffer layer 511 can be performed using a dry etching process. In this case, in the regions where the material of the first active layer 520 on the buffer layer 511 is present, since the material of the first active layer 520 serves as a mask, contact holes of the buffer layer 511 may not be formed in the corresponding regions.

[0191] That is, such as Figure 5 As shown, even when the respective contact holes are formed in the first insulating film 512 and the buffer layer 511 using the same process, since the first contact of the buffer layer 511 is not formed in the region where the first active layer 520 exists, and there is no material on the first insulating film 512 serving as a mask for the first active layer 520, the width W1 of the first contact hole CH1 of the buffer layer 511 can be smaller than the width W2 of the second contact hole CH2 of the first insulating film 512. Here, each of the widths W1 of the first contact hole CH1 of the buffer layer 511 and W2 of the second contact hole CH2 of the first insulating film 512 can be the minimum length in the second direction ( Figure 3 (In the middle, the direction in which the third signal line extends).

[0192] The first insulating film 512 can expose a portion of the top surface of the first active layer 520 disposed on the buffer layer 511 through the second contact hole CH2. The region of the first active layer 520 that does not overlap with the first insulating film 512 can be a conductive region 521a.

[0193] As described above, the material of the first insulating film 512 can be patterned using a plasma dry etching process to form a first insulating film 512 having a second contact hole CH2. Furthermore, the first active layer 520 disposed in the region corresponding to the region where the material of the first insulating film 512 has been removed by dry etching can become conductive due to the plasma.

[0194] In addition, the region of the first active layer 520 that overlaps with the first insulating film 512 can be a non-conductive region 521b.

[0195] Figure 5 An example is shown where the conductive region 521a of the first active layer 520 does not overlap with the first insulating film 512, and the non-conductive region 521b of the first active layer 520 overlaps with the first insulating film 512; however, embodiments of this disclosure are not limited thereto. Here, depending on the dry etching process conditions, a structure can be provided where a portion of the conductive region 521a of the first active layer 520 overlaps with the first insulating film 512.

[0196] The second conductive layer 330 can be disposed above the substrate 300 on which the first insulating film 512 is disposed.

[0197] The second conductive layer 330 may include any one of metals such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti), or alloys thereof; however, embodiments of this disclosure are not limited thereto.

[0198] The second conductive layer 330 can contact the top surface of the first conductive layer 310 exposed through the first contact hole CH1 of the buffer layer 511 and the second contact hole CH2 of the first insulating film 512.

[0199] In addition, the second conductive layer 330 may be disposed above the buffer layer 511 and contact the conductive region 521a of the first active layer 520 disposed around the first contact hole CH1 of the buffer layer 511.

[0200] In other words, the second conductive layer 330 can be electrically connected to the first conductive layer 310, and can also be electrically connected to the first active layer 520.

[0201] The second insulating film 513 can be disposed on the second conductive layer 330.

[0202] The second insulating film 513 may include an inorganic insulating material such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiON); however, embodiments of this disclosure are not limited thereto.

[0203] The second insulating film 513 may include a third contact hole CH3 that exposes a portion of the top surface of the second conductive layer 330. The third contact hole CH3 of the second insulating film 513 may overlap with a portion of the first contact hole CH1 formed in the buffer layer 511 and with a portion of the second contact hole CH2 formed in the first insulating film 512.

[0204] Therefore, a portion of the second conductive layer 330 that contacts the first conductive layer 310, and at least a portion of the second conductive layer 330 disposed on the buffer layer 511 and the first insulating film 512, can overlap with the third contact hole CH3 of the second insulating film 513.

[0205] The third insulating film 514 can be disposed on the second insulating film 513.

[0206] The third insulating film 514 may include organic insulating materials; however, embodiments of this disclosure are not limited thereto.

[0207] The third insulating film 514 may include a fourth contact hole CH4 overlapping the third contact hole CH3 of the second insulating film 513. The third insulating film 514 may expose a portion of the top surface of the second conductive layer 330 through the fourth contact hole CH4.

[0208] The areas of the third contact hole CH3 of the second insulating film 513 and the fourth contact hole CH4 of the third insulating film 514 may have the same size; however, the embodiments of this disclosure are not limited thereto. For example, the area of ​​the third contact hole CH3 of the second insulating film 513 may be smaller than the area of ​​the fourth contact hole CH4 of the third insulating film 514. In this case, the entire third contact hole CH3 of the second insulating film 513 may overlap with a portion of the fourth contact hole CH4 of the third insulating film 514.

[0209] The third conductive layer 360 can be disposed on the third insulating film 514.

[0210] The third conductive layer 360 may include a transparent conductive material, such as at least one of indium tin oxide (ITO), indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO); however, embodiments of this disclosure are not limited thereto.

[0211] The third conductive layer 360 can contact the second conductive layer 330 via the third contact hole CH3 of the second insulating film 513 and the fourth contact hole CH4 of the third insulating film 514. In other words, the contact holes 342 of the second insulating film 513 and the third insulating film 514, which are insulating films disposed between the second conductive layer 330 and the third conductive layer 360, can overlap with a portion of the second conductive layer 330, and since the third conductive layer 360 is disposed in the contact holes 342 of the second insulating film 513 and the third insulating film 514, the third conductive layer 360 can contact the second conductive layer 330.

[0212] Therefore, the third conductive layer 360 can be electrically connected to the second conductive layer 330, and the second conductive layer 330 is electrically connected to the first conductive layer 310 and the first active layer 520.

[0213] As described above, in the region corresponding to the second node N2 of the driving transistor T1 of the organic light-emitting display device 100 according to the embodiment described herein, the first contact hole CH1 of the buffer layer 511 may overlap with a portion of the second contact hole CH2 of the first insulating film 512. Furthermore, a portion of the first contact hole CH1 of the buffer layer 511 and a portion of the second contact hole CH1 of the first insulating film 512 may overlap with a portion of the third contact hole CH3 of the second insulating film 513 and a portion of the fourth contact hole CH4 of the third insulating film 514.

[0214] Furthermore, the first conductive layer 310, the first active layer 520, the second conductive layer 330, and the third conductive layer 360 are electrically connected to each other via contact holes (CH1, CH2, CH3, and CH4).

[0215] at the same time, Figure 5 An example is shown where the first active layer 520 has a single-layer structure; however, embodiments of this disclosure are not limited thereto.

[0216] For example, the first active layer 520 can have a multilayer structure with two or more layers. (See reference...) Figure 6 This multi-layered structure will be discussed in detail.

[0217] Figure 6 This is illustrated in another embodiment according to various aspects of this disclosure along... Figure 3 A cross-sectional view of the region intercepted by line AB.

[0218] In the following description, for ease of description, some structures, effects, etc. of the embodiments or examples discussed above may be described without repetition. Furthermore, in the following description, similar reference numerals will be used for the same structures or elements as those in the embodiments or examples described above.

[0219] like Figure 6As shown, the organic light-emitting display device 100 according to the embodiments described herein includes a first conductive layer 310, a buffer layer 511 including a first contact hole CH1, an active layer 620, a first insulating film 512 including a second contact hole CH2, a second conductive layer 330, a second insulating film 513 including a third contact hole CH3, a third insulating film 514 including a fourth contact hole CH4, and a third conductive layer 360.

[0220] The first active layer 620 disposed on the buffer layer 511 may include an active pattern 621 and at least one conductive pattern 622 disposed on the active pattern 621.

[0221] The active pattern 621 can be formed of an oxide semiconductor. The material included in the first active layer 620 can be a metal oxide semiconductor and can be formed of the following materials: i) oxides of metals such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti); or ii) combinations of metals such as molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) with oxides of molybdenum (Mo), zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti).

[0222] For example, the active pattern 621 may include at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO); however, the embodiments of this disclosure are not limited thereto.

[0223] The conductive pattern 622 may include any metal or alloy thereof, such as aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), titanium (Ti); however, embodiments of this disclosure are not limited thereto. For example, the conductive pattern 622 may include an alloy of molybdenum (Mo) and titanium (Ti); however, embodiments of this disclosure are not limited thereto.

[0224] The conductive pattern 622 can be disposed on the active pattern 621 to facilitate electrical connection with other components. Furthermore, the conductive pattern 622 can be used as a mask during the conduction process of the active pattern 621, thereby assisting the conduction process of the active pattern 621 without the need for an additional mask.

[0225] The first insulating film 512 may be configured to expose a portion of the top surface and at least one side surface of the active pattern 621.

[0226] The conductive pattern 622 may be configured to expose a portion of the top surface and at least one side surface of the active pattern 621.

[0227] The active pattern 621 may include a conductive region 621a and a non-conductive region 621b.

[0228] The conductive region 621a of the active pattern 621 may be or include a region that does not overlap with the first insulating film 512 and the conductive pattern 622. In this embodiment, the non-conductive region 621b of the active pattern 621 may be a region that overlaps with the conductive pattern 622.

[0229] In another embodiment, the conductive region 621a of the active pattern 621 may include a region that does not overlap with the first insulating film 512 but overlaps with the conductive pattern 622. In this embodiment, the non-conductive region 621b of the active pattern 621 may overlap with the first insulating film 512 and a portion of the conductive pattern 622.

[0230] In another embodiment, a portion of the conductive region 621a of the active pattern 621 may overlap with the first insulating film 512 and the conductive pattern 622. In this embodiment, a portion of the non-conductive region 621b of the active pattern 621 may overlap with a portion of the first insulating film 512.

[0231] The conductive region 621a of the active pattern 621 can be formed by a dry etching process on the first insulating film 512 and the buffer layer 511. In this case, the conductive pattern 622 disposed on the active pattern 621 is used as a mask, so the region of the active pattern 621 that does not overlap with the conductive pattern 622 can be made conductive by plasma.

[0232] Furthermore, depending on the dry etching process conditions, the conductive region 621a of the active pattern 621 can extend to a portion of the region overlapping with the conductive pattern 622.

[0233] An extension of the conductive region 621a of the active pattern 621 can contact the conductive pattern 622. For example, as Figure 6 As shown, when one end of the conductive pattern 622 is located at the boundary between the conductive region 621a and the non-conductive region 621b of the active pattern 621, the conductive pattern 622 can at least contact a portion of the conductive region 621a of the active pattern 621 at the boundary between the conductive region 621a and the non-conductive region 621b of the conductive pattern 622.

[0234] Furthermore, when a portion of the conductive region 621a of the active pattern 621 overlaps with a portion of the conductive pattern 622, the conductive pattern 622 can contact a portion of the top surface of the conductive region 621a of the active pattern 621.

[0235] The second conductive layer 330 can be disposed above the substrate 300 on which the first insulating film 512 is disposed.

[0236] A portion of the second conductive layer 330 may overlap with a portion of the first active layer 620, and the remainder of the second conductive layer 330 may not overlap with the first active layer 620.

[0237] In addition, the second conductive layer 330 can contact a portion of the active pattern 621 and a portion of the conductive pattern 622 of the first active layer 620 through the second contact hole CH2 disposed in the first insulating film 512.

[0238] Specifically, the second conductive layer 330 can contact a portion of the top surface and at least one side surface of the conductive pattern 622 that does not overlap with the first insulating film 512. In addition, the second conductive layer 330 can contact a portion of the top surface and at least one side surface (i.e., the conductive region 621a of the active pattern 621) that does not overlap with the conductive pattern 622.

[0239] The second conductive layer 330 can contact a portion of the top surface of the first conductive layer 310 via the second contact hole CH2 provided in the first insulating film 512 and the first contact hole CH1 provided in the buffer layer 511.

[0240] Therefore, the second conductive layer 330 can be electrically connected to the first conductive layer 310, the active pattern 521 and the conductive pattern 522 of the first active layer 520 via the first contact hole CH1 and the second contact hole CH2.

[0241] According to the embodiments described herein, the resistance of the conductive pattern 622 can be lower than the resistance of the active pattern 621. In this way, since the conductive pattern 622 is disposed on the active pattern 621 and the second conductive layer 330 is electrically connected to the conductive pattern 622 of the first active layer 620, the contact resistance can be reduced.

[0242] The second insulating film 513 having the third contact hole CH3 and the third insulating film 514 having the fourth contact hole CH4 can be disposed on or above the second conductive layer 330.

[0243] A portion of each of the third contact hole CH3 and the fourth contact hole CH4 may overlap with a portion of the first contact hole CH1 and a portion of the second contact hole CH2.

[0244] like Figure 6 As shown, a portion of the second contact hole CH2 overlaps with a portion of the first active layer 620, but all or one or more of the first contact hole CH1, the third contact hole CH3, and the fourth contact hole CH4 may not overlap with the first active layer 620.

[0245] The third conductive layer 360 can be disposed above the substrate on which the second insulating film 513 and the third insulating film 514 are disposed. The third conductive layer 360 can be electrically connected to the second conductive layer 330 via the third contact hole CH3 and the fourth contact hole CH4.

[0246] Here, a portion of the third conductive layer 360 may contact a portion of the second conductive layer 330 in the region where the third contact hole CH3 and the fourth contact hole CH4 overlap with a portion of the first contact hole CH1 and a portion of the second contact hole CH2, and the remaining portion or another portion of the third conductive layer 360 may contact a portion of the second conductive layer 330 in the region where the third contact hole CH3 and the fourth contact hole CH4 do not overlap with the first contact hole CH1 and the second contact hole CH2.

[0247] At the same time, Figure 5 and Figure 6 The illustration shows a structure in which one edge of the active layers 320 and 520 overlaps with one edge of the buffer layer 411, but the structure of the organic light-emitting display device 100 according to the embodiments described herein is not limited thereto.

[0248] The following section will provide a detailed discussion of the further structure of the organic light-emitting display device 100 according to embodiments of the present disclosure.

[0249] Figure 7 This is exemplified in yet another embodiment according to the present disclosure, along Figure 3 A cross-sectional view of the region intercepted by line AB.

[0250] In the following description, for ease of description, some structures, effects, etc. of the embodiments or examples discussed above may be described without repetition. Furthermore, in the following description, similar reference numerals will be used for the same structures or elements as those in the embodiments or examples described above.

[0251] Reference Figure 7 The active pattern 721 of the first active layer 720 can be disposed on a portion of the top surface of the buffer layer 511, and the conductive pattern 722 of the first active layer 720 can be disposed on the active pattern 721.

[0252] The active pattern 721 may include a conductive region 721a and a non-conductive region 721b.

[0253] The active pattern 721 and the conductive pattern 722 may be configured to expose a portion of the top surface of the buffer layer 511. The conductive pattern 722 may be configured to expose a portion of the top surface of the active pattern 721 and at least one side surface.

[0254] The buffer layer 511 may include a first contact hole CH1 that exposes a portion of the top surface of the first conductive layer 310. A portion of the top surface of an extension of the buffer layer 511 that extends from a side surface 711 corresponding to the interior of the first contact hole CH1 may not overlap with the active pattern 721 and conductive pattern 722 of the first active layer 720, and may also not overlap with the first insulating film 512 disposed on the first active layer 720.

[0255] Multiple protrusions 770 may be disposed in at least a portion of the top surface of an extension of the buffer layer 511 that does not overlap with the first active layer 720 and the first insulating film 512 and extends from a side surface 711 formed by the first contact hole CH1.

[0256] The shapes of the plurality of protrusions 770 may be irregular; however, the embodiments of this disclosure are not limited thereto.

[0257] Multiple protrusions 770 can be formed by a dry etching process used to form the second contact hole CH2 of the first insulating film 512.

[0258] Specifically, before forming the first insulating film 512, the material of the active pattern 721 and the material of the conductive pattern 722 can be sequentially deposited on the material of the first buffer layer 511 in which the first contact hole CH1 is not formed.

[0259] Furthermore, after patterning the conductive pattern 722 using wet etching, a first active layer 720 including the active pattern 721 that maintains a non-conductive state can be formed by using a process of patterning the material of the active pattern 721 using wet etching.

[0260] In this configuration, since the conductive pattern 722 is disposed on the active pattern 721, it prevents the active pattern 721 from being completely removed by the etching solution during the patterning of the material of the active pattern 721, and allows the material forming the active pattern 721 to be patterned, thereby enabling the active pattern 721 to be formed beneath the conductive pattern 722. In other words, the process stability of the first active layer 720 can be improved by using the conductive pattern 722.

[0261] As described above, when the active pattern 721 is patterned using wet etching, the outer edge of the active pattern 721 can have a very thin thickness due to the effect of the etching solution.

[0262] Subsequently, after depositing the material of the first insulating film 512 on the first active layer 720, which includes the active pattern 721 and the conductive pattern 722 that remain in a non-conductive state, the first contact hole CH1 and the second contact hole CH2 can be formed substantially simultaneously by performing dry etching on the material of the first insulating film 512 and the material of the buffer layer 511.

[0263] In the dry etching process for removing the material of the first insulating film 512, the first contact hole CH1 of the buffer layer 511 can be formed by removing the material of the buffer layer 511 located in the region corresponding to the region where the active pattern 721 is not provided.

[0264] Additionally, the outer edge (with a thin thickness) of the active pattern 721 can be removed by plasma to expose a portion of the top surface of the buffer layer 511. Therefore, a plurality of protrusions 770 can be formed by plasma on a portion of the top surface of the buffer layer 511 adjacent to the first contact hole CH1.

[0265] In other words, during the formation of the first contact hole CH1 in the buffer layer 511, the material of the thin active pattern 721 is retained from the buffer layer 511. Figure 7 In a portion of the top surface of the extension of the side surface 711 where the first contact hole CH1 is formed, a plurality of protrusions 770 can be formed on the top surface of the buffer layer 511 by removing the thin active pattern 721 in which the first contact hole CH1 is not formed.

[0266] Furthermore, during the formation of the first contact hole CH1 and the second contact hole CH2, the portion of the material of the active pattern 721 that was not removed by plasma and exposed can become conductive and serve as a conductive region of the active pattern 721.

[0267] Figure 7 An example is shown where the conductive region 721a of the active pattern 721 does not overlap with the first insulating film 512, and the non-conductive region 721b of the active pattern 721 overlaps with the first insulating film 512; however, embodiments of this disclosure are not limited thereto. Here, depending on the dry etching process conditions, a structure in which a portion of the conductive region 721a of the active pattern 721 overlaps with the first insulating film 512 can be provided.

[0268] The conductive region 721a of the active pattern 721 can be electrically connected to a portion of the conductive pattern 722 by contact.

[0269] The second conductive layer 330 may be disposed on or above the buffer layer 511, the first active layer 720 and the first insulating film 512.

[0270] The second conductive layer 330 can contact a portion of the top surface and at least one side surface of the active pattern 722 of the first active layer 720 via the second contact hole CH2 disposed in the first insulating film 512. The second conductive layer 330 can contact a portion of the top surface and at least one side surface of the conductive region 721a of the active pattern 721 of the first active layer 720 via the second contact hole CH2 disposed in the first insulating film 512.

[0271] The second conductive layer 330 may be in contact with the surface of all or some of the protrusions 770 disposed on a portion of the top surface of the buffer layer 511.

[0272] A second insulating film 513 including a third contact hole CH3 and a third insulating film 513 including a fourth contact hole CH4 can be disposed on the second conductive layer 330.

[0273] A portion of each of the third contact holes CH3 and the fourth contact hole CH4 may overlap with a portion of the first contact hole CH1 and a portion of the second contact hole CH2 of the buffer layer 511. The remaining portions of each of the third contact holes CH3 and the fourth contact holes CH4 may not overlap with the first contact hole CH1 and the second contact hole CH2.

[0274] The third contact hole CH3 and the fourth contact hole CH4 may not overlap with the plurality of protrusions 770 of the buffer layer 511. The plurality of protrusions 770 of the buffer layer 511 may not overlap with the first contact hole CH1, but may overlap with a portion of the second contact hole CH2.

[0275] The third conductive layer 360 can be disposed on the third insulating film 513.

[0276] The third conductive layer 360 can be electrically connected to the second conductive layer 330 via the third contact hole CH3 and the fourth contact hole CH4.

[0277] At the same time, in relation to Figure 2 In the region corresponding to the second node N2 of the driving transistor T1, the arrangement structure of the buffer layer 511, the first active layer (320, 520, 620 and 720), the first insulating film 512 and the second conductive layer 330 of the organic light-emitting display device 100 according to the embodiments described herein is not limited to... Figures 5 to 7 The structure shown can therefore be formed in various ways.

[0278] In the following text, refer to Figure 8 and Figure 10 The following will provide a discussion of other structures of organic light-emitting display devices according to various aspects of this disclosure.

[0279] Figures 8 to 10Various embodiments of the arrangement of the buffer layer, the first active layer, the first insulating film, and the second conductive layer in an organic light-emitting display device according to various aspects of the present disclosure are illustrated.

[0280] In the following description, for ease of description, some structures, effects, etc. of the embodiments or examples discussed above may be described without repetition. Furthermore, in the following description, similar reference numerals will be used for the same structures or elements as those in the embodiments or examples described above.

[0281] Reference Figure 8 The active pattern 821 of the first active layer 820 can be disposed on a portion of the top surface of the buffer layer 511, and the conductive pattern 822 of the first active layer 820 can be disposed on the active pattern 821.

[0282] The active pattern 821 may include a conductive region 821a and a non-conductive region 821b. Figure 8 An example is illustrated where the conductive region 821a of the active pattern 821 is a region that does not overlap with the first insulating film 512, while the non-conductive region 821b of the active pattern 821 is a region that overlaps with the first insulating film 512; however, embodiments of this disclosure are not limited thereto. Here, depending on the process conditions, a structure in which a portion of the conductive region 821a of the active pattern 821 overlaps with the first insulating film 512 can be provided.

[0283] A portion of the conductive pattern 822 may contact a portion of the conductive region 821a of the active pattern 821.

[0284] The active pattern 821 and the conductive pattern 822 may be configured to expose a portion of the top surface of the buffer layer 511. The conductive pattern 822 may be configured to expose a portion of the top surface of the active pattern 821 and at least one side surface.

[0285] The buffer layer 511 may include a first contact hole CH1 that exposes a portion of the top surface of the first conductive layer 310. A portion of the top surface of an extension of the buffer layer 511 extending from a side surface 711 formed by the first contact hole CH1 may not overlap with the active pattern 821 and conductive pattern 822 of the first active layer 820, and may also not overlap with the first insulating film 512 disposed on the first active layer 820.

[0286] The second conductive layer 330 can contact the surfaces of the first active layer 820 and the buffer layer 511 that do not overlap with the first insulating film 512.

[0287] The second conductive layer 330 can contact a portion of the conductive region 821a and a portion of the conductive pattern 822 of the first active layer 820 via the second contact hole CH2 of the first insulating film 512.

[0288] form Figure 8 The process of the first contact hole CH1 of the buffer layer 511 and the second contact hole CH2 of the first insulating film 512 shown can be compared with the reference. Figure 7 The described process is the same.

[0289] and Figure 7 Compared to the structure, in Figure 8 In the structure, depending on the process conditions for forming the first contact hole CH1 of the buffer layer 511 and the second contact hole CH2 of the first insulating film 512, a protrusion may not be formed in a portion of the top surface of the extension that does not overlap with the first active layer 820 and the first insulating film 512 and extends from a side surface 711 of the buffer layer 511.

[0290] The second insulating film 513 including the third contact hole CH3 and the third insulating film 513 including the fourth contact hole CH4 can be disposed on or above the second conductive layer 330.

[0291] The third contact hole CH3 and the fourth contact hole CH4 may overlap with a portion of the first contact hole CH1 and a portion of the second contact hole CH2 of the buffer layer 511.

[0292] The third conductive layer 360 can be disposed on the third insulating film 513.

[0293] The third conductive layer 360 can be electrically connected to the second conductive layer 330 via the third contact hole CH3 and the fourth contact hole CH4.

[0294] At the same time, despite Figures 6 to 8 An example is illustrated where a portion of the top surface of the active pattern (621, 721, or 821) of the first active layer (620, 720, or 820) does not overlap with the conductive pattern (622, 722, or 822); however, embodiments of this disclosure are not limited thereto.

[0295] Reference Figure 9 At least one outer edge of the active pattern 921 of the first active layer 920 may overlap with the outer edge of its conductive pattern 922.

[0296] In this embodiment, after the material of the active pattern 921 is deposited on the material of the buffer layer 511, the material of the conductive pattern 922 can be deposited on the material of the active pattern 921, and then the material of the conductive layer can be patterned by wet etching using a photoresist.

[0297] Subsequently, by wet etching and patterning the material of the active pattern 921 using a photoresist and conductive pattern 922, the active pattern 921 and conductive pattern 922 of the first active layer 920 can be formed, such as... Figure 9 As shown. Specifically, one outer edge of the photoresist pattern can overlap with one outer edge of the conductive pattern 922, and when the photoresist pattern and the conductive pattern 922 are used as masks to wet etch the material of the active pattern 921, the outer edges of the conductive pattern 922 and the active pattern 921 can overlap, as shown. Figure 9 As shown.

[0298] Furthermore, the top surface of the active pattern 921, which remains in a non-conductive state, can be covered by the conductive pattern 922, and the side surface of the active pattern 921 can be left uncovered by the conductive pattern 922 and can exist in an exposed state.

[0299] After removing the photoresist pattern set on the conductive pattern 922, the material of the first insulating film 512 can be deposited.

[0300] The second contact hole CH2 can be formed in the first insulating film 512 by a dry etching process, and simultaneously, the first contact hole CH2 can be formed in the buffer layer 511. During this process, the side surface of the active pattern 921 that is not covered by the conductive pattern 922 can become conductive by plasma.

[0301] By changing conditions such as the dry etching process time and the magnitude of the plasma energy, the interior of the active pattern 921 and the surface of the side surface forming the active pattern 921 can become conductive.

[0302] In this way, the active pattern 921 may include a conductive region 921a and a non-conductive region 921b.

[0303] The conductive pattern 922 may overlap with the conductive region 921a of the active pattern 921 corresponding to at least one side of the active pattern 921. Therefore, the conductive region 921a of the active pattern 921 may be electrically connected to a portion of the conductive pattern 922.

[0304] The first insulating film 512 can be disposed on the first active layer 920, and the second conductive layer 330 can be disposed on the first insulating film 512.

[0305] The second conductive layer 330 can contact a portion of the top surface and at least one side surface of the active pattern 922 of the first active layer 920 via a second contact hole CH2 formed in the first insulating film 512. Furthermore, the second conductive layer 330 can contact the conductive region 921a of the active pattern 921 of the first active layer 920.

[0306] A second insulating film 513 including a third contact hole CH3 and a third insulating film 513 including a fourth contact hole CH4 can be disposed on the second conductive layer 330.

[0307] The third contact hole CH3 and the fourth contact hole CH4 may overlap with a portion of the first contact hole CH1 and a portion of the second contact hole CH2 of the buffer layer 511.

[0308] The third conductive layer 360 can be disposed on the third insulating film 513.

[0309] The third conductive layer 360 can be electrically connected to the second conductive layer 330 via the third contact hole CH3 and the fourth contact hole CH4.

[0310] Next, refer to Figure 10 The active pattern 1021 of the first active layer 1020 can be set to expose a portion of the rear surface of the conductive pattern 1022.

[0311] It can be done Figure 9 The process described herein forms a first active layer 1020 having an active pattern 1021 that exposes a portion of the rear surface of a conductive pattern 1022.

[0312] and Figure 9 Compared to the structure, in Figure 10 In the structure, since the material of the active pattern 1021 can be over-etched by the etching solution during the wet etching process using the photoresist pattern and the conductive pattern 1022, the following structure is provided to allow the active pattern 1021 to expose a portion of the back surface of the conductive pattern 1022.

[0313] In the dry etching process following the deposition of the first active layer 1020, where a second contact hole CH2 is formed in the first insulating film 512 and a first contact hole CH1 is formed in the buffer layer 511, the side surface of the active pattern 1021 not covered by the conductive pattern 1022 can become conductive through plasma. Specifically, since plasma is not only linear, but also ensures that the conductive pattern 1022 does not contact the side surface of the active pattern 1021 even when the side surface of the active pattern 1021 has a structure overlapping with the conductive pattern 1022, the side surface of the active pattern 1021 can become conductive through plasma.

[0314] In this case, the top surface of the active pattern 1021, which remains in a non-conductive state, can be covered by the conductive pattern 1022, and the side surface of the active pattern 1021 can be left uncovered by the conductive pattern 1022 and can exist in an exposed state.

[0315] The active pattern 1021 may include a conductive region 1021a and a non-conductive region 921b. The conductive region 1021a of the active pattern 1021 may be a region corresponding to at least one side surface of the active pattern 1021, while the remaining regions may be non-conductive regions 1021b.

[0316] The boundary region between a side surface and a top surface of the active pattern 1021 can also become conductive, and the rear surface of the conductive pattern 1022 can contact the boundary region between a side surface and a top surface of the active pattern 1021.

[0317] The first insulating film 512 can be disposed on the first active layer 1020, and the second conductive layer 330 can be disposed on the first insulating film 512.

[0318] The second conductive layer 330 can contact one or more portions of the top surface, at least one side, and / or the rear surface of the conductive pattern 1022 of the first active layer 1020 via the second contact hole CH2 disposed in the first insulating film 512.

[0319] The second conductive layer 330 can contact the side surface of the active pattern 1021 of the active pattern 1021 of the active pattern 1021 of the first active layer 1020 via the second contact hole CH2 formed in the first insulating film 512.

[0320] That is, even when the active pattern 1021 is over-etched by forming an element disposed above the substrate 300 to expose a portion of the rear surface of the conductive pattern 1022, the structure enables the associated sub-pixels to be easily driven because the conductive pattern 1011 can contact a side surface of the active pattern 1021, which is the conductive region 1021b of the active pattern 1021, and the second conductive layer 330 can contact the first active layer 1020.

[0321] A second insulating film 513 including a third contact hole CH3 and a third insulating film 513 including a fourth contact hole CH4 can be disposed on the second conductive layer 330.

[0322] The third contact hole CH3 and the fourth contact hole CH4 may overlap with a portion of the first contact hole CH1 and a portion of the second contact hole CH2 of the buffer layer 511.

[0323] The third conductive layer 360 can be disposed on the third insulating film 513.

[0324] The third conductive layer 360 can be electrically connected to the second conductive layer 330 via the third contact hole CH3 and the fourth contact hole CH4.

[0325] Next, another structure of the region included in the second node N2 of the driving transistor T1 in the sub-pixel of the organic light-emitting display device 100 according to the embodiments described herein will be described with reference to the accompanying drawings.

[0326] Figure 11 It is based on all aspects of this disclosure. Figure 3 The cross-sectional view taken from line CD.

[0327] In the following description, for ease of description, some structures, effects, etc. of the embodiments or examples discussed above may be described without repetition. Furthermore, in the following description, similar reference numerals will be used for the same structures or elements as those in the embodiments or examples described above.

[0328] In the following description, the application will be used as a basis. Figure 6 The structure of the first active layer 620 shown is used to describe the first active layer.

[0329] Reference Figure 11 The first conductive layer 310 can be disposed on the substrate 300.

[0330] The buffer layer 511 can be disposed on the first conductive layer 310.

[0331] The buffer layer 511 may include a first contact hole CH1 that exposes a portion of the top surface of the first conductive layer 310.

[0332] The first insulating film 512 can be disposed on the buffer layer 511.

[0333] The first insulating film 512 may include a second contact hole CH2 that overlaps with the first contact hole CH1.

[0334] The second conductive layer 330 can be disposed on the first insulating film 512.

[0335] The second conductive layer 330 can contact a portion of the top surface of the first conductive layer 310 via the first contact hole CH1 of the buffer layer 511 and the second contact hole CH2 of the first insulating film 512.

[0336] The second insulating film 513 can be disposed on the second conductive layer 330.

[0337] The second insulating film 513 may include a third contact hole CH3 that overlaps with the first contact hole CH1 and the second contact hole CH2.

[0338] The third contact hole CH3 can expose a portion of the top surface of the second conductive layer 330. Specifically, the third contact hole CH3 can overlap with the entire second conductive layer 330 disposed in the first contact hole CH1 and the second contact hole CH2, and overlap with a portion of the second conductive layer 330 disposed in a portion of the top surface of the first insulating film 512 surrounding the second contact hole CH2.

[0339] The third insulating film 514 can be disposed on the second insulating film 315.

[0340] The third insulating film 514 may include a fourth contact hole CH4 that overlaps with the third contact hole CH3.

[0341] The fourth contact hole CH4 may overlap with the third contact hole CH3 to expose a portion of the top surface of the second conductive layer 330. Specifically, the fourth contact hole CH4 may overlap with the entire second conductive layer 330 disposed in the first contact hole CH1 and the second contact hole CH2, and may also overlap with a portion of the second conductive layer 330 disposed in a portion of the top surface of the first insulating film 512 surrounding the second contact hole CH2.

[0342] The third conductive layer 360 can be disposed on the third insulating film 514.

[0343] The third conductive layer 360 can contact a portion of the top surface of the second conductive layer 330 via the third contact hole CH3 and the fourth contact hole CH4.

[0344] Specifically, the third conductive layer 360 may contact the second conductive layer 330 disposed in the first contact hole CH1 and the second contact hole CH2, and may also overlap a portion of the second conductive layer 330, wherein the portion of the second conductive layer 330 may be disposed on a portion of the top surface of the first insulating film 512 surrounding the second contact hole CH2.

[0345] That is, along Figure 3 In the area where the CD is cut, the first conductive layer 310, the second conductive layer 330 and the third conductive layer 360 can be electrically connected.

[0346] In addition, such as Figure 11 As shown, in Figure 3 In the region along the CD cut, the first active layer may not be provided. That is, it can be seen that the region where CH1, CH2, CH3 and CH4 from the first contact hole to the fourth contact hole do not overlap with the first active layer.

[0347] At the same time, when the regions where multiple contact holes overlap (such as the structure where the first to fourth contact holes CH1, CH2, CH3 and CH4 overlap) are... Figure 3 When the first active layer or the second active layer described in the structure shown overlaps, there is a possibility that the first active layer or the second active layer may be damaged during the process of forming multiple contact holes, or because the first active layer or the second active layer is over-etched, portions of the first insulating layer or the second active layer, including the first contact holes to the fourth contact holes CH1, CH2, CH3 and CH4, may be exposed, and thus these insulating films may be damaged.

[0348] Specifically, when a portion of at least one element disposed above the substrate 300 is patterned using a wet etching process, unintended over-etching of the associated active layer may occur due to the etching solution, which may also damage the buffer layer 511 disposed below the active layer. For example, structural defects such as forming an oversized first contact hole CH1 may occur.

[0349] However, in the organic light-emitting display device 100 according to the embodiments described herein, not only the overlapping areas of the third contact hole CH3 and the fourth contact hole CH4, but also the overlapping areas of the first contact hole to the fourth contact hole CH1, CH2, CH3 and CH4 do not overlap with the first active layer. Therefore, it is possible to prevent damage to the buffer layer due to over-etching of the active layer.

[0350] Furthermore, as described above, since the entire first contact hole CH1 overlaps with the second contact hole CH2, and the first contact hole CH1 and the second contact hole CH2 overlap with the third contact hole CH3 and the fourth contact hole CH4, the area occupied by the multiple contact holes can be reduced, thereby increasing the size of the storage capacitor located in the associated sub-pixel.

[0351] The storage capacitor of the organic light-emitting display device 100 according to the embodiments described herein may include multiple layers of electrodes, thereby enabling the realization of a storage capacitor with high capacitance characteristics.

[0352] Reference Figure 12 The structure of the storage capacitor according to the embodiments described herein is discussed.

[0353] Figure 12 It is based on all aspects of this disclosure. Figure 3 The cross-sectional view taken from line EF.

[0354] In the following description, for ease of description, some structures, effects, etc. of the embodiments or examples discussed above may be described without repetition. Furthermore, in the following description, similar reference numerals will be used for the same structures or elements as those in the embodiments or examples described above.

[0355] In the following description, the application will be used as a basis. Figure 6 The structure of the first active layer 620 shown is used to describe the first active layer.

[0356] Reference Figure 12 The first conductive layer 310, buffer layer 511, active pattern 621 and conductive pattern 622 of the first active layer 620, first insulating film 512, plate 340, second insulating film 513, third insulating film 514 and third conductive layer 360 can be sequentially disposed above the substrate 300.

[0357] As described above, plate 340 can be disposed in the same layer as the second conductive layer 330.

[0358] When one or more layers of inorganic insulating material are disposed between the first conductive layer 310, the active pattern 621 of the first active layer 620, and the plate 340, each of the first conductive layer 310, the active pattern 621 of the first active layer 620, and the plate 340 is disposed overlapping each other, thereby serving as an electrode of a storage capacitor.

[0359] According to the embodiments described herein, since the first active layer 620 includes a conductive pattern 622, and most of the overlapping area of ​​the plate 340, the first active layer 620 and the first conductive layer 310 is used as a storage capacitor Cst, an organic light-emitting display device 100 with high resolution can be realized.

[0360] Although Figure 12 The structure of the first active layer 620, including the conductive pattern 621, is shown; however, as Figure 5 As shown, the first active layer 520 may have a structure that includes only active patterns. In this case, the region of the active pattern located in the area where the storage capacitor is disposed may be a conductive region.

[0361] Since the storage capacitor of the organic light-emitting display device 100 according to the embodiments described herein has a multilayer structure, it is possible to realize a storage capacitor with high capacitance characteristics.

[0362] According to various aspects of this disclosure, since the multiple contact holes disposed in the region where the second node of the driving transistor is located are arranged to overlap, and thus the size of the conductive layer overlapping with the multiple contact holes can be reduced, an organic light-emitting display panel with high brightness characteristics and an organic light-emitting display device including the display panel can be provided by making it possible to reduce the area of ​​the non-light-emitting area and increase the area of ​​the light-emitting area relative to the area of ​​the non-light-emitting area without reducing the area of ​​the storage capacitor.

[0363] Furthermore, according to aspects of this disclosure, since the multiple contact holes disposed in the region where the second node of the driving transistor is located overlap, and thus the size of the conductive layer overlapping with the multiple contact holes can be reduced, the size or capacity of the storage capacitor can be increased without reducing the area of ​​the light-emitting region, and thus an organic light-emitting display panel with high brightness and high resolution and an organic light-emitting display device including the display panel can be provided.

[0364] Furthermore, according to aspects of this disclosure, since the active layer includes an active pattern and a conductive pattern disposed on the active pattern, an organic light-emitting display panel capable of easily driving sub-pixels and an organic light-emitting display device including the display panel can be provided.

[0365] Furthermore, according to aspects of this disclosure, since the active layer does not overlap with a portion of the formation area of ​​the plurality of contact holes, an organic light-emitting display panel having a structure capable of preventing damage to the active layer or buffer layer during the relevant process, and an organic light-emitting display device including the display panel, can be provided.

[0366] The foregoing description has been provided to enable any person skilled in the art to make and use the technical concept of the invention, and has been provided above and below in the context of specific applications and their requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The foregoing description and drawings are merely examples of the technical concept of the invention for illustrative purposes. That is, the disclosed embodiments are intended to illustrate the scope of the technical concept of the invention. Therefore, the scope of the invention is not limited to the embodiments shown, but is consistent with the broadest scope consistent with the claims. The scope of protection of the invention should be interpreted based on the appended claims, and all technical concepts within their equivalents should be interpreted as being included within the scope of the invention.

[0367] Cross-reference to related applications

[0368] This application claims priority to Korean Patent Application No. 10-2020-0178383, filed on December 18, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference.

Claims

1. An organic light-emitting display device, the organic light-emitting display device comprising: substrate; A first conductive layer is disposed on the substrate; A buffer layer is disposed on the first conductive layer and includes a first contact hole overlapping a portion of the first conductive layer; An active layer is disposed on the buffer layer and overlaps with the first conductive layer; A first insulating film is disposed above the active layer and the buffer layer, and includes a second contact hole overlapping the first contact hole; A second conductive layer is disposed on the first insulating film, and contacts a portion of the first conductive layer via the first contact hole and the second contact hole, and contacts a portion of the active layer via the second contact hole; A second insulating film is disposed on the second conductive layer and includes a third contact hole that overlaps with a portion of each of the first and second contact holes; as well as A third conductive layer is disposed on the second insulating film and contacts a portion of the second conductive layer via the second contact hole. The third contact hole does not overlap with the active layer.

2. The organic light-emitting display device according to claim 1, wherein, The first contact hole does not overlap with the active layer.

3. The organic light-emitting display device according to claim 1, wherein, The active layer includes at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO). The area where the active layer overlaps with the second contact hole is a conductive area.

4. The organic light-emitting display device according to claim 1, wherein, The active layer includes an active pattern disposed on the buffer layer and at least one conductive pattern disposed on the active pattern. The active pattern includes at least one of zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), and indium zinc tin oxide (IZTO), and the conductive pattern includes any one of a metal or alloy, wherein the metal includes aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti), and the alloy includes two or more of aluminum (Al), gold (Au), silver (Ag), copper (Cu), tungsten (W), molybdenum (Mo), chromium (Cr), tantalum (Ta), or titanium (Ti).

5. The organic light-emitting display device according to claim 4, wherein, The active pattern includes conductive and non-conductive regions, and the conductive pattern contacts the conductive region of the active pattern.

6. The organic light-emitting display device according to claim 4, wherein, The conductive pattern exposes a portion of the top surface and at least one side surface of the active pattern.

7. The organic light-emitting display device according to claim 4, wherein, At least one outer edge of the conductive pattern overlaps with the outer edge of the active pattern.

8. The organic light-emitting display device according to claim 4, wherein, The active pattern exposes a portion of the back surface of the conductive pattern.

9. The organic light-emitting display device according to claim 1, wherein, The active layer exposes a portion of the top surface of the buffer layer, and the portion of the top surface of the buffer layer exposed by the active layer includes a plurality of protrusions.

10. The organic light-emitting display device according to claim 1, wherein, The active layer includes a conductive region, which is either a region where the active layer does not overlap with the first insulating film, or a region that includes both the region where the active layer does not overlap with the first insulating film and a portion of the region where the active layer overlaps with the first insulating film.

11. The organic light-emitting display device according to claim 1, further comprising a plate, the plate being disposed in the same layer as the second conductive layer and spaced apart from the second conductive layer. in, The plate forms a storage capacitor by overlapping with a portion of the first conductive layer and a portion of the active layer.

12. The organic light-emitting display device according to claim 11, wherein, The plate includes a first extension that overlaps with the portion of the active layer, and the first extension is the gate of a driving transistor in a sub-pixel of the organic light-emitting display device.

13. The organic light-emitting display device according to claim 12, wherein, The region where the first contact hole, the second contact hole, and the third contact hole are located is the region of the node to which the reference voltage is applied to the driving transistor.

14. The organic light-emitting display device according to claim 1, wherein, The third conductive layer is the anode or cathode of the organic light-emitting element.

15. The organic light-emitting display device according to claim 1, wherein, The area where two or more of the first contact hole, the second contact hole, and the third contact hole overlap does not overlap with the active layer.

16. An organic light-emitting display panel, the organic light-emitting display panel comprising: substrate; A first conductive layer is disposed on the substrate; A buffer layer is disposed on the first conductive layer and includes a first contact hole overlapping a portion of the first conductive layer; An active layer, comprising an active pattern disposed on the buffer layer and a conductive pattern disposed on the active pattern, the active layer overlapping the first conductive layer; A first insulating film is disposed above the active layer and the buffer layer, and includes a second contact hole overlapping the first contact hole; A second conductive layer is disposed on the first insulating film, and contacts a portion of the first conductive layer via the first contact hole and the second contact hole, and contacts a portion of the active layer via the second contact hole; A plate, which is disposed in the same layer as the second conductive layer and is spaced apart from the second conductive layer; as well as A second insulating film is disposed above the second conductive layer and the plate, and includes a third contact hole overlapping a portion of each of the first and second contact holes. Wherein, the third contact hole does not overlap with the active layer, and In this configuration, one or more of the first conductive layer, the active layer, and the plate form a storage capacitor.

17. The organic light-emitting display panel according to claim 16, wherein, The storage capacitor includes the conductive pattern of the active layer as the electrode of the storage capacitor.

18. The organic light-emitting display panel according to claim 16, wherein, The first contact hole does not overlap with the active layer.

19. The organic light-emitting display panel according to claim 16, wherein, The region where the first contact hole, the second contact hole, and the third contact hole are located is the region of the node that applies a reference voltage to the driving transistor in the sub-pixel of the organic light-emitting display panel.

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