Semiconductor device and method of forming the same

Abstract

A semiconductor device includes a substrate. A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first nanosheet structure and the second nanosheet structure has at least one nanosheet forming a source / drain region and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first nanosheet structure and the second nanosheet structure. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure, and the gate structure of the first nanosheet structure define a capacitor. Embodiments of the present application also relate to methods of forming a semiconductor device.

Description

Technical Field

[0001] Embodiments of this application relate to semiconductor devices and methods of forming the same. Background Technology

[0002] Capacitors are common components within the internal structure of semiconductor devices. For example, 30% or more of the analog region of a semiconductor device may be covered by capacitors. Approximately 10% or more of the digital region of a semiconductor may be covered by capacitors. Higher capacitance density (e.g., including more capacitors in a smaller area) offers the advantage of a smaller die area and lower die cost. Furthermore, capacitance density typically needs to increase with each generation of semiconductor devices. Summary of the Invention

[0003] Some embodiments of this application provide a semiconductor device, including: a substrate; a first nanosheet structure and a second nanosheet structure disposed on the substrate, each of the first nanosheet structure and the second nanosheet structure including: at least one nanosheet forming a source / drain region; a gate structure including a conductive gate contact; a first oxide structure disposed on the substrate between the first nanosheet structure and the second nanosheet structure; and a conductive terminal disposed in or on the first oxide structure; wherein the conductive terminal, the first oxide structure, and the gate structure of the first nanosheet structure define a capacitor.

[0004] Other embodiments of this application provide a semiconductor device comprising: a first nanosheet structure including at least one nanosheet forming a source / drain region and a gate structure including a conductive gate contact; an oxide structure wherein there is no p-type epitaxy (P-EPI) or n-type epitaxy (N-EPI) in or on the oxide structure; and a conductive terminal disposed in or on the oxide structure; wherein the conductive terminal, the oxide structure, and the gate structure of the first nanosheet structure form a first capacitor.

[0005] Further embodiments of this application provide a method for forming a semiconductor device, comprising: patterning fin elements from an epitaxial stack; forming a gate structure over the fin elements; forming an oxide diffusion (OD) adjacent to the gate structure; forming a metal diffusion (MD) within the oxide diffusion; connecting the gate structure as a first terminal of a vertical metal-oxide-metal (VMOM) capacitor; and connecting the metal diffusion as a second terminal of the vertical metal-oxide-metal capacitor, wherein the oxide diffusion is a dielectric between the gate structure and the metal diffusion. Attached Figure Description

[0006] Aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figure 1A This is a cross-sectional block diagram illustrating an aspect of an exemplary semiconductor device according to an example of this application.

[0008] Figure 1B This illustrates an example according to this application. Figure 1A A top view block diagram of other aspects of the exemplary semiconductor device shown.

[0009] Figure 1C This illustrates an example according to this application. Figure 1B A cross-sectional block diagram of other aspects of the exemplary semiconductor device shown.

[0010] Figure 2 This illustrates an example according to this application. Figures 1A to 1C A top view of other aspects of the exemplary semiconductor device shown.

[0011] Figure 3 This illustrates an example according to this application. Figures 1A to 1C A top view of other aspects of the exemplary semiconductor device shown.

[0012] Figure 4A and Figure 4B This illustrates an example according to this application. Figures 1A to 1C A top view of other aspects of the exemplary semiconductor device shown.

[0013] Figure 5 This illustrates an example according to this application. Figure 2 A top view of other aspects of the exemplary semiconductor device shown.

[0014] Figure 6 It is a process diagram showing the process for forming one or more devices as described herein, according to an example of this application.

[0015] Figure 7A It is an isometric view formed according to an example of this application for forming a structure of one or more devices as described herein.

[0016] Figure 7B This is another isometric view formed according to an example of this application for forming a structure of one or more devices as described herein.

[0017] Figure 7C This is another isometric view formed according to an example of this application for forming a structure of one or more devices as described herein.

[0018] Figure 7D This is another isometric view formed according to an example of this application for forming a structure of one or more devices as described herein.

[0019] Figure 7E This is another isometric view formed according to an example of this application for forming a structure of one or more devices as described herein.

[0020] Figure 7F This is another isometric view formed according to an example of this application for forming a structure of one or more devices as described herein.

[0021] Figure 7G This is another isometric view formed according to an example of this application for forming a structure of one or more devices as described herein.

[0022] Figure 7H This is another isometric view formed according to an example of this application for forming a structure of one or more devices as described herein. Detailed Implementation

[0023] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component on or over a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0024] Furthermore, for ease of description, this document uses spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship between one element or component and another (or other elements or components) as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0025] In the accompanying drawings, the thickness and width of layers and regions may be exaggerated for illustrative purposes. The same reference numerals in the drawings denote the same elements. The elements and regions shown in the figures are schematic in nature, and therefore the relative dimensions or spacing shown in the figures are not intended to limit the scope of the inventive concept.

[0026] Higher capacitance density (e.g., including more capacitors in a smaller area) offers the advantage of a smaller die area and lower die cost. Furthermore, capacitance density typically needs to increase with each generation of semiconductor devices. To provide low leakage and high capacitance density, many previous capacitors were built as input / output (I / O) oxide-metal-oxide-semiconductor field-effect transistors (MOSFETs) or passive metal-dielectric-metal (MDM) capacitors. Unfortunately, the gate leakage of core MOSFETs is too high to be used as capacitors. Additionally, I / O oxide MOSFETs and known passive MDM capacitors may require additional masks to build these capacitors. In other words, higher capacitance density requires additional masks. Other capacitors that can be used include metal-oxide-metal (MOM) capacitors. MOM capacitors can utilize wiring / power / ground metals, but known MOM capacitors also increase the die area.

[0027] Conventional MOM capacitors can be formed using CMOS fabrication processes. Electrodes can comprise multiple conductive electrode layers formed on a substrate, and the capacitance of a conventional MOM capacitor can be based on the capacitance of a pair of adjacent electrodes, which includes the capacitance between each metal layer of the pair of adjacent electrodes. Additional capacitance can be similarly formed between the two contact metal portions of adjacent electrodes. To further increase the capacitance of a conventional MOM capacitor, additional electrodes can be added. However, the surface area of ​​a conventional MOM capacitor may be limited by design rules associated with CMOS fabrication processes, which may prevent conventional MOM capacitors from achieving certain capacitances without undesirable increases in surface area.

[0028] A nanosheet transistor is a type of field-effect transistor (FET) comprising multiple stacked nanosheets extending between a pair of source / drain epitaxial (EPI) regions formed on an active region, which may include an oxide layer or oxide diffusion (OD). The term nanosheet is used herein to refer to any portion of material having a nanometer-scale or even micrometer-scale size and an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, as well as bundles or strips of material including, for example, cylindrical or substantially rectangular cross-sections.

[0029] Epitaxy is a type of material deposition in which a crystalline layer is formed with a defined orientation relative to a crystalline substrate. A FET typically comprises doped source / drain epitaxial regions formed in a semiconductor substrate and separated by channel regions. A gate insulating layer lies above the channel regions, and a conductive gate electrode lies above the gate insulating layer. The source / drain EPI regions can be doped with N-type and / or P-type dopants. For example, N-type epitaxy (N-EPI) can be provided to form the source / drain regions of an N-type FET, while P-type EPI (N-EPI) can be provided to form the source / drain regions of a P-type FET. The gate electrode is typically formed from a conductive material such as polysilicon (PO). The gate insulating layer and the gate electrode can together be referred to as the device's "gate stack," "gate structure," etc. By applying an appropriate voltage to the gate electrode, the channel regions become conductive and allow current to flow between the source and drain regions of the structure.

[0030] To improve the operating speed of FETs and increase the density of FETs on integrated circuits (ICs), designs can be progressively smaller in size. Reducing the size and channel length within a FET can improve its switching speed. Device architectures such as "gate all-around" (GAA) nanosheet structures allow for further scaling down of ICs, partly because the gate is constructed to wrap around the channel. This structure can provide better control with lower leakage current, faster operation, and lower output resistance.

[0031] Therefore, the nanosheet FET comprises multiple channel layers, each separated by a gate stack comprising an electrically conductive gate material layer and a gate dielectric layer. The gate stack covers all sides of the channel layer, thereby forming a GAA structure. The EPI region at the end of the nanosheet channel layer forms the source / drain region of the nanosheet FET. Spacers are used to electrically isolate the gate from the source / drain region of the nanosheet transistor. The nanosheet transistor spacer may comprise two parts: an external spacer and an internal spacer.

[0032] This paper provides aspects of capacitors in nanosheet processes. In some instances, nanosheet FET structures are provided without N-EPI or P-EPI on the OD. In nanosheet processes, when there is no filled N-EPI or P-EPI in the source / drain (S / D) region of the nanosheet FET structure, the metal diffusion (MD) depth can be much deeper (e.g., two or more times the MD depth on shallow trench isolation (STI)). This paper provides design schemes that fully utilize some of these nanosheet processes. These aspects can provide low-leakage or zero-leakage vertical MD-polysilicon (PO) capacitors in nanosheet structures and can include MD-PO capacitors on STI and MD-PO capacitors without N-EPI or P-EPI on the OD. These disclosed capacitor types are referred to as nanosheet OD-VMOM (OD-VMOM) without EPI.

[0033] An example of an on-OD VMOM capacitor has capacitor plates formed by the gate electrode MD and PO, with the oxide of the OD located between the plates to form the capacitor dielectric (“MD-PO capacitor”). The on-OD VMOM may lack N-EPI or P-EPI, as noted above. Furthermore, the on-OD VMOM capacitor can coexist with the STI VMOM, as discussed further below. The on-OD VMOM capacitor can be connected to the on-OD MD, the length of which can be between 2 nm and 200 nm. The MD-PO capacitor can be connected to the on-STI MD, the length of which can be between 10 nm and 100 nm.

[0034] VMOM capacitors on the OD can be implemented using logic rules. Dual-height SOC standard cells can be created to provide VMOM capacitors on the OD. Cell height can be, for example, between 10 nm and 400 nm. Contact polycrystalline spacing can be, for example, between 20 nm and 100 nm. The number of ODs can be two or three, for example, a larger OD located between two other ODs. Wide metal P / G width can be, for example, between 8 nm and 50 nm. Signal metal width can be, for example, between 4 nm and 30 nm. VMOM capacitors on the OD can be combined on top of them with MOM capacitors. In this configuration, wide metal P / G width can be, for example, between 8 nm and 50 nm. Signal metal width can be, for example, between 4 nm and 30 nm. A transistor boundary can include at least one M0, in addition to the wide metal for power / ground. The number of M0s is unrestricted. For example, a transistor boundary can include 2, 3, 4, or 5 M0s. Furthermore, logic FIN boundary design rules can be applied to nanosheets, where the nanosheets correspond to FinFETs.

[0035] As noted above, this invention proposes a design scheme for realizing zero-leakage vertical MD-PO capacitors in nanosheets, including MD-PO capacitors on the STI and MD-PO capacitors without N-EPI or P-EPI on the OD. In nanosheet fabrication, when there is no N-EPI or P-EPI filling in the S / D region, the MD depth can be twice or more than the MD depth on the STI. Typically, there can be EPIs between nanosheet units, and each EPI can have an MD disposed thereon.

[0036] Incorporating VMOM on the die within the semiconductor offers advantages. VMOM capacitors on the die can improve the capacitance density of zero-leakage MD-PO. In some configurations, capacitance density can be increased by 1% to over 100%. No additional mask is required, allowing for cost reduction. Furthermore, the die area can be reduced. Additionally, low leakage and high capacitance density can be achieved.

[0037] Figures 1A to 7H Planar and cross-sectional views of semiconductor devices 100 and 130, formed as nanosheet semiconductor structures according to aspects of the present invention, are shown. Embodiments of semiconductor device 100 may be as follows: Figure 1A and Figure 1B As shown in the image. Figure 1A The cross-sectional view is usually along Figure 1B and Figure 2 Line 204 is cut off in the diagram. Semiconductor device 100 may include capacitors (collectively referred to as capacitor 102) indicated by symbols 102a and 102b. Capacitor 102 can be any device capable of storing charge in an electric field. Capacitor 102 is a passive electronic component that may be formed by two terminals separated by a spacer. In many embodiments, the spacer is filled with a dielectric, while the terminals are formed of conductors.

[0038] Semiconductor device 100 may have nanosheet semiconductor device 200. Nanosheet semiconductor structure 100 may include two nanosheet units 122a, 122b (collectively referred to as nanosheet unit 122) having source (S) and drain (D) regions. Nanosheet unit 122 may include one or more nanosheet structures 124a-124f (collectively referred to as nanosheet structure 124) and gate contacts, such as PO gates 110a, 110b (collectively referred to as PO gate 110, PO region 110, or simply PO 110). Typically, nanosheet units 122a, 122b will have an EPI between them, which may be N-EPI or P-EPI. In the illustrated structure, nanosheet units 122a, 122b have an OD 108 without an EPI between them. The capacitor 102 provided in semiconductor device 100 may be formed as a VMOM capacitor. Figure 1AAs shown, conductive contacts such as MD 104 are disposed in or on OD 108a, and a first capacitor terminal may be formed by MD 104, and a second capacitor terminal may be formed by a region of PO gate 110, where PO gate 110 refers to a polysilicon gate region. MD 104 and PO gate 110 are separated by a region of OD 108 that can be used as a dielectric.

[0039] MD 104 can be formed on and / or in OD 108. MD 104 can be made of various metals, such as palladium, platinum, rhodium, iridium, etc. MD 104 can be deposited on and / or in OD 108. For example, MD 104 can have a first portion 116 located on OD 108 and a second portion 114 formed within OD 108. The separation between the two portions 114, 116 can be represented by a line 118. This embodiment of MD 104 allows MD 104 to be placed in physical proximity to the PO gate 110 to form a VMOM capacitor 102. In this way, the formation of MD 104 within OD 108 forms a VMOM capacitor 102. The distance from where MD 104 is formed to the OD 108 can be represented by a measurement of a first depth 112, such as... Figure 1A As shown in the image. MD 104 can have various shapes, for example, Figure 1A The MD 104 shown can have a wedge shape with small angles to the vertical on both sides and a top that is slightly wider than the bottom of the MD 104.

[0040] To change the capacitance provided by the VMOM capacitor 102, the length of MD 104 or OD 108 can be adjusted. In this embodiment, the length of MD 104 can be between 2 nm and 20 nm. The configuration of MD 104, OD 108, and PO gate 110 provides a zero-leakage capacitor.

[0041] The PO gate 110 can be a region including the PO gate 110 (also referred to as the PO region or simply PO) surrounding and connected to the source and drain regions 106. The PO region 110 can be a highly doped region of silicon that can form a gate connection. The PO gate 110 can be connected to place the capacitor 102 into a circuit. Therefore, the PO gate 110 represents a second terminal for the capacitor 102.

[0042] OD 108 can be an oxide structure with dielectric properties. OD 108 can be formed from silicon oxide or similar compounds. OD 108 can have various depths and / or lengths to provide a dielectric for capacitor 102 and vary the capacitance provided by capacitor 102. The insulating material of OD 108 can be formed from a dielectric material based on silicon oxide, such as undoped silicate glass (USG), fluorinated silicate glass (FSG), plasma-enhanced CVD (PECVD) silicon oxide, and oxide / nitride / oxide. Furthermore, the insulating material of OD 108 can be formed from one or more high-k (high dielectric constant) materials, such as those having a dielectric constant of at least 8, for example, Ta2O5, HfO2, SrTiO3, PbTiO3, KNO3, and / or Al2O3.

[0043] like Figure 1B As shown, the OD without EPI 108 is separated by STI 138. In some instances, additional VMOM capacitors 132a and 132b (collectively referred to as capacitors 132) are formed on STI 138. These structures are referred to herein as VMOM capacitors 132 on STI.

[0044] The implementation of the VMOM capacitor 130 on STI can be as follows: Figure 1C As shown in the diagram. In this embodiment, an STI VMOM capacitor 132 is formed between MD 104 and PO 110. The capacitor 132 has an STI 138 region separating MD 104 and PO 110. The capacitor 132 may be included in... Figure 1A In the capacitor 102 shown. Therefore, both types of capacitors 102 and 132 can exist within the nanosheet structure, such as Figure 1B As shown in the image.

[0045] refer to Figure 1A and Figure 1C The distance from MD 104 to OD 108 can be represented by a measurement of the first depth 112, such as... Figure 1A As shown. The MD 104 formed in / on OD 108 can be two or more times deeper than the MD 104 formed in STI 138, as shown by Figure 1C The measurement value 144 shown is indicated. Furthermore, MD 104 can be closer to the bottom portion of OD 108, as indicated by the depth measurement value 120, and... Figure 1C The depth measurement 142 shown here forms a contrast, representing the depth of MD 104 in STI 138.

[0046] In some implementations, the first depth 112 of MD 104 in OD 108 may be two or more times the second depth 144 of MD 104 in STI 138. In general, the depth or height of MD 104 may be two or more times the depth or height of MD 104. MD 104 may have various shapes, for example, Figure 1A and Figure 1C The MD 104 shown can have a wedge shape with small angles to the vertical on both sides and a top that is slightly wider than the bottom of the MD 104.

[0047] Figure 2 It shows Figure 1B Other aspects of the nanosheet semiconductor device 200 shown. The nanosheet semiconductor device 200 may include a substrate 202, which may include, but is not limited to, one or more of bulk silicon, semiconductor wafers, silicon-on-insulator (SOI) substrates, or silicon-germanium substrates. In some embodiments, other semiconductor materials may include group III, group IV, and group V elements. The substrate 202 is a support material on which the semiconductor device 200 is formed. The substrate 202 may include various materials that support thin-film circuit elements and possibly other components.

[0048] The device 200 shown includes having Figure 1A The capacitor 102 shown has two VMOM regions on its two ODs and has Figure 1C The capacitor 132 shown has two MOM regions on the STI. Therefore, device 200 includes an OD 108 without EPI separated by STI 138. PO 110 and MD 104 are in... Figure 2 In this example, the vertically extending, cut MD 210 is configured to physically and electrically separate portions of MD 104. Gate via (VG) 220 and MD via (VD) 222 provide corresponding electrical connections to PO 110 and MD 104.

[0049] Figure 3 An example of a semiconductor device 200 comprising multiple OD 108s without EPIs, separated from each other by STI 132, is shown. As noted above, the depth of MD 104 entering OD 108 can be greater than the depth of MD 104 entering STI 132. For example, the depth of MD 104 in OD 108 can be two or more times that of MD 104 in STI 138. Figure 3 In the examples, the MD 104 length (i.e., depth) on the OD in OD regions A1, A2, and A3 is between 2 nm and 200 nm. The MD 104 length (i.e., depth) on the STI in STI regions B1, B2, and B3 is between 10 nm and 100 nm.

[0050] The examples of the semiconductor devices 200 disclosed herein can be implemented using design rules. ICs are typically designed using a highly automated process called Electronic Design Automation (EDA). Such EDA tools and methods facilitate the design, partitioning, and placement of microelectronic integrated circuits on semiconductor substrates. This process typically involves converting a behavioral description of the circuit into a functional description, then decomposing it into logical functions and mapping them to cells using a standard cell library. The standard cell library contains a list of pre-designed components or cells, each of which can implement discrete logical functions. Cells are stored in the cell library as information including internal circuit elements, various connections to these circuit elements, and a pre-designed physical layout pattern, including the unit height of each cell and the cell's design power rails, dopant implants, wells, etc. Furthermore, the stored cells may also include the cell's shape, terminal locations for external connections, delay characteristics, power consumption, etc.

[0051] Standard cell logic design rules can be used in the design of cells stored in the standard cell library. For example, FinFET logic design rules can be applied to nanosheet structures, where the nanosheets correspond to FinFET structures. Such logic design rules can include, for example, rules such as... Figure 2 The spacing standards between the vias of VG 220 and MD 222 are shown. In some embodiments, the logic design rules include spacing standards between nanosheet layout patterns, spacing standards between via layout patterns and cut component layout patterns, spacing standards between OD regions, MD design rules, metal zero (MO) track design rules, etc.

[0052] Return to reference Figure 2 The semiconductor device 200 shown can be implemented as a dual-height, system-on-chip (SOC) standard cell 230, which includes one or more single-optical logic cells 232. Figure 3 An example may include two standard units 234 indicated by a dashed line.

[0053] Figure 4A and Figure 4B Examples of a range of logic design rules that can be used in the design and manufacture of semiconductor devices as standard units are shown. Figure 4A An aspect of an exemplary standard unit 250 including three OD 108s is shown, and Figure 4B Another standard cell 252, comprising two OD 108s, is shown. The logic design rules applied to standard cells 250 and 252 may include the number of OD 108s. Furthermore, the logic design rules may define the relative dimensions of the OD 108s. For example, Figure 4AThe standard cell 250 shown is situated between two smaller ODs 108 as a large OD 108. Other logic design rules can define the cell heights for the standard cells 250 and 252. For example, in some embodiments, the logic design rules can define the cell heights 260 and 262 of the respective standard cells 250 and 252 to be between 10 nm and 400 nm. Other logic design rules can define the contact polycrystalline pitch (CPP) 264 to be between 20 nm and 100 nm.

[0054] Figure 5 Examples of other design rules that can be applied to semiconductor device 200 are shown. For clarity, Figure 5 The semiconductor device 200 shown includes a plurality of metal layers O (MO) conductors shown separated from the semiconductor device 200. The nanosheet semiconductor device 200 includes a substrate 202, which may be one or more of bulk silicon, a semiconductor wafer, a silicon-on-insulator (SOI) substrate, or a silicon-germanium substrate. The device 200 shown includes having… Figure 1A The capacitor 102 shown has an OD region 108 and has Figure 1C The capacitor 132 shown has an STI 132. As discussed above, device 200 therefore includes an OD 108 without an EPI, separated by an STI 138. In addition to VG 220 and VD 222, Figure 5 The example shown includes a through-hole (VD2) 224 connecting the M0 conductor, as illustrated.

[0055] Logical design rules can limit the width used for M0 metal tracks. For example, such as... Figure 5 As shown, the power / ground M0 rail can have a width of 8nm-50nm. Other M0 rails, such as signal metal rails, can have a width of 4nm-30nm. The number of M0 rails is unlimited.

[0056] Figure 6 The diagram illustrates a semiconductor manufacturing method 600. Figures 7A to 7H It is based on Figure 6The diagram shows views of the semiconductor device 100 at various stages of method 600. As with other method implementations and exemplary devices discussed herein, it should be understood that portions of the semiconductor device 100 can be fabricated using CMOS technology processes, and therefore only some processes are briefly described herein. Furthermore, the exemplary semiconductor device may include various other devices and components, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random access memory (SRAM), and / or other logic circuits, but simplification is provided for a better understanding of the inventive concept. In some embodiments, the exemplary device includes multiple semiconductor devices (e.g., transistors), including interconnectable PFETs, NFETs, etc. Furthermore, it should be noted that the process steps of method 600 (including references to…) Figures 7A to 7H Any descriptions given are, as are the remainder of the methods and exemplary figures provided in this invention, merely exemplary and not intended to be limiting.

[0057] In stage 602, a substrate is provided. (Reference) Figure 7A Examples include a substrate 202. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon substrate. Substrate 202 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 202 may include various doping configurations, depending on design requirements. For example, different doping profiles (e.g., n-wells, p-wells) may be formed in regions on substrate 202 designed for different device types (e.g., n-type field-effect transistors (NFETs), p-type field-effect transistors (PFETs)). Suitable doping may include ion implantation and / or diffusion processes of dopants. Substrate 202 typically has isolation components (e.g., shallow trench isolation (STI) components) between regions providing different device types. Substrate 202 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Optionally, substrate 202 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 202 may optionally include epitaxial layers (epi layers), may be strained for performance enhancement, may include silicon-on-insulator (SOI) structures, and / or have other suitable enhancement components.

[0058] In stage 602, punch-through resistance (APT) implantation may also be performed. APT implantation can be performed in a region located below the channel region of the device, for example, to prevent punch-through or unwanted diffusion. In some embodiments, a first photolithography (photolithography) step is performed to pattern a P-type APT region and a second photolithography step is performed to pattern an N-type APT region. For example, performing the first photolithography step may include forming a photoresist layer over substrate 202, exposing the photoresist to the pattern (e.g., a P-type APT implantation mask), performing a post-exposure baking process, and developing the photoresist to form a patterned photoresist layer. For example, the P-type dopant implanted by an ion implantation process to form the P-type APT region may include boron, aluminum, gallium, indium, or other P-type acceptor materials. Subsequently, the second photolithography step may be performed, which may include forming a photoresist layer over substrate 202, exposing the photoresist to the pattern (e.g., an N-type APT implantation mask), performing a post-exposure baking process, and developing the photoresist to form a patterned photoresist layer. For example, the N-type dopant implanted into the N-type APT region via an ion implantation process may include arsenic, phosphorus, antimony, or other N-type donor materials. Furthermore, in various embodiments, the APT implantation may have, for example, a range of approximately 1 x 10⁻⁶. 18 cm -3 and 1x10 19 cm -3 High dopant concentrations are possible. In some embodiments, such high APT dopant concentrations can be advantageously used, as described below, because an isolation layer subsequently formed above the APT-implanted substrate can serve as a dopant diffusion barrier layer.

[0059] In stage 604, one or more epitaxial layers can then be grown on substrate 202. In an embodiment of stage 604, an epitaxial stack 702 is formed over the APT-implanted substrate 202. The epitaxial stack 702 includes a first-component epitaxial layer 704 inserted by an epitaxial layer 706 of a second component. The first and second components can be different. In one embodiment, epitaxial layer 704 is SiGe and epitaxial layer 706 is silicon. However, other embodiments are also possible, including those that provide a first component and a second component with different oxidation rates. For example, in various embodiments, epitaxial layer 704 has a first oxidation rate, and epitaxial layer 706 has a second oxidation rate less than the first oxidation rate. In some embodiments, epitaxial layer 704 comprises SiGe, and where epitaxial layer 706 comprises Si, the Si oxidation rate of epitaxial layer 706 is less than the SiGe oxidation rate of epitaxial layer 704. During the subsequent oxidation process, as discussed below, a portion of epitaxial layer 704 may be completely oxidized, while only epitaxial layer 706 may remain unoxidized, or in some embodiments, be only slightly oxidized.

[0060] It should be noted that, for ease of reference in subsequent process steps, the bottommost epitaxial layer is designated as 704a. However, in embodiments, epitaxial layer 704a is made of a material substantially similar to epitaxial layer 704b formed above epitaxial layer 704a. In embodiments, epitaxial layer 704a is SiGe and epitaxial layer 704b may also be SiGe. In other embodiments, epitaxial layer 704a has a different composition than epitaxial layers 704b and / or epitaxial layers 706a-706c. The thickness of epitaxial layer 704a may be greater than the thickness of the preceding epitaxial layers 704b-704c.

[0061] Epitaxial layers 706a-706c, or portions thereof, may form the channel region of device 100. For example, epitaxial layers 706a-706c may be referred to as “nanowires” for forming the channel region of multi-gate device 100, such as a GAA device. These “nanowires” are also used to form portions of the source / drain components of multi-gate device 100, as discussed below. Again, as used herein, “nanowire” refers to a cylindrical semiconductor layer as well as other configurations such as stripes. The use of epitaxial layers 706a-706c to define one or more channels of a device is further discussed below.

[0062] It should be pointed out that, Figure 7A The diagram illustrates four (4) layers of each of epitaxial layers 704 (including 704a-704c) and 706, which are for illustrative purposes only and are not intended to limit the scope beyond what is specifically stated in the claims. It should be understood that any number of epitaxial layers may be formed in the epitaxial stack 702; the number of layers depends on the desired number of channel regions for device 100. In some embodiments, the number of epitaxial layers 704 is between 2 and 10.

[0063] In some embodiments, epitaxial layer 704 has a thickness ranging from about 2 to 6 nanometers (nm). Epitaxial layers 704b-704c (provided above layer 704a) can have substantially uniform thickness. In some embodiments, epitaxial layer 704a has a thickness of about 8 to 15 nm. In some embodiments, epitaxial layer 706 has a thickness ranging from about 6 to 12 nm. In some embodiments, the thickness of epitaxial layer 706 in the stack is substantially uniform. As described in more detail below, epitaxial layer 706 can be used as a channel region for subsequently formed multi-gate devices, and its thickness is selected based on device performance considerations. Epitaxial layer 704 can be used to define the gap distance between adjacent channel regions for subsequently formed multi-gate devices, and its thickness is selected based on device performance considerations.

[0064] For example, the epitaxial growth of the layers of stack 702 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxially grown layer, such as layer 706, comprises the same material as the substrate 202. In some embodiments, the epitaxially grown layers 704 and 706 comprise a different material from the substrate 202. As described above, in at least some instances, epitaxial layer 704 comprises an epitaxially grown silicon-germanium (SiGe) layer and epitaxial layer 706 comprises an epitaxially grown silicon (Si) layer. In some embodiments, epitaxial layer 704a is also SiGe. Optionally, in some embodiments, either of the epitaxial layers 704 and 706 may include: other materials, such as germanium; compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, and / or GaInAsP; or combinations thereof. As discussed, the materials of the epitaxial layers 704 and 706 can be selected based on providing different oxidation and etch selectivity characteristics. In various embodiments, the epitaxial layers 704 and 706 are substantially dopant-free (i.e., having a dopant content from 0 cm⁻¹). -3 To approximately 1x10 17 cm -3 The non-inherent dopant concentration, where, for example, no intentional doping is performed during the epitaxial growth process.

[0065] Also Figure 7A As shown in the examples, a hard mask (HM) layer 704d may be formed over the epitaxial stack 702. In some embodiments, the HM layer 704d includes an oxide layer (e.g., a pad oxide layer that may include SiO2) and a nitride layer formed over the oxide layer (e.g., a pad nitride layer that may include Si3N4). In some embodiments, the HM layer 704d includes thermally grown oxide, CVD-deposited oxide, and / or ALD-deposited oxide. In some embodiments, the HM layer 704d includes a nitride layer deposited by CVD or other suitable techniques. The HM layer 704d may be used to protect portions of the substrate 202 and / or the epitaxial stack 702 and / or to define patterns (e.g., fin elements).

[0066] In stage 606, the fin elements are patterned and formed. (See reference) Figure 7B In some embodiments, a plurality of fin elements 708a-708b are formed extending from the substrate 202. In various embodiments, each of the fin elements 708 includes a substrate portion formed by the substrate 202, a portion of each of the epitaxial layers 702 including epitaxial layers 704 and 706, and an HM layer portion from the HM layer 704d.

[0067] Fin 708 can be fabricated using suitable processes including photolithography and etching. The photolithography process can be performed over substrate 202 (e.g., on...). Figure 7B A photoresist layer is formed above the HM layer 704d, the resist is exposed to the pattern, a post-exposure baking process is performed, and the resist is developed to form a masking element including the resist. In some embodiments, an electron beam lithography process can be used to pattern the resist to form the masking element. The masking element can then be used to protect areas of the substrate 202 and the layers formed thereon, while an etching process forms trenches 710 in the unprotected areas, through the HM layer 704d, through the epitaxial stack 702, and into the substrate 202, thereby leaving a plurality of extending fins 708. The trenches 710 can be etched using dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes.

[0068] Many other embodiments of the method of forming fins on a substrate can also be used, including, for example, defining a fin region (e.g., by means of a mask or isolation region) and epitaxially growing an epitaxial stack 702 in the form of fin 708. In some embodiments, forming fin 708 may include a trimming process to reduce the width of fin 708. The trimming process may include a wet etching process or a dry etching process.

[0069] In stage 608, an oxidation process can be performed to form an isolation region within the fin element. In an embodiment of stage 608, device 100 is exposed to an oxidation process that completely oxidizes the epitaxial layer portion 704a of each of the plurality of fin elements 708. The epitaxial layer portion 704a is transformed into an oxide layer that provides the isolation region / layer. In some embodiments, the oxide layer has a thickness ranging from about 5 to about 25 nanometers (nm). In embodiments, the oxide layer may include silicon germanium oxide (SiGeO). x ).

[0070] The oxidation process in stage 608 may include forming and patterning various masking layers to control the oxidation of the epitaxial layer 704a. In other embodiments, the oxidation process is selective oxidation due to the composition of the epitaxial layer 704a. In some instances, the oxidation process may be carried out by exposing device 100 to a wet oxidation process, a dry oxidation process, or a combination thereof. In at least some embodiments, device 100 is exposed to a wet oxidation process using water vapor or steam as an oxidant at a pressure of about 1 ATM, at a temperature range of about 400-600 degrees Celsius, and for a duration of about 0.5-2 hours. It should be noted that the oxidation process conditions provided herein are exemplary only and are not intended to be limiting.

[0071] As described above, in some embodiments, the first epitaxial layer portion 704a may include a material having a first oxidation rate, and the second epitaxial layer portion 706 may include a material having a second oxidation rate less than the first oxidation rate. For example, in an embodiment where the first epitaxial layer portion 704a includes SiGe and the second epitaxial layer portion 706 includes Si, the faster SiGe oxidation rate (i.e., compared to Si) ensures that the SiGe layer (i.e., epitaxial layer portion 704a) becomes fully oxidized, while minimizing or eliminating oxidation of the other epitaxial layers 704. It should be understood that any of the various materials discussed above can be used for each selection of the first and second epitaxial layer portions to provide different suitable oxidation rates.

[0072] The resulting oxide layer of each fin element 708 can act as a diffusion barrier against APT dopant previously implanted into substrate 202, and it can be present in substrate 202 directly beneath the oxide layer. Therefore, in various embodiments, the oxide layer serves to prevent APT dopant within substrate portion 202 from diffusing into, for example, the epitaxial layer 706 above, which can be used as a channel region for subsequently formed multi-gate devices. In other embodiments, the oxide layer is omitted.

[0073] Method 600 then proceeds to stage 610, in which shallow trench isolation (STI) components are formed between the fin elements. (See reference) Figure 7C In some embodiments, the STI component 712 is disposed between fins 708. For example, in some implementations, a dielectric layer is first deposited over the substrate 202, filling the trench 710 with the dielectric material. In some implementations, the dielectric layer may include SiO2, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectrics, combinations thereof, and / or other suitable materials known in the art. In various examples, the dielectric layer may be deposited using CVD processes, subatmospheric pressure CVD (SACVD) processes, flowable CVD processes, ALD processes, PVD processes, and / or other suitable processes. In some implementations, after depositing the dielectric layer, the device 100 may be annealed, for example, to improve the quality of the dielectric layer. In some implementations, the dielectric layer (and the subsequently formed STI component 712) may include a multilayer structure, for example, having one or more pad layers.

[0074] In the formation of an STI component, after depositing a dielectric layer, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The CMP process can planarize the top surface to form the STI component 712. (Example...) Figure 7CAs shown, in some embodiments, the CMP process used to planarize the top surface of device 100 and form STI component 712 can also be used to remove the HM layer 704d from each of the plurality of fin elements 708. In some embodiments, the removal of the HM layer 704d can be carried out alternately by using a suitable etching process (e.g., dry etching or wet etching).

[0075] The STI component between the fin elements is recessed. (Reference) Figure 7C In one example, the STI component 712 is recessed, providing a fin 708 extending above the STI component 712. In some embodiments, the recessing process may include dry etching, wet etching, and / or combinations thereof. In some embodiments, the recess depth is controlled (e.g., by controlling the etching time) to produce a desired height of the exposed upper portion of the fin element 708. This height exposes each layer of the epitaxial stack 702. The recess of the STI component 712 may be substantially coplanar with the top surface of the isolation region; in other embodiments, this may not be necessary.

[0076] In stage 612, a sacrificial layer / component may be formed. In some embodiments, a pseudo-dielectric layer and / or gate structure may be formed. For example, stage 612 may include pseudo-oxide deposition followed by a gate structure. While this discussion relates to a replacement gate process, thereby forming and subsequently replacing the gate structure, other configurations are possible.

[0077] Now for reference Figure 7C In a further embodiment of stage 612, the fabrication and processing of the gate stack are carried out. Using... Figure 7C An example is formed by creating a gate stack 714. The gate stack 714, or a portion thereof, may be a high-k / metal gate stack. In some embodiments, the gate stack 714 is formed over the substrate 202 and at least partially disposed over the fin element 708. The portion of the fin element 708 located below the gate stack 714 may be referred to as a channel region. The gate stack 714 may also define source / drain regions of the fin element 708, for example, regions of the fin and epitaxial stack 702 adjacent to and located on opposite sides of the channel region.

[0078] In some embodiments, the gate stack 714 may include, but is not limited to, one or more of a dielectric layer, an electrode layer 716, and a hard mask 720, the hard mask 720 comprising multiple layers (e.g., oxide layers and nitride layers). In some embodiments, the dielectric layer is not included in the gate stack 714, for example, it is removed before the gate stack 714 is deposited. In some embodiments, an additional gate dielectric layer is included in the gate stack as a complement to or replacement of the dielectric layer. In some embodiments, the gate stack 714 is formed by various process steps, such as layer deposition, patterning, etching, and other suitable processing steps. Exemplary layer deposition processes include CVD (including low-pressure CVD and plasma-enhanced CVD), PVD, ALD, thermal oxidation, electron beam evaporation, or other suitable deposition techniques or combinations thereof. For example, in forming a gate stack, the patterning process includes a photolithography process (e.g., photolithography or electron beam lithography), which may further include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable photolithography techniques and / or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching and / or other etching methods.

[0079] As noted above, the gate stack 714 may include an additional gate dielectric layer. For example, the gate stack 714 may include silicon oxide. Optionally or additionally, the gate dielectric layer of the gate stack 714 may include silicon nitride, a high-k dielectric material, or other suitable materials. In some embodiments, the electrode layer 716 of the gate stack 714 may include polysilicon. In some embodiments, the hard mask layer 720 includes an oxide layer, for example, a pad oxide layer that may include SiO2. In some embodiments, the hard mask layer 720 includes a nitride layer, such as a pad nitride layer, which may include Si3N4, silicon oxynitride, or optionally silicon carbide. In some embodiments, after the gate 714 is formed, the dielectric layer is removed from the substrate, including exposed areas of the fin 708 not covered by the gate 714.

[0080] In stage 614, a selected epitaxial layer of the epitaxial stack can be removed from the source / drain region of the fin (e.g., the region of the fin adjacent to the channel region below the gate stack). Epitaxial layer 704 has been removed from the substrate 202 in the source / drain region of the fin 708, as... Figure 7DAs shown in the diagram. Furthermore, gaps 722 may be formed at the locations of the epitaxial layer 704. These gaps 722 may be filled with the surrounding environment (e.g., air, N2). In embodiments, the epitaxial layer 704 is removed by a selective wet etching process. In some embodiments, selective wet etching includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some embodiments, selective removal includes SiGe oxidation followed by SiGeO. x Removal. For example, oxidation can be provided by cleaning with O3, and then SiGeO can be provided by an etchant such as NH4OH. x Removal. In this embodiment, epitaxial layer 704 is SiGe and epitaxial layer 706 is silicon that allows for selective removal of epitaxial layer 704.

[0081] In stage 616, spacer layers 718 / 724 can then be deposited on the substrate. Spacer layers 718 / 724 can be conformal dielectric layers formed on the substrate. Spacer layers 718 / 724 can form spacer elements 724 on the sidewalls of the gate structure. Spacer layers 718 / 724 can also fill gaps 722 provided by removing the epitaxial layers described in stage 614 above. Spacer layers 718 / 724 are disposed on substrate 202, including gaps 722 between epitaxial layers filling the source / drain regions of the fin element 708.

[0082] Spacer layers 718 / 724 may include dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, spacer layers 718 / 724 include multiple layers, such as primary spacer walls, liner layers, etc. For example, spacer layers 718 / 724 may be formed by depositing dielectric material over gate stack 714 using processes such as CVD, subatmospheric pressure CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes. In some embodiments, deposition may be followed by etch-back (e.g., anisotropic) of the dielectric material. In some embodiments, an ion implantation process may be performed to form lightly doped drain (LDD) components within semiconductor device 100 prior to forming sidewall spacers 718 / 724.

[0083] In some embodiments, after the spacer layers 718 / 724 are formed, the spacer layers 718 / 724 may be etched back to expose portions of the fin element 708 adjacent to and not covered by the gate structure 714 (e.g., source / drain regions). The spacer layer material may remain on the sidewalls of the gate structure 714 to form the spacer element. In some embodiments, the etch-back of the spacer layers 718 / 724 may include wet etching, dry etching, multi-step etching, and / or combinations thereof. Although the spacer layers 718 / 724 can be removed from the top surface and sides of the exposed epitaxial stack 702, as... Figure 7C As shown, the spacer layer 724 is held between the epitaxial layers 706 of the epitaxial stack 702 in the source / drain regions. The thickness of the spacer layer 724 between the epitaxial layers 706 can be between approximately 2-6 nm.

[0084] In stage 618, method 600 abandons the construction of the source / drain components. In previous device formation, the source / drain components would be formed by performing an epitaxial growth process that provides epitaxial material covering a portion of the epitaxial layer retained in the source / drain regions of the fin. However, this part of the process is not completed when forming the VMOM capacitor. Therefore, in region 726, instead of EPI filling between gate structures 714a, 714b, there is no gap. Since there is no EPI, the VMOM capacitor can be formed in region 726. Furthermore, no additional mask is needed to form this gap in region 726 because EPI growth in region 726 is simply prevented.

[0085] Then method 600 proceeds to stage 620, in which oxide diffusion (OD) dielectric 108 is formed. (See reference) Figure 7FIn some embodiments, OD 108 is formed over substrate 202. In some embodiments, a contact etch stop layer (CESL) is also formed over substrate 202 prior to the formation of OD 108. In some instances, CESL comprises a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art. CESL can be formed using plasma-enhanced chemical vapor deposition (PECVD) and / or other suitable deposition or oxidation processes. OD 108 can be, but is not limited to, one or more of tetraethyl orthosilicate (TEOS) oxide, doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG)), other materials with high dielectric constants (e.g., Ta2O5, HfO2, SrTiO3, PbTiO3, KNO3, and / or Al2O3), and / or other suitable dielectric materials. OD 108 can be deposited using PECVD or other suitable deposition techniques. In some implementations, after forming OD 108, the semiconductor device 100 may undergo a high thermal budget process to anneal the OD layer. As described above, during such a high thermal budget process, the insulating layer can prevent some potential diffusion of APT dopants from the substrate region to the device channel region.

[0086] In some instances, a planarization process may be performed after depositing the OD (and / or CESL) to expose the top surface 728 of the OD 108. For example, the planarization process includes a chemical mechanical planarization (CMP) process, which removes the portion of the OD 108 (and the CESL layer, if present) located above the gate stack 714 and planarizes the top surface of the semiconductor device 100.

[0087] Method 600 then proceeds to stage 622, in which selective removal of OD 108 is provided in region 726 between gate structures 714a, 714b of the device. In one embodiment, a portion of OD 108 is removed downwards to the fin element, forming a trench. (See reference...) Figure 7H For example, OD 108 is removed from region 726. In some embodiments, OD 108 is removed by a selective wet etching process. In some embodiments, selective wet etching includes HF.

[0088] In stage 624, MD 104 is formed in the trench created in stage 622. MD 104 can be one of the terminals of a VMOM capacitor. MD 104 can be a metal deposition formed from various metals, such as Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metallic materials, or combinations thereof. Reference Figure 7H In an example, in the embodiment of stage 624, MD 104 is formed within trench 730 of device 100. The metal deposition used within MD 104 may include metal, metal alloy, or metal silicide. Furthermore, the formation of MD 104 may include deposition to form various structures, one or more pad layers, and one or more CMP processes to remove excess material and thereby planarize the top surface of semiconductor device 100. In various embodiments, MD 104 may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Furthermore, MD 104 may be formed for N-FET and P-FET transistors using different metal layers, respectively.

[0089] Device 100 can be implemented as a VMOM capacitor device, with MD 104 and gate structure 714 formed on the side of OD 108 to form the terminals of the VMOM capacitor. VMOM capacitor device 100 in Figure 7H The VMOM capacitor device 100 can be further processed to form various components and regions known in the art. For example, subsequent processing may form contact openings, contact metals, and various contacts / vias / lines and multilayer interconnects (e.g., metal layers and interlayer dielectrics) on substrate 202, configured to connect the various components to form a functional VMOM capacitor, which may include two or more terminals, including, for example, MD 104 and gate structure 714. In a further example, the multilayer interconnects may include vertical interconnects such as vias or contacts and horizontal interconnects such as metal lines. The various interconnect components may be made of various conductive materials, including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes are used to form copper-associated multilayer interconnect structures. Furthermore, additional process steps may be performed before, during, and after method 600, and some of the process steps described above may be replaced or eliminated according to various embodiments of method 600.

[0090] Furthermore, the present invention therefore provides a capacitor in a nanosheet structure. The capacitor is formed on an OD (Operational Device) or an OD without EPI (Electronic Particulate Injection) in the nanosheet structure. The disclosed capacitor can be formed without the need for an additional mask, thereby reducing cost and complexity, as well as reducing the required die area. The disclosed capacitor exhibits low leakage and high capacitance density.

[0091] Therefore, aspects of the present invention include a device comprising a substrate and a first nanosheet structure and a second nanosheet structure disposed on the substrate. Each of the first and second nanosheet structures has at least one nanosheet forming a source / drain region and a gate structure including a conductive gate contact. A first oxide structure is disposed on the substrate between the first and second nanosheet structures. A conductive terminal is disposed in or on the first oxide structure. The conductive terminal, the first oxide structure, and the gate structure of the first nanosheet structure define a capacitor.

[0092] Another aspect of the invention includes a device having a first nanosheet structure, the first nanosheet structure comprising at least one nanosheet forming a source / drain region and a gate structure including a conductive gate contact. An oxide structure without p-type epitaxy (P-EPI) or n-type epitaxy (N-EPI) in or on the oxide structure is provided. Conductive terminals are disposed in or on the oxide structure. The conductive terminals, the oxide structure, and the gate structure of the first nanosheet structure form a first capacitor.

[0093] Other aspects of the invention include a method in which a fin element is patterned from an epitaxial stack. A gate structure is formed over the fin element, and an OD is formed adjacent to the gate structure. An MD is formed within the OD. The gate structure is connected as a first terminal of a VMOM capacitor, and the MD is connected as a second terminal of a VMOM capacitor, wherein the OD is the dielectric between the gate structure and the MD.

[0094] Some embodiments of this application provide a semiconductor device, including: a substrate; a first nanosheet structure and a second nanosheet structure disposed on the substrate, each of the first nanosheet structure and the second nanosheet structure including: at least one nanosheet forming a source / drain region; a gate structure including a conductive gate contact; a first oxide structure disposed on the substrate between the first nanosheet structure and the second nanosheet structure; and a conductive terminal disposed in or on the first oxide structure; wherein the conductive terminal, the first oxide structure, and the gate structure of the first nanosheet structure define a capacitor.

[0095] In some embodiments, there is no epitaxial growth (EPI) in or on the first oxide structure. In some embodiments, there is no N-type epitaxial growth (N-EPI) in or on the first oxide structure. In some embodiments, there is no P-type epitaxial growth (P-EPI) in or on the first oxide structure. In some embodiments, the semiconductor device further includes: a third nanosheet structure disposed on the substrate; and a shallow trench isolation (STI) separating the first nanosheet structure and the third nanosheet structure. In some embodiments, the conductive terminal, the shallow trench isolation, and the gate structure of the first nanosheet structure define a second capacitor. In some embodiments, the conductive terminal, the gate structure of the first oxide structure, and the second nanosheet structure define a second capacitor. In some embodiments, the conductive terminal, the shallow trench isolation, and the gate structure of the second nanosheet structure define a third capacitor. In some embodiments, the conductive terminal comprises a metal. In some embodiments, each of the gate structures of the first nanosheet structure and the second nanosheet structure comprises polycrystalline silicon (PO). In some embodiments, a first depth of the conductive terminal in oxide diffusion (OD) is deeper than a second depth of metal diffusion (MD) in the shallow trench isolation. In some embodiments, the first depth is more than twice the second depth. In some embodiments, the capacitor formed by the gate structure of the conductive terminals, the first oxide structure, and the first nanosheet structure defines a standard cell. In some embodiments, the capacitor formed by the gate structure of the conductive terminals, the first oxide structure, and the first nanosheet structure is designed according to logic rules. In some embodiments, the semiconductor device further includes a second oxide structure disposed on the substrate adjacent to the third nanosheet structure, wherein a first width of the first oxide structure is wider than a second width of the second oxide structure. In some embodiments, the gate structure includes a gate stack that surrounds all sides of the source / drain regions to form a gate all-around (GAA) structure.

[0096] Other embodiments of this application also provide a semiconductor device, comprising: a first nanosheet structure including at least one nanosheet forming a source / drain region and a gate structure including a conductive gate contact; an oxide structure, wherein there is no p-type epitaxy (P-EPI) or n-type epitaxy (N-EPI) in or on the oxide structure; and a conductive terminal disposed in or on the oxide structure; wherein the conductive terminal, the oxide structure, and the gate structure of the first nanosheet structure form a first capacitor.

[0097] In some embodiments, the semiconductor device further includes: a second nanosheet structure comprising at least one nanosheet forming a source / drain region and a gate structure including a conductive gate contact; wherein the oxide structure is disposed between the first nanosheet structure and the second nanosheet structure; wherein the conductive terminal, the oxide structure, and the gate structure of the second nanosheet structure define a second capacitor.

[0098] Other embodiments of this application provide a method for forming a semiconductor device, including: patterning fin elements from an epitaxial stack; forming a gate structure over the fin elements; forming an oxide diffusion (OD) adjacent to the gate structure; forming a metal diffusion (MD) within the oxide diffusion; connecting the gate structure as a first terminal of a vertical metal-oxide-metal (VMOM) capacitor; and connecting the metal diffusion as a second terminal of the vertical metal-oxide-metal capacitor, wherein the oxide diffusion is a dielectric between the gate structure and the metal diffusion.

[0099] In some embodiments, the method further includes: abandoning the use of epitaxial growth to form source / drain components to allow the formation of the vertical metal-oxide-metal capacitor.

[0100] The foregoing outlines features of several examples to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the examples described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor device, comprising: Substrate; A first nanosheet structure and a second nanosheet structure are disposed on the substrate. Each of the first nanosheet structure and the second nanosheet structure includes: at least one nanosheet and a gate structure, wherein the at least one nanosheet forms a source / drain region and the gate structure includes a conductive gate contact. A first oxide structure is disposed on the substrate between the source / drain region of the first nanosheet structure and the source / drain region of the second nanosheet structure; and Conductive terminals are disposed in and on the first oxide structure; The gate structure of the conductive terminal, the first oxide structure, and the first nanosheet structure defines a capacitor.

2. The semiconductor device according to claim 1, wherein, There is no source / drain epitaxy (EPI) in or on the first oxide structure.

3. The semiconductor device according to claim 2, wherein, There is no N-type source / drain epitaxy (N-EPI) in or on the first oxide structure.

4. The semiconductor device according to claim 2, wherein, There is no P-type source / drain epitaxy (P-EPI) in or on the first oxide structure.

5. The semiconductor device according to claim 1, further comprising: A third nanosheet structure is disposed on the substrate; as well as Shallow trench isolation (STI) separates the first nanosheet structure and the third nanosheet structure.

6. The semiconductor device according to claim 5, wherein, The conductive terminal, the shallow trench isolation, and the gate structure of the first nanosheet structure define a second capacitor.

7. The semiconductor device according to claim 5, wherein, The gate structure comprising the conductive terminal, the first oxide structure, and the second nanosheet structure defines a second capacitor.

8. The semiconductor device according to claim 6, wherein, The conductive terminal, the shallow trench isolation, and the gate structure of the second nanosheet structure define a third capacitor.

9. The semiconductor device according to claim 1, wherein, The conductive terminal comprises metal.

10. The semiconductor device according to claim 1, wherein, The gate structure of both the first nanosheet structure and the second nanosheet structure comprises polycrystalline silicon (PO).

11. The semiconductor device according to claim 6, wherein, The first depth of the conductive terminal in the first oxide structure is deeper than the second depth of the conductive terminal in the shallow trench isolation.

12. The semiconductor device according to claim 11, wherein, The first depth is more than twice the second depth.

13. The semiconductor device according to claim 1, wherein, The capacitor, formed by the gate structure of the conductive terminal, the first oxide structure, and the first nanosheet structure, defines a standard cell.

14. The semiconductor device according to claim 1, wherein, The capacitor formed by the gate structure of the conductive terminal, the first oxide structure, and the first nanosheet structure is designed according to logic rules.

15. The semiconductor device according to claim 1, further comprising: A second oxide structure is disposed on the substrate adjacent to the second nanosheet structure, wherein the first width of the first oxide structure is wider than the second width of the second oxide structure.

16. The semiconductor device according to claim 1, wherein, The gate structure includes a gate stack that encloses all sides of the source / drain regions to form a gate all-around (GAA) structure.

17. A semiconductor device, comprising: The first nanosheet structure includes at least one nanosheet forming a source / drain region and a gate structure containing a conductive gate contact. An oxide structure laterally adjacent to the source / drain region of the at least one nanosheet, wherein there is no p-type epitaxy (P-EPI) or n-type epitaxy (N-EPI) in or on the oxide structure; and Conductive terminals are disposed in and on the oxide structure; The conductive terminal, the oxide structure, and the gate structure of the first nanosheet structure form a first capacitor.

18. The semiconductor device of claim 17, further comprising: The second nanosheet structure includes at least one nanosheet forming a source / drain region and a gate structure containing conductive gate contacts; The oxide structure is disposed between the first nanosheet structure and the second nanosheet structure; The gate structure of the conductive terminal, the oxide structure, and the second nanosheet structure defines a second capacitor.

19. A method of forming a semiconductor device, comprising: A first nanosheet structure and a second nanosheet structure are formed on a substrate, each of the first nanosheet structure and the second nanosheet structure comprising: at least one nanosheet and a gate structure, the at least one nanosheet forming a source / drain region, and the gate structure comprising a conductive gate contact. Oxide diffusion (OD) is formed on the substrate between the source / drain regions of the first nanosheet structure and the source / drain regions of the second nanosheet structure. Metal diffusion (MD) is formed within the oxide diffusion. The gate structure is connected as the first terminal of a vertical metal-oxide-metal (VMOM) capacitor; and The metal diffusion is connected as the second terminal of the vertical metal-oxide-metal capacitor, wherein the oxide diffusion is the dielectric between the gate structure and the metal diffusion.

20. The method of claim 19, further comprising: A spacer layer is formed between the vertically adjacent source / drain components.

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