Trench-type semiconductor device and method of manufacturing the same

Abstract

The present disclosure relates to a trench type semiconductor device and a manufacturing method thereof. The semiconductor device comprises a substrate (101), an epitaxial layer (102), a well region layer (103), a potential well layer (104), a potential barrier layer (105), an insulating gate dielectric layer (106), a gate electrode layer (108), an interlayer dielectric (ILD) layer (109), a source electrode layer (110), and a drain electrode layer (111). The polarization effect of the potential well layer (104) and the potential barrier layer (105) forms a 2DEG or 2DHG at the interface. The trench type semiconductor device uses the 2DEG or 2DHG formed by the heterojunction as the channel carrier. The interface between the potential well layer and the potential barrier layer is parallel to the direction of the gate electrode layer pointing to the drain electrode layer, so that the trench structure size is smaller, and the high carrier mobility of the 2DEG or 2DHG is added, thereby improving the cell power density and further reducing the on-resistance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor device manufacturing technology, and more specifically, to a trench semiconductor device and a method for manufacturing the same. Background Technology

[0002] Two-dimensional electron gas (2DEG) and two-dimensional hole gas (2DHG) are generally formed by the polarization effect of heterojunctions. This avoids large Coulomb scattering of charge carriers caused by a large number of ionized donors or acceptors introduced by doping, thus resulting in higher carrier mobility. This allows heterojunction semiconductor devices to provide larger current density, higher power density, and better high-frequency characteristics.

[0003] In related technologies, devices with 2DEG or 2DHG still have problems such as low withstand voltage and large reverse leakage current, and they have certain limitations in terms of device size and device performance. Summary of the Invention

[0004] The purpose of this disclosure is to provide a reliable and efficient trench semiconductor device and a method for manufacturing the same. This disclosure does not limit the materials used to form the heterojunction semiconductor of 2DEG or 2DHG; for example, GaN can be used.

[0005] To achieve the above objectives, this disclosure provides a trench semiconductor device that utilizes a 2DEG or 2DHG formed by a heterojunction as the channel carrier. The trench semiconductor device includes a substrate of a first conductivity type, an epitaxial layer of the first conductivity type, a well layer of a second conductivity type, a potential well layer, a barrier layer, an insulating gate dielectric layer, a gate electrode layer, an interlayer dielectric (ILD) layer, a source layer, and a drain layer. The interface between the potential well layer and the barrier layer is parallel to the direction from the gate electrode layer to the drain layer.

[0006] Optionally, the trench semiconductor device further includes a gate control layer deposited between the barrier layer and the gate electrode layer. If the gate control layer is of a first conductivity type, the trench semiconductor device is depletion-mode; if the gate control layer is of a second conductivity type, the trench semiconductor device is enhancement-mode.

[0007] Optionally, the well region layer, the potential well layer, the potential barrier layer, and the insulating gate dielectric layer are all deposited on the epitaxial layer.

[0008] A trench is formed by the barrier layer and the epitaxial layer, an insulating gate dielectric layer is deposited at the bottom of the trench, a gate control layer is deposited on the sidewall of the trench, the insulating gate dielectric layer separates the gate control layer and the epitaxial layer, and a gate electrode layer is deposited in the trench.

[0009] The ILD layer covers a portion of the barrier layer, the gate control layer, and the gate electrode layer, while the source layer covers another portion of the barrier layer, the well layer, the potential well layer, and the ILD layer.

[0010] Optionally, the width of the potential well layer is greater than 1 μm.

[0011] Optionally, the thickness of the barrier layer is 0.005 μm to 5 μm.

[0012] This disclosure also provides a method for manufacturing a trench semiconductor device, the method comprising:

[0013] Deposit an epitaxial layer on the substrate;

[0014] A trap region layer is formed by etching the epitaxial layer or by ion implantation.

[0015] A potential well layer and a potential barrier layer are formed by etching on the epitaxial layer;

[0016] An insulating gate dielectric layer, a gate electrode layer, an interlayer dielectric (ILD) layer, a source layer, and a drain layer are deposited sequentially, such that the interface between the potential well layer and the potential barrier layer is parallel to the direction from the gate electrode layer to the drain layer, and the interface between the potential well layer and the potential barrier layer forms a 2DEG or 2DHG.

[0017] Optionally, an insulating gate dielectric layer, a gate electrode layer, an interlayer dielectric (ILD) layer, a source layer, and a drain layer are deposited sequentially, including:

[0018] An insulating gate dielectric layer, a gate control layer, a gate electrode layer, an interlayer dielectric (ILD) layer, a source layer, and a drain layer are deposited sequentially. If the gate control layer is of a first conductivity type, the trench semiconductor device is a depletion type; if the gate control layer is of a second conductivity type, the trench semiconductor device is an enhancement type.

[0019] Optionally, etching an epitaxial well layer and a barrier layer on the epitaxial layer includes:

[0020] The potential well layer is deposited on the epitaxial layer such that the potential well layer partially covers the epitaxial layer; the barrier layer is deposited on the epitaxial layer such that the barrier layer partially covers the epitaxial layer, such that the interface between the potential well layer and the barrier layer is perpendicular to the plane extending from the substrate and the epitaxial layer, and the barrier layer and the epitaxial layer form a trench.

[0021] The following layers are deposited sequentially: an insulating gate dielectric layer, a gate control layer, a gate electrode layer, an interlayer dielectric (ILD) layer, a source layer, and a drain layer, including:

[0022] The insulating gate dielectric layer is deposited at the bottom of the trench, and the gate control layer is deposited on the sidewall of the trench, wherein the gate control layer may or may not cover the insulating gate dielectric layer, and the insulating gate dielectric layer separates the gate control layer from the epitaxial layer;

[0023] Deposit the gate electrode layer in the trench;

[0024] The ILD layer is deposited to cover a portion of the barrier layer, the gate control layer, and the gate electrode layer;

[0025] Deposit the source layer to cover another portion of the barrier layer, the well layer, the potential well layer, and the ILD layer;

[0026] Deposit the source layer;

[0027] The drain layer is deposited beneath the substrate.

[0028] Optionally, the width of the potential well layer is greater than 1 μm.

[0029] Optionally, the thickness of the barrier layer is 0.005 μm to 5 μm.

[0030] The above technical solution ensures that the interface between the well layer and the barrier layer is parallel to the direction from the gate electrode layer to the drain layer, resulting in a smaller trench structure size. Combined with the high carrier mobility of 2DEG or 2DHG, this improves the cell power density and further reduces the on-resistance. Under reverse conditions, it can also reduce the thickness of the drift region to some extent, thereby lowering the on-resistance.

[0031] Other features and advantages of this disclosure will be described in detail in the following detailed description section. Attached Figure Description

[0032] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the following detailed description to explain the present disclosure, but do not constitute a limitation thereof. In the drawings:

[0033] Figure 1 This is a schematic diagram of the structure of a trench semiconductor device provided in an exemplary embodiment;

[0034] Figure 2 This is a flowchart of a method for manufacturing a trench semiconductor device provided in an exemplary embodiment;

[0035] Figures 3a-3j This is a schematic diagram illustrating the manufacturing steps of a trench semiconductor device provided in an exemplary embodiment.

[0036] Explanation of reference numerals in the attached figures

[0037] 101 Substrate; 102 Epitaxial layer; 103 Well region layer

[0038] 104 Potential well layer 105 Potential barrier layer 106 Insulating gate dielectric layer

[0039] 107 Gate control layer 108 Gate electrode layer 109 ILD layer

[0040] 110 Source layer 111 Drain layer Detailed Implementation

[0041] The specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit this disclosure.

[0042] In this disclosure, unless otherwise stated, directional terms such as "up," "down," "horizontal," and "vertical" are generally used relative to the direction of the semiconductor chip manufacturing process.

[0043] Figure 1 This is a schematic diagram of a trench semiconductor device provided in an exemplary embodiment. This trench semiconductor device utilizes a 2DEG or 2DHG formed by a heterojunction as the channel carrier. For example... Figure 1 As shown, the trench semiconductor device may include a substrate 101 of a first conductivity type, an epitaxial layer 102 of a first conductivity type, a well layer 103 of a second conductivity type, a potential well layer 104, a barrier layer 105, an insulating gate dielectric layer 106, a gate electrode layer 108, an interlayer dielectric (ILD) layer 109, a source layer 110, and a drain layer 111. The interface between the potential well layer 104 and the barrier layer 105 forms a 2DEG or 2DHG due to polarization effects. The interface between the potential well layer 104 and the barrier layer 105 is parallel to the direction from the gate electrode layer 108 to the drain layer 111.

[0044] In related technologies, the interface of a 2DEG or 2DHG is parallel to the gate-source interface, referred to in this disclosure as a "vertical structure." In this structure, charge carriers need to pass through the channel and part of the potential well layer, which reduces the carrier mobility to some extent. Figure 1 A trench gate structure perpendicular to the gate-source interface (2DEG or 2DHG) can reduce the channel length and cell size. Under reverse conditions, it can also reduce the thickness of the drift region to a certain extent, thereby reducing the on-resistance and improving device performance.

[0045] exist Figure 1 In one embodiment, the semiconductor device may be depletion-type. In yet another embodiment, as described below... Figure 3j As shown, the trench semiconductor device may further include a gate control layer 107. The gate control layer 107 is deposited between the barrier layer 105 and the gate electrode layer 108. If the gate control layer 107 is of a first conductivity type, the trench semiconductor device is depletion-mode; if the gate control layer 107 is of a second conductivity type, the trench semiconductor device is enhancement-mode.

[0046] In other words, the presence or absence of the gate control layer 107 or its material properties can be used to control whether the semiconductor device is enhancement-mode or depletion-mode.

[0047] exist Figure 3j In the embodiment, the well layer 103, the potential well layer 104, the barrier layer 105 and the insulating gate dielectric layer 106 are all deposited on the epitaxial layer 102.

[0048] A trench is formed by a barrier layer 105 and an epitaxial layer 102. A gate control layer 107 is deposited on the sidewalls of the trench. An insulating gate dielectric layer 106 is deposited at the bottom (or around and at the bottom) of the trench. The insulating gate dielectric layer 106 separates the gate control layer 107 and the epitaxial layer 102. A gate electrode layer 108 is deposited in the trench.

[0049] ILD layer 109 covers a portion of barrier layer 105 and gate electrode layer 108, and source layer 110 covers well layer 103, well layer 104 and ILD layer 109.

[0050] In this process, from the well layer 103 inwards, a potential well layer 104 and a potential barrier layer 105 are sequentially formed on the epitaxial layer 102. The interface between the potential well layer 104 and the potential barrier layer 105 is formed by etching. This interface is vertical and is consistent with the direction from the gate electrode layer 108 to the drain layer 111.

[0051] This disclosure also provides a method for manufacturing a trench semiconductor device. Figure 2 This is a flowchart illustrating a method for manufacturing a trench-type semiconductor device according to an exemplary embodiment. Figure 2 As shown, the method may include the following steps.

[0052] Step S11: Deposit an epitaxial layer 102 on the substrate 101.

[0053] Step S12: Etch epitaxial layer 102 or ion implantation to form trap layer 103.

[0054] Step S13: Etch epitaxial layer 104 and barrier layer 105 on epitaxial layer 102.

[0055] In step S14, an insulating gate dielectric layer 106, a gate electrode layer 108, an ILD layer 109, a source layer 110, and a drain layer 111 are deposited sequentially, such that the interface between the potential well layer 104 and the barrier layer 105 is parallel to the direction from the gate electrode layer 108 to the drain layer 111. The interface between the potential well layer 104 and the barrier layer 105 forms a 2DEG or a 2DHG.

[0056] In one embodiment, the step of sequentially depositing the insulating gate dielectric layer 106, the gate electrode layer 108, the interlayer dielectric ILD layer 109, the source layer 110, and the drain layer 111 (step S14) may include:

[0057] An insulating gate dielectric layer 106, a gate control layer 107, a gate electrode layer 108, an interlayer dielectric (ILD) layer 109, a source layer 110, and a drain layer 111 are deposited sequentially. If the gate control layer 107 is of a first conductivity type, the trench-type semiconductor device is depletion-mode; if the gate control layer 107 is of a second conductivity type, the trench-type semiconductor device is enhancement-mode. In other words, the presence or absence of the gate control layer 107, or its material properties, controls whether the semiconductor device is enhancement-mode or depletion-mode.

[0058] Those skilled in the art will understand that the first conductivity type can be either P-type or N-type, and the second conductivity type can be either P-type or N-type. For example, the first conductivity type is N-type, and the second conductivity type is P-type.

[0059] In yet another embodiment, Figure 2 Based on this, the step of etching the epitaxial layer 102 to form the potential well layer 104 and the barrier layer 105 (step S13) may include:

[0060] A potential well layer 104 is deposited on the epitaxial layer 102 such that the potential well layer 104 partially covers the epitaxial layer 102; a barrier layer 105 is deposited on the epitaxial layer 102 such that the barrier layer 105 partially covers the epitaxial layer 102, such that the interface between the potential well layer 104 and the barrier layer 105 is perpendicular to the plane extending from the substrate 101 and the epitaxial layer 102, and a trench is formed by the barrier layer 105 and the epitaxial layer 102.

[0061] The step of sequentially depositing the insulating gate dielectric layer 106, the gate control layer 107, the gate electrode layer 108, the interlayer dielectric ILD layer 109, the source layer 110, and the drain layer 111 may include:

[0062] 1. An insulating gate dielectric layer is deposited at the bottom (or around the bottom) of a trench, and then a gate control layer 107 is deposited on the sidewalls of the trench. The gate control layer 107 may or may not cover the insulating gate dielectric layer 106. The insulating gate dielectric layer 106 separates the gate control layer 107 from the epitaxial layer 102.

[0063] 2. Deposit a gate electrode layer 108 in the trench;

[0064] 3. Deposit an ILD layer 109 to cover a portion of the barrier layer 105, the gate control layer 107, and the gate electrode layer 108;

[0065] 4. Deposit source layer 110 to cover another part of barrier layer 105, well layer 103, potential well layer 104 and ILD layer 109;

[0066] 5. Deposition source layer 110;

[0067] 6. Deposit a drain layer 111 under the substrate 101.

[0068] Figures 3a-3j This is a schematic diagram of the manufacturing steps of a trench semiconductor device provided in an exemplary embodiment, the specific steps of which are as follows:

[0069] 1. Provide a substrate 101 with suitable parameters, and deposit an epitaxial layer 102 on the substrate 101, such as... Figure 3a As shown. The substrate 101 is not limited to homoepitaxial growth but also includes substrate materials for heteroepitaxial growth. The epitaxial parameters are related to the voltage withstand capability requirements of the device. Higher voltage withstand capability requirements allow for lower epitaxial doping concentrations and thicker thicknesses. The epitaxial doping concentration can be as low as 10⁻⁶. 15 ~10 17 cm -3 The thickness can be greater than 10μm;

[0070] 2. The well layer 103 is formed through epitaxial growth and selective etching, such as... Figure 3b As shown. The substrate 101, epitaxial layer 102, and well layer 103 can be made of materials such as GaN, Si, and SiC. The concentration of the epitaxially formed well layer 103 can be 10... 16 cm -3 ~10 18 cm -3 The thickness can range from 1μm to 5μm;

[0071] 3. A potential well layer 104 is formed through epitaxial growth and selective etching, such as... Figure 3c As shown. The potential well layer 104 can be made of materials such as GaN. The width of the potential well layer 104 can be greater than 1 μm.

[0072] 4. A barrier layer 105 is formed through epitaxial growth and selective etching, such as... Figure 3d As shown. The barrier layer 105 can be made of materials such as AlGaN, with a thickness of 0.005 μm to 5 μm.

[0073] 5. The insulating gate dielectric layer 106 is deposited by deposition and selective etching, such as... Figure 3eAs shown, the thickness of the insulating gate dielectric layer 106 can be between 0.1 μm and 0.2 μm.

[0074] 6. The gate control layer 107 is deposited through epitaxial growth and selective etching, such as... Figure 3f As shown. The gate control layer 107 can be N-type or P-type doped, with a concentration of up to 10. 16 cm -3 ~10 18 cm -3 The thickness can be greater than 2μm, and it can also be an undoped crystalline or amorphous material.

[0075] 7. Deposit gate electrode layer 108, such as Figure 3g As shown. The thickness can range from 0.5μm to 5μm.

[0076] 8. Deposit silicon dioxide or silicon nitride, remove a portion using photolithography etching to form the ILD layer 109, such as... Figure 3h As shown. The thickness of the ILD layer 109 can range from 0.1 μm to 3 μm.

[0077] 9. Deposit the front-side metal, i.e., the source layer 110, such as... Figure 3i As shown. The source layer 110 can be a titanium-aluminum-nickel-gold alloy with a thickness of about 4 μm.

[0078] 10. Deposit the back metal, i.e., the drain layer 111, such as Figure 3j As shown. The drain layer 111 can be a titanium-aluminum-nickel-gold alloy with a thickness of about 2 μm.

[0079] The above technical solution ensures that the interface between the well layer and the barrier layer is parallel to the direction from the gate electrode layer to the drain layer, resulting in a smaller trench structure size. Combined with the high carrier mobility of 2DEG or 2DHG, this improves the cell power density and further reduces the on-resistance. Under reverse conditions, it can also reduce the thickness of the drift region to some extent, thereby lowering the on-resistance.

[0080] The preferred embodiments of the present disclosure have been described in detail above with reference to the accompanying drawings. However, the present disclosure is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present disclosure, various simple modifications can be made to the technical solutions of the present disclosure, and these simple modifications all fall within the protection scope of the present disclosure.

[0081] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, this disclosure will not describe the various possible combinations separately.

[0082] Furthermore, various different embodiments of this disclosure can be combined in any way, as long as they do not violate the spirit of this disclosure, they should also be regarded as the content disclosed in this disclosure.

Claims

1. A trench-type semiconductor device, characterized in that, The trench semiconductor device utilizes a 2DEG or 2DHG formed by a heterojunction as the channel carrier. The trench semiconductor device includes a substrate (101) of a first conductivity type, an epitaxial layer (102) of a first conductivity type, a well layer (103) of a second conductivity type, a potential well layer (104), a barrier layer (105), an insulating gate dielectric layer (106), a gate control layer (107), a gate electrode layer (108), an interlayer dielectric ILD layer (109), a source layer (110), and a drain layer (111). The interface between the potential well layer (104) and the barrier layer (105) is parallel to the direction from the gate electrode layer (108) to the drain layer (111). The gate control layer (107) is deposited between the barrier layer (105) and the gate electrode layer (108). If the gate control layer (107) is of the first conductivity type, the trench semiconductor device is depletion type. If the gate control layer (107) is of the second conductivity type, the trench semiconductor device is enhancement type. The well layer (103), the potential well layer (104), the barrier layer (105), and the insulating gate dielectric layer (106) are all deposited on the epitaxial layer (102). A trench is formed by the barrier layer (105) and the epitaxial layer (102). The insulating gate dielectric layer (106) is deposited at the bottom of the trench. The gate control layer (107) is deposited on the sidewall of the trench. The insulating gate dielectric layer (106) separates the gate control layer (107) and the epitaxial layer (102). The gate electrode layer (108) is deposited in the trench. The ILD layer (109) covers a portion of the barrier layer (105), the gate control layer (107), and the gate electrode layer (108). The source layer (110) covers another portion of the barrier layer (105), the well layer (103), the potential well layer (104), and the ILD layer. Layer (109).

2. The trench semiconductor device according to claim 1, characterized in that, The width of the potential well layer (104) is greater than 1 μm.

3. The trench semiconductor device according to claim 1, characterized in that, The thickness of the barrier layer (105) is 0.005 μm to 5 μm.

4. A method for manufacturing a trench-type semiconductor device, characterized in that, The method includes: An epitaxial layer (102) of a second conductivity type is deposited on a substrate (101) of a first conductivity type; The epitaxial layer (102) is etched or ion implanted to form a trap region layer (103); A potential well layer (104) is deposited on the epitaxial layer (102) such that the potential well layer (104) partially covers the epitaxial layer (102); a barrier layer (105) is deposited on the epitaxial layer (102) such that the barrier layer (105) partially covers the epitaxial layer (102), such that the interface between the potential well layer (104) and the barrier layer (105) is perpendicular to the plane extending from the substrate (101) and the epitaxial layer (102), and the barrier layer (105) and the epitaxial layer (102) form a trench; An insulating gate dielectric layer (106) is deposited at the bottom of the trench, and a gate control layer (107) is deposited on the sidewall of the trench, wherein the gate control layer (107) covers the insulating gate dielectric layer (106) and the insulating gate dielectric layer (106) separates the gate control layer (107) and the epitaxial layer (102); a gate electrode layer (108) is deposited in the trench; an ILD layer (109) is deposited to cover a portion of the barrier layer (105), the gate control layer (107), and the gate electrode layer (108); a source layer (110) is deposited to cover another portion of the barrier layer (105), the well layer (103), the well layer (104), and the ILD. Layer (109); deposit a drain layer (111) under the substrate (101); such that the interface between the potential well layer (104) and the barrier layer (105) is parallel to the direction of the gate electrode layer (108) pointing to the drain layer (111), and the interface between the potential well layer (104) and the barrier layer (105) forms a 2DEG or 2DHG; Wherein, if the gate control layer (107) is of the first conductivity type, the trench semiconductor device is of the depletion type; if the gate control layer (107) is of the second conductivity type, the trench semiconductor device is of the enhancement type.

5. The method according to claim 4, characterized in that, The width of the potential well layer (104) is greater than 1 μm.

6. The method according to claim 4, characterized in that, The thickness of the barrier layer (105) is 0.005 μm to 5 μm.

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