Monolithic integrated VCSEL chip and method for manufacturing the same

Abstract

The present application relates to a monolithic integrated VCSEL chip, comprising a first substrate; a first VCSEL unit formed on the first substrate, the first VCSEL unit comprising a first P-DBR layer at an upper region thereof; a second substrate formed on the first P-DBR layer of the first VCSEL unit; and a second VCSEL unit formed on the second substrate, wherein the first VCSEL unit is configured to project laser light having a first wavelength, and the second VCSEL unit is configured to project laser light having a second wavelength. In this way, the monolithic integrated VCSEL chip is capable of multi-wavelength wide spectrum laser output.

Description

Technical Field

[0001] This application relates to the field of VCSELs, and more particularly to a monolithic integrated VCSEL chip capable of multi-wavelength broadband laser output. Background Technology

[0002] A VCSEL (Vertical Cavity Surface Emitting Laser) is a semiconductor laser that forms a resonant cavity perpendicular to the substrate, emitting laser light in a vertical direction. VCSEL technology has been widely used in fields including consumer electronics, industry, medicine, and optical communications. However, in practical applications, VCSEL lasers have many limitations.

[0003] The existing VCSEL lasers have extremely short cavity (i.e., resonant cavity) lengths, resulting in large longitudinal mode spacing. Therefore, the output frequencies and modes of existing VCSEL lasers are limited, which means that the width range of the output spectrum of existing VCSEL lasers is limited.

[0004] To achieve multi-wavelength laser output (i.e., outputting lasers with a broad spectrum), existing manufacturers primarily utilize MEMS (Micro-electromechanical Systems) and HCG (High Contrast Grating) to achieve tunable wavelength output, with a tunable spectral range exceeding 15nm. However, both of these technologies are costly and present significant challenges in practical implementation.

[0005] Therefore, a more optimized VCSEL solution capable of multi-wavelength broadband laser output is needed. Summary of the Invention

[0006] One advantage of this application is that it provides a monolithic integrated VCSEL chip, wherein the monolithic integrated VCSEL chip is capable of multi-wavelength broadband laser output.

[0007] Another advantage of this application is that it provides a monolithic integrated VCSEL chip, wherein the monolithic integrated VCSEL chip can be implemented based on existing VCSEL laser fabrication processes, with low process difficulty and low cost.

[0008] Another advantage of this application is that it provides a monolithically integrated VCSEL chip, wherein the monolithically integrated VCSEL chip includes at least two VCSEL units that are structurally monolithically integrated with each other, and by reasonably arranging the positional relationship between the at least two VCSEL units, the monolithically integrated VCSEL chip can solve the interference problem caused by the laser it generates when entering the optical system.

[0009] Another advantage of this application is that it provides a monolithic integrated VCSEL chip, wherein the monolithic integrated VCSEL chip can be used as a highly coherent light source by changing its own structural configuration. That is, the VCSEL chip according to this application can not only output multi-wavelength broadband lasers, but also be used as a highly coherent light source, for example, as a coherent light source for testing.

[0010] To achieve at least one of the above-mentioned technical advantages, a monolithic integrated VCSEL chip is provided, comprising:

[0011] First substrate;

[0012] A first VCSEL cell formed on the first substrate, the first VCSEL cell including a first P-DBR layer located in its upper region;

[0013] A second substrate formed on the first P-DNR layer of the first VCSEL cell; and

[0014] A second VCSEL cell formed on the second substrate;

[0015] The first VCSEL unit and the second VCSEL unit are offset from each other in the lateral direction set by the monolithic integrated VCSEL chip.

[0016] The first VCSEL unit is configured to project a laser with a first wavelength; the second VCSEL unit is configured to project a laser with a second wavelength, wherein the first wavelength is different from the second wavelength, and the range of the first wavelength is 600nm to 1000nm, and the range of the second wavelength is 1100nm to 1300nm.

[0017] In the monolithic integrated VCSEL chip according to this application, the spacing between the first VCSEL unit and the second VCSEL unit is 10um to 200um.

[0018] In the monolithic integrated VCSEL chip according to this application, the first VCSEL unit and the second VCSEL unit are formed at different height positions in the height direction set by the monolithic integrated VCSEL chip.

[0019] In the monolithic integrated VCSEL chip according to this application, the height difference between the first VCSEL unit and the second VCSEL unit in the height direction set in the monolithic integrated VCSEL chip is 5um to 10um.

[0020] In the monolithic integrated VCSEL chip according to this application, the thickness of the second substrate ranges from 500 nm to 600 nm.

[0021] In the monolithic integrated VCSEL chip according to this application, the thickness of the first P-DBR layer of the first VCSEL unit ranges from 2µm to 5µm.

[0022] In the monolithic integrated VCSEL chip according to this application, the first VCSEL unit includes a first N-DBR layer formed on the first substrate, a first active region located on the first N-DBR layer, a first oxide confinement layer having a first oxide aperture for limiting the light emission aperture of the first active region, a first P-DBR layer located on the first active region, and a first positive electrode and a first negative electrode for conducting the first active region; wherein, the first active region is sandwiched between the first N-DBR layer and the first P-DBR layer, and the first N-DBR layer and the first P-DBR layer form a first resonant cavity of the first active region.

[0023] In the monolithic integrated VCSEL chip according to this application, the second VCSEL unit includes a second N-DBR layer formed on the second substrate, a second active region located on the second N-DBR layer, a second oxide confinement layer having a second oxide aperture for limiting the light emission aperture of the second active region, a second P-DBR layer located on the second active region, and a second positive electrode and a second negative electrode for conducting the second active region; wherein the second active region is sandwiched between the second N-DBR layer and the second P-DBR layer, and the second N-DBR layer and the second P-DBR layer form the second resonant cavity of the second VCSEL unit.

[0024] In the monolithic integrated VCSEL chip according to this application, the length of the first resonant cavity is equal to the length of the second resonant cavity.

[0025] In the monolithic integrated VCSEL chip according to this application, the aperture of the first oxide hole in the first oxide confinement layer is equal to the aperture of the second oxide hole in the second oxide confinement layer.

[0026] In the monolithic integrated VCSEL chip according to this application, the length of the first resonant cavity is not equal to the length of the second resonant cavity.

[0027] In the monolithic integrated VCSEL chip according to this application, the spacing between the first VCSEL unit and the second VCSEL unit is 10um to 20um.

[0028] In the monolithic integrated VCSEL chip according to this application, the aperture of the first oxide hole in the first oxide confinement layer is not equal to the aperture of the second oxide hole in the second oxide confinement layer.

[0029] In the monolithically integrated VCSEL chip according to this application, the first positive electrode and the second positive electrode are electrically connected to form a positive electrode conductive layer.

[0030] In the monolithic integrated VCSEL chip according to this application, the first negative electrode and the second negative electrode are electrically connected to each other to form a negative electrode conductive layer.

[0031] According to another aspect of this application, a method for fabricating a monolithic integrated VCSEL chip is also provided, comprising:

[0032] A multilayer epitaxial structure is formed, the multilayer epitaxial structure including a first epitaxial structure and a second epitaxial structure stacked on the first epitaxial structure, the first epitaxial structure including a first substrate, a first N-DBR layer on the first substrate, a first active region on the first N-DBR, and a first P-DBR layer on the first active region; the second epitaxial structure including a second substrate on the first P-DBR layer, a second N-DBR layer on the second substrate, a second active region on the second N-DBR, and a second P-DBR layer on the second active region;

[0033] Etch a portion of the second epitaxial structure in the multilayer epitaxial structure to expose the first epitaxial structure;

[0034] The first epitaxial structure is oxidized to form a first oxide confinement layer above the first active region for confining the light emission aperture of the first active region;

[0035] The second epitaxial structure is oxidized to form a second oxide confinement layer above the second active region for confining the light emission aperture of the second active region;

[0036] A first positive electrode and a first negative electrode are respectively formed to conduct the first active region, so as to form a first VCSEL cell on the first substrate; and

[0037] A second positive electrode and a second negative electrode are formed to conduct the second active region, thereby forming a second VCSEL unit on the second substrate. The first VCSEL unit and the second VCSEL unit are offset from each other in the lateral direction set by the monolithic integrated VCSEL chip. The first VCSEL unit is configured to project a laser with a first wavelength. The second VCSEL unit is configured to project a laser with a second wavelength, wherein the first wavelength is different from the second wavelength, and the range of the first wavelength is 600nm to 1000nm, and the range of the second wavelength is 1100nm to 1300nm.

[0038] In the preparation method according to this application, the lateral spacing between the first VCSEL unit and the second VCSEL unit is 10 μm to 200 μm.

[0039] In the fabrication method according to this application, the first VCSEL unit and the second VCSEL unit are formed at different height positions in the height direction set by the monolithic integrated VCSEL chip.

[0040] In the preparation method according to this application, the spacing between the first VCSEL unit and the second VCSEL unit is 10 μm to 20 μm.

[0041] Further advantages and benefits of this application will become fully apparent from the following description and accompanying drawings.

[0042] These and other advantages, features and benefits of this application are fully apparent from the following detailed description, the accompanying drawings and the claims. Attached Figure Description

[0043] Figure 1 The illustration shows a schematic diagram of a monolithic integrated VCSEL chip according to an embodiment of this application.

[0044] Figure 2 The illustration shows a schematic diagram of a modified embodiment of the monolithic integrated VCSEL chip according to an embodiment of this application.

[0045] Figure 3 The illustration shows a schematic diagram of another modified embodiment of the monolithic integrated VCSEL chip according to an embodiment of this application.

[0046] Figure 4 The illustration shows a schematic diagram of the fabrication process of the monolithic integrated VCSEL chip according to an embodiment of this application. Detailed Implementation

[0047] The following description is intended to disclose this application and enable those skilled in the art to implement it. The preferred embodiments described below are merely examples, and other obvious variations will occur to those skilled in the art. The basic principles of this application defined in the following description can be applied to other embodiments, modifications, improvements, equivalents, and other technical solutions that do not depart from the spirit and scope of this application.

[0048] Those skilled in the art should understand that, in the disclosure of this application, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, the above terms should not be construed as limitations on this application.

[0049] It is understood that the term "a" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element can be one, while in another embodiment, the number of the element can be multiple, and the term "a" should not be understood as a limitation on the number.

[0050] Schematic illustration of a monolithic integrated VCSEL chip

[0051] As mentioned earlier, the extremely short cavity length of existing VCSEL lasers results in a large longitudinal mode spacing, thus limiting their output frequency and modes. In other words, the width and range of the output spectrum of existing VCSEL lasers are limited. While this limitation does exist for a single VCSEL laser, those skilled in the art will understand that changing the material and structural configuration of a VCSEL laser will alter its optical output characteristics (especially its wavelength characteristics).

[0052] Furthermore, the inventors of this application studied the general consistency of different VCSEL lasers in terms of wafer-level structure and fabrication process, and conceived a technical solution for monolithically integrating VCSEL lasers with different specific output wavelengths at the wafer level, so that the final monolithically integrated VCSEL chip can achieve multi-wavelength broadband laser output.

[0053] Accordingly, the monolithic integrated VCSEL chip formed based on the technical concept of this application includes a multi-layer VCSEL structure, wherein each layer of the VCSEL structure can form at least one VCSEL unit. Here, in the embodiment of this application, taking the monolithic integrated VCSEL chip including two layers of VCSEL structure, and each layer of VCSEL structure forming one VCSEL unit as an example, that is, the monolithic integrated VCSEL chip includes at least two VCSEL units, and the at least two VCSEL units have different wavelength output characteristics, so that the monolithic integrated VCSEL chip can realize multi-wavelength broadband laser output.

[0054] The following describes the technical solution of the embodiments of this application using the example of a monolithic integrated VCSEL chip comprising two VCSEL structures, wherein each VCSEL structure comprises one VCSEL unit.

[0055] Figure 1 The illustration shows a schematic diagram of a monolithic integrated VCSEL chip according to an embodiment of this application. Figure 1 As shown, the monolithic integrated VCSEL chip includes a first substrate 11, a first VCSEL unit 12 formed on the first substrate 11, the first VCSEL unit 12 including a first P-DBR layer 124 located in its upper region, a second substrate 13 formed on the first P-DNR layer of the first VCSEL unit 12, and a second VCSEL unit 14 formed on the second substrate 13.

[0056] like Figure 1 As shown in this embodiment, the first VCSEL unit 12 and the second VCSEL unit 14 are staggered from each other in the lateral direction of the monolithic integrated VCSEL chip. This positional relationship ensures sufficient space for laser emission from both the first VCSEL unit 12 and the second VCSEL unit 14. More specifically, in this embodiment, the spacing between the first VCSEL unit and the second VCSEL unit is 10µm to 200µm.

[0057] Specifically, in this embodiment, the first VCSEL unit 12 and the second VCSEL unit 14 have different output wavelength characteristics, thereby enabling the monolithic integrated VCSEL chip to achieve multi-wavelength broadband laser output. That is, the output wavelength of the monolithic integrated VCSEL chip has multiple transverse modes. More specifically, in this embodiment, the first VCSEL unit 12 is configured to project a laser with a first wavelength; the second VCSEL unit 14 is configured to project a laser with a second wavelength, wherein the first wavelength is different from the second wavelength, that is, the first wavelength is not equal to the second wavelength, wherein the range of the first wavelength is 600nm-1000nm, and the range of the second wavelength is 1100nm-1300nm.

[0058] Those skilled in the art will understand that the wavelength output characteristics of the first VCSEL unit 12 and the second VCSEL unit 14 are determined by the materials used to fabricate the first VCSEL unit 12 and the second VCSEL unit 14 and are affected by their respective resonant cavities. The specific principles will be explained later. That is, in other examples of this application, the wavelength output characteristics of the first VCSEL unit 12 and the second VCSEL unit 14 can be adjusted by the materials used to fabricate their active regions and the characteristics of their resonant cavities to generate lasers in other wavelength ranges. This is not limited to this application.

[0059] like Figure 1 As shown in the embodiment of this application, the first VCSEL unit 12 includes a first N-DBR layer 121 formed on the first substrate 11, a first active region 122 located on the first N-DBR layer 121, a first oxide confinement layer 123 having a first oxide aperture 120 for confining the light emission aperture of the first active region 122, a first P-DBR layer 124 located on the first active region 122, and a first positive electrode 125 and a first negative electrode 126 for conducting the first active region 122; wherein, the first active region 122 is sandwiched between the first N-DBR layer 121 and the first P-DBR layer 124, and the first N-DBR layer 121 and the first P-DBR layer 124 form a first resonant cavity 127 of the first active region 122.

[0060] The second VCSEL unit 14 includes a second N-DBR layer 141 formed on the second substrate 13, a second active region 142 located on the second N-DBR layer 141, a second oxide confinement layer 143 having a second oxide aperture 140 for confining the light emission aperture of the second active region 142, a second P-DBR layer 144 located on the second active region 142, and a second positive electrode 145 and a second negative electrode 146 for conducting the second active region 142; wherein the second active region 142 is sandwiched between the second N-DBR layer 141 and the second P-DBR layer 144, and the second N-DBR layer 141 and the second P-DBR layer 144 form the second resonant cavity 147 of the second VCSEL unit 14.

[0061] More specifically, in the embodiments of this application, the first active region 122 and the second active region 142 include quantum wells (of course, in other examples of this application, the first active region 122 and the second active region 142 may include quantum dots), which may be made of AlInGaAs (e.g., AlInGaAs, GaAs, AlGaAs, and InGaAs), InGaAsP (e.g., InGaAsP, GaAs, InGaAs, GaAsP, and GaP), GaAsSb (e.g., GaAsSb, GaAs, and GaSb), InGaAsN (e.g., InGaAsN, GaAs, InGaAs, GaAsN, and GaN) or AlInGaAsP (e.g., AlInGaAsP, AlInGaAs, AlGaAs, InGaAs, InGaAsP, GaAs, InGaAs, GaAsP, and GaP). Of course, in the embodiments of this application, the first active region 122 and the second active region 142 may also be made of other compositions for forming quantum well layers. The output wavelength characteristics of the first VCSEL unit 12 and the second VCSEL unit 14 are determined by the materials used to fabricate the first active region 122 and the second active region 142, respectively.

[0062] The first P-DBR layer 124, the second P-DBR layer 144, the first N-DBR layer 121, and the second N-DBR layer 141 each comprise a system of alternating layers of materials with different refractive indices, forming a distributed Bragg reflector. The material selection of the alternating layers depends on the desired laser wavelength; that is, the material selection of the first P-DBR layer 124 and the first N-DBR layer 121 is determined by the material of the first active region 122; the material selection of the second P-DBR layer 144 and the second N-DBR layer 141 is determined by the material of the second active region 142. For example, in a specific example of this application, the first P-DBR layer 124 and the first N-DBR layer 121 (or the second P-DBR layer 144 and the second N-DBR layer 141) can be formed by alternating layers of AlGaAs with high aluminum content and AlGaAs with low aluminum content. It is worth noting that the optical thickness of the alternating layers is equal to or approximately equal to 1 / 4 of the laser wavelength.

[0063] The first oxide confinement layer 123 serves to confine the light emission space of the first VCSEL unit 12 (i.e., the light emission aperture of the first active region 122). The first oxide confinement layer 123 has a first oxide aperture 120, the aperture configuration of which determines the light emission aperture of the first VCSEL unit 12. Similarly, the second oxide confinement layer 143 serves to confine the light emission range of the second VCSEL unit 14 (i.e., to confine the light emission aperture of the second active region 142). The second oxide confinement layer 143 has a second oxide aperture 140, the aperture configuration of which determines the light emission aperture of the second VCSEL unit 14. Here, the apertures of the first oxide aperture 120 and the second oxide aperture 140 refer to their diameters.

[0064] Those skilled in the art will understand that, in other examples of this application, the aperture sizes of the first VCSEL unit 12 and the second VCSEL unit 14 can be limited in other ways. For example, in other examples of this application, the aperture sizes of the first VCSEL unit 12 and the second VCSEL unit 14 can be determined by the particles (e.g., H ions) implanted in the first P-DBR layer 124 and the second P-DBR.

[0065] like Figure 1As shown in this embodiment, the first positive electrode 125 of the first VCSEL unit 12 is formed on the first P-DBR layer 124, and the first negative electrode 126 of the first VCSEL unit 12 is formed below the first substrate 11; the second positive electrode 145 of the second VCSEL unit 14 is formed on the second P-DBR layer 144, and the second negative electrode 146 of the second VCSEL unit 14 is formed in the second substrate 13. That is, in this embodiment, the second negative electrode 146 is a part of the second substrate 13, and the second negative electrode 146 extends to the side of the second VCSEL unit 14.

[0066] During operation, the first and second VCSEL units 14 can achieve laser excitation only if the following two conditions are met: (1) Population inversion process: When population inversion exists in the active region, and the gain provided by the laser medium is sufficient to exceed the loss, the light intensity will continue to increase when current is injected through the negative and positive electrodes. When electrons in the high-energy conduction band transition to the low-energy band, as light of a specific wavelength is reflected back and forth between the P-DBR layer and the N-DBR layer, the amplification process is repeated continuously, thus forming laser; (2) Resonant cavity: Composed of P-DBR layer, N-DBR layer and gain medium, it is one of the main conditions for generating laser. The main function of the resonant cavity is to form multiple light energy feedbacks and laser oscillation when the light generated in the active region is reflected back and forth between the P-DBR layer and N-DBR. Finally, the first VCSEL unit 12 and the second VCSEL unit 14 emit lasers from their front sides respectively.

[0067] Furthermore, in this embodiment, the length of the first resonant cavity 127 of the first VCSEL unit 12 can be configured to be equal to or different from the length of the second resonant cavity 147 of the second VCSEL unit 14.

[0068] When the length of the first resonant cavity 127 is configured to be unequal to the length of the second resonant cavity 147, the output center wavelength and number of modes of the first VCSEL unit 12 and the second VCSEL unit 14 differ. In this case, preferably, the lateral spacing between the first VCSEL unit and the second VCSEL unit is set to 10µm to 20µm, thus enabling multi-wavelength output of the VCSEL array.

[0069] When the length of the first resonant cavity 127 can be configured to be equal to the length of the second resonant cavity 147, preferably, the first VCSEL unit 12 and the second VCSEL unit 14 are configured to have different light-emitting apertures, that is, the aperture of the first oxide hole 120 of the first oxide confinement layer 123 is not equal to the aperture of the second oxide hole 140 of the second oxide confinement layer 143.

[0070] It is worth mentioning that, in the application embodiment, if the length of the first resonant cavity 127 of the first VCSEL unit 12 is equal to the length of the second resonant cavity 147 of the second VCSEL unit 14, and both the first VCSEL unit 12 and the second VCSEL unit 14 achieve single longitudinal mode output and the wavelengths they generate are not equal, and the lateral distance between the first VCSEL unit and the second VCSEL unit is controlled within 20um, then the monolithic integrated VCSEL chip can be used as a light source with high coherence, for example, in fields such as lidar and object measurement.

[0071] Furthermore, such as Figure 1 As shown, it should be noted that in this embodiment, the second VCSEL unit 14 is formed on the second substrate 13, which is formed on the first P-DBR layer 124 of the first VCSEL unit 12. Therefore, the first VCSEL unit 12 and the second VCSEL unit 14 are formed at different heights in the height direction of the monolithic integrated VCSEL chip. This arrangement reduces interference between the laser light projected by the first VCSEL unit 12 and the laser light projected by the second VCSEL unit 14. Accordingly, the monolithic integrated VCSEL chip according to this embodiment can solve the interference problem it generates when applied to an optical system.

[0072] More specifically, in this embodiment, the height difference between the first VCSEL unit 12 and the second VCSEL unit 14 in the height direction set by the monolithic integrated VCSEL chip is 5µm to 10µm. It should be understood that the height difference between the first VCSEL unit 12 and the second VCSEL unit 14 in the height direction set by the monolithic integrated VCSEL chip is related to the height configuration of the first P-DBR layer 124 of the first VCSEL unit 12 and the height configuration of the second substrate 13. Accordingly, in this embodiment, the thickness of the second substrate 13 is 500nm to 600nm, and the thickness of the first P-DBR layer 124 is 2µm to 5µm.

[0073] Figure 2The illustration shows a schematic diagram of a modified embodiment of the monolithic integrated VCSEL chip according to an embodiment of this application. For example... Figure 2 As shown, in this modified embodiment, the first positive electrode 125 and the second positive electrode 145 are electrically connected to each other to form a positive electrode conductive layer. That is, in this modified embodiment, the first VCSEL unit 12 and the second VCSEL unit 14 share a common anode.

[0074] Figure 3 The illustration shows a schematic diagram of another modified embodiment of the monolithic integrated VCSEL chip according to an embodiment of this application. For example... Figure 3 As shown, in this modified embodiment, the second negative electrode 146 of the second VCSEL unit 14 is also formed below the first substrate 11. That is, in this modified embodiment, the first VCSEL unit 12 and the second VCSEL unit 14 share a common cathode.

[0075] It is worth mentioning that, in the embodiments of this application, the first P-DBR layer 124 of the first VCSEL unit 12 and the second P-DBR layer 144 of the second VCSEL unit 14 can be made of dielectric films with higher reflectivity. When selecting dielectric films, considering stability, adhesion to GaAs materials, and mechanical properties, materials with a large difference in refractive index can be selected, such as SiO2 and TiO2; SiOx and SiNx; SiO2 and Ta2O5. The number of dielectric film layers is proportional to the reflectivity of the film system. Depending on the laser's transmittance, the number of film layers varies. For example, in a SiO2 and Ta2O5 film system design, with SiO2 having a refractive index of 1.5 and Ta2O5 around 2.2, the reflectivity at 1300nm is approximately 96% when the film system has 5 pairs. When the film system is increased to 6 pairs, the reflectivity at 1300nm can reach over 98%. If higher reflectivity is required, the number of film pairs can be further increased.

[0076] In summary, the monolithic integrated VCSEL chip described in the embodiments of this application is explained, which is capable of multi-wavelength broadband laser output.

[0077] Furthermore, the monolithically integrated VCSEL chip is implemented based on existing VCSEL laser technology, which is less difficult and less costly in terms of manufacturing process.

[0078] Furthermore, the monolithically integrated VCSEL chip includes at least two VCSEL units that are structurally monolithically integrated with each other. By rationally arranging the positional relationship between the at least two VCSEL units, the monolithically integrated VCSEL chip can solve the interference problem caused by the laser it generates when entering the optical system.

[0079] Furthermore, the monolithically integrated VCSEL chip can be modified in its structural configuration to enable it to be used as a highly coherent light source. In other words, the VCSEL chip according to this application can not only output multi-wavelength broadband laser light, but also be used as a highly coherent light source, for example, as a coherent light source for testing.

[0080] illustrative preparation method

[0081] Furthermore, the monolithic integrated VCSEL chip described above can be fabricated using the following fabrication method.

[0082] Figure 4 The illustration shows a schematic diagram of the fabrication process of the monolithic integrated VCSEL chip according to an embodiment of this application.

[0083] like Figure 4 As shown, the fabrication process of the monolithic integrated VCSEL chip includes:

[0084] First, a multilayer epitaxial structure is formed using MOCVD (Metal-organic Chemical Vapor Deposition) or other metal growth processes. The multilayer epitaxial structure includes a first epitaxial structure and a second epitaxial structure stacked on the first epitaxial structure. The first epitaxial structure includes a first substrate 11, a first N-DBR layer 121 on the first substrate 11, a first active region 122 on the first N-DBR, and a first P-DBR layer 124 on the first active region 122. The second epitaxial structure includes a second substrate 13 on the first P-DBR layer 124, a second N-DBR layer 141 on the second substrate 13, a second active region 142 on the second N-DBR, and a second P-DBR layer 144 on the second active region 142.

[0085] Then, a portion of the second epitaxial structure in the multilayer epitaxial structure is etched by photolithography or other etching processes to expose the first epitaxial structure;

[0086] Next, an oxidation process is performed to oxidize the first epitaxial structure to form a first oxide confinement layer 123 above the first active region 122 for confining the light-emitting aperture of the first active region 122.

[0087] Then, an oxidation process is performed to oxidize the second epitaxial structure to form a second oxide confinement layer 143 above the second active region 142 for confining the light emission aperture of the second active region 142.

[0088] Next, a first positive electrode 125 and a first negative electrode 126 are formed to conduct the first active region 122, so as to form a first VCSEL cell 12 on the first substrate 11.

[0089] Then, a second positive electrode 145 and a second negative electrode 146 are formed to conduct the second active region 142, so as to form a second VCSEL unit 14 on the second substrate 13, wherein the first VCSEL unit 12 and the second VCSEL unit 14 are offset from each other in the lateral direction set by the monolithic integrated VCSEL chip; the first VCSEL unit 12 is configured to project a laser with a first wavelength; the second VCSEL unit 14 is configured to project a laser with a second wavelength, wherein the first wavelength ranges from 600nm to 1000nm, and the second wavelength ranges from 1100nm to 1300nm.

[0090] In the above preparation method, in one example of this application, the spacing between the first VCSEL unit and the second VCSEL unit is 10um to 200um.

[0091] In the above preparation method, in one example of this application, the first VCSEL unit 12 and the second VCSEL unit 14 are formed at different height positions in the height direction set by the monolithic integrated VCSEL chip.

[0092] In the above preparation method, in one example of this application, the height difference between the first VCSEL unit 12 and the second VCSEL unit 14 in the height direction set in the monolithic integrated VCSEL chip is 5um to 10um.

[0093] In the above preparation method, in one example of this application, the thickness of the second substrate 13 is in the range of 500 nm to 600 nm.

[0094] In the above preparation method, in one example of this application, the thickness of the first P-DBR layer 124 of the first VCSEL unit 12 ranges from 2µm to 5µm.

[0095] In the above preparation method, in one example of this application, the length of the first resonant cavity 127 is equal to the length of the second resonant cavity 147.

[0096] In the above preparation method, in one example of this application, the pore diameter of the first oxide pore 120 of the first oxide confinement layer 123 is equal to the pore diameter of the second oxide pore 140 of the second oxide confinement layer 143.

[0097] In the above-described preparation method, in one example of this application, the length of the first resonant cavity 127 is not equal to the length of the second resonant cavity 147.

[0098] In the above preparation method, in one example of this application, the spacing between the first VCSEL unit and the second VCSEL unit is 10um to 20um.

[0099] In the above preparation method, in one example of this application, the pore size of the first oxide pore 120 of the first oxide confinement layer 123 is not equal to the pore size of the second oxide pore 140 of the second oxide confinement layer 143.

[0100] In the above preparation method, in one example of this application, the first positive electrode 125 and the second positive electrode 145 are electrically connected to each other to form a positive electrode conductive layer, that is, the first VCSEL unit 12 and the second VCSEL unit 14 share the same anode.

[0101] In the above preparation method, in one example of this application, the first negative electrode 126 and the second negative electrode 146 are simultaneously formed below the first substrate 11, that is, the first VCSEL unit 12 and the second VCSEL unit 14 share a common cathode.

[0102] The basic principles of this application have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this application are merely examples and not limitations, and should not be considered as essential features of each embodiment of this application. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the application to the necessity of employing the aforementioned specific details for implementation.

[0103] The block diagrams of devices, apparatuses, devices, and systems involved in this application are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0104] It should also be noted that in the apparatus, equipment, and methods of this application, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions of this application.

[0105] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this application. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of this application. Therefore, this application is not intended to be limited to the aspects shown herein, but rather to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0106] The above description has been given for the purpose of illustration and description. Furthermore, this description is not intended to limit the embodiments of this application to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A monolithically integrated VCSEL chip, characterized in that, include: First substrate; A first VCSEL cell formed on the first substrate includes a first N-DBR layer formed on the first substrate, a first active region located on the first N-DBR layer, a first oxide confinement layer having a first oxide aperture for confining the light emission aperture of the first active region, a first P-DBR layer located on the first active region, and a first positive electrode and a first negative electrode for conducting the first active region; wherein the first active region is sandwiched between the first N-DBR layer and the first P-DBR layer, and the first N-DBR layer and the first P-DBR layer form a first resonant cavity of the first active region; A second substrate formed on the first P-DNR layer of the first VCSEL cell; and A second VCSEL cell is formed on the second substrate. The second VCSEL cell includes a second N-DBR layer formed on the second substrate, a second active region located on the second N-DBR layer, a second oxide confinement layer having a second oxide aperture for confining the light emission aperture of the second active region, a second P-DBR layer located on the second active region, and a second positive electrode and a second negative electrode for conducting the second active region; wherein the second active region is sandwiched between the second N-DBR layer and the second P-DBR layer, and the second N-DBR layer and the second P-DBR layer form a second resonant cavity of the second VCSEL cell; The first VCSEL unit and the second VCSEL unit are offset from each other in the lateral direction set by the monolithic integrated VCSEL chip. The first VCSEL unit is configured to project a laser with a first wavelength; the second VCSEL unit is configured to project a laser with a second wavelength, wherein the first wavelength is different from the second wavelength, wherein the range of the first wavelength is 600nm to 1000nm, and the range of the second wavelength is 1100nm to 1300nm. The first VCSEL unit and the second VCSEL unit are formed at different height positions in the height direction set by the monolithic integrated VCSEL chip to reduce the interference between the laser projected by the first VCSEL unit and the laser projected by the second VCSEL unit; the height difference between the first VCSEL unit and the second VCSEL unit in the height direction set by the monolithic integrated VCSEL chip is 5um to 10um, and the height difference is related to the height of the first P-DBR layer of the first VCSEL unit and the height configuration of the second substrate.

2. The monolithically integrated VCSEL chip according to claim 1, wherein, The spacing between the first VCSEL unit and the second VCSEL unit is 10µm to 200µm.

3. The monolithically integrated VCSEL chip according to claim 1, wherein, The thickness of the second substrate ranges from 500 nm to 600 nm.

4. The monolithically integrated VCSEL chip according to claim 1, wherein, The thickness of the first P-DBR layer of the first VCSEL unit ranges from 2µm to 5µm.

5. The monolithically integrated VCSEL chip according to claim 1, wherein, The length of the first resonant cavity is equal to the length of the second resonant cavity.

6. The monolithically integrated VCSEL chip according to claim 5, wherein, The diameter of the first oxide pore in the first oxide confinement layer is equal to the diameter of the second oxide pore in the second oxide confinement layer.

7. The monolithically integrated VCSEL chip according to claim 1, wherein, The length of the first resonant cavity is not equal to the length of the second resonant cavity.

8. The monolithically integrated VCSEL chip according to claim 7, wherein, The spacing between the first VCSEL unit and the second VCSEL unit is 10µm to 20µm.

9. The monolithically integrated VCSEL chip according to claim 7, wherein, The pore size of the first oxide pore in the first oxide confinement layer is not equal to the pore size of the second oxide pore in the second oxide confinement layer.

10. The monolithically integrated VCSEL chip according to claim 1, wherein, The first positive electrode and the second positive electrode are electrically connected to each other to form a positive electrode conductive layer.

11. The monolithically integrated VCSEL chip according to claim 1, wherein, The first negative electrode and the second negative electrode are electrically connected to each other to form a negative electrode conductive layer.

12. A method for fabricating a monolithic integrated VCSEL chip, characterized in that, include: A multilayer epitaxial structure is formed, the multilayer epitaxial structure including a first epitaxial structure and a second epitaxial structure stacked on the first epitaxial structure, the first epitaxial structure including a first substrate, a first N-DBR layer on the first substrate, a first active region on the first N-DBR, and a first P-DBR layer on the first active region; the second epitaxial structure including a second substrate on the first P-DBR layer, a second N-DBR layer on the second substrate, a second active region on the second N-DBR, and a second P-DBR layer on the second active region; Etch a portion of the second epitaxial structure in the multilayer epitaxial structure to expose the first epitaxial structure; The first epitaxial structure is oxidized to form a first oxide confinement layer above the first active region for confining the light emission aperture of the first active region; The second epitaxial structure is oxidized to form a second oxide confinement layer above the second active region for confining the light emission aperture of the second active region; A first positive electrode and a first negative electrode are formed respectively to conduct the first active region, so as to form a first VCSEL cell on the first substrate; A second positive electrode and a second negative electrode are formed respectively to conduct the second active region, thereby forming a second VCSEL unit on the second substrate. The first VCSEL unit and the second VCSEL unit are offset from each other in the lateral direction set by the monolithic integrated VCSEL chip. The first VCSEL unit is configured to project a laser with a first wavelength. The second VCSEL unit is configured to project a laser with a second wavelength, wherein the first wavelength is different from the second wavelength, and the range of the first wavelength is 600nm to 1000nm, and the range of the second wavelength is 1100nm to 1300nm. The first VCSEL unit and the second VCSEL unit are formed at different height positions in the height direction set by the monolithic integrated VCSEL chip to reduce the interference between the laser projected by the first VCSEL unit and the laser projected by the second VCSEL unit; the height difference between the first VCSEL unit and the second VCSEL unit in the height direction set by the monolithic integrated VCSEL chip is 5um to 10um, and the height difference is related to the height of the first P-DBR layer of the first VCSEL unit and the height configuration of the second substrate.

13. The preparation method according to claim 12, wherein, The lateral spacing between the first VCSEL unit and the second VCSEL unit is 10um to 200um.

14. The preparation method according to claim 13, wherein, The spacing between the first VCSEL unit and the second VCSEL unit is 10µm to 20µm.

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