System comprising a plurality of units

Abstract

A system comprising: a first unit and one or more second units. The first unit comprising: a timing reference configured to provide a master timing reference signal; a master time block configured to provide a master time signal of the first unit based on the master timing reference signal; and a first interface configured to: receive a time-stamped processed second RF signal from the one or more second units; and provide a first unit timing signal to the one or more second units based on the master time signal. The one or more second units each comprising: a slave time block configured to: determine a slave time signal of a second unit based on a master timing reference signal; determine one or more second timing values based on the slave time signal; determine an adjustment time based on the first unit timing signal received from the first unit and the second timing values; and adjust the slave time signal based on the adjustment time.

Description

Technical Field

[0001] This disclosure relates to a system having multiple elements, each element having an antenna. Such systems can be used to apply phase diversity schemes in some, but not all, instances. Background Technology

[0002] This relates to the use of high-speed interface-based sampling time alignment for phase diversity systems. Summary of the Invention

[0003] According to a first aspect of this disclosure, a system is provided, comprising:

[0004] Unit 1; and

[0005] One or more second units;

[0006] The first unit includes:

[0007] A first antenna, configured to receive a first RF signal;

[0008] A first signal processing block is configured to process the first RF signal in order to provide a processed first RF signal;

[0009] A timing reference, configured to provide a master timing reference signal;

[0010] A master time block, configured to provide the master time signal for the first unit based on the master timing reference signal;

[0011] A first timestamp processor is configured to apply timestamps to the processed first RF signal based on the master time signal in order to provide a timestamped processed first RF signal.

[0012] The first interface is configured as follows:

[0013] Receive a timestamped processed second RF signal from the one or more second units; and

[0014] The first unit timing signal is provided to the one or more second units based on the main time signal;

[0015] Each of the one or more second units includes:

[0016] A second antenna, configured to receive a second RF signal;

[0017] A second signal processing block is configured to process the second RF signal in order to provide a processed second RF signal;

[0018] From the time block, the time block is configured to:

[0019] Receive the main timing reference signal;

[0020] The slave time signal of the second unit is determined based on the master timing reference signal;

[0021] One or more second timing values ​​are determined based on the time signal;

[0022] The adjustment time is determined based on the timing signal received from the first unit and the second timing value; and

[0023] The time signal is adjusted based on the adjustment time;

[0024] A second timestamp processor is configured to apply a timestamp to the processed second RF signal based on the time signal to provide a timestamped processed second RF signal; and

[0025] The second interface is configured as follows:

[0026] The timestamped processed second RF signal is provided to the first unit; and

[0027] Receive the timing signal from the first unit;

[0028] The system is configured to provide the timestamped processed first RF signal and the timestamped processed second RF signal from the one or more second units for further processing.

[0029] Advantageously, this system can utilize a shared reference signal (master timing reference signal) to process time-aligned samples and can provide fully aligned, timestamped processed RF signals for precise time information exchange.

[0030] In one or more embodiments, the system further includes a processor configured to combine a timestamped processed first RF signal with timestamped processed second RF signals from one or more second units to provide a combined RF signal.

[0031] In one or more embodiments, the processor is a baseband processor.

[0032] In one or more embodiments, the processor is configured to use phase diversity to combine a timestamped processed first RF signal with a timestamped processed second RF signal from one or more second units in order to provide a combined RF signal.

[0033] In one or more embodiments, the time block is configured to determine one or more second timing values ​​by: storing the value of the time signal when the second unit sends a request signal to the first unit; and / or storing the value of the time signal when the second unit receives a timing signal from the first unit.

[0034] In one or more embodiments, the first unit timing signal includes one or more first timing values, said one or more first timing values ​​including one or two of the following: the value of the master time signal when an earlier request signal is received from one or more second units; and the value of the master time signal when the first unit transmits an earlier first unit timing signal to one or more second units.

[0035] In one or more embodiments, the slave time block is configured to add an adjustment time to the master timing reference signal or subtract it from the master timing reference signal in order to adjust the slave time signal.

[0036] In one or more embodiments, the first unit timing signal provided by the first unit includes:

[0037] t2, where t2 is the value of the main time signal at the time (t2) when an earlier request signal is received from one or more second units; and / or

[0038] t3, where t3 is the value of the master time signal at the time (t3) when the first unit transmits an earlier first unit timing signal to one or more second units.

[0039] In one or more embodiments, each of one or more second units is configured to:

[0040] Store t1 as a second timing value, where t1 is the value of the slave time signal when the second unit transmits the earlier request signal; and / or

[0041] Store t4 as a second timing value, where t4 is the value of the slave time signal when the second unit receives an earlier timing signal from the first unit.

[0042] The time block can be configured to determine the adjustment time based on t1, t2, t3, and t4.

[0043] In one or more embodiments, the first interface and the second interface are high-speed interfaces. The high-speed interface may be a standard high-speed interface.

[0044] In one or more embodiments:

[0045] The first unit includes a time alignment block configured to adjust the processed first RF signal using the master time signal to perform subsample time alignment; and / or

[0046] The second unit includes a time alignment block configured to adjust the processed second RF signal using the time signal to perform subsample time alignment.

[0047] In one or more embodiments:

[0048] The first timestamp processor is configured to apply the timestamp as metadata to the processed first RF signal; and / or

[0049] The second timestamp processor is configured to apply the timestamp as metadata to the processed second RF signal.

[0050] In one or more embodiments, the maximum deviation between the master timing reference signal and the target frequency / time period is + / - 50 ppm.

[0051] In one or more embodiments, the master time signal and the slave time signal have the same resolution.

[0052] In one or more embodiments, the first signal processing block and the second signal processing block each include an ADC, such that the processed first RF signal and the processed second RF signal are digital signals.

[0053] According to another aspect of this disclosure, a method is provided comprising:

[0054] About Unit 1:

[0055] Receive the first RF signal;

[0056] Process the first RF signal to provide a processed first RF signal;

[0057] The timing reference provides the main timing reference signal;

[0058] The main time signal of the first unit is provided based on the main timing reference signal;

[0059] The timestamp is applied to the processed first RF signal based on the main time signal in order to provide a timestamped processed first RF signal;

[0060] Receive a timestamped processed second RF signal from one or more second units; and

[0061] The first unit timing signal is provided to the one or more second units based on the main time signal;

[0062] Regarding one or more second units:

[0063] Receive the second RF signal;

[0064] Process the second RF signal to provide a processed second RF signal;

[0065] Receive the main timing reference signal;

[0066] The slave time signal of the second unit is determined based on the master timing reference signal;

[0067] One or more second timing values ​​are determined based on the time signal;

[0068] The adjustment time is determined based on the timing signal received from the first unit and the second timing value; and

[0069] The time signal is adjusted based on the adjustment time;

[0070] The timestamp is applied to the processed second RF signal based on the time signal to provide a timestamped processed second RF signal;

[0071] The timestamped processed second RF signal is provided to the first unit; and

[0072] Receive the timing signal from the first unit;

[0073] The method further includes:

[0074] The timestamped processed first RF signal and the timestamped processed second RF signal from the one or more second units are provided for further processing.

[0075] While this disclosure allows for various modifications and alternatives, details of this disclosure have been illustrated by way of example in the accompanying drawings and will be described in detail. However, it should be understood that other embodiments besides the specific embodiments described may exist. All modifications, equivalents, and alternative embodiments falling within the spirit and scope of the appended claims are also covered.

[0076] The foregoing discussion is not intended to represent every exemplary embodiment or every implementation within the scope of the present or future claims. Various exemplary embodiments are further illustrated in the following figures and detailed descriptions. A more comprehensive understanding of these various exemplary embodiments can be achieved by considering the following detailed descriptions in conjunction with the accompanying drawings. Attached Figure Description

[0077] One or more embodiments will now be described with reference to the accompanying drawings, by way of example only, in which:

[0078] Figure 1 An example embodiment of a system including a first unit and one or more second units is shown;

[0079] Figure 2 This shows how timing information can be displayed. Figure 1 The timing diagram for the exchange between the first and second units;

[0080] Figure 3 Provides clock alignment Figure 2 Another schematic illustration of the timing diagram overview; and

[0081] Figure 4 Example implementations of an integrated circuit (IC) associated with a first unit and an integrated circuit (IC) associated with a second unit are shown. Detailed Implementation

[0082] Examples disclosed herein relate to the use of high-speed interface-based sampling time alignment for use in phase diversity systems. Advantageously, such examples can establish reliable real-time subsample and sample alignment in radio frequency broadcasting system applications, but the examples disclosed herein are not limited to such applications. Such examples can be considered as synchronous preprocessing systems that can be used to implement subsequent baseband processing for combining digitized signals from two different antennas.

[0083] Figure 1 An example embodiment of a system 100 including a first unit 102 and one or more second units 104, 106 is shown. In this example, there are two second units 104, 106, but it should be understood that in other examples, any number of second units may be present. As will be discussed in detail below, each of the units 102, 104, 106 has an antenna for receiving signals. In one application, these antennas may be located at different locations on a vehicle and may be used to receive FM radio signals. Using such multiple antennas can be advantageous if the signal received at one or more of the antennas is weak while the signal received at another of the antennas is strong. In this case, an antenna diversity scheme can be employed to achieve reliable signal reception of acceptable quality.

[0084] First unit 102 includes a first antenna 108 that receives a first radio frequency (RF) signal. The first antenna 108 is connected to a first signal processing block 110, such that the first signal processing block 110 processes the first RF signal to provide a processed first RF signal 112. The processed first RF signal 112 may include a series of data packets / symbols received at the first antenna 108. In this example, the first signal processing block 110 includes an RF receive chain 128, an RF analog-to-digital converter (ADC), and a preprocessing block 132. It should be understood that the required functionality of the first signal processing block 110 will depend on the application of system 100, and therefore the components included in the first signal processing block 110 may be selected accordingly. In the example where the first signal processing block 110 includes an ADC, the processed first RF signal 112 may be a digital signal.

[0085] The first unit 102 also includes a timing reference that provides a master timing reference signal. The master timing reference signal can be very accurate and has a high frequency, and therefore the timing reference can also be considered a precise timing reference. If the master timing reference signal is based on a crystal oscillator, the accuracy / maximum deviation from the target frequency / time period can be + / - 50 ppm (parts per million), including aging / temperature drift / manufacturing tolerances.

[0086] In this example, a timing reference is provided as oscillator 114, which in this example is a crystal oscillator. Oscillator 114 is connected to an external crystal 134. Oscillator 114 provides a master oscillator signal (which is an example of a master timing reference signal), which, as will be discussed below, is used by each of the first unit 102 and the second units 104, 106.

[0087] The first unit 102 includes a main time block 116 that provides the main time signal of the first unit 102 based on the main oscillator signal provided by the oscillator 114. The main time signal is... Figure 1 It is schematically shown as number 117 and is used by various blocks / modules of the first unit 102, including for setting a timestamp associated with the time of receiving or transmitting a signal at or from the first unit 102.

[0088] A first timestamp processor 118 is also included as part of the first unit 102. The first timestamp processor 118 can apply a timestamp to the processed first RF signal 112 based on a master time signal to provide a timestamped processed first RF signal 120. For example, the first timestamp processor 118 can add the value of the master time signal 117 as a timestamp at the moment it receives the processed first RF signal 112. In some examples, the timestamp can be included as metadata of the processed first RF signal 112. In this way, the first timestamp processor 118 can tag the sample stream with absolute time information.

[0089] In this example, the first timestamp processor 118 includes a calculator 119 for calculating time alignment and timestamps. The first timestamp processor 118 also includes a time alignment block 124. The calculator 119 provides the functionality of a time alignment extraction unit, which compares the timing information of the input stream (derived from the first RF signal) with the master time signal 117 (i.e., the master time of the processing system). The time alignment block 124 then adjusts the processed first RF signal 112 (in this example, a digitized RF baseband sample stream) against the master time signal 117. Advantageously, the resolution of the master time signal 117 is sufficient for the time alignment block 124 to perform subsample time alignment. That is, the time alignment block 124 can perform subsample grid-based adjustments to the processing chain of the first unit 102.

[0090] The first unit 102 further includes a first interface 122 for communicating with one or more second units 104, 106. The first interface 122 of the first unit 102 can communicate directly with each of the second units 104, 106, or indirectly with one or more of the second units 104, 106. Figure 1 In the example, the first interface 122 communicates directly with the second unit 104 labeled "System Unit 2" and indirectly with the second unit 106 labeled "System Unit x" (and any intermediate units located between "System Unit 2" 104 and "System Unit" 106).

[0091] The first interface 122 receives a timestamped processed second RF signal from one or more second units 104, 106. The timestamped processed second RF signal is similar to the timestamped processed first RF signal 120 and is expected to represent the same data as the timestamped processed first RF signal 120. In this way, the first unit 102 can combine timestamped processed RF signals received at different antennas in any manner known in the art to improve the quality and reliability of signal reception.

[0092] For reference Figure 2In detail, the first interface 122 can provide a first unit timing signal based on the master time signal 117 to one or more second units 104, 106. The first unit timing signal may include one or more first timing values. The one or more first timing values ​​may include one or both of the following: the value of the master time signal 117 when an earlier request signal is received from one or more second units 104, 106; and the value of the master time signal 117 when the first unit 102 transmits an earlier first unit timing signal to one or more second units 104, 106. (The request signal will be described below.) In this way, one or more second units 104, 106 can determine the offset between their local time signal (which will be described below as slave time signal 142) and the master time signal 117 of the first unit 102.

[0093] In this example, each of units 104 and 106 in the second unit is the same. Therefore, we will only describe one of the units, 104; the one labeled "System Unit 2".

[0094] The second unit 104 includes a second antenna 136 for receiving a second RF signal. As indicated above, although the signal strength may be higher or lower due to the different positions of the first antenna 108 and the second antenna 136, the second RF signal is expected to represent the same data as the first RF signal.

[0095] The second unit 104 includes a second signal processing block 138 capable of processing the second RF signal to provide a processed second RF signal 148. In this example, the second signal processing block 138 includes the same components as the first signal processing block 110.

[0096] The second unit 104 further includes a slave time block 140 that receives a master oscillator signal from the oscillator 114 of the first unit 102. The slave time block 140 can receive the master oscillator signal via any communication link, whether wired or wireless, between the first unit 102 and the second unit 104. In some examples, the slave time block 140 can receive the master oscillator signal at a second (high-speed) interface 146 of the second unit 104, which can communicate with a first (high-speed) interface 122 of the first unit 102. The slave time block 140 determines the slave time signal of the second unit 104 based on the master oscillator signal. The slave time signal in... Figure 1 It is illustrated schematically using number 142.

[0097] The second unit 104 also includes a time adjuster 156. In this example, the time adjuster 156 is shown as part of the time block 140. The time adjuster 156 determines one or more second timing values ​​based on the time signal 142, and can subsequently determine the adjustment time based on the first unit timing signal received from the first unit 102 and the second timing values. (See reference...) Figure 2 As discussed in detail below, the time adjuster 156 may determine one or more second timing values ​​by: storing the value from the time signal 142 when the second unit 104 sends a request signal to the first unit 102; and / or storing the value from the time signal 142 when the second unit 104 receives a first unit timing signal from the first unit 102.

[0098] Then, the time adjuster 156 can adjust the time signal 142 based on the adjustment time, as referenced. Figure 2 To elaborate further. For example, as will be discussed below, time adjuster 156 can add or subtract adjustment time from the master oscillator signal to adjust slave time signal 142. In this way, slave time signal 142 can be adjusted so that it is fully aligned with master time signal 117 of first unit 102.

[0099] In this example, the slave time block 140 includes a clock buffer 141 that receives and stores the master oscillator signal from the oscillator 114 of the first unit 102, such that the slave time signal 142 can be provided based on the stored / buffered master oscillator signal. The clock buffer 141 may have a reference crystal quality for receiving and transmitting, such that the resolution and accuracy of the slave time signal 142 can match the resolution and accuracy of the master time signal 117.

[0100] like Figure 1 As shown, any subsequent second unit 106 can receive the master oscillator signal from an earlier second unit 104 in the chain of second units 104—in this example, from the clock buffer 141 of the earlier second unit 104. In other examples, each second unit 104 can be directly connected to the first unit 102 to directly receive the master oscillator signal.

[0101] The second unit 104 also includes a second timestamp processor 144, which can apply a timestamp to the processed second RF signal 148 based on a time signal to provide a timestamped processed second RF signal 150. In this example, the second timestamp processor 144 is implemented in the same manner as the first timestamp processor 118, wherein the second timestamp processor 144 includes a calculator 152 and a time alignment block 154.

[0102] The second unit 104 further includes a second interface 146 that provides a timestamped processed second RF signal 150 to the first unit 102. In this manner, the first unit 102 can receive and combine timestamped processed second RF signals 150 from one or more second units 104 in any manner known in the art. The second interface 146 also receives a first unit timing signal from the first unit 102, such that the time adjuster 156 of the second unit 104 can use the first unit timing signal to calculate the adjustment time, as discussed in more detail below.

[0103] Then, Figure 1 The system 100 can provide a timestamped processed first RF signal 120 and a timestamped processed second RF signal 150 from one or more second units 104 for further processing. (As will be described below) Figure 1 In the case described above, such additional processing can be performed by components / modules of system 100. Alternatively, system 100 may simply provide synchronized, timestamped processed RF signals 120, 150 as output of system 100, such that the synchronized, timestamped processed RF signals 120, 150 can be processed by a remote device.

[0104] exist Figure 1 In this example, further processing of the timestamped processed RF signals 120, 150 is performed by a processor associated with system 110. In this example, the processor is a baseband processor 126 associated with the first unit infrastructure 102. The baseband processor 126 combines the timestamped processed first RF signal 120 with timestamped processed second RF signals 150 from one or more second units 104, 106 to provide a combined RF signal 158. For example, the baseband processor 126 can implement a phase diversity system by using phase diversity to combine the timestamped processed RF signals. In this way, the baseband processor 126 can perform sample raster-based adjustments for each sample stream using timestamps.

[0105] Figure 1 System 100 can be considered a fully aligned sampling system, which includes the exchange of a master timestamp and a local timestamp between units in the system to achieve precise time information exchange. System 100 may also involve adjusting the local clock relative to the master clock, adjusting each processing chain based on a subsample grid using local clock information and master clock information, and adjusting each sample stream based on a sample grid using timestamps.

[0106] The first interface 122 and the second interface 146 can be high-speed interfaces, having a structure that supports precise time measurement and transmission protocols for digital RF baseband samples, including timestamps (to limit system connectivity resources). Advantageously, the first interface 122 and the second interface 146 can be standard high-speed interfaces; that is, the first interface 122 and the second interface 146 do not need to be dedicated interfaces. This greatly facilitates ease of implementation. Figure 1 System 100. In some applications, the timestamps and timing information disclosed herein, as well as the processed RF signals exchanged between units 102, 104, and 106, may be directly included to implement... Figure 1 An improved system.

[0107] Advantageously, the time resolution of the master time signal 117 (provided by master time block 116) is the same as the time resolution of the slave time signal 142 (provided by slave time block 140). This ensures that any time alignment performed at the first unit 102 and the second units 104, 106 has the same resolution. It also ensures that the timestamps provided by each of the first unit 102 and the second units 104, 106 have the same resolution.

[0108] Figure 2 This shows how timing information can be displayed. Figure 1 The timing diagram for the exchange between the first unit and the second unit. Figure 2 An example of a precise time protocol implemented using a request-response communication system is shown.

[0109] exist Figure 2 The top of the symbol indicates the downstream port of the first interface of the first unit, where the main time signal 217 provides timing information for the timestamp / timing value provided by the first unit. Figure 2 In this context, the master time signal 217 is marked as the precise time (PT) master time.

[0110] exist Figure 2 The bottom indicates the upstream port of the second interface of the second unit, where timing information, including the timestamp / timing value provided by the second unit, is obtained from the time signal 242. Figure 2 In this example, the local time, marked as precise time (PT), is derived from time signal 242. For the subsequent calculations, it is assumed that time signal 242 is less than master time signal 217. However, it should be understood that if this is not the case, or if the value of the time signal is offset by the second unit, the calculation will be directly adjusted so that the time signal is less than master time signal 217.

[0111] As will now be discussed, the downstream port of the first interface and the upstream port of the second interface exchange messages, enabling the adjustment of the slave time signal 242 to better align the slave time signal 242 with the master time signal 217. This includes the downstream port of the first interface (refer to...) Figure 1 The first unit's timing signal is sent to the upstream port of the second interface.

[0112] Figure 2 A first request signal 260 is shown, which is sent from the second unit to the first unit. In some examples, the first request signal is provided as part of a control flow separate from the delivery of processed RF signals received at the second unit. The second unit stores the time of transmission of the first request signal 260 as a second timing value t1. The second timing value t1 is the value of the slave time signal 242 (i.e., the local time at the second unit) when the second unit transmits the request signal. This first request signal 260 can be considered a precision time (PT) request in this context.

[0113] In response to the first request signal 260, the first unit sends a first first unit timing signal 262 back to the second unit. The first unit timing signal includes the following information (however, not all of this information is available for the first first unit timing signal 262):

[0114] ·t2 n-1 The t2 n-1 The value of the master time signal 217 when the earlier request signal is received from the second unit;

[0115] ·t2 n The t2 n The value of the master time signal 217 when the latest request signal is received from the second unit; and

[0116] ·t3 n-1 The t3 n-1 The value of the main time signal 217 is the time (t3) at which the earlier timing signal from the first unit is transmitted to the second unit.

[0117] Here, 'n' represents the current PT request signal and first unit timing signal pair, and 'n-1' represents the previous PT request signal and first unit timing signal pair, making it possible to identify the relative timing of the signals in the timing diagram. In the diagram, each PT request signal and first unit timing signal pair is marked with an increasing number of superscript symbols to indicate the absolute position of the signal in the timing diagram.

[0118] For the first unit timing signal 262, t2 n-1 and t3 n-1The value cannot be used as part of the first unit timing signal 262. Therefore, the first unit timing signal 262 may only include t2. n .

[0119] After sending the first unit timing signal 262, the first unit stores:

[0120] ·t2 n The t2 n The value of the main time signal 217 at the time (t2) when the latest request signal is received from the second unit; and

[0121] ·t3 n The t3 n The value of the main time signal 217 is the time (t3) at which the latest first unit timing signal 262 is transmitted from the first unit to the second unit.

[0122] In response to receiving the first unit timing signal 262, the second unit stores:

[0123] ·t1 n The t1 n The value of the slave time signal 242 for the time (t1) at which the latest timestamped processed second RF signal (first request signal 260) is transmitted in the second unit;

[0124] ·t4 n The t4 n The value of slave time signal 242 at the time (t4) when the second unit receives the current first unit timing signal (first first unit timing signal 262) from the first unit; and

[0125] ·t2 n The t2 n It has been received from the first unit as part of the first unit timing signal, and is the value of the main time signal 217 at the time (t2) when the latest request signal is received from the second unit.

[0126] In this example, the first (PT) request signal 260 and the response message (i.e., the first unit timing signal 262) are used by the upstream port of the second unit to check whether the downstream port of the first unit supports the precise time protocol, and are also used to store the timing value / timestamp described above. That is, from the beginning to the end of the communication, and to receive the initial timestamp from the downstream port.

[0127] We will now move to the second PT request signal and the first unit timing signal pair (signals labeled 264 and 266). The timing of these signals is... Figure 2 The symbol is t1′-4′, and will now be referred to as t1-4. nThe timing of the current signal is used to reflect the timing of the aforementioned timing. The timing of the first signal (signals labeled 260 and 262) will be referred to as t1. n-1 -4 n-1 The timing is to reflect the timing of the previous pair of signals.

[0128] Figure 2 The second request signal 264, which can be embodied as a second example of a timestamped processed second RF signal, is sent from the second unit to the first unit. The second unit stores the time of transmission of the second request signal 264 as t1 according to the time signal 242 (i.e., the local time at the second unit). n (t1′ in the attached figure).

[0129] In response to the second request signal 264, the first unit sends a second first unit timing signal 266 back to the second unit. The second first unit timing signal 266 includes:

[0130] ·t2 n-1 (t2 in the attached figure), the t2 n-1 The value of the master time signal 217 when the earlier request signal is received from the second unit;

[0131] ·t2 n (t2′ in the attached figure), the t2 n The value of the master time signal 217 when the latest request signal is received from the second unit; and

[0132] ·t3 n-1 (t3 in the attached figure), the t3 n-1 This is the value of the main time signal 217 when the first unit transmits the earlier first unit timing signal to the second unit.

[0133] After sending the second timing signal 266 from the first unit, the first unit stores:

[0134] ·t2 n The t2 n The value of the main time signal 217 at the time (t2′) when the latest request signal is received from the second unit; and

[0135] ·t3 n The t3 n The value of the main time signal 217 is the time (t3′) at which the latest first unit timing signal 262 is transmitted from the first unit to the second unit.

[0136] In response to receiving the second timing signal 266 from the first unit, the second unit stores:

[0137] ·t1 n The t1n The value of the slave time signal 242 for the time (t1′) at which the latest timestamped processed second RF signal (second request signal 264) is transmitted in the second unit;

[0138] ·t4 n The t4 n The value of slave time signal 242 is the time (t4′) at which the second unit receives the current timing signal of the first unit (the second timing signal 262 of the first unit) from the first unit;

[0139] ·t2 n The t2 n The value of the main time signal 217, received from the first unit as part of the second first unit timing signal, and being the time (t2′) at which the latest timestamped processed second RF signal is received from the second unit; and

[0140] ·t3 n-1 The t3 n-1 It has been received from the first unit as part of the second first unit timing signal, and is the value of the main time signal 217 at the time (t3) when the latest timestamped processed second RF signal is received from the second unit.

[0141] The second (PT) request signal 264 and the response message (second first unit timing signal 266) are used to retrieve two historical timestamps (t2 and t3) of the first message and the actual downstream port timestamp at the time point (t2′) when the request message was received.

[0142] The second unit now has a complete set of timing information (t1) of the earlier PT first timing signal and the first unit timing signal pair. n-1 t2 n-1 t3 n-1 t4 n-1 (Timing is labeled t1-t4 in the attached diagram). The second unit (and more specifically, in some examples, the time adjuster of the second unit) may be based on t1. n-1 t2 n-1 t3 n-1 t4 n-1 To determine the adjustment time. That is, the second unit can determine the amount from the timing signal that should be adjusted so that the timestamps applied to the processed first RF signal and the processed second RF signal are accurately aligned. Accurately aligning these timestamps makes it possible (in...) Figure 1 In the example, (by the baseband processor) at the sample raster level and (in Figure 1 In the example, the time-aligned block accurately processes the signal at both the subsample raster level and the subsample raster level.

[0143] exist Figure 2In the example, assuming a symmetrical TX / RX high-speed serial interface is used to transmit signals between the downstream port of the first unit and the upstream port of the second unit, the link delay can be calculated by dividing the difference between (t4-t1) and (t3-t2) by 2. That is:

[0144] Link delay / latency: t_lat = [(t4-t1)-(t3-t2)] / 2

[0145] It should be understood that asymmetric interface connections can be mitigated by measuring a fixed delay in the application of the system and then adding that fixed delay as a configuration parameter to the system.

[0146] Based on the determined link delay (t_lat), the value of the main time signal at the downstream port of the first unit when the second request signal 264 is sent by the second unit can be determined at the second unit using the received timestamp t2′ and the calculated link delay including the protocol delay (t_lat).

[0147] The principal time of PT at t1′ is: t1′_M = t2′ - t_lat

[0148] The adjustment time (t4′_adj) can then be calculated as follows:

[0149] PT local time adjustment: t4′_adj=t4′-(t1′_M-t1′)

[0150] In this way, the adjustment time (t4′_adj) represents the amount by which the slave time signal 242 is offset from the master time signal 217. The second unit can then use the determined adjustment time (t4′_adj) to update the slave time signal 242 (e.g., by adding or subtracting the offset based on the adjustment time (t4′_adj)) so that the value of the adjustment time (t4′_adj) decreases for subsequent iterations. (In...) Figure 2 The upper right side schematically shows subsequent iterations, where timing values ​​are marked with double superscript symbols (e.g., tl″) under the heading "Protocol continues to be optional". It should be understood that such additional iterations are not essential, but in some applications, these additional iterations can be used to increase the accuracy of the determined adjustment time, especially when the offset between the master timing signal and the slave timing signal varies over time.

[0151] It should be understood that the calculations identified above are just one of many ways to calculate and adjust time based on various timings stored or transmitted.

[0152] Figure 3 Provides clock alignment Figure 2 Another schematic illustration of the timing diagram overview. Figure 3 middle, Figure 1The first unit is shown as a phase diversity (PD) master device 302, and Figure 1 The second unit is shown as a phase diversity (PD) slave device 304. A master time signal 317 is schematically shown with reference to the PD master device 302. A first value of the slave time signal 342a before the adjustment time has been calculated and applied is schematically shown with reference to the PD slave device 304. A second value of the slave time signal 342b after the adjustment time has been calculated and applied is schematically shown as having a different value from the slave time signal 342a before adjustment.

[0153] Advantageous, reference Figure 2 and 3 The described and illustrated processing utilizes a shared reference signal (master oscillator signal) along with a high-precision master clock and local clocks (master time signal and slave time signal) to handle samples of time alignment. In some applications, absolute time reference mismatches well below 100 ns can be achieved. The absolute accuracy of such systems is, of course, affected by implementation details (e.g., circuit clock speed and timer bit resolution), which should be tailored to the intended application of the system.

[0154] The applications of the system described in this article include (subsample) time alignment blocks (as referenced). Figure 1 As described, the timing alignment block supports challenging applications, such as phase diversity processing implemented by analog broadcast systems using two or more antenna input signals. A key objective of the timing alignment block unit is to pre-align all processing streams above the final sample raster processing level, thus achieving precise timing alignment below the threshold required for the envisioned application.

[0155] Figure 4 Example embodiments of an integrated circuit (IC) associated with the first unit 402 and an integrated circuit (IC) associated with the second unit 404 are shown. These example embodiments are provided to illustrate the accuracy achievable based on known or measured system delays.

[0156] Each of the two ICs, 402 and 404, has a high-speed interface (HS IF CTRL and PHY), a master clock unit or a local clock unit (correspondingly), and two Enable Generation Units (EGUs) for precise subsample grid processing stream alignment.

[0157] The fixed delay in such systems can be:

[0158] ·PT protocol master finite state machine,

[0159] The PT protocol originates from a finite state machine.

[0160] • High-speed interface link latency can be calculated via timestamps in the case of symmetrical connection or determined by measurements in the application.

[0161] Variable delays can be caused by design-dependent circuit domain boundaries and master clock resolution limitations or local clock resolution limitations. In this example, and due to fairly synchronous circuit operation, the remaining variable delay is:

[0162] • The resolution of the PT master clock and PT local clock when compensating for fixed delay.

[0163] • Jitter associated with the RF phase-locked loop (PLL)

[0164] • The PT master clock and local clock timer are sampled by the EGU sample timer.

[0165] The PT master clock and local clock are controlled by f 电路 The timer circuitry operating at 124.8MHz represents a timer circuit that limits any fixed delay compensation and adjusts for a maximum resolution of approximately 8ns. Jitter introduced by the high-speed interface reference PLL (RF PLL) is typically small and well below 1ns. Both the master PT clock and the local PT clock are transmitted to f 电路 The EGU sample timer operates at 166.4MHz within the processing domain. This introduces cross-domain sampling uncertainty, including approximately 2*6ns of sampling effect recovery.

[0166] Then, the total worst-case deviation between the processing streams is approximately 21 ns. Considering that the absolute timing mismatch is less than 100 ns suitable for phase diversity processing systems, this example implementation leaves a very good margin for even less synchronization implementations at reasonable circuit design operating speeds.

[0167] An example application applicable to the high-speed interfaces described herein is Peripheral Component Interconnect High Speed ​​(PCIe) and its associated Precision Time Measurement (PTM) protocol, as added to the PCIe Foundation Specification 3.0 and fully embedded in the PCIe standard of December 7, 2015. As described in the Engineering Change Notice (ECN) in Basic Specification Amendment 3.1a.

[0168] As demonstrated by the examples disclosed herein, by using a standardized, precise time-sharing mechanism via a high-speed serial interface, it is possible to represent absolute time across several system components / units while remaining within the elements of standard interface technologies.

[0169] Advantageously, the examples disclosed herein enable digital signal processing (DSP) software to satisfactorily implement the subsample-to-sample alignment required for phase diversity processing in a direct manner. Adjusting the master time and / or local time using the same shared crystal-based reference signal establishes a robust and stable time base across all system application components / units.

[0170] Aspects of this disclosure may include:

[0171] • A precise timing information sharing mechanism based on a high-speed interface is used in phase diversity processing to simulate multiple antenna configurations in a radio receiving system.

[0172] • In distributed broadcast processing systems, a shared reference signal is used for the generation of master time and local time.

[0173] • Introducing a master time and local time scheme that uses exactly the same granularity / time resolution to combine different antenna signals, and

[0174] • Adjust the distributed broadcast processing system to an absolute time base.

[0175] Advantageously, the examples disclosed herein do not rely on proprietary vendor-specific implementations for exchanging absolute time information in broadcast applications. Instead, standard interfaces can be used to exchange time information, for example, by exchanging timestamps / timing values ​​as request signals and first unit timing signals. The request signals and / or first unit timing signals can be provided as metadata, thus advantageously enabling the use of standard interfaces. Furthermore, there is no need to capture interface latency in an adjustment or calibration manner. This is because the systems disclosed herein can exchange time information (e.g., using exchange protocols such as PCIe PTM) to allow for automatic latency adjustment.

[0176] One or more of the examples disclosed herein may: use high-speed interface for precise time sharing for broadcast-related applications; use precise time sharing in conjunction with a high-precision reference signal within a distributed system; and may include a subsample alignment mechanism based on the use of transmitted precise master time information and local clock information, the subsample alignment mechanism including system delays introduced by the high-speed interface without any calibration.

[0177] The examples disclosed in this paper can be used as part of a broadcast tuner system for automotive entertainment applications. Due to several factors, such as automotive design, broadcast receiver antennas are moving into a technically less advantageous position in today's automotive designs. Therefore, combining the signals from two or more antennas in phase diversity processing may be particularly important for many automakers. Furthermore, very stringent timing requirements can be applied, making precise subsample and sample time alignment processing in these systems a key enabler for such applications. By using standardized interfaces and protocols for the necessary alignment steps, it is possible to build such challenging real-time-critical applications on reliable and well-known interface technologies.

[0178] This document discloses a system for aligning digitized broadcast signals with different antenna sources for subsequent phase diversity processing. The system uses a high-speed interface-based timestamping method and a calibration-free reference signal as the origin for aligning the master clock with the local clock, allowing for signal adjustment at the sub-sample and sample time granularity. The system can be used in consumer and automotive broadcast receiver systems and is scalable to various antenna configurations.

[0179] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the above diagrams may be performed in any order. Furthermore, those skilled in the art will recognize that while an example set of instructions / methods has been discussed, the material in this specification can be combined in various ways to produce other examples, and should be understood within the context of the detailed description provided herein.

[0180] In some example embodiments, the instruction set / method steps described above are implemented as functional and software instructions embodied in an executable instruction set, which is implemented on a computer or a machine programmed and controlled with said executable instructions. Such instructions are loaded for execution on a processor (e.g., one or more CPUs). The term processor includes a microprocessor, microcontroller, processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing device. A processor may refer to a single component or multiple components.

[0181] In other examples, the instruction sets / methods illustrated herein, along with their associated data and instructions, are stored in appropriate storage devices, which are implemented as one or more non-transitory machine- or computer-readable or computer-usable storage media. Such computer-readable or computer-usable storage media are considered part of an article (or article of manufacture). An article or article of manufacture can refer to any single or multiple components manufactured. Non-transitory machine- or computer-usable media as defined herein do not include signals, but such media are capable of receiving and processing information from signals and / or other transient media.

[0182] Example embodiments of the materials discussed in this specification may be implemented, wholly or in part, via networks, computers, or data-based devices and / or services. These may include cloud, Internet, intranet, mobile devices, desktop computers, processors, lookup tables, microcontrollers, consumer devices, infrastructure, or other enabling devices and services. As may be used herein and in the claims, the following non-exclusive limitations are provided.

[0183] In one example, one or more instructions or steps discussed in this article are automated. The terms automation or automaticity (and similar variations) mean the use of computers and / or mechanical / electrical devices to control the operation of equipment, systems, and / or processes without human intervention, observation, effort, and / or decision-making.

[0184] It should be understood that any components that are alleged to be coupled can be coupled or connected directly or indirectly. In the case of indirect coupling, an additional component may be placed between the two components that are alleged to be coupled.

[0185] In this specification, exemplary embodiments have been presented with respect to a selected set of details. However, those skilled in the art will understand that many other exemplary embodiments, including different selected sets of these details, can be practiced. It is intended that the appended claims cover all possible exemplary embodiments.

Claims

1. A time synchronization system, characterized in that, include: Unit 1; as well as One or more second units; The first unit includes: A first antenna, configured to receive a first RF signal; A first signal processing block is configured to process the first RF signal in order to provide a processed first RF signal; A timing reference, configured to provide a master timing reference signal; A master time block, configured to provide the master time signal for the first unit based on the master timing reference signal; A first timestamp processor is configured to apply timestamps to the processed first RF signal based on the master time signal in order to provide a timestamped processed first RF signal. The first interface is configured as follows: Receive a timestamped processed second RF signal from the one or more second units; and The first unit timing signal is provided to the one or more second units based on the main time signal; Each of the one or more second units includes: A second antenna, configured to receive a second RF signal; A second signal processing block is configured to process the second RF signal in order to provide a processed second RF signal; From the time block, the time block is configured to: Receive the main timing reference signal; The slave time signal of the second unit is determined based on the master timing reference signal; One or more second timing values ​​are determined based on the time signal; The adjustment time is determined based on the timing signal received from the first unit and the second timing value; and The time signal is adjusted based on the adjustment time; A second timestamp processor is configured to apply a timestamp to the processed second RF signal based on the time signal to provide a timestamped processed second RF signal; and The second interface is configured as follows: The timestamped processed second RF signal is provided to the first unit; and Receive the timing signal from the first unit; The system is configured to provide the timestamped processed first RF signal and the timestamped processed second RF signal from the one or more second units for further processing.

2. The system according to claim 1, characterized in that, The system further includes a processor configured to combine the timestamped processed first RF signal with the timestamped processed second RF signal from the one or more second units to provide a combined RF signal.

3. The system according to claim 2, characterized in that, The processor is a baseband processor.

4. The system according to claim 2 or claim 3, characterized in that, The processor is configured to use phase diversity to combine the timestamped processed first RF signal with the timestamped processed second RF signal from the one or more second units in order to provide a combined RF signal.

5. The system according to any one of claims 1-3, characterized in that, The slave time block is configured to determine the one or more second timing values ​​by: storing the value of the slave time signal when the second unit sends a request signal to the first unit; And / or when the second unit receives the timing signal from the first unit, it stores the value of the timing signal.

6. The system according to any one of claims 1-3, characterized in that, The first unit timing signal includes one or more first timing values, which include one or two of the following: the value of the master time signal when an earlier request signal is received from the one or more second units; and the value of the master time signal when the first unit transmits an earlier first unit timing signal to the one or more second units.

7. The system according to any one of claims 1-3, characterized in that, The slave time block is configured to add the adjustment time to the master timing reference signal or subtract it from the master timing reference signal in order to adjust the slave time signal.

8. The system according to any one of claims 1-3, characterized in that: The timing signal provided by the first unit includes: t2, where t2 is the value of the main time signal at the time (t2) when an earlier request signal is received from the one or more second units; and t3, where t3 is the value of the main time signal at the time (t3) when the first unit transmits an earlier first unit timing signal to the one or more second units; Each of the one or more second units is configured to: Store t1 as a first and second timing value, where t1 is the value of the slave time signal when the second unit transmits the earlier request signal; and Store t4 as a second timing value, where t4 is the value of the slave timing signal when the second unit receives the earlier timing signal from the first unit; and The time block is configured to determine the adjustment time based on t1, t2, t3, and t4.

9. The system according to any one of claims 1-3, characterized in that, The first interface and the second interface are high-speed interfaces.

10. The system according to claim 9, characterized in that, The high-speed interface is a standard high-speed interface.

11. The system according to any one of claims 1-3, characterized in that: The first unit includes a time alignment block configured to adjust the processed first RF signal using the master time signal to perform subsample time alignment; and The second unit includes a time alignment block configured to adjust the processed second RF signal using the time signal to perform subsample time alignment.

12. The system according to any one of claims 1-3, characterized in that: The first timestamp processor is configured to apply the timestamp as metadata to the processed first RF signal; and The second timestamp processor is configured to apply the timestamp as metadata to the processed second RF signal.

13. The system according to any one of claims 1-3, characterized in that, The maximum deviation between the main timing reference signal and the target frequency or time period is + or -50 ppm.

14. The system according to any one of claims 1-3, characterized in that, The master time signal and the slave time signal have the same resolution.

15. A time synchronization method, characterized in that, include: About Unit 1: Receive the first RF signal; Process the first RF signal to provide a processed first RF signal; The timing reference provides the main timing reference signal; The main time signal of the first unit is provided based on the main timing reference signal; The timestamp is applied to the processed first RF signal based on the main time signal in order to provide a timestamped processed first RF signal; Receive a timestamped processed second RF signal from one or more second units; and The first unit timing signal is provided to the one or more second units based on the main time signal; Regarding one or more second units: Receive the second RF signal; Process the second RF signal to provide a processed second RF signal; Receive the main timing reference signal; The slave time signal of the second unit is determined based on the master timing reference signal; One or more second timing values ​​are determined based on the time signal; The adjustment time is determined based on the timing signal received from the first unit and the second timing value. and The time signal is adjusted based on the adjustment time; The timestamp is applied to the processed second RF signal based on the time signal to provide a timestamped processed second RF signal; The timestamped processed second RF signal is provided to the first unit; and Receive the timing signal from the first unit; The method further includes: The timestamped processed first RF signal and the timestamped processed second RF signal from the one or more second units are provided for further processing.

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