Data processing method and device, electronic equipment and computer readable storage medium

Abstract

A data processing method, device, electronic equipment and computer readable storage medium are provided. The data processing method comprises: a processing core receiving a synchronization signal (301); the processing core determining, according to the synchronization signal, a first storage area used by a self task of the processing core and a second storage area used by a non-self task (302); the first storage area and the second storage area are different; the processing core accessing the first storage area to execute the self task and accessing the second storage area to execute the non-self task (303). By the above method, the storage areas corresponding to different tasks of the processing core are distinguished, and the technical problems of the prior art, such as complex data consistency processing mechanism and low processing efficiency caused by reading and writing of the same storage area, are solved.

Description

Technical Field

[0001] This disclosure relates to the field of neural network computing, and more particularly to a data processing method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] With the development of science and technology, human society is rapidly entering the intelligent era. A key characteristic of the intelligent era is that people are acquiring more and more types of data, the volume of data is increasing, and the demand for faster data processing is also rising.

[0003] Chips are the cornerstone of data processing, fundamentally determining our ability to process data. From an application perspective, chips mainly follow two paths: one is the general-purpose chip path, such as CPUs (central processing units), which offer great flexibility but have relatively low effective computing power when processing algorithms in specific domains; the other is the dedicated chip path, such as TPUs (Tensor Processing Units), which can exert high effective computing power in certain specific domains, but their processing power is relatively poor or even incapable of handling more general and flexible domains.

[0004] Because the data in the intelligent era is diverse and massive in quantity, chips are required to be highly flexible, capable of handling algorithms from different fields and constantly evolving, and also possess strong processing power, capable of rapidly processing extremely large and rapidly increasing amounts of data.

[0005] Multi-core architectures in existing technologies, such as Figure 1a As shown. In multi-core architectures (such as Symmetric Multi-Processor (SMP), there are generally two ways for data to be transferred between cores: Option 1: Data is transferred via shared memory. The sending core writes data to the shared memory, and then the receiving core reads the data from the shared memory. The process is as follows: Figure 1bAs shown. Scheme 1 has the following disadvantages: the data consistency handling mechanism is relatively complex; the task order of the sending and receiving cores needs to be specially arranged, for example, the receiving core cannot read data before the sending core writes data; dedicated circuitry is required to ensure data consistency, such as adding memory locks. When the sending core writes data to the shared memory, the memory is locked with the lock signal S_Locked, preventing any other core from operating on this shared memory. When the receiving core reads data from the shared memory, the shared memory is locked with the lock signal D_Locked, preventing any other core from operating on the shared memory; a dedicated program is needed to handle data consistency, for example, the receiving core needs to check whether the shared memory is locked before reading data, and can only read data if the shared memory is not locked; data needs to be transferred once in the shared memory, adding one more read / write operation.

[0006] Existing Solution 2: The sending core sends data to the mailbox of the receiving core. The mailbox of the receiving core is a fixed storage area within the receiving core, capable of receiving information from different sending cores. The process is as follows: Figure 1c As shown. Scheme 2 has the following disadvantages: the mailbox size is limited, which restricts the amount of data that the sending core can send; when the processing speeds of the receiving core and the sending core are inconsistent, the faster core needs to wait for the slower core, affecting the overall performance of the multi-core system; the receiving core needs to interrupt the currently executing program to process the received data, thus reducing the processing efficiency of the receiving core.

[0007] As can be seen from the two solutions above, the existing technologies for handling data consistency issues during data exchange between multiple cores suffer from complex data consistency processing mechanisms and low processing efficiency. Summary of the Invention

[0008] This summary section provides a brief overview of the concepts, which will be described in detail in the subsequent detailed description section. This summary section is not intended to identify key or essential features of the claimed technical solutions, nor is it intended to limit the scope of the claimed technical solutions. To address the problems of complex and inefficient data consistency processing mechanisms in the prior art when handling data exchange between multi-core processors, embodiments of this disclosure provide the following data processing methods, apparatus, electronic devices, and computer-readable storage media.

[0009] In a first aspect, embodiments of this disclosure provide a data processing method, including: Process the core to receive synchronization signals; The processing core determines the first storage area used by its own task and the second storage area used by non-its own task based on the synchronization signal; The first storage region is different from the second storage region; The processing core accesses the first storage area to perform its own task and accesses the second storage area to perform the non-self task.

[0010] The above scheme separates the storage areas corresponding to different types of tasks of the processing core in each synchronization signal, so that multiple tasks of the processing core can read and write different storage areas in parallel, without the need for a complex data consistency processing mechanism, thus improving the efficiency of the processing core.

[0011] Furthermore, the first storage area includes a plurality of first memories; the self-task includes a computation task and a transmission task, wherein the computation task and the transmission task use the same first memory; or the computation task and the transmission task use different first memories.

[0012] Furthermore, there are multiple sending tasks, each corresponding to a different or the same target processing core, and each sending task carries a tag of a storage area in the target processing core.

[0013] Furthermore, the second storage area includes a plurality of second memories; the non-self task includes at least one receiving task, and different receiving tasks use different second memories.

[0014] Furthermore, the different receiving tasks correspond to different or the same source processing cores.

[0015] Furthermore, before the processing core receives the synchronization signal, the following is also included: The processing core receives configuration information, which includes the task of the processing core in the synchronization period determined by each synchronization signal and the storage area corresponding to the task.

[0016] Secondly, embodiments of this disclosure provide a data processing method, including: Process the core to receive synchronization signals; The processing core performs computational tasks and receiving tasks during the synchronization period determined by the synchronization signal, wherein the data for the receiving task comes from the source processing core; The processing core accesses the first storage area to execute the computational task; The processing core receives the data transmitted by the source processing core and writes the data into the second storage area; The first storage area is different from the second storage area.

[0017] Furthermore, there are multiple source processing cores, and each processing core has multiple second storage areas corresponding to different or the same source processing core.

[0018] Thirdly, embodiments of this disclosure provide a data processing apparatus, including: Synchronization signal receiving module, used to process the synchronization signal received by the core; A storage area determination module is used for the processing core to determine, based on the synchronization signal, a first storage area used by the processing core for its own tasks and a second storage area used by tasks other than its own tasks; The first storage region is different from the second storage region; The task execution module is used by the processing core to access the first storage area to execute its own task and to access the second storage area to execute the non-own task.

[0019] Furthermore, the first storage area includes a plurality of first memories; the self-task includes a computation task and a transmission task, wherein the computation task and the transmission task use the same first memory; or the computation task and the transmission task use different first memories.

[0020] Furthermore, there are multiple sending tasks, each corresponding to a different or the same target processing core, and each sending task carries a tag of a storage area in the target processing core.

[0021] Furthermore, the second storage area includes a plurality of second memories; the non-self task includes at least one receiving task, and different receiving tasks use different second memories.

[0022] Furthermore, the different receiving tasks correspond to different or the same source processing cores.

[0023] Furthermore, the data processing device also includes: A configuration information receiving module is used for the processing core to receive configuration information, which includes the task of the processing core in the synchronization period determined by each synchronization signal and the storage area corresponding to the task.

[0024] Fourthly, embodiments of this disclosure provide a data processing apparatus, including: Synchronization signal receiving module, used to process the synchronization signal received by the core; The task determination module is used for the processing core to perform computation tasks and receiving tasks within the synchronization period determined by the synchronization signal, wherein the data of the receiving task comes from the source processing core; A computation task execution module is used for the processing core to access the first storage area to execute the computation task; A task execution module is provided for the processing core to receive data transmitted by the source processing core and write the data into a second storage area. The first storage area is different from the second storage area.

[0025] Furthermore, there are multiple source processing cores, and each processing core has multiple second storage areas corresponding to different or the same source processing core.

[0026] Fifthly, embodiments of this disclosure provide an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, such that the processors, when running, implement any of the data processing methods described in the first aspect above.

[0027] In a sixth aspect, embodiments of this disclosure provide a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions for causing a computer to perform any of the data processing methods described in the first aspect above.

[0028] In a seventh aspect, embodiments of this disclosure provide a computer program product, wherein the program includes a sequence of instructions for implementing any of the data processing methods described in the first aspect when the program is executed on a computer.

[0029] This disclosure provides a data processing method, apparatus, electronic device, and computer-readable storage medium. The data processing method includes: a processing core receiving a synchronization signal; the processing core determining, based on the synchronization signal, a first storage area used by its own task and a second storage area used by tasks other than its own; wherein the first storage area and the second storage area are different; the processing core accesses the first storage area to execute its own task and accesses the second storage area to execute the tasks other than its own. This method separates the storage areas corresponding to different tasks of the processing core, solving the technical problems of complex data consistency handling mechanisms and low processing efficiency in the prior art when reading and writing to the same storage area.

[0030] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0031] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0032] Figures 1a-1c This is a schematic diagram illustrating the background technology of this disclosure; Figure 2 This is a schematic diagram illustrating the application scenario of this disclosure; Figure 3 A flowchart illustrating an embodiment of the data processing method provided in this disclosure; Figure 4 A flowchart illustrating yet another embodiment of the data processing method provided in this disclosure; Figure 5 This is a schematic diagram illustrating the data exchange between cores in the data processing method provided in this disclosure; Figure 6 A sequence diagram of the data exchange tasks between processing cores in the data processing method provided in this disclosure; Figure 7 A schematic diagram of the structure of an embodiment of the data processing apparatus provided in this disclosure; Figure 8 A schematic diagram of the structure of another data processing apparatus provided in this disclosure; Figure 9 This is a schematic diagram of the structure of an electronic device provided according to an embodiment of the present disclosure. Detailed Implementation

[0033] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0034] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0035] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0036] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0037] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0038] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0039] Figure 2 This is a schematic diagram illustrating an application scenario of an embodiment of this disclosure. For example... Figure 2 As shown, the synchronization signal generator 201 generates a synchronization signal Sync to multiple processing cores 202. After receiving Sync, the multiple processing cores 202 enter the superstep determined by the Sync signal and begin processing their own tasks. When all processing cores have completed their tasks, the synchronization signal generator 201 generates a new synchronization signal Sync, causing the multiple processing cores to enter a new superstep to complete new tasks.

[0040] Figure 3 This is a flowchart illustrating an embodiment of the data processing method provided in this disclosure. The data processing method provided in this embodiment can be executed by any processing core of a multi-core processor. Alternatively, the data processing method can be executed by a data processing device, which can be implemented as software or a combination of software and hardware. This data processing device can be integrated into a device within a data processing system, such as a data processing server or a data processing terminal device. Figure 3 As shown, the method includes the following steps: Step S301: Process the core to receive the synchronization signal; This disclosed technical solution is applied to multi-core architecture systems using the BSP (Bulk Synchronous Parallel) synchronization mechanism. The BSP synchronization mechanism synchronizes all processing cores in the multi-core system using a single synchronization signal. The time between two synchronization signals is called a superstep, and each processing core processes its tasks within that superstep duration. In step S301, the processing core receives the synchronization signal generated by the synchronization signal generator 201, indicating that the processing core can process a new task.

[0041] Step S302: The processing core determines the first storage area used by its own task and the second storage area used by non-its own task according to the synchronization signal. In this step, once the synchronization signal is determined, the first storage area used by the task itself and the second storage area used by the non-task itself will be determined within the synchronization period determined by the synchronization signal.

[0042] It should be noted that within the synchronization cycle determined by the next synchronization signal, the correspondence between the processing core's own tasks, non-own tasks, and memory regions may change. For example, the processing core's own tasks may use the second memory region, while non-own tasks may use the first memory region. The memory regions used by the processing core's own tasks and non-own tasks are adjusted according to different synchronization signals.

[0043] In this disclosure, the first storage area and the second storage area are not the same; the first storage area and the second storage area are not the same means that the reading and writing of the first storage area and the reading and writing of the second storage area are independent of each other. For example, the first storage area and the second storage area are two physically separate memories or two sets of memories.

[0044] In this disclosure, the synchronization signals have a predetermined order or parameters that uniquely identify a synchronization signal. For example, if a complete task needs to be completed within n synchronization cycles, the complete task is divided into multiple subtasks, each of which is assigned to one or more processing cores for execution. The specific processing cores (or those cores) that complete a subtask within a specific superstep determined by a given synchronization signal are predetermined. Therefore, in this step, a processing core can uniquely identify a synchronization signal based on its order or parameters, and thus determine its own task through the synchronization signal. Since the task is predetermined, the storage area used by the task can also be predetermined.

[0045] Optionally, the first storage area includes multiple first memories; the task itself includes a computation task and a sending task, wherein the computation task and the sending task use the same first memory; or the computation task and the sending task use different first memories. The computation task involves a processing core retrieving data to be computed from the first storage area, performing computation on the data to obtain a result, and storing the result in the first storage area. The sending task involves the processing core retrieving data to be sent from the first storage area, and sending the data to be sent to the target processing core according to the target processing core to which the sending task is directed and the storage area of ​​the target processing core. The computation task and the sending task can use the same first memory; for example, the processing core executes the computation task and stores the result in the first memory, then sends the result to the target processing core, in which case the computation task and the sending task use the same first memory. Alternatively, the computation task and the sending task use different first memories, in which case the data sent by the sending task is unrelated to the data used by the computation task, and the two are stored in different first memories, allowing for parallel processing.

[0046] Optionally, there are multiple sending tasks, each corresponding to a different or the same target processing core, and each sending task carries a marker for a storage area within the target processing core. For example, there are three sending tasks, with target processing cores C1, C2, and C3. The marker for a storage area within the target processing core indicates which storage area of ​​the target processing core the data being sent needs to be stored in. For instance, if the target processing core is C1, and the second storage area has an ID of 1, it means the data sent to the target processing core C1 needs to be stored in the first memory location within the second storage area of ​​C1. The marker can also be a specific storage address of the storage area.

[0047] Optionally, the second storage area includes multiple second memories; the non-self task includes at least one receiving task, and different receiving tasks use different second memories. In this optional embodiment, the second storage area is used to store data sent by the source processing core. The processing core includes a receiving circuit for receiving data sent by the source processing core and storing the data sent by the source processing core into the second memory indicated by the address according to the address in the receiving task. Different receiving tasks use different second memories; that is, within a superstep, the receiving task of the processing core is determined, and the second memory corresponding to the receiving task is also determined.

[0048] In this step, based on the pre-determined tasks of the processing core and the corresponding storage areas, the storage areas used by the processing core's own tasks and those not used by its own tasks can be isolated to maintain data consistency.

[0049] In step S303, the processing core accesses the first storage area to execute its own task and accesses the second storage area to execute the non-own task.

[0050] After determining the storage area used by the task in the processing core in step S302, the processing core accesses the storage area to execute the corresponding task. For example, within the overstep period determined by the synchronization signal, the processing core needs to complete three sub-tasks: retrieving computational data from the first memory in the first storage area of ​​the processing core, performing computation, and storing it back in the first memory of the first storage area; retrieving transmission data from the second memory in the first storage area of ​​the processing core and sending it to the third memory in the first storage area of ​​processing core C2; ​​and receiving data from processing core C3 and storing it in the first memory in the second storage area of ​​the processing core. When the processing core executes the above sub-tasks, since the storage areas and the memories within them are physically independent, no data inconsistency problem arises, and no dedicated circuitry is needed to ensure data consistency.

[0051] Optionally, before step S301, step S3001 is further included: the processing core receives configuration information, the configuration information including the task of the processing core in the synchronization period determined by each synchronization signal and the storage area corresponding to the task.

[0052] In this step, the processing core receives configuration information, which includes the tasks of the processing core in each synchronization cycle determined by the synchronization signal and the corresponding storage area for each task. This configuration information is generated by the upper-layer program, which divides a complete task into multiple subtasks. Subtasks that can be completed in parallel are assigned to the same synchronization cycle. For example, a convolutional neural network includes multiple neural nodes. The tasks performed by the neural nodes in the same layer are assigned to multiple processing cores to process in the same synchronization cycle (assuming there are enough processing cores). The number of synchronization cycles is equal to the number of layers in the neural network. In this way, the task processed by each processing core in each synchronization cycle is predetermined, and storage areas can be pre-allocated to each task so that the storage areas do not need to be shared among multiple tasks, thus avoiding data inconsistency problems.

[0053] Figure 4This is a flowchart illustrating another embodiment of the data processing method provided in this disclosure. The data processing method provided in this embodiment can be executed by any processing core of a multi-core processor. Alternatively, the data processing method can be executed by a data processing device, which can be implemented as software or a combination of software and hardware. This data processing device can be integrated into a device within a data processing system, such as a data processing server or a data processing terminal device. Figure 4 As shown, the method includes the following steps: Step S401: Process the core to receive the synchronization signal; Step S402, the processing core performs computational tasks and receiving tasks within the synchronization period determined by the synchronization signal, wherein the data for the receiving task comes from the source processing core; Step S403: The processing core accesses the first storage area to execute the computational task; In step S404, the processing core receives the data transmitted by the source processing core and writes the data into a second storage area; wherein the first storage area is different from the second storage area.

[0054] This embodiment will be described in detail using two processing cores as an example. Figure 5 The diagram illustrates an example of a processing core C2 in this embodiment. C2 includes a processing unit PU for performing computational tasks and a receiving circuit Rx for performing a receiving task, wherein the data for the receiving task originates from the processing core C1. In the first superstep determined by the current synchronization signal, the computational task of the processing core C2 is to access storage area M1 and perform computational operations on the data in storage area M1, and the receiving task is to receive data from C1 and store the received data in storage area M0.

[0055] like Figure 5 As shown, the PU of processing core C2 reads data D1 from storage area M1 through address A1; processing core C2 stores the data D2 received from C1 into storage area M0 corresponding to address A0.

[0056] Figure 6 A fragment of a complete task, such as Figure 6As shown, in the first superstep, C2's computation task accesses M1, and the receiving task accesses M0; in the second superstep, C2's computation task accesses M0, and the receiving task accesses M1; in the third superstep, C2's computation task accesses M1, and the receiving task accesses M0. Since the data of the computation task in the current superstep is generally the data received by the receiving task in the previous superstep, the computation task and the receiving task alternate between the two regions, which can improve the execution efficiency of the tasks and avoid data inconsistency problems. Similarly, the first storage region and the second storage region are two physically independent memories or two sets of memories.

[0057] Optionally, the source processing core in step S402 may be multiple, and each processing core may have multiple second storage areas corresponding to different or the same source processing core.

[0058] In this optional embodiment, the processing core receives data sent by multiple source processing cores during a synchronization period determined by a synchronization signal. Each source processing core corresponds to a different second storage area in the processing core. The different second storage areas can be multiple second memories in the second storage area or multiple different storage spaces in the second storage area.

[0059] This disclosure provides a data processing method, apparatus, electronic device, and computer-readable storage medium. The data processing method includes: a processing core receiving a synchronization signal; the processing core determining, based on the synchronization signal, a first storage area used by its own task and a second storage area used by tasks other than its own; wherein the first storage area and the second storage area are different; the processing core accesses the first storage area to execute its own task and accesses the second storage area to execute the tasks other than its own. This method separates the storage areas corresponding to different tasks of the processing core, solving the technical problems of complex data consistency handling mechanisms and low processing efficiency in the prior art when reading and writing to the same storage area.

[0060] Although the steps in the above method embodiments have been described in the above order, those skilled in the art should understand that the steps in the embodiments of this disclosure are not necessarily executed in the above order. They can also be executed in reverse, in parallel, or in other orders. Moreover, those skilled in the art can add other steps based on the above steps. These obvious variations or equivalent substitutions should also be included within the protection scope of this disclosure, and will not be elaborated here.

[0061] Figure 7 This is a schematic diagram of the structure of an embodiment of the data processing apparatus provided in this disclosure, as shown below. Figure 7As shown, the device 700 includes: a synchronization signal receiving module 701, a storage area determination module 702, and a task execution module 703. Among them, Synchronization signal receiving module 701 is used to process the synchronization signal received by the core. The storage area determination module 702 is used by the processing core to determine, based on the synchronization signal, a first storage area used by the processing core for its own tasks and a second storage area used by tasks other than its own tasks. The first storage region is different from the second storage region; The task execution module 703 is used for the processing core to access the first storage area to execute its own task and to access the second storage area to execute the non-own task.

[0062] Furthermore, the first storage area includes a plurality of first memories; the self-task includes a computation task and a transmission task, wherein the computation task and the transmission task use the same first memory; or the computation task and the transmission task use different first memories.

[0063] Furthermore, there are multiple sending tasks, each corresponding to a different or the same target processing core, and each sending task carries a tag of a storage area in the target processing core.

[0064] Furthermore, the second storage area includes a plurality of second memories; the non-self task includes at least one receiving task, and different receiving tasks use different second memories.

[0065] Furthermore, the different receiving tasks correspond to different or the same source processing cores.

[0066] Furthermore, the data processing device 700 also includes: A configuration information receiving module is used for the processing core to receive configuration information, which includes the task of the processing core in the synchronization period determined by each synchronization signal and the storage area corresponding to the task.

[0067] Figure 7 The device shown can perform Figure 3 For the methods shown in the embodiments, the parts not described in detail in this embodiment can be referred to the following: Figure 3 The relevant descriptions of the illustrated embodiments are provided below. For the execution process and technical effects of this technical solution, please refer to [link / reference]. Figure 3 The descriptions in the illustrated embodiments will not be repeated here.

[0068] Figure 8 This is a schematic diagram of the structure of an embodiment of the data processing apparatus provided in this disclosure, as shown below. Figure 8As shown, the device 800 includes: a synchronization signal receiving module 801, a task determination module 802, a computation task execution module 803, and a receiving task execution module 804. Among them, Synchronization signal receiving module 801 is used to process the synchronization signal received by the core. The task determination module 802 is used for the processing core to perform arithmetic tasks and receiving tasks in the synchronization period determined by the synchronization signal, wherein the data of the receiving task comes from the source processing core; The computation task execution module 803 is used for the processing core to access the first storage area to execute the computation task; The receiving task execution module 804 is used for the processing core to receive data transmitted by the source processing core and write the data into the second storage area; The first storage area is different from the second storage area.

[0069] Furthermore, there are multiple source processing cores, and each processing core has multiple second storage areas corresponding to different or the same source processing core.

[0070] Figure 8 The device shown can perform Figures 4-6 For the methods shown in the embodiments, the parts not described in detail in this embodiment can be referred to the following: Figures 4-6 The relevant descriptions of the illustrated embodiments are provided below. For the execution process and technical effects of this technical solution, please refer to [link / reference]. Figures 4-6 The descriptions in the illustrated embodiments will not be repeated here.

[0071] The following is for reference. Figure 9 This document illustrates a structural diagram of an electronic device (e.g., a terminal device or a server) suitable for implementing embodiments of the present disclosure. The terminal device in the embodiments of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), and fixed terminals such as digital TVs and desktop computers. Figure 9 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0072] like Figure 9As shown, the electronic device may include a processing unit 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage device 908 into a random access memory (RAM) 903. The RAM 903 also stores various programs and data required for the operation of the electronic device. The processing unit 901, ROM 902, and RAM 903 are interconnected via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904. The processing unit includes one or more processors or processing cores.

[0073] Typically, the following devices can be connected to I / O interface 905: input devices 906 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 907 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 908 including, for example, magnetic tapes, hard disks, etc.; and communication devices 909. Communication device 909 allows electronic devices to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 9 Electronic devices with various devices are shown, but it should be understood that it is not required to implement or have all of the devices shown. More or fewer devices may be implemented or have alternatively.

[0074] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via a communication device 909, or installed from a storage device 908, or installed from a ROM 902. When the computer program is executed by a processing device 901, it performs the functions defined in the methods of embodiments of this disclosure.

[0075] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof.

[0076] In this disclosure, a computer-readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0077] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0078] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0079] The aforementioned computer-readable medium carries one or more programs that, when executed by the electronic device, cause the electronic device to: receive a synchronization signal; determine, based on the synchronization signal, a first storage area used by the processing core for its own task and a second storage area used by a non-own task; wherein the first storage area and the second storage area are different; and the processing core accesses the first storage area to perform its own task and accesses the second storage area to perform the non-own task.

[0080] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0081] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0082] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0083] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0084] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0085] The above description is merely a preferred embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A data processing method, comprising: Process the core to receive synchronization signals; The processing core determines, based on the synchronization signal, a first storage area used by its own task and a second storage area used by non-tasks within the processing core. The first storage area and the second storage area are different and their read and write operations are independent of each other. The synchronization signal is used to indicate the processing core's own task and the first storage area used by the own task, the non-own task and the second storage area used by the non-own task in the synchronization period determined by the synchronization signal. The processing core accesses the first storage area to perform its own task and accesses the second storage area to perform the non-self task.

2. The data processing method as described in claim 1, characterized in that, The first storage area includes multiple first memories; the self-task includes a computation task and a transmission task; The computation task and the sending task use the same first memory; or The computation task and the sending task use different first memories.

3. The data processing method as described in claim 2, characterized in that: There are multiple sending tasks, each of which corresponds to a different or the same target processing core, and each sending task carries a tag of a storage area in the target processing core.

4. The data processing method according to any one of claims 1-3, characterized in that, The second storage area includes multiple second memories; the non-self task includes at least one receiving task, and different receiving tasks use different second memories.

5. The data processing method as described in claim 4, characterized in that, The different receiving tasks correspond to different or the same source processing cores.

6. The data processing method according to any one of claims 1-3, characterized in that, The process includes the following steps before the processing core receives the synchronization signal: The processing core receives configuration information, which includes the processing core's own task and the first storage area used by the own task, the non-own task and the second storage area used by the non-own task in the synchronization period determined by each synchronization signal.

7. A data processing method, comprising: Process the core to receive synchronization signals; The processing core performs computational tasks and receiving tasks during the synchronization period determined by the synchronization signal, wherein the data for the receiving task comes from the source processing core; The processing core accesses the first storage area to execute the computational task; The processing core receives the data transmitted by the source processing core and writes the data into the second storage area; The first storage area is different from the second storage area and their read / write operations are independent. The first storage area and the second storage area are located in the processing core. The synchronization signal is used to indicate the operation task of the processing core and the first storage area used by the operation task, the receiving task and the second storage area used by the receiving task in the synchronization period determined by the synchronization signal.

8. The data processing method as described in claim 7, characterized in that: There are multiple source processing cores, and each processing core has multiple second storage areas corresponding to different or the same source processing core.

9. A data processing apparatus, comprising: Synchronization signal receiving module, used to process the synchronization signal received by the core; A storage area determination module is used by the processing core to determine, based on the synchronization signal, a first storage area used by its own task and a second storage area used by non-its own task within the processing core. The first storage area and the second storage area are different and their read and write operations are independent of each other. The synchronization signal is used to indicate the processing core's own task and the first storage area used by the own task, the non-own task and the second storage area used by the non-own task in the synchronization period determined by the synchronization signal. The task execution module is used by the processing core to access the first storage area to execute its own task and to access the second storage area to execute the non-own task.

10. A data processing apparatus, comprising: Synchronization signal receiving module, used to process the synchronization signal received by the core; The task determination module is used for the processing core to perform computation tasks and receiving tasks within the synchronization period determined by the synchronization signal, wherein the data of the receiving task comes from the source processing core; A computation task execution module is used for the processing core to access the first storage area to execute the computation task; A task execution module is provided for the processing core to receive data transmitted by the source processing core and write the data into a second storage area. The first storage area is different from the second storage area and their read / write operations are independent. The first storage area and the second storage area are located in the processing core. The synchronization signal is used to indicate the operation task of the processing core and the first storage area used by the operation task, the receiving task and the second storage area used by the receiving task in the synchronization period determined by the synchronization signal.

11. An electronic device, comprising: Memory, used to store computer-readable instructions; as well as One or more processors are configured to execute the computer-readable instructions such that the processor, when running, implements the data processing method according to any one of claims 1-8.

12. A non-transitory computer-readable storage medium for storing computer-readable instructions that, when executed by a computer, cause the computer to perform the data processing method according to any one of claims 1-8.

13. A computer program product, wherein, The program includes computer-readable instructions that, when executed by a computer, cause the computer to perform the data processing method according to any one of claims 1-8.

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