Method of manufacturing high-density logic and memory for advanced circuit architectures

Abstract

The technology herein includes a method for fabricating high-density logic and memory for advanced circuit architectures. Such a method can include forming multiple-layer stacks on separate substrates and forming bonding films over the multiple-layer stacks, then contacting and bonding the bonding films to form a combined structure including each of the multiple-layer stacks. The method can be repeated to form other combinations. Between iterations, transistor devices can be formed from the combined structures. Ionized atomic implantation can facilitate cleaving of a substrate predestined for growth of other multiple layers, where annealing weakens the substrate at a predestined penetration depth of the ionized atomic implantation.

Description

[0001] Cross-reference to related applications

[0002] This disclosure claims the benefits of U.S. Provisional Application No. 62 / 901,591, filed September 17, 2019, and U.S. Application No. 16 / 854,340, filed April 21, 2020, which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a method for manufacturing integrated circuits and microelectronic devices, particularly a method for forming high-density logic and memory. Background Technology

[0004] The background description provided herein is intended to present the overall context of this disclosure. The present inventor's work, to the extent described in this background section, and aspects of this description that might not have been considered prior art at the time of submission, neither expressly nor implicitly acknowledges that it is prior art to this disclosure.

[0005] In the fabrication of semiconductor devices (especially at the micrometer or nanometer scale), various fabrication processes are performed, such as film deposition, etch mask creation, patterning, material etching and removal, and doping. These processes are repeated to form the desired semiconductor device elements on a substrate. Microfabrication has been used to create transistors on a plane and form wiring / metallization layers above the active device plane, and this is therefore characterized as two-dimensional (2D) circuitry or 2D fabrication. While miniaturization has greatly increased the number of transistors per unit area in 2D circuits, it will face even greater challenges as it moves into the nanometer scale of semiconductor device fabrication. Semiconductor device manufacturers have expressed aspirations for three-dimensional (3D) semiconductor circuits with transistors stacked on top of each other.

[0006] 3D integration is considered a viable option for continuing semiconductor miniaturization. 2D transistor density miniaturization stops when the contact gate pitch reaches its miniaturization limit due to manufacturing variability and limitations of electrostatic devices.

[0007] 3D integration (i.e., the vertical stacking of multiple devices) aims to overcome these miniaturization limitations by increasing transistor density in terms of volume rather than area. For example, complementary metal-oxide-semiconductor (CMOS) very large-scale integration (VLSI) miniaturization used in CPU or GPU products is exploring the adoption of 3D integration as a primary means of advancing the semiconductor blueprint, and therefore requires supporting technologies. One such technology can utilize thermal bonding of individual nanoplanar layer stacks on separate substrates to form combined layer stacks and increase the resulting transistor density. Summary of the Invention

[0008] This disclosure relates to a method of manufacturing a semiconductor device, the method comprising: forming a first multilayer stack on a first surface of a first substrate, the first substrate having a second surface opposite to the first surface of the first substrate, the first multilayer stack comprising alternating layers of a first material and a second material; forming a second multilayer stack on a second surface of a second substrate, the second substrate having a first surface opposite to the second surface of the second substrate, the second multilayer stack comprising alternating layers of a third material and a fourth material; implanting ionized atoms into the first surface of the second substrate to a predetermined depth; forming a first bonding film on the top surface of the first multilayer stack and a second bonding film on the top surface of the second multilayer stack; aligning the first substrate and the second substrate such that the first bonding film contacts the second bonding film; annealing the first substrate and the second substrate to bond the first bonding film and the second bonding film together to form a combined structure, the annealing also weakening a portion of the second substrate approximately at the predetermined depth of implantation.

[0009] The method further includes: removing the weakened portion of the second substrate; and after removing the weakened portion, reducing the fracture thickness of the second substrate to a predetermined thickness.

[0010] The method further includes: forming a third multilayer stack on a first surface of a third substrate, the third substrate having a second surface opposite to the first surface of the third substrate, the third multilayer stack including alternating layers of the third material and the fourth material; forming a fourth multilayer stack on a second substrate of the combined structure, the fourth multilayer stack including alternating layers of the first material and the second material, wherein each layer is formed by epitaxial growth starting from a surface formed by removing a weakened portion of the second substrate after thickness reduction; forming a third bonding film on the top surface of the third multilayer stack and a fourth bonding film on the top surface of the fourth multilayer stack; aligning the third substrate with the combined structure such that the third bonding film contacts the fourth bonding film; and annealing the combined structure and the third substrate to bond the third bonding film to the fourth bonding film, thereby making the third substrate part of the combined structure.

[0011] It should be noted that the Summary of this Exploration does not specify all embodiments and / or additional novel aspects of the invention disclosed herein or claimed. Rather, the Summary provides only a preliminary discussion of different embodiments and corresponding points of novelty. For additional details and / or possible perspectives on the invention and its embodiments, the reader should refer to the Detailed Description of this Exploration and the accompanying drawings, as discussed further below. Attached Figure Description

[0012] Various embodiments of this disclosure will be described in detail by way of example with reference to the following accompanying drawings, wherein the same reference numerals refer to the same elements, and in the drawings:

[0013] Figure 1 This is a cross-sectional view of a substrate according to an embodiment of this disclosure, showing an example result of nanolayer stacking.

[0014] Figure 2 This is a cross-sectional view of a substrate according to an embodiment of the present disclosure, showing the stacking of nanolayers during ionization atom implantation on a second wafer.

[0015] Figure 3 This is a cross-sectional view of a substrate according to an embodiment of this disclosure, showing the stacking of nanolayers during oxide formation.

[0016] Figure 4 This is a cross-sectional view of a substrate according to an embodiment of this disclosure, showing the stacking of nanolayers during bonding.

[0017] Figure 5 This is a cross-sectional view of the combined structure according to an embodiment of the present disclosure, showing the thinning of the substrate of the second wafer.

[0018] Figure 6 This is a cross-sectional view of the fabrication of a third wafer according to an embodiment of this disclosure.

[0019] Figure 7 This is a cross-sectional view of a substrate according to an embodiment of this disclosure, showing the stacking of nanolayers during oxide formation.

[0020] Figure 8 This is a cross-sectional view of a substrate according to an embodiment of this disclosure, showing the stacking of nanolayers during bonding.

[0021] Figure 9 This is a cross-sectional view of a substrate according to an embodiment of this disclosure, showing an example result of nanolayer stacking.

[0022] Figure 10 This is a cross-sectional view of a substrate according to an embodiment of the present disclosure, showing the stacking of nanolayers during ionization atom implantation on a second wafer.

[0023] Figure 11 This is a cross-sectional view of a substrate according to an embodiment of this disclosure, showing the stacking of nanolayers during oxide deposition.

[0024] Figure 12 This is a cross-sectional view of the substrate, showing the stacking of nanolayers before and after the third wafer bonding.

[0025] Figure 13 This is a cross-sectional view of a substrate according to an embodiment of this disclosure, showing the stacking of nanolayers during bonding.

[0026] Figures 14 to 15 This is a cross-sectional view of the fabrication and bonding of a combined structure with a double oxide layer according to an embodiment of this disclosure.

[0027] Figure 16 This is a cross-sectional view of a substrate according to an embodiment of this disclosure, showing an example result of nanolayer stacking.

[0028] Figure 17 This is a cross-sectional view of a substrate according to an embodiment of the present disclosure, showing the stacking of nanolayers during ionization atom implantation on a second wafer.

[0029] Figure 18 This is a cross-sectional view of a substrate according to an embodiment of the present disclosure, showing the stacking of nanolayers during the formation of a carbon-bonded film.

[0030] Figure 19 This is a cross-sectional view of a substrate according to an embodiment of the present disclosure, showing the stacking of nanolayers after and before third wafer bonding.

[0031] Figure 20 This is a cross-sectional view of a substrate according to an embodiment of this disclosure, showing the stacking of nanolayers during bonding.

[0032] Figures 21 to 22 This is a cross-sectional view of the fabrication and bonding of a combined structure with a double oxide layer according to an embodiment of this disclosure.

[0033] Figure 23 This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of this disclosure. Detailed Implementation

[0034] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples throughout this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, for ease of description, spatially related terms such as “top,” “bottom,” “below,” “under,” “lower,” “above,” “upper”, etc., may be used herein to describe the relationship of one element or feature as shown in the figures to other elements(s)(s). In addition to the orientations depicted in the figures, spatially related terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relevant descriptors used herein can be interpreted in a similar manner accordingly.

[0035] For clarity, the order in which the different steps described herein are discussed has been presented. Generally, these steps can be performed in any suitable order. Furthermore, although each different feature, technique, configuration, etc., may be discussed in different places within this disclosure, it is intended that each concept can be implemented independently of or in combination with each other. Therefore, the invention can be practiced and viewed in many different ways.

[0036] The techniques described herein include methods for creating high-density 3D logic circuits. The techniques involve forming a stack of nanoplanar layers on two or more substrates and bonding these substrates together at a relatively low temperature. The nanoplanar layer stack can then be transformed into a transistor or logic or memory plane. Alternatively, stacks of logic and / or memory formed on single-crystal silicon can be stacked and bonded together. The stack can be a partially formed device or a fully formed device.

[0037] The bonding described in this paper is achieved through molecular bonds established between the surfaces of two contact-placed substrates. Bonding surfaces, such as oxide films or carbon-containing films, are formed on substrates with epitaxial or device stacks. These interfacial films are brought into contact and aligned with each other under ambient conditions. Initial adhesion occurs due to van der Waals forces, and then a thermal annealing process is used to transform room-temperature bonds (weak bonds) into covalent bonds (strong bonds). This technique provides strong bonds from thin interfaces at low temperatures and enables efficient bonding of nanoplanar surfaces to meet the requirements of 3D integrated logic. Such a technique maximizes the area of ​​vertically stacked silicon substrates. The technique described in this paper enables the formation of more transistor planes with high-quality silicon and channel materials.

[0038] The embodiments described herein provide methods for forming semiconductor devices. Figure 1 This is a cross-sectional view of substrate 105 according to an embodiment of this disclosure, illustrating an example result of a micrometer- or nanometer-scale multilayer stack 107 (hereinafter referred to as "nanolayer stack 107"). In the embodiment, substrate 105 includes a top surface and a bottom surface, and nanolayer stack 107 can be formed on the top surface of substrate 105 on a first wafer 100a. For example, twelve alternating nanolayer materials can be formed. For example, nanolayer stack 107 can include alternating layers of a first material 110 and a second material 115, wherein the first material 110 can be silicon and the second material 115 can be SiGe. For example, nanolayers can be formed via a complementary field-effect transistor (CFET) process flow, which can be followed by post-nanolayer epitaxial growth. It is understood that different numbers of layers can be formed based on the desired final device and different techniques can be used to form layers on substrate 105. Nanolayer stack 107 can be formed on more than one wafer in a similar manner, for example, on a second wafer 100b. The substrate 105 of the second wafer 100b may include a top surface and a bottom surface, and the nanolayer stack 107 may be formed on the bottom surface of the substrate 105 of the second wafer 100b. It is understood that the nanolayer stack 107 of the first wafer 100a and the nanolayer stack 107 of the second wafer 100b may include different materials in their respective nanolayer stacks 107. Therefore, the nanolayer stack 107 of the first wafer 100a may include a first material 110 and a second material 115, while the nanolayer stack 107 of the second wafer 100b may include alternating third and fourth materials.

[0039] Figure 2This is a cross-sectional view of substrate 105 according to an embodiment of this disclosure, showing a nanolayer stack 107 during ionization atom implantation on a second wafer 100b. In this embodiment, ionized atoms (e.g., cleavage particles) can be implanted into the surface of the second wafer 100b opposite to the nanolayer stack 107 to produce cleavage 109. For the following figures of this embodiment, the multiple layers of the nanolayer stack 107 are simplified to a single layer on the first wafer 100a and the second wafer 100b. As shown, ionized atoms can be implanted into the top surface of the second wafer 100b. The ionized atoms can be selected from relatively light elemental materials such as H2, H, He, or B. For example, implantation can include dual implantation of paired elements, such as a combination of H2 and He, or a combination of H2 and boron. By way of a non-limiting example, when boron and H2 are selected, the energy of boron can be 180 keV and the energy of H2 can be 129 keV to match the implantation range, wherein the dose of boron is 5 x 10⁻⁶. 14 Up to 5x10 15 ions / cm 2 And the dose of H2 is 2 to 6 x 10 16 ions / cm 2 In another example, to match the injection ranges of He and H2, He can be injected at an energy of 45 keV, while H2 can be injected at an energy of 30 keV, with both species having a dose range of 2 to 6 x 10⁻⁶. 16 ions / cm 2 The range of dual implantation can be adjusted so that the energy of each peak of the implanted ion species has the same range. One or more elements can be implanted in one or more process steps. Note that any energy can be used. Because the energy used determines the depth of cleavage 109, the two energies should be adjusted so that the projection range of each ion is aligned to have the same ionized atom implantation depth to produce cleavage 109. In the example, dual implantation can significantly reduce the annealing temperature to <300°C to separate substrate 105 at cleavage 109. Alternatively, if only a single implantation is used, for example, only H2, the annealing temperature can be from 400°C to 600°C. The first wafer 100a can also accept ionized atom implantation, but in this embodiment, the first wafer 100a does not accept ionized atom implantation.

[0040] Figure 3This is a cross-sectional view of substrate 105 according to an embodiment of this disclosure, showing a nanolayer stack 107 during oxide formation. In an embodiment, a chemically bonded film 120 may be formed on the nanolayer stack 107. The top surface of the nanolayer stack 107 may be defined as the surface furthest from the substrate 105. Thus, as shown, the top surface of the nanolayer stack 107 on the first wafer 100a is in the direction of the top surface of the substrate 105 of the first wafer 100a, but the top surface of the nanolayer stack 107 on the second wafer 100b is in the direction of the bottom surface of the substrate 105 of the second wafer 100b. The example bonding film 120 includes oxide and carbon-containing films, but other options may be used.

[0041] In this embodiment, the bonding film 120 may be a chemical oxide film or interface formed on each substrate 105. Both the first wafer 100a and the second wafer 100b can be cleaned using a two-step cleaning sequence. For example, the first cleaning may use a mixture of H₂SO₄:H₂O₂ in a ratio of, for example, (2.5 to 3.5):1 or preferably 3:1, for 10 to 20 minutes. After the first cleaning, the first wafer 100a and the second wafer 100b may be ultrasonically rinsed in deionized (DI) water for 10 to 20 minutes. The second cleaning may use a mixture of NH₄OH:H₂O₂:H₂O in a ratio of, for example, (0.7 to 1.3):1:5 or preferably 1:1:5. The second cleaning may be performed at a temperature of, for example, 20°C to 30°C, or preferably 25°C, for 10 to 20 minutes. Since NH₃ evaporates at higher temperatures, it is advantageous to keep the second cleaning at a lower temperature. This results in the formation of more -NH₂ groups, thereby strengthening the bonding of the covalent silicon after annealing. This leaves a chemical oxide film (i.e., chemical bonding film 120) of approximately 5 to 15 angstroms (Å) on each of the first wafer 100a and the second wafer 100b, which is suitable for forming strong covalent silicon bonds upon heating. The chemical bonding film 120 may also cover other surfaces of the substrate 105.

[0042] Figure 4This is a cross-sectional view of substrate 105 according to an embodiment of the present disclosure, showing the nanolayer stack 107 during bonding. With the formation of the chemical bonding film 120, the nanolayer stack 107 of the first wafer 100a and the second wafer 100b can be bonded together. The first wafer 100a and the second wafer 100b can be aligned such that the chemical bonding film 120 on the first wafer 100a contacts the chemical bonding film 120 on the second wafer 100b. With the bonding films 120 of the first wafer 100a and the second wafer 100b in contact with each other, the first wafer 100a and the second wafer 100b can remain in place due to van der Waals forces. Annealing can then be performed. The first wafer 100a and the second wafer 100b can be heated to, for example, between 200°C and 500°C for three to six hours. Annealing can promote the formation of stronger, permanent covalent silicon bonds. Additionally, when ionized atoms are implanted into the top surface of the substrate 105 of the second wafer 100b, annealing can induce separation at the cleavage 109 where the peak of the ionized atom implantation range is located, thereby achieving wafer thinning. Cleaving the substrate 105 of the second wafer 100b can reduce the thickness of the substrate 105 (e.g., back bulk silicon) without etching or polishing the entire thickness of the bulk substrate 105 material.

[0043] Note that the annealing can be a two-step process because pyrolysis can occur in a short time (e.g., a few minutes), followed by a relatively long annealing process to bond two of the bonding films 120 together. The chemical bonding films 120 of the first wafer 100a and the second wafer 100b can be aligned and bonded together via annealing to produce an intermediate chemical bonding film 120 with a thickness in the range of, for example, 10 Å to 30 Å, or preferably 20 Å.

[0044] Figure 5This is a cross-sectional view of the combined structure according to an embodiment of this disclosure, showing the thinning of the substrate 105 of the second wafer 100b. With the permanent bonding of the first wafer 100a and the second wafer 100b, they become a combined structure. The broken portions can then be removed and / or cleaned from the combined structure. Further thinning can be performed. Further thinning is useful for accessing one of the nanolayer stacks 107 to facilitate subsequent formation of a semiconductor device and the addition of other nanolayer stacks 107. For example, the entire substrate 105 of the second wafer 100b can be removed and the nanolayer stacks 107 (now having up to twice the number of layers compared to before the combination, each half spaced apart by bonding films 120) can be formed into a semiconductor device. For example, a gate-all-around (GAA) device can be made from the nanolayer stacks 107. Various techniques can be used to thin the material of the bulk substrate 105. For example, the top surface of the substrate 105 of the second wafer 100b can be etched or polished by chemical mechanical polishing (CMP) to produce single-crystal silicon of a desired thickness (such as 10 to 50 nm). Note that the pyrolyzed bulk silicon can be polished before other uses. The pyrolyzed portion left from the pyrolysis can be recycled as a substrate dozens of times. For lighter, inert elements, this cleaning can be optional. If other elements such as boron are used, a cleaning or polishing step can be used to remove boron, as this element can be used as a dopant if it remains in the bulk silicon.

[0045] At this point, the two nanolayer stacks 107 are bonded and can be used for other stacks. As described above, for each of the nanolayer stacks 107 having twelve layers, there are now twenty-four alternating layers very close together. Other nanoplanar layers can then be added to the composite structure by repeating the preceding steps.

[0046] Figure 6 This is a cross-sectional view of the fabrication of a third wafer 100c according to an embodiment of this disclosure. In the embodiment, a nanolayer stack 107 may be formed on a substrate 105 of the third wafer 100c, wherein the substrate 105 of the third wafer 100c includes a top surface and a bottom surface, and the nanolayer stack 107 is formed on the bottom surface. Alternatively, the nanolayer stack 107 may be formed on a thinned substrate 105 of a second wafer 100b on the combined structure. The top surface of the substrate 105 of the third wafer 100c may then optionally be implanted with ionized atoms for dicing or cleavage during annealing. The combined structure does not need to receive any ionized atom implantation. As similarly performed previously, if two or more different types of ionized atoms are used, the energy of the ionized atom implantation can be adjusted such that the peak range or implantation depth of the ionized atoms is the same for all implantations.

[0047] Figure 7This is a cross-sectional view of substrate 105 according to an embodiment of this disclosure, showing the nanolayer stack 107 during oxide formation. In the embodiment, chemically bonded films 120 (e.g., one or more oxide layers and / or carbon-containing layers) may be formed on the uncovered nanolayer stack 107 of each structure (i.e., the combined structure and the third wafer 100c).

[0048] The process continues as described above. Figure 8 This is a cross-sectional view of substrate 105 according to an embodiment of this disclosure, showing the nanolayer stack 107 during bonding. In the embodiment, the nanolayer stack 107 of the combined structure and the third wafer 100c can be bonded together. The combined structure and the third wafer 100c can be aligned such that the chemical bonding film 120 on the combined structure contacts the chemical bonding film 120 on the third wafer 100c. Annealing subsequently forms strong, permanent silicon covalent bonds between the bonding films 120. Annealing can also cause cleaving or pyrolysis in the substrate 105 of the third wafer 100c.

[0049] The fractured substrate 105 of the third wafer 100c can be polished and thinned. At this point, fabrication can proceed to create transistors. As described so far, forty-eight semiconductor material nanolayers have been assembled. In this example, the assembled structure includes twenty-four single-crystal silicon planes, which can be used as transistor channel materials. For example, the assembled structure can be masked and etched to form nanochannels for FETs, memory components, etc. Alternatively, more nanolayers can be formed by repeating the formation of the nanolayer stack 107 and bonding via thermal annealing.

[0050] As can be understood, the first wafer 100a and the second wafer 100b of the combination can be formed by any combination of bonding films 120 on the nanolayer stack 107 as described above.

[0051] Figure 9 This is a cross-sectional view of substrate 105 according to an embodiment of the present disclosure, showing an example result of nanolayer stack 107. In the embodiment, nanolayer stack 107 may be formed on the top surface of substrate 105 of first wafer 100a. Nanolayer stack 107 may additionally be formed on second wafer 100b, wherein nanolayer stack 107 may be formed on the bottom surface of substrate 105 of second wafer 100b.

[0052] Figure 10This is a cross-sectional view of substrate 105 according to an embodiment of the present disclosure, showing a nanolayer stack 107 during ionization atom implantation of a second wafer 100b. In this embodiment, ionized atoms can be implanted into the surface of the second wafer 100b opposite to the nanolayer stack 107 to create a fracture 109. As shown, ionized atoms can be implanted into the top surface of the second wafer 100b.

[0053] Figure 11 This is a cross-sectional view of substrate 105 according to an embodiment of this disclosure, showing a nanolayer stack 107 during oxide deposition. In the embodiment, a deposited bonding film 121 can be formed on the nanolayer stack 107 via deposition. If a cleaning step is subsequently performed, a final cleaning step using HF can be used so that no chemical oxide is left. An oxide is then deposited on the nanolayer stack 107 with a deposition thickness in the range of, for example, 30 Å to 300 Å, or preferably 100 Å, which is thicker than the chemically bonded film 120 from the wet cleaning process. For example, atomic layer deposition (ALD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), and metal-organic chemical vapor deposition (MOCVD) can be used. The bond films 121 deposited on the first wafer 100a and the second wafer 100b can be aligned and bonded together via annealing to produce an intermediately deposited bond film 121 with a thickness in the range of, for example, 60 Å to 600 Å, or preferably 200 Å.

[0054] Figure 12 This is a cross-sectional view of substrate 105, showing the nanolayer stack 107 before and after bonding of the third wafer 100c. In an embodiment, the nanolayer stack 107 may be formed on the bottom surface of substrate 105 of the third wafer 100c. Alternatively, the nanolayer stack 107 may be formed on a thinned substrate 105 of the second wafer 100b in the combined structure. The top surface of substrate 105 of the third wafer 100c may then be optionally implanted with ionized atoms for dicing or cleavage during annealing.

[0055] Figure 13 This is a cross-sectional view of substrate 105 according to an embodiment of this disclosure, showing the nanolayer stack 107 during bonding. In an embodiment, the nanolayer stack 107 of the combined structure and the third wafer 100c can be bonded together via depositing a bonding film 121 together during annealing.

[0056] Figures 14 to 15This is a cross-sectional view showing the fabrication and bonding of a combined structure with two oxide layers according to an embodiment of this disclosure. In the embodiment, a chemically bonded film 120 is first formed on a nanolayer stack 107 of a first wafer 100a, a second wafer 100b, and a third wafer 100c, followed by the deposition of a bonded film 121 on the chemically bonded film 120. This incorporates oxides left by cleaning chemicals, followed by deposition processes using ALD, CVD, etc.

[0057] Figure 16 This is a cross-sectional view of substrate 105 according to an embodiment of the present disclosure, showing an example result of nanolayer stack 107. In the embodiment, nanolayer stack 107 may be formed on the top surface of substrate 105 of first wafer 100a. Nanolayer stack 107 may additionally be formed on second wafer 100b, wherein nanolayer stack 107 may be formed on the bottom surface of substrate 105 of second wafer 100b.

[0058] Figure 17 This is a cross-sectional view of substrate 105 according to an embodiment of the present disclosure, showing a nanolayer stack 107 during ionization atom implantation of a second wafer 100b. In this embodiment, ionized atoms can be implanted into the surface of the second wafer 100b opposite to the nanolayer stack 107 to create a fracture 109. As shown, ionized atoms can be implanted into the top surface of the second wafer 100b.

[0059] Figure 18 This is a cross-sectional view of substrate 105 according to an embodiment of the present disclosure, showing a nanolayer stack 107 during the formation of a carbon-containing bonding film 122. In this embodiment, the carbon-containing bonding film 122 may be epitaxially grown on the nanolayer stack 107. Alternatively, the carbon-containing bonding film 122 may be deposited on the top surface of the nanolayer stack 107. For example, the carbon-containing bonding film 122 may be SiC or SiCN. For each of the first wafer 100a and the second wafer 100b, the thickness of the carbon-containing bonding film 122 may be in the range of, for example, 10 to 100 Å. The bonding films 121 deposited on the first wafer 100a and the second wafer 100b may be aligned and bonded together via annealing.

[0060] Figure 19 This is a cross-sectional view of substrate 105 according to an embodiment of the present disclosure, showing a nanolayer stack 107 after and before bonding of the third wafer 100c. In this embodiment, the nanolayer stack 107 may be formed on the bottom surface of the substrate 105 of the third wafer 100c. Alternatively, the nanolayer stack 107 may be formed on a thinned substrate 105 of the second wafer 100b in a combined structure. The top surface of the substrate 105 of the third wafer 100c may then be optionally implanted with ionized atoms for dicing or cleavage during annealing.

[0061] Figure 20 This is a cross-sectional view of substrate 105 according to an embodiment of the present disclosure, showing the nanolayer stack 107 during bonding. In an embodiment, the nanolayer stack 107 of the combined structure and the third wafer 100c can be bonded together via bonding a carbon-containing bonding film 122 together during annealing.

[0062] Figures 21 to 22 This is a cross-sectional view showing the fabrication and bonding of a combined structure with two oxide layers according to an embodiment of this disclosure. In the embodiment, a chemically bonded film 120 is first formed on a nanolayer stack 107 of a first wafer 100a, a second wafer 100b, and a third wafer 100c, followed by the formation of a carbon-containing bonded film 122 on top of the chemically bonded film 120. This combines the oxides left by cleaning chemicals, followed by deposition processes using ALD, CVD, etc. For example, SiC or SiC x N y (x ranging from 0.7 to 1.1 and y ranging from 0.1 to 0.4) can be deposited on the chemically bonded film 120. The carbon-bonded film 122 can be deposited by ALD, CVD, PECVD, MOCVD, and sputtering deposition, etc. Note that, depending on the selected deposition technique, post-SiCN annealing is an option from 200°C to 400°C. Optionally, a thicker film can be deposited and then polished. Other interfaces besides oxides can also be used.

[0063] Figure 23This is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present disclosure. The described method is summarized below. In step S2301, a first nanolayer stack 107 is formed on a substrate 105 of a first wafer 100a. In step S2303, a second nanolayer stack 107 is formed on a substrate 105 of a second wafer 100b. In step S2305, ionized atoms are implanted into the substrate 105 of the second wafer 100b, which is opposite to the side of the second nanolayer stack 107 on the substrate 105 of the second wafer 100b. In step S2307, a first bonding film 120 is formed on the first nanolayer stack 107. In step S2309, a second bonding film 120 is formed on the second nanolayer stack 107. In step S2311, the first bonding film and the second bonding film 120 are aligned and contacted to bond the first nanolayer stack and the second nanolayer stack 107 into a combined structure. In step S2313, the combined structure is annealed, which weakens a portion of the implanted substrate 105 of the second wafer 100b. In step S2315, the weakened portion of the substrate 105 of the second wafer 100b is removed. In step S2317, the thickness (i.e., fracture thickness) of the remaining portion of the substrate 105 of the second wafer 100b is reduced via, for example, etching or CMP. In step S2319, a third nanolayer stack 107 is formed on the substrate 105 of the third wafer 100c. In step S2321, a fourth nanolayer stack 107 is formed on the substrate 105 of the second wafer 100b where the weakened portion has been removed. In step S2323, a third bonding film 120 is formed on the third nanolayer stack 107. In step S2325, a fourth bonding film 120 is formed on the fourth nanolayer stack 107. In step S2327, the third bonding film 120 and the fourth bonding film 120 are aligned and brought into contact to bond the combined structure and the third nanolayer stack 107. In step S2329, the combined structure, which includes a third wafer 100c, is annealed.

[0064] Therefore, the techniques described herein enable various embodiments and process flows for forming stacks of numerous single-crystal silicon layers or other silicon layers to achieve high density (per volume) of semiconductor devices. Thus, a certain amount of epitaxial silicon layers can be grown. The number of layers can be limited to maintain high-quality material. For example, epitaxial growth of more than 12 layers can lead to poor electrical performance and even failure. The epitaxial stack can form transistor devices before or after bonding. Instead of an epitaxial stack, the stack can be a memory stack or other logic circuitry. Therefore, these epitaxial stacks can be device planes of logic, memory, or other devices. As will be understood, various combinations are possible.

[0065] Bonding is then accomplished using one or more bonding layers on each epitaxial stack. The bonding layers are preferably oxides or carbon-containing. Depending on design specifications, the bonding layers can be formed to varying thicknesses. An accompanying implantation step can be used to assist in thinning the back-side bulk silicon to combine with and / or touch epitaxial stacks to continue manufacturing.

[0066] Understandably, the techniques described in this paper can be used for more than 48 high-quality single-crystal silicon nanoplanes. The bonding process can be performed at relatively low temperatures. Optionally, complete devices can be formed prior to bonding the wafers, with metal connections, enabling any type of stacking (logical memory, custom circuit designs). Bonding can be performed using relatively thin interface thicknesses. Optionally, isolation layers can be used between the silicon planes.

[0067] In the foregoing description, specific details, such as the particular geometry of the machining system and the description of the various components and processes used therein, have been set forth. However, it should be understood that the techniques described herein may be practiced in other embodiments departing from these specific details, and such details are for illustrative purposes rather than limiting. The embodiments disclosed herein have been described with reference to the accompanying drawings. Similarly, for illustrative purposes, specific figures, materials, and configurations have been set forth to provide a thorough understanding. However, embodiments may be practiced without such specific details. Components having substantially the same functional construction are indicated by similar reference numerals, and therefore any redundant description may be omitted.

[0068] Various techniques have been described as multiple discrete operations to aid in understanding the various embodiments. The order of the description should not be construed as meaning that these operations are necessarily order-dependent. In fact, these operations do not need to be performed in the order presented. The described operations may be performed in a different order than the described embodiments. In additional embodiments, various additional operations may be performed and / or the described operations may be omitted.

[0069] As used herein, "substrate" or "target substrate" generally refers to the object being processed according to the invention. A substrate may include any material portion or structure of a device (particularly a semiconductor or other electronic device) and may be, for example, a base substrate structure (such as a semiconductor wafer, a photomask) or a layer (such as a thin film) on or overlaid on a base substrate structure. Therefore, a substrate is not limited to any particular base structure, underlayer, or overlayer, whether patterned or unpatterned, but is contemplated to include any such layer or base structure, and any combination of layers and / or base structures. This description may refer to specific types of substrates, but this is for illustrative purposes only.

[0070] Those skilled in the art will also understand that many changes can be made to the operation of the above-described techniques while still achieving the same objectives of the invention. The scope of this disclosure is intended to encompass these changes. Therefore, the foregoing description of embodiments of the invention is not intended to be limiting. Rather, any limitations on embodiments of the invention are set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A first multilayer stack is formed on a first surface of a first substrate, the first substrate having a second surface opposite to the first surface of the first substrate, the first multilayer stack comprising alternating layers of a first material and a second material, the first multilayer stack having at least four layers; A second multilayer stack is formed on a second surface of a second substrate, the second substrate having a first surface opposite to the second surface of the second substrate, the second multilayer stack comprising alternating layers of a third material and a fourth material, the second multilayer stack having at least four layers; Ionized atoms are implanted to a predetermined depth on the first surface of the second substrate; A first bonding film is formed on the top surface of the first multilayer stack, and a second bonding film is formed on the top surface of the second multilayer stack; Align the first substrate with the second substrate so that the first bonding film contacts the second bonding film; as well as The first substrate and the second substrate are annealed to bond the first bonding film and the second bonding film together to form a combined structure. The annealing also weakens a portion of the second substrate approximately at the predetermined depth of implantation. The first and third materials are silicon, and the second and fourth materials are SiGe.

2. The method of claim 1, wherein, These ionized atoms have atomic numbers less than 12.

3. The method of claim 1, wherein, Injecting these ionized atoms involves injecting a first type of ionized atom and injecting a second type of particle.

4. The method of claim 3, wherein, The first type of ionized atoms are selected from the group consisting of H, H2, He and boron.

5. The method of claim 1, wherein, Forming the first bonded film and forming the second bonded film includes performing an oxide deposition process.

6. The method of claim 5, wherein, The thickness of the first bonding film and the second bonding film is 30 angstroms to 300 angstroms respectively.

7. The method of claim 1, wherein, Forming the first bonded film and forming the second bonded film includes cleaning the top surface of the first multilayer stack with a liquid chemical substance to form a first chemical oxide film on the top surface of the first multilayer stack, and cleaning the top surface of the second multilayer stack with the liquid chemical substance to form a second chemical oxide film on the top surface of the second multilayer stack.

8. The method of claim 7, wherein, The thickness of the first chemical oxide film and the second chemical oxide film is 5 to 30 angstroms.

9. The method of claim 7, wherein, Forming the first bonded film and the second bonded film includes performing an oxide deposition process after cleaning, which deposits oxide layers on the first chemical oxide film and the second chemical oxide film, thereby forming a double oxide layer on each of the first multilayer stack and the second multilayer stack.

10. The method of claim 1, further comprising: A first carbon-containing bonding film is formed on the first bonding film; as well as A second carbon-containing bonding film is formed on the second bonding film, wherein Aligning the first substrate with the second substrate includes contact between the first carbon-containing bonding film and the second carbon-containing bonding film.

11. The method of claim 1, further comprising: Remove the weakened portion of the second substrate.

12. The method of claim 11, further comprising: After removing the weakened portion, the fracture thickness of the second substrate is reduced to a predetermined thickness.

13. The method of claim 12, wherein, The fracture thickness of the second substrate was reduced to less than 60 nm.

14. The method of claim 12, further comprising: A third multilayer stack is formed on a first surface of a third substrate, the third substrate having a second surface opposite to the first surface of the third substrate, the third multilayer stack comprising alternating layers of the third material and the fourth material; A fourth multilayer stack is formed on the second substrate of the combined structure. The fourth multilayer stack includes alternating layers of the first material and the second material, wherein each layer is formed by epitaxial growth starting from a surface formed by removing a weakened portion of the second substrate after thickness reduction. A third bonding film is formed on the top surface of the third multilayer stack, and a fourth bonding film is formed on the top surface of the fourth multilayer stack. Align the third substrate with the combined structure so that the third bonding film contacts the fourth bonding film; as well as The combined structure and the third substrate are annealed to bond the third bonding film to the fourth bonding film, thereby making the third substrate part of the combined structure.

15. The method of claim 14, further comprising: Before forming the third bonding film on the top surface of the third multilayer stack, ionized atoms are implanted to the predetermined depth on the first surface of the third substrate, wherein, The annealing of the combined structure and the third substrate also weakens a portion of the third substrate approximately at the predetermined depth of the implantation.

16. The method of claim 15, further comprising: Remove the weakened portion of the third substrate; as well as After removing the weakened portion, the fracture thickness of the third substrate is reduced to a predetermined thickness.

17. A method for manufacturing a semiconductor device, the method comprising: A first multilayer stack is formed on a first surface of a first substrate, the first substrate having a second surface opposite to the first surface of the first substrate, the first multilayer stack comprising alternating layers of a first material and a second material, and the first multilayer stack comprising at least six epitaxial growth layers; A second multilayer stack is formed on a second surface of a second substrate, the second substrate having a first surface opposite to the second surface of the second substrate, the second multilayer stack comprising alternating layers of a third material and a fourth material, and the second multilayer stack comprising at least six epitaxial growth layers; Ionized atoms are implanted to a predetermined depth on the first surface of the second substrate; A first bonding film is formed on the top surface of the first multilayer stack, and a second bonding film is formed on the top surface of the second multilayer stack; Align the first substrate with the second substrate so that the first bonding film contacts the second bonding film; The first substrate and the second substrate are annealed to bond the first bonding film and the second bonding film together to form a combined structure. The annealing also weakens a portion of the second substrate approximately at the predetermined depth of implantation. Remove the weakened portion of the second substrate; as well as This combined structure forms at least one transistor device; The first and third materials are silicon, and the second and fourth materials are SiGe.

18. The method of claim 17, further comprising: After removing the weakened portion of the second substrate, the remaining portion of the second substrate is thinned to completely remove the remaining portion of the second substrate and expose the combined first and second multilayer stacks.

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