Group computing devices, methods, integrated circuit chips, computing devices and boards

Abstract

This disclosure relates to a grouping operation apparatus, method, integrated circuit chip, computing device, and board, wherein the computing device may be included in a combined processing device, which may further include a general interconnect interface and other processing devices. The computing device interacts with other processing devices to jointly complete user-specified computational operations. The combined processing device may also include a storage device connected to both the computing device and other processing devices for storing data from these devices. The solutions disclosed herein can be widely applied to accelerate grouping operations.

Description

Technical Field

[0001] This disclosure generally relates to the field of parallel computing. More specifically, this disclosure relates to grouping computing apparatus, methods, integrated circuit chips, computing devices, and circuit boards. Background Technology

[0002] In parallel computing, the array of arithmetic units organized in a fractal structure and the computational tasks they perform are known as fractal computing. Many current processor architectures employ fractal computing because they organize simple basic arithmetic units in a specific way to achieve parallel computing effects. However, this fractal computing approach still falls short of current requirements. Therefore, developing a device capable of further accelerating computation is a problem that needs to be solved in the existing technology. Summary of the Invention

[0003] In order to at least partially solve the technical problems mentioned in the background art, the present disclosure provides a packet computing device and method thereof, an integrated circuit chip including the packet computing device, a computing device and a board.

[0004] In one aspect, this disclosure provides a grouping operation apparatus, wherein the grouping operation apparatus includes a first processing unit and a plurality of second processing units, the first processing unit being configured to distribute the input data to at least one of the plurality of second processing units according to a data distribution mode of the input data, and at least one of the plurality of second processing units performing grouping operations on the input data received by each of them and their respective stored local data.

[0005] In another aspect, this disclosure provides a grouping operation method, wherein the grouping operation method includes: using a first processing unit of a grouping operation device to distribute the input data to at least one of a plurality of second processing units of the grouping operation device according to the data distribution mode of the input data, and using at least one of the plurality of second processing units to perform grouping operations on the input data received by each unit and the local data stored by each unit.

[0006] In another aspect, this disclosure provides an integrated circuit chip that includes the aforementioned packet processing device. In yet another embodiment, the packet processing device of this disclosure can constitute a standalone integrated circuit chip.

[0007] In another aspect, this disclosure provides a computing device that includes the aforementioned grouping arithmetic device or the aforementioned integrated circuit chip.

[0008] In another aspect, this disclosure provides a board that includes the aforementioned computing device.

[0009] By utilizing the grouping operation device, corresponding operation method, integrated circuit chip, computing device, and board disclosed herein, the distribution of input data can be controlled through a data distribution mode, thereby achieving faster grouping operations. Therefore, the grouping operation device of this disclosure is flexible and can be widely applied to various accelerated operations. Attached Figure Description

[0010] The above and other objects, features, and advantages of this disclosure will become readily apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0011] Figure 1 This is a schematic block diagram illustrating a grouping operation apparatus according to an embodiment of the present disclosure;

[0012] Figure 2 This is a schematic block diagram illustrating a grouping operation apparatus according to another embodiment of the present disclosure;

[0013] Figure 3 This is a schematic block diagram illustrating a grouping operation apparatus according to yet another embodiment of the present disclosure;

[0014] Figure 4 This is a flowchart illustrating a grouping operation method according to an embodiment of the present disclosure;

[0015] Figure 5 This is a flowchart illustrating a grouping operation method according to another embodiment of the present disclosure;

[0016] Figure 6 This is a structural diagram illustrating a combined processing apparatus according to an embodiment of the present disclosure; and

[0017] Figure 7 This is a schematic diagram illustrating the structure of a circuit board according to an embodiment of the present disclosure. Detailed Implementation

[0018] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0019] The technical solution disclosed herein provides a grouping operation device, method, integrated circuit chip, computing device, and board as a whole. Unlike existing grouping operation devices, this disclosure provides a grouping operation device that can control the distribution of input data to better achieve fast grouping operations, thereby improving the operation speed. In particular, this disclosure can perform different grouping operations according to different data distribution modes. Therefore, the grouping operation device of this disclosure has the characteristics of high operation speed and high flexibility.

[0020] Figure 1 This is a schematic block diagram illustrating a grouping operation apparatus 100 according to an embodiment of the present disclosure. Figure 1 As shown, the grouping operation device 100 may include a first processing unit 101 and a plurality of second processing units 102. The first processing unit 101 may be used to distribute the input data to at least one of the plurality of second processing units according to the data distribution mode of the input data. At least one of the plurality of second processing units 102 may perform grouping operations on the input data received by each unit and the local data stored by each unit.

[0021] According to this embodiment, the first processing unit 101 can send input data to different numbers of designated second processing units 102 according to different data distribution modes. Multiple second processing units 102 receiving the same input data can share the input data and perform calculations on their own stored local data and the input data. Furthermore, the aforementioned second processing units 102 sharing input data can be grouped together, but the local data used by this group of second processing units 102 in the calculations with the input data can be the same or different.

[0022] According to embodiments of this disclosure, the data distribution mode can be determined based on the grouping information of the plurality of second processing units 102 storing local data, and the data distribution mode can include a broadcast mode, a multicast mode, and a unicast mode.

[0023] In this embodiment, the data distribution mode can be determined based on the grouping of multiple second processing units 102 storing local data. The grouping of the multiple second processing units 102 can be determined based on pre-set input data required for grouping operations and local data, thus the grouping of the second processing units 102 can change. Therefore, the data distribution mode can be adjusted according to the changes in the grouping of the second processing units 102 and can include broadcast mode, multicast mode, and unicast mode.

[0024] The following three examples illustrate the three data distribution models described above in detail.

[0025] According to the first example, when the data distribution mode of the input data is the broadcast mode, the first processing unit 101 can send the input data to each of the plurality of second processing units.

[0026] In this example, the grouping information corresponding to the broadcast mode can be that all the second processing units 102 receive the input data as a group, so the first processing unit 101 can send the input data to all the second processing units 102.

[0027] According to the second example, when the data distribution mode of the input data is the multicast mode, the first processing unit 101 may send the input data to a portion of the plurality of second processing units indicated by the multicast mode.

[0028] In this example, the grouping information corresponding to the multicast mode is that at least two, but not all, second processing units 102 are treated as a group to receive input data. Therefore, the first processing unit 101 can send the input data to this group of second processing units 102. Furthermore, for example, when the current input data is sent to a group of second processing units 102, the next input data can be sent to this group of second processing units 102 or another group of second processing units 102.

[0029] According to the third example, when the data distribution mode of the input data is the unicast mode, the first processing unit 101 can send the input data to one of the plurality of second processing units indicated by the multicast mode.

[0030] In this example, the unicast mode corresponds to a group of second processing units 102 receiving input data. Therefore, the first processing unit 101 can send the input data to one of the second processing units 102. Furthermore, for example, when the current input data is sent to one second processing unit 102, the next input data can be sent to that second processing unit 102 or another second processing unit 102.

[0031] According to embodiments of this disclosure, the first processing unit 101 may include an addressing module. The addressing module can be used to address the second processing unit 102 to receive the input data based on the address of the second processing unit 102 indicated by the data distribution mode.

[0032] In this embodiment, in order for the first processing unit 101 to locate the second processing unit 102 that needs to receive input data, the first processing unit 101 may include an addressing module, and the data distribution mode may indicate the address of the second processing unit 102 that needs to receive the input data. Therefore, the addressing module can address the second processing unit 102 that needs to receive the input data according to the data distribution mode of the input data.

[0033] According to an embodiment of this disclosure, the first processing unit 101 can also be used to concatenate the calculation results obtained by the plurality of second processing units 102 together to obtain a concatenated calculation result.

[0034] In this embodiment, when multiple second processing units 102 perform group operations, each second processing unit 102 obtains its own operation result after the operation is completed. To improve data transmission efficiency, the first processing unit 101 can control the operation results of multiple second processing units 102 to be concatenated together via instructions and returned to the first processing unit 101 through the output path. For this purpose, the bit width of the input path of the input data can be set to be smaller than the bit width of the output path of the concatenated result. This allows the corresponding number of operation results to be concatenated according to the bit width of the output path and returned to the first processing unit 101.

[0035] It should be understood that in the above operations, there is a transmission of data and instructions between the first processing unit 101 and the second processing unit 102. The first processing unit 101 may transmit instructions in parallel to the plurality of second processing units 102 and transmit data serially to the plurality of second processing units 102; or the first processing unit 101 may transmit data in parallel to the plurality of second processing units 102 and transmit instructions serially to the plurality of second processing units 102.

[0036] In this embodiment, by setting the data and instruction transmission method between the first processing unit 101 and the plurality of second processing units 102 to serial instruction and parallel data, or parallel instruction and serial data, the problem of excessive instantaneous power consumption of the computing device can be effectively avoided.

[0037] In other embodiments, the first processing unit 101 can serially transmit both instructions and data to the plurality of second processing units 102, thereby enabling the plurality of second processing units 102 to start sequentially, effectively avoiding the problem of excessive instantaneous power consumption of the computing device. In this embodiment, compared to the above-described combination of serial and parallel processing, the increase in instantaneous power consumption is more slow.

[0038] The aforementioned serial transmission refers to the transmission of data or instructions from a first processing unit 101 to a second processing unit 102, and then sequentially among multiple second processing units 102, starting from that first second processing unit 102. For example, after receiving an instruction or data from a first processing unit 101, a second processing unit 102 copies the instruction or data for use, and the instruction or data can then be transmitted to the next second processing unit 102. The aforementioned parallel transmission refers to the transmission of data or instructions from a first processing unit 101 to multiple second processing units 102 in parallel.

[0039] Furthermore, in order to better realize instruction and data transmission between the first processing unit 101 and the second processing unit 102, and to better complete data operations, the first processing unit 101 and the multiple second processing units 102 can be arranged in an H-shaped structure, a tree structure, or an array structure.

[0040] According to embodiments of this disclosure, the input data may be a neuron or a weight; when the input data is a neuron, the local data is a weight; when the input data is a weight, the local data is a neuron.

[0041] In this embodiment, when the grouping operation apparatus of this disclosure performs neural network-related operations, the grouping operation can be a grouping operation for convolution. In this case, the data involved in the operation can be neurons and weights. Therefore, when the input data is a neuron, the local data can be weights; when the input data is weights, the local data can be neurons.

[0042] Reference Figure 2 , Figure 2 This is a schematic block diagram illustrating a grouping operation apparatus 200 according to another embodiment of the present disclosure. Figure 2 The grouping operation device 200 shown is Figure 1 The difference between the group processing device 100 shown is that the group processing device 200 may also include a data control unit 201. The data control unit 201 can be used to acquire the data distribution mode and transmit the input data to the first processing unit 101 in segments, and configure the data distribution mode for each segment of input data.

[0043] In this embodiment, the data control unit 201 can obtain the data distribution mode by parsing external instructions. Furthermore, the data control unit 201 can directly receive input data in segments and transmit the input data to the first processing unit 101 in segments. Alternatively, the data control unit 201 can also obtain data segmentation information by parsing external instructions, and segment the received data into multiple input data segments according to the data segmentation information, so as to transmit the input data to the first processing unit 101 in segments. Moreover, the data control unit 201 can first configure the aforementioned data distribution mode for each input data segment, and then transmit each input data segment configured with the data distribution mode to the first processing unit 101.

[0044] Therefore, various data distribution modes for a single input data can be achieved through a single external instruction, that is, any number of second processing units 102 can share the single input data to participate in group operations.

[0045] Furthermore, referring to Figure 3 , Figure 3 This is a schematic block diagram illustrating a grouping operation apparatus 300 according to yet another embodiment of the present disclosure. Figure 3 The grouping operation device 300 shown is Figure 2 The difference in the grouping operation device 200 shown is that the data control unit 201 includes a controller unit 2011 and an input / output unit 2012. The controller unit 2011 is used to acquire the data distribution mode and send the data distribution mode to the input / output unit 2012; the input / output unit 2012 is used to transmit the input data to the first processing unit 101 in segments and configure the data distribution mode for each segment of input data.

[0046] In one embodiment, the controller unit 2011 can obtain the data distribution mode of the input data by parsing external instructions and send the data distribution mode to the input / output unit 2012. The input / output unit 2012 can directly receive the input data in segments (e.g., segmented input data obtained from a DMA unit (Direct Memory Access Unit, not shown) or other devices) and transmit the input data to the first processing unit 101 segment by segment. Furthermore, the input / output unit 2012 can first configure the aforementioned data distribution mode for each input data segment, and then transmit each input data segment configured with the data distribution mode to the first processing unit 101.

[0047] In another embodiment, the controller unit 2011 can obtain the data distribution mode and data segmentation information of the input data by parsing external instructions, and send the data distribution mode and data segmentation information to the input / output unit 2012. The input / output unit 2012 can segment the received data (e.g., data obtained from a DMA unit (Direct Memory Access Unit, not shown) or other devices) into multiple input data entries according to the data segmentation information, and then transmit the input data to the first processing unit 101 in segments. Furthermore, the input / output unit 2012 can first configure the aforementioned data distribution mode for each input data entry, and then transmit each input data entry configured with the data distribution mode to the first processing unit 101.

[0048] When the data distribution mode of the current input data is broadcast mode, the second processing unit 102 to receive the current input data is all second processing units 102. The first processing unit 101 can, for example, use an addressing module to send the current input data to all second processing units 102. When the data distribution mode of the current input data is multicast mode, the second processing unit 102 to receive the current input data is a group of at least two, but not all, second processing units 102. The first processing unit 101 can, for example, use an addressing module to send the current input data to this group of second processing units 102. Furthermore, for example, when the current input data is sent to a group of second processing units 102, the next input data can be sent to that group of second processing units 102 or another group of second processing units 102. When the data distribution mode of the current input data is unicast mode, the second processing unit 102 to receive the current input data is a single second processing unit 102. The first processing unit 101 can, for example, use an addressing module to send the current input data to this single second processing unit 102. Furthermore, for example, when the current input data is sent to a second processing unit 102, the next input data can be sent to that second processing unit 102 or another second processing unit 102.

[0049] Furthermore, when multiple second processing units 102 perform grouped operations, each second processing unit 102 obtains its own operation result after the operation is completed. The first processing unit 101 can concatenate the operation results of multiple second processing units 102 together via instructions and return them to the first processing unit 101. The first processing unit 101 can output the concatenated result to any other device or storage unit (e.g., a DMA unit) that needs the result via the input / output unit 2012, as needed; or the first processing unit 101 can first split the concatenated result back into multiple original operation results, and then output the multiple original operation results to any other device or storage unit (e.g., a DMA unit) that needs the result via the input / output unit 2012, as needed; or the first processing unit 101 can first split the concatenated result back into multiple original operation results, and then perform a fusion calculation on the multiple original operation results to obtain the desired intermediate or final result, and then output the intermediate or final result to any other device or storage unit (e.g., a DMA unit) that needs the result via the input / output unit 2012, as needed.

[0050] This disclosure also provides a method for grouping operations. (See reference...) Figure 4 , Figure 4 This is a flowchart illustrating a grouping operation method according to an embodiment of the present disclosure. Figure 4 As shown, it can be understood that the grouping operation device used in this grouping operation method is the one mentioned above. Figures 1-3 The detailed description of the grouping arithmetic device means that the preceding description of the grouping arithmetic device and its internal components, functions and operations also applies to the description herein.

[0051] The grouping operation method disclosed herein includes the following steps S101-S102.

[0052] In step S101, the first processing unit of the grouping arithmetic device distributes the input data to at least one of the plurality of second processing units of the grouping arithmetic device according to the data distribution mode of the input data.

[0053] In step S102, at least one of the plurality of second processing units performs grouping operations on the input data received by each unit and the local data stored by each unit.

[0054] According to embodiments of this disclosure, a data distribution mode can be determined based on grouping information of a plurality of second processing units storing local data, and the data distribution mode may include a broadcast mode, a multicast mode, and a unicast mode.

[0055] The following three examples illustrate the three data distribution models described above in detail.

[0056] When the data distribution mode of the input data is the broadcast mode, the first processing unit can be used to send the input data to each of the plurality of second processing units.

[0057] When the data distribution mode of the input data is the multicast mode, the first processing unit can be used to send the input data to a portion of the multiple second processing units indicated by the multicast mode.

[0058] When the data distribution mode of the input data is the unicast mode, the first processing unit can be used to send the input data to one of the plurality of second processing units indicated by the multicast mode.

[0059] According to embodiments of this disclosure, the addressing module included in the first processing unit can be used to address the second processing unit to receive input data according to the address of the second processing unit indicated by the data distribution mode.

[0060] According to embodiments of this disclosure, the first processing unit can also be used to concatenate the calculation results obtained by multiple second processing units together to obtain a concatenated calculation result.

[0061] According to embodiments of this disclosure, a first processing unit can be used to transmit instructions in parallel to multiple second processing units and transmit data serially to multiple second processing units; or a first processing unit can be used to transmit data in parallel to multiple second processing units and transmit instructions serially to multiple second processing units.

[0062] According to embodiments of this disclosure, the first processing unit and a plurality of second processing units can be arranged in an H-shaped structure, a tree structure, or an array structure.

[0063] According to embodiments of this disclosure, the input data can be a neuron or a weight; when the input data is a neuron, the local data is a weight; when the input data is a weight, the local data is a neuron.

[0064] Reference Figure 5 , Figure 5 This is a flowchart illustrating a grouping operation method according to another embodiment of the present disclosure. Figure 5 As shown, the grouping operation method may further include step S201 before step S101. In step S201, the data distribution mode is obtained by using the data control unit of the grouping operation device and the input data is transmitted to the first processing unit of the grouping operation device in segments, and a data distribution mode is configured for each input data segment.

[0065] According to embodiments of this disclosure, a data distribution mode can be obtained using a controller unit included in the data control unit, and the data distribution mode can be sent to an input / output unit included in the data control unit; and the input / output unit can be used to transmit input data to the first processing unit in segments, and a data distribution mode can be configured for each segment of input data.

[0066] Based on the above Figure 4 As described above, when the data distribution mode of the current input data is broadcast mode, the second processing unit to receive the current input data is all second processing units, and the current input data can be sent to all second processing units using, for example, the addressing module of the first processing unit. When the data distribution mode of the current input data is multicast mode, the second processing unit to receive the current input data is a group of at least two, but not all, second processing units, and the current input data can be sent to this group of second processing units using, for example, the addressing module of the first processing unit. When the data distribution mode of the current input data is unicast mode, the second processing unit to receive the current input data is a single second processing unit, and the current input data can be sent to this single second processing unit using, for example, the addressing module of the first processing unit.

[0067] In the above embodiments of this disclosure, the descriptions of each embodiment have their own emphasis. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0068] Figure 6 This is a structural diagram illustrating a combined processing apparatus 600 according to an embodiment of the present disclosure. As shown, the combined processing apparatus 600 includes a computing device 602, which may include the grouping computing device of the present disclosure as described above in conjunction with the accompanying drawings. Additionally, the combined processing apparatus includes a general interconnect interface 604 and other processing devices 606. The computing device according to the present disclosure interacts with other processing devices to jointly complete user-specified operations.

[0069] According to the scheme of this disclosure, the other processing device may include one or more types of processors such as a central processing unit (“CPU”), a graphics processing unit (“GPU”), a neural network processor, and other general-purpose and / or special-purpose processors, and the number is not limited but determined according to actual needs. In one or more embodiments, the other processing device may serve as an interface between the computing device of this disclosure (which may be embodied as a machine learning computing device) and external data and control, performing tasks including but not limited to data transfer, and completing basic control such as starting and stopping the machine learning computing device; the other processing device may also cooperate with the machine learning computing device to jointly complete computing tasks.

[0070] According to the present disclosure, the universal interconnect interface can be used to transfer data and control commands between a computing device and other processing devices. For example, the computing device can obtain required input data from other processing devices via the universal interconnect interface and write it to on-chip storage. Furthermore, the computing device can obtain control commands from other processing devices via the universal interconnect interface and write them to on-chip control cache. Alternatively or optionally, the universal interconnect interface can also read data from the computing device's storage module and transmit it to other processing devices.

[0071] Optionally, the combined processing apparatus may further include a storage device 608, which may be connected to the computing device and the other processing device respectively. In one or more embodiments, the storage device may be used to store data from the computing device and the other processing device, particularly suitable for data that cannot be fully stored in the internal storage of the computing device or other processing device, requiring computation.

[0072] Depending on the application scenario, the combined processing device disclosed herein can serve as a System-on-a-Chip (SoC) for devices such as mobile phones, robots, drones, video capture equipment, and video surveillance equipment. This effectively reduces the core area of ​​the control unit, increases processing speed, and lowers overall power consumption. In this case, the general-purpose interconnect interface of the combined processing device connects to certain components of the device. These components may include, for example, a camera, monitor, mouse, keyboard, network card, or Wi-Fi interface.

[0073] In some embodiments, this disclosure also discloses a chip or integrated circuit chip that includes the aforementioned computing device, combined processing device, and grouping computing device. In other embodiments, this disclosure also discloses a chip package structure that includes the aforementioned chip.

[0074] In some embodiments, this disclosure also discloses a circuit board that includes the above-described chip packaging structure. See also... Figure 7The aforementioned exemplary board 700 is provided. In addition to the aforementioned chip 702, the board may also include other supporting components, which may include, but are not limited to, a storage device 704, an interface device 706, and a controller 708.

[0075] The storage device is connected to the chip within the chip package structure via a bus for storing data. The storage device may include multiple sets of storage cells 710. Each set of storage cells is connected to the chip via a bus. It is understood that each set of storage cells may be DDR SDRAM (“Double Data Rate SDRAM”).

[0076] DDR can double the speed of SDRAM without increasing the clock frequency. DDR allows data to be read on both the rising and falling edges of the clock pulse. DDR is twice as fast as standard SDRAM. In one embodiment, the memory device may include four groups of memory cells. Each group of memory cells may include multiple DDR4 chips. In one embodiment, the chip may internally include four 72-bit DDR4 controllers, of which 64 bits are used for data transmission and 8 bits are used for ECC verification.

[0077] In one embodiment, each group of memory cells may include multiple Double Data Rate (DDR) synchronous dynamic random access memories (DRAMs) arranged in parallel. DDR can transfer data twice within one clock cycle. A controller for controlling the DDR is provided in the chip for controlling the data transfer and data storage of each memory cell.

[0078] The interface device is electrically connected to the chip within the chip package structure. The interface device is used to realize data transmission between the chip and an external device 712 (e.g., a server or computer). For example, in one embodiment, the interface device can be a standard PCIe interface. For instance, data to be processed is transferred from the server to the chip via a standard PCIe interface, realizing data transfer. In another embodiment, the interface device can also be other interfaces; this disclosure does not limit the specific form of the other interfaces mentioned above, as long as the interface unit can realize the switching function. Furthermore, the calculation results of the chip are still transmitted back to the external device (e.g., the server) by the interface device.

[0079] The controller is electrically connected to the chip to monitor its status. Specifically, the chip and the controller can be electrically connected via an SPI interface. The controller may include a microcontroller ("MCU"). The chip may include multiple processing chips, multiple processing cores, or multiple processing circuits, and can drive multiple loads. Thus, the chip can operate in different states, such as high load and low load. The controller can regulate the operating states of multiple processing chips, multiple processing cores, and / or multiple processing circuits within the chip.

[0080] In some embodiments, this disclosure also discloses an electronic device or apparatus that includes the aforementioned circuit board. Depending on the application scenario, the electronic device or apparatus may include a data processing device, robot, computer, printer, scanner, tablet computer, smart terminal, mobile phone, dashcam, navigator, sensor, camera, server, cloud server, camera, camcorder, projector, watch, earphone, mobile storage, wearable device, vehicle, home appliance, and / or medical device. The vehicle includes airplanes, ships, and / or vehicles; the home appliances include televisions, air conditioners, microwave ovens, refrigerators, rice cookers, humidifiers, washing machines, lights, gas stoves, and range hoods; the medical devices include MRI scanners, ultrasound machines, and / or electrocardiographs.

[0081] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that this disclosure is not limited to the described order of actions, because according to this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all optional embodiments, and the actions and modules involved are not necessarily essential to this disclosure.

[0082] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0083] In the several embodiments provided in this disclosure, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the circuit division is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple circuits or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual couplings, direct couplings, or communication connections may be indirect couplings or communication connections between devices or circuits through some interfaces, and may be electrical, optical, acoustic, magnetic, or other forms.

[0084] The circuit described as a separate component may or may not be physically separate. The components shown as circuits may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0085] Furthermore, the functional circuits in the various embodiments of this disclosure can be integrated into one processing unit, or each circuit can exist physically separately, or two or more circuits can be integrated into one unit. The integrated unit can be implemented in hardware or as a software program module.

[0086] If the integrated unit is implemented as a software program module and sold or used as an independent product, it can be stored in a computer-readable storage device (CMD). Based on this understanding, when the technical solution of this disclosure can be embodied in the form of a software product, the computer software product is stored in a storage device and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this disclosure. The aforementioned storage device includes various media capable of storing program code, such as a USB flash drive, read-only memory ("ROM"), random access memory ("RAM"), portable hard drive, magnetic disk, or optical disk.

[0087] The foregoing can be better understood in accordance with the following terms:

[0088] Clause A1, a grouping operation apparatus, wherein the grouping operation apparatus includes a first processing unit and a plurality of second processing units, the first processing unit being configured to distribute the input data to at least one of the plurality of second processing units according to a data distribution mode of the input data, and at least one of the plurality of second processing units performing grouping operations on the input data received by each of them and their respective stored local data.

[0089] Clause A2, the grouping operation apparatus according to Clause A1, wherein the grouping operation apparatus further includes: a data control unit, configured to acquire the data distribution mode and transmit the input data to the first processing unit in segments, and configure the data distribution mode for each segment of input data.

[0090] Clause A3, the grouping operation apparatus according to Clause A2, wherein the data control unit includes a controller unit and an input / output unit; the controller unit is configured to acquire the data distribution mode and send the data distribution mode to the input / output unit; the input / output unit is configured to transmit the input data to the first processing unit in segments and configure the data distribution mode for each segment of input data.

[0091] Clause A4, the packet processing apparatus according to any one of Clauses A1-A3, wherein the data distribution mode is determined based on the packet information of the plurality of second processing units storing local data, and the data distribution mode includes a broadcast mode, a multicast mode, and a unicast mode.

[0092] Clause A5, the group processing apparatus according to Clause A4, wherein when the data distribution mode of the input data is the broadcast mode, the first processing unit sends the input data to each of the plurality of second processing units.

[0093] Clause A6, the packet processing apparatus according to Clause A4, wherein when the data distribution mode of the input data is the multicast mode, the first processing unit sends the input data to a portion of the plurality of second processing units indicated by the multicast mode.

[0094] Clause A7, the packet processing apparatus according to Clause A4, wherein when the data distribution mode of the input data is the unicast mode, the first processing unit sends the input data to one of the plurality of second processing units indicated by the multicast mode.

[0095] Clause A8, the packet processing apparatus according to any one of Clauses A1-A3, wherein the first processing unit includes: an addressing module configured to address the second processing unit to receive the input data according to the address of the second processing unit indicated by the data distribution mode.

[0096] Clause A9, the grouping operation apparatus according to any one of clauses A1-A3, wherein the first processing unit is further configured to concatenate the operation results obtained by the plurality of second processing units together to obtain a concatenated operation result.

[0097] Clause A10, the grouping arithmetic apparatus according to Clause A9, wherein the first processing unit transmits instructions in parallel between the plurality of second processing units and transmits data serially between the plurality of second processing units; or the first processing unit transmits data in parallel between the plurality of second processing units and transmits instructions serially between the plurality of second processing units.

[0098] Clause A11, the grouping operation apparatus according to any one of clauses A1-A3, wherein the first processing unit and the plurality of second processing units are arranged in an H-shaped structure, a tree structure or an array structure.

[0099] Clause A12, a grouping operation apparatus according to any one of clauses A1-A3, wherein the input data is a neuron or a weight; when the input data is a neuron, the local data is a weight; when the input data is a weight, the local data is a neuron.

[0100] Clause A13, a grouping operation method, wherein the grouping operation method includes: using a first processing unit of a grouping operation device to distribute the input data to at least one of a plurality of second processing units of the grouping operation device according to a data distribution mode of the input data, and using at least one of the plurality of second processing units to perform grouping operations on the input data received by each unit and the local data stored by each unit.

[0101] Clause A14, an integrated circuit chip, including a grouping arithmetic device according to any one of Clauses A1-A12.

[0102] Clause A15, a computing device comprising a grouping arithmetic device according to any one of Clauses A1-A12 or an integrated circuit chip according to Clause A14.

[0103] Clause A16, a board including a computing device as described in Clause A15.

[0104] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The description of the above embodiments is only for the purpose of helping to understand the methods and core ideas of this disclosure. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

[0105] It should be understood that the terms "first," "second," "third," and "fourth," etc., in the claims, specification, and drawings of this disclosure are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" as used in the specification and claims of this disclosure indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0106] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0107] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0108] The embodiments of this disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this disclosure. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this disclosure, and on the specific implementation methods and application scope of this disclosure, are all within the scope of protection of this disclosure. Therefore, the content of this specification should not be construed as a limitation of this disclosure.

Claims

1. A grouping arithmetic device, wherein, The grouping operation device includes a first processing unit and multiple second processing units. The first processing unit is configured to distribute the input data to at least one of the plurality of second processing units according to the data distribution pattern of the input data. At least one of the plurality of second processing units performs grouping operations on the input data received by each unit and the local data stored by each unit. The first processing unit includes: An addressing module is used to address the second processing unit to receive the input data according to the address of the second processing unit indicated by the data distribution mode; The grouping operation device further includes: a data control unit; the data control unit includes a controller unit and an input / output unit; the controller unit is used to acquire the data distribution mode and send the data distribution mode to the input / output unit; the input / output unit is used to transmit the input data to the first processing unit in segments and configure the data distribution mode for each segment of input data, wherein the data distribution mode is determined based on the grouping information of the plurality of second processing units storing local data.

2. The grouping operation device according to claim 1, wherein, The data distribution modes include broadcast mode, multicast mode, and unicast mode.

3. The grouping operation device according to claim 2, wherein, When the data distribution mode of the input data is the broadcast mode, the first processing unit sends the input data to each of the plurality of second processing units.

4. The grouping operation device according to claim 2, wherein, When the data distribution mode of the input data is the multicast mode, the first processing unit sends the input data to a portion of the second processing units among the plurality of second processing units indicated by the multicast mode.

5. The grouping operation device according to claim 2, wherein, When the data distribution mode of the input data is the unicast mode, the first processing unit sends the input data to one of the plurality of second processing units indicated by the multicast mode.

6. The grouping operation device according to claim 1, wherein, The first processing unit is also used to concatenate the calculation results obtained by the plurality of second processing units together to obtain a concatenated calculation result.

7. The grouping operation device according to claim 6, wherein, The first processing unit transmits instructions in parallel to the plurality of second processing units and transmits data serially to the plurality of second processing units; or The first processing unit transmits data in parallel to the plurality of second processing units and transmits instructions serially to the plurality of second processing units.

8. The grouping operation device according to claim 1, wherein, The first processing unit and the plurality of second processing units are arranged in an H-shaped structure, a tree structure, or an array structure.

9. The grouping operation device according to claim 1, wherein, The input data is a neuron or weights; When the input data is a neuron, the local data is the weights; When the input data is weights, the local data is neurons.

10. A grouping operation method, wherein, The grouping operation method includes: The first processing unit of the group processing device distributes the input data to at least one of a plurality of second processing units of the group processing device according to the data distribution pattern of the input data. At least one of the plurality of second processing units performs grouping operations on the input data received by each unit and the local data stored by each unit. Using the addressing module included in the first processing unit, the address of the second processing unit indicated by the data distribution mode is used to address the second processing unit to receive the input data; The controller unit included in the data control unit of the grouping operation device acquires the data distribution mode and sends the data distribution mode to the input / output unit included in the data control unit; and the input / output unit transmits input data to the first processing unit in segments, and configures a data distribution mode for each segment of input data, wherein the data distribution mode is determined based on the grouping information of the plurality of second processing units storing local data.

11. An integrated circuit chip, comprising the grouping arithmetic device according to any one of claims 1 to 9.

12. A computing device comprising a grouping arithmetic device according to any one of claims 1 to 9 or an integrated circuit chip according to claim 11.

13. A board comprising the computing device according to claim 12.

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