Perform data operations on grouped memory cells

Abstract

This disclosure relates to performing data operations on grouped memory cells. A request is received to perform a data operation associated with at least one of a plurality of memory cells of a memory device. The at least one memory cell includes a first group of memory cells, each memory cell supporting a specified number of charge levels such that each memory cell having a specified charge level represents a non-integer number of bits. The first group of memory cells represents the first bit sequence of a first charge level sequence formed based on the first group of memory cells. The data operation is performed relative to the at least one memory cell based on a mapping stored in the system. The mapping assigns individual charge level sequences from individual group cells to individual bit sequences represented by individual memory cell groups.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to performing data operations on grouped memory cells. Background Technology

[0002] A memory subsystem can be a storage device, a memory module, or a combination of both. A memory subsystem can contain one or more memory components for storing data. Memory components can be, for example, non-volatile memory components and volatile memory components. Generally, a host system can utilize a memory subsystem to store data at memory components and retrieve data from memory components. Summary of the Invention

[0003] In one aspect, this disclosure provides a system comprising: a memory device including a plurality of memory cells, each memory cell including one or more memory information cells; and a memory controller of the memory device configured to perform operations including: receiving a request to perform a data operation associated with at least one of the plurality of memory cells, the at least one memory cell including a first group of memory information cells, each memory information cell in the first group of memory information cells supporting a specified number of charge levels such that each memory information cell having a specified charge level represents a non-integer number of bits, the first group of memory information cells representing a first bit sequence based on a first charge level sequence stored in the first group of memory information cells, and the first bit sequence having an integer number of bits; and performing a data operation on the at least one memory cell based on a mapping stored in the system, the mapping assigning individual charge level sequences stored in individual memory information cell groups to individual bit sequences represented by the individual memory information cell groups.

[0004] In another aspect, this disclosure provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations including: generating a first matrix representing a first mapping of a charge level sequence to a bit sequence of a first group having two memory cells, each memory cell of the first group supporting two charge levels and representing one data bit; generating a second matrix representing a second mapping of a charge level sequence to a bit sequence of a second group having two memory cells, each memory cell of the second group supporting three charge levels and representing 1.5 data bits; applying matrix operations to the first matrix and the second matrix to generate a third matrix representing a third mapping of a charge level sequence to a bit sequence of a third group having two memory cells, each memory cell of the third group supporting six charge levels and representing 2.5 data bits; and storing each of the first matrix, the second matrix, and the third matrix on a memory device coupled to the processing device.

[0005] In another aspect, this disclosure provides a method performed at a memory device comprising a plurality of memory cells, each memory cell including one or more memory information elements, the method comprising: receiving at a memory controller of the memory device a request to perform a data operation associated with at least one of the plurality of memory cells, the at least one memory cell including a first group of memory information elements, each memory information element in the first group of memory information elements supporting a specified number of charge levels such that each memory information element having a specified charge level represents a non-integer number of bits, the first group of memory information elements representing a first bit sequence of a first charge level sequence formed based on the first group of memory information elements, and the first bit sequence having an integer number of bits; identifying corresponding information for the first charge level sequence or the first bit sequence from a mapping allocation matrix of the first group of memory information elements based on the request; and performing the data operation based on the identified mapping allocation for the at least one memory cell. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed descriptions and accompanying drawings of various embodiments of the present disclosure given below. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are merely for explanation and understanding.

[0007] Figure 1 An example computing environment including a memory subsystem is shown according to some embodiments of the present disclosure.

[0008] Figure 2An example matrix is ​​shown that maps the charge level of a group of memory cells to a bit representation according to some embodiments of the present disclosure.

[0009] Figures 3A-3B An example matrix for performing matrix operations according to an embodiment of this disclosure is shown.

[0010] Figures 4A-4C A flowchart of an example method for performing data operations on grouped memory cells according to embodiments of the present disclosure is shown.

[0011] Figures 5A-5C A flowchart illustrating an example method for mapping matrices for grouped memory cells according to embodiments of the present disclosure is shown.

[0012] Figure 6 An interaction diagram is shown that illustrates the interaction between components providing a computing environment in the context of some embodiments, in which methods for performing data operations on grouped memory cells as described herein are executed.

[0013] Figure 7 A block diagram of an example computer system in which embodiments of the present disclosure may operate is shown. Detailed Implementation

[0014] Various aspects of this disclosure relate to performing data operations on grouped memory cells, which may be part of a memory subsystem. The memory subsystem may be a storage device, a memory module, or a mixture of both. The following is combined with… Figure 1 Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more memory components (hereinafter also referred to as "memory devices"). The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0015] Memory devices can be non-volatile memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section will discuss this further. Figure 1Other examples of non-volatile memory devices are described. Some memory devices, such as NAND memory devices, contain arrays of memory cells (e.g., flash cells) for storing data. Each cell contains a transistor, and within each cell, data is stored as a threshold voltage of the transistor based on the cell's logic value (e.g., 0 or 1). Memory cells in these devices can be grouped into pages that can refer to logical units of the memory device used for storing data. For example, memory cells in a NAND memory device are horizontally connected to word lines at their control gates to form pages. For some types of memory devices (e.g., NAND), pages are grouped to form blocks (also referred to herein as "memory blocks").

[0016] The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on a memory device at the memory subsystem, read data from a memory device at the memory subsystem, or construct read / write operations relative to a memory device at the memory subsystem. The data to be read or written, as specified by the host request, is referred to hereinafter as "host data". The host request may contain logical address information (e.g., logical block address (LBA), namespace) of the host data, which is the location associated between the host system and the host data. The logical address information (e.g., LBA, namespace) may be part of the metadata of the host data. The metadata may include error handling data (e.g., error correction code (ECC) codewords, parity check codes), data version (e.g., expiration date used to distinguish the written data), a validity bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0017] Data operations can be performed by the memory subsystem. Data operations can be host-initiated. For example, the host system can initiate data operations (e.g., write, read, erase, etc.) on the memory subsystem. The host system can send access requests (e.g., write commands, read commands) to the memory subsystem to store data on the memory devices located in the memory subsystem and to read data from the memory devices located in the memory subsystem.

[0018] The memory subsystem can initiate media management operations, such as write operations, on host data stored on the memory device. For example, the firmware of the memory subsystem can rewrite previously written host data from one location on the memory device to a new location as part of a garbage collection management operation. The rewritten data (e.g., as initiated by the firmware) is referred to below as "garbage collection data".

[0019] In the following text, "user data" broadly refers to host data and garbage collection data. "System data" refers to data created and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Instances of system data include, but are not limited to, system tables (e.g., logical-to-physical (L2P) memory address mapping tables (also referred to as L2P tables herein), data from logging, high-speed scratchpad data, etc.

[0020] The memory device can be a non-volatile memory device. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. For some memory devices, a block is the smallest erasable area. Each block consists of a set of pages. Each page consists of a set of memory cells storing data bits. The memory device can be a raw memory device (e.g., NAND) that is managed externally, for example, by an external controller. The memory device can be a managed memory device (e.g., managed NAND) that is a raw memory device combined with a local embedded controller for memory management within the same device package.

[0021] Traditional computer systems, such as conventional supercomputers, can perform operations on memory cells that store an integer number of data bits. Memory cells (e.g., flash memory cells) store data by applying a specified voltage or charge level to the memory cell. The stored charge level indicates the bit representation of the memory cell. A single-level cell can store two charge levels indicating 0 or 1. A single-level cell can therefore store one data bit. As memory cells become more complex to store more data bits, the number of charge levels increases by powers of 2. The physical limitations of memory cells make it difficult to reliably increase the number of charge levels to store more bits. For example, a multi-level cell (MLC) has four charge levels and can store two data bits. A three-level cell (TLC) has eight charge levels and can store three data bits. A four-level cell (QLC) has sixteen charge levels and can store four data bits. The more charge levels per cell, the more bits can be represented, and the cell density increases. However, the physical limitations of memory cells make it difficult to distinguish between charge levels, and memory cells wear out faster. As data density increases, charge leakage can occur and cause data corruption. For memory cells such as five-level cells (PLCs), it can be very difficult to distinguish between thirty-two charge levels. While it is desirable to have single memory cells that store four, five, or more data bits, conventional memory cells do not have the reliability required to make such cells useful.

[0022] Part of this disclosure addresses the aforementioned and other problems by performing various data operations on grouped memory cells. Specifically, various embodiments enable the memory device to store an integer number of data bits without sacrificing reliability based on a high number of charge levels in each individual memory cell.

[0023] By using various embodiments, data operations on grouped memory cells can be performed on the memory device or memory subsystem. Therefore, some embodiments can provide the ability to store larger amounts of data without adding physical memory cells. Regarding transactional memory, data operation mechanisms can be used to enable the memory device or memory subsystem to virtually group two or more memory cells together to create grouped cells with the capacity to store an integer number of data bits. This integer number of data bits is greater than the capacity of each individual memory cell before grouping. In this way, memory devices of various embodiments can store more data without sacrificing reliability.

[0024] Although various embodiments are described herein with respect to a memory subsystem controller, some embodiments implement the features described herein (e.g., operations for reading and writing data) as part of a memory device (e.g., a controller, processor, or state machine for a memory die). For example, various embodiments implement read operations as part of a controller, processor, or state machine for each bank of memory within the memory device.

[0025] The benefits include the ability to create groups using a stable memory cell charge level capacity, which can store more integer bits than each individual memory cell alone.

[0026] Figure 1 An example computing environment 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 140), or a combination thereof.

[0027] The memory subsystem 110 can be a storage device, a memory module, or a combination of both. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing environment 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is shown. The host system 120 uses the memory subsystem 110, for example, to write data to and read data from the memory subsystem 110. As used herein, “coupled to” generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediate component), whether wired or wireless, and includes connections such as electrical connections, optical connections, magnetic connections, etc.

[0029] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more cache memories, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect High Speed ​​(PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110. Host system 120 may be a computing device, such as a desktop computer, laptop computer, network server, mobile device, or such a computing device that includes memory and processing power.

[0030] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Small Computer System Interface (SCSI), Dual Data Rate (DDR) memory bus, Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), Open NAND Flash Interface (ONFI), Low Power Dual Data Rate (LPDDR), or any other suitable interface. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a PCIe interface, host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access memory components (e.g., memory device 140). The physical host interface can provide an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1Memory subsystem 110 is shown as an example. Generally, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or combinations of communication connections.

[0031] Memory device 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0032] Some examples of non-volatile memory devices (e.g., memory device 140) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. The crosspoint array of non-volatile memory can perform bit storage based on variations in volume resistance in conjunction with a stackable cross-grid data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-place write operations, where non-volatile memory cells can be programmed without pre-erasing them. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0033] Each of the memory devices 140 may contain one or more arrays of memory cells, such as single-level cells (SLC) or multi-level cells (MLC) (e.g., three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC)), each cell storing multiple bits. In some embodiments, each of the memory devices 140 may contain one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory component may contain an SLC portion of memory cells, as well as an MLC portion, a TLC portion, or a QLC portion. The memory cells of the memory device 140 may be grouped into pages or blocks of memory that can refer to cells of a memory component used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0034] Although non-volatile memory components—such as NAND flash memory (e.g., 2D NAND, 3D NAND) and 3D cross-point arrays of non-volatile memory cells—are described, memory device 140 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0035] The memory subsystem controller 115 can communicate with memory device 140 and / or memory component 130 to perform operations, such as reading data, writing data, erasing data, and other such operations at memory device 140. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The memory subsystem controller 115 can be a microcontroller, a special-purpose logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0036] The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logical flows, and routines that control the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0037] In some embodiments, local memory 119 may include memory registers storing memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The example memory subsystem 110 has been shown to include a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0038] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to enable the desired access to the memory component 130 and / or memory device 140. The memory subsystem controller 115 may handle other operations such as wear leveling, garbage collection, error detection and correction coding (ECC) operations, encryption, caching, and address translation between logical block addresses and physical block addresses associated with the memory device 140. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 140 and translate responses associated with the memory device 140 into information for the host system 120.

[0039] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache memory or buffer (e.g., DRAM) and an address circuitry (e.g., a row decoder and a column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 140.

[0040] In some embodiments, memory device 140 includes a local media controller 135, which operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 140. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 140 (e.g., perform media management operations on memory device 140). In some embodiments, memory device 140 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local media controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0041] The memory subsystem controller 115 includes a mapping matrix component 113 that can provide and / or generate mapping information for grouped memory cells corresponding to the charge levels of their bit representations on a memory device (e.g., memory device 140). The mapping matrix component 113 enables the memory subsystem 110 to perform operations, such as read and write operations, (via the memory subsystem controller 115). The memory subsystem can maintain a matrix that stores the allocation of charge levels to bit representations of multiple memory cell groups. By utilizing a matrix representation of the mapping between memory cell groups and charge levels to bit representations, more data can be stored using the same number of memory cells compared to conventional memory storage devices. Furthermore, each memory cell can efficiently store a non-integer number of bits (e.g., X.5 bits) (via the charge level of the memory cell).

[0042] Mapping matrix component 113 can store some or all of the mapping information of grouped memory cells of individual memory devices. Mapping matrix component 113 can correspond to memory cell group component 109 to locate, read from, or program into a requested memory cell group. Furthermore, compared to a conventional system with the same number of physical memory cells, memory cell groups and mapping matrices can store more data in a given set of physical memory cells. Further details regarding the operation of mapping matrix component 113 and memory cell group component 109 are described below. (The text here refers to...) Figure 2 An example of this situation is shown and described.

[0043] Figure 2 This is a schematic matrix mapping 200 for the first cell group. As shown in the figure, Figure 2 A matrix mapping 200 is shown for a first cell 204 (e.g., an X-cell) and a second cell 206 (e.g., a Y-cell) in a memory cell group 202, which may also be referred to herein as a “supercell.” In this example, both the first cell 204 and the second cell 206 support three charge levels (0, 1, 2). These three charge levels can be used to represent three bits (e.g., column bit 0, bit 1, and bit 2; 208). The charge levels used for the first cell 204 and the second cell 206 are combined to form a “supercell” capable of accommodating nine different charge levels (0 to 8), thus allowing a “supercell” to represent three bits.

[0044] The last row of matrix map 200 is shown in gray shading. This row can be considered "don't care" charge levels when the number of charge levels in memory cell group 202 exceeds the number of charge levels required to represent three bits. In some embodiments, charge level 8 of cell group 202 is considered a "don't care" level. In some embodiments, any of the charge levels in a cell group is considered a "don't care" level. The number of "don't care" levels can correspond to the number of bits represented and the number of charge levels in the cell group.

[0045] Figures 3A-3B The matrix mapping 300 for the cell group is shown. For example... Figure 3A As shown, the first matrix 302 is a 9×9 matrix used to map 3.5 bits per cell or 7 bits per group. This first matrix 302 can be manipulated to create a mapping of 4.5 bits per cell or 9 bits per group. By applying one or more matrix functions, a second matrix 304 can be generated to represent the mapping of cell groups with higher bit-level storage capacity. For example, the first matrix 302 is organized into the same 3×3 matrix quadrant. Integer matrix multiplication is applied to the upper left matrix 302-1. In turn, the same integer matrix multiplication is applied to the upper right matrix 302-2, and the first integer is added. The same integer matrix multiplication is applied to the lower left matrix 302-3, and the second integer is added. The same integer matrix multiplication is applied to the lower right matrix 302-4, and the third integer is added. In matrix mapping 300, the top-left matrix 302-1 is multiplied by four, the top-right matrix 302-2 is multiplied by four and incremented by one, the bottom-left matrix 302-3 is multiplied by four and incremented by two, and the bottom-right matrix 302-4 is multiplied by four and incremented by three. The resulting mapping of the second matrix 304 is a mapping of 4.5 bits per cell or 9 bits per memory cell group (e.g., per supercell). For example, in... Figures 5A-5C As described in more detail, these matrix maps can be manipulated to create new matrix maps and maps compatible with read and / or write operations.

[0046] Figure 3B The second matrix 304, which is further manipulated to the third matrix 306, is shown (e.g., Figure 3A The second matrix (304). In Figure 3B In this matrix, both the second and third matrices represent a mapping of 4.5 bits per cell or 9 bits per memory cell group. A matrix operation, such as a 1-bit cyclic shift operation, is applied to the rows and columns of the second matrix 304 to generate the third matrix 306.

[0047] In some embodiments, the mapping assignment matrix satisfies the following constraint: {0,1,2,…,2} k -1} Unique (∑) p 2p M p ), where M p It is a matrix of size L×L, where L is the number of charge levels and k is the number of assignments.

[0048] Figures 4A-4C This is a flowchart of an example method 400 for performing data operations on a group of memory cells according to some embodiments of this disclosure. Method 400 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, by Figure 1 Mapping matrix component 113 alone or in combination Figure 1 The memory cell group component 109 executes method 400. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0049] In operation 405, the processing device receives a request to perform a data operation associated with at least one memory cell. The memory device may include a plurality of memory cells, each memory cell containing a first group of memory cells. Each memory cell in the first group of memory cells supports a specified number of charge levels, such that each charge level represents a non-integer number of bits. The first group of memory cells represents the first bit sequence based on a first charge level sequence stored in the first group of memory cells, and the first bit sequence has an integer number of bits.

[0050] In some embodiments of this disclosure, the first memory cell group comprises two or more memory cells. Each memory cell supports the same number of charge levels. For example, the first memory cell and the second memory cell may each support 23 charge levels, which allows the first memory cell and the second memory cell to each represent a non-integer number of bits (e.g., 4.5 bits for each of the first memory cell and the second memory cell).

[0051] For example, the first memory cell group includes first memory cells and second memory cells, each of which supports 23 charge levels, and the first memory cell group supports 529 different charge level sequences. The first bit sequence includes 9 data bits. The memory device may contain 16KB of data word lines, and each word line is represented by 9 pages of 8KB of data.

[0052] In some embodiments, each of the first memory cell and the second memory cell supports 24 charge levels, and the first memory cell group supports 579 different charge level sequences.

[0053] In some embodiments, the first memory cell group includes first memory cells and second memory cells, each of which supports three charge levels and an individual sequence of 1.5 data bits. In some other embodiments, each of the first and second memory cells supports six charge levels and represents 2.5 data bits. In some other embodiments, each of the first and second memory cells supports 12 charge levels and represents 3.5 data bits. In some other embodiments, each of the first and second memory cells supports 23 or 24 charge levels and represents 4.5 data bits.

[0054] exist Figure 4B Operation 406-A: The processing device reads the charge level sequence from the first memory cell group.

[0055] In operation 407-A, the processing device determines the first sequence corresponding to the first charge level sequence based on a mapping stored in the memory device. The processing device may contain a number of mappings stored in the system for different groups of memory cells. It should be understood that although memory cells are referred to as grouped memory cells, memory cells are not necessarily within the same physical vicinity of each other.

[0056] In operation 408-A, the processing device performs data operations at least in part by providing a first-bit sequence in response to a request.

[0057] exist Figure 4C In operation 406-B, the processing device determines a second charge level sequence corresponding to a second bit sequence of a second group of memory cells to be written to at least one memory cell, based on a mapping stored in the system. Each memory cell in the second group of memory cells supports a specified number of charge levels, such that each charge level can represent a non-integer number of bits.

[0058] In operation 407-B, the processing apparatus performs data operations at least in part by causing a second group of memory cells to store a second charge level sequence. In some embodiments, the second group of memory cells stores the second charge level sequence by applying a voltage to a memory cell as indicated by the second charge level sequence.

[0059] return Figure 4AIn the final operation 410, the processing apparatus performs data operations relative to at least one memory cell based on a mapping stored on the system. This mapping assigns individual charge level sequences stored in individual memory cell groups to individual bit sequences represented by those individual memory cell groups. In some embodiments, the mapping assigns individual charge level sequences to individual bit sequences that satisfy a specified Gray code constraint or are below a specified Gray code penalty value. A Gray code is a specific mapping from bit to symbol (e.g., charge level) that minimizes the Hamming distance (bit difference) between two adjacent symbols (e.g., charge levels). The Gray code constraint is the number of bit flips per symbol error, with an error rate (e.g., a Gray code constraint) of 1. Operations 405 to 410 can be repeated as needed.

[0060] Figures 5A-5C This is a flowchart of an example method 500 for preparing a mapping matrix according to some embodiments of the present disclosure, the mapping matrix comprising a mapping of charge levels to bit representations on a group of memory cells. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuit system, dedicated logic, programmable logic, microcode, device hardware, integrated circuit, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, by Figure 1 Mapping matrix component 113 alone or in combination Figure 1 The memory cell group component 109 executes method 500. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0061] In operation 505, the processing device generates a first matrix representing a first mapping from a sequence of charge levels to a sequence of bits in a first group having two memory cells. Each memory cell in the first group supports two charge levels and represents one data bit. In some embodiments, the generated first matrix is ​​represented as:

[0062]

[0063] In operation 510, the processing device generates a second matrix representing a second mapping from a sequence of charge levels to a bit sequence in a second group having two memory cells. Each memory cell in the second group supports three charge levels and represents 1.5 data bits. In some embodiments, the generated second matrix is ​​represented as follows:

[0064]

[0065] In operation 515, the processing device applies matrix operations to the first matrix and the second matrix.

[0066] exist Figure 5B In operation 516, the processing device generates a fourth matrix, which represents a fourth mapping from the charge level sequence to the bit sequence of a third group having two memory cells. Each memory cell in the third group supports 12 charge levels and represents 3 data bits.

[0067] In operation 517, the processing device applies a second matrix operation to the second and fourth matrices. For example, a matrix operation such as the Kronecker product is applied between the second and fourth matrices to generate a fifth matrix (see operation 518).

[0068] In operation 518, the processing device generates a fifth matrix, which represents the fifth mapping of a sequence of 529 charge levels and represents 9 data bits.

[0069] Figure 5C Described about in Figure 5B The operation at position 518 generates the fifth matrix. Figure 5C In operation 519-1, the processing device divides the fifth matrix into equal quadrants. For example, as... Figure 3A The 9×9 matrix 302 shown is divided into four identical 3×3 matrix quadrants.

[0070] In operation 519-2, the processing device applies one or more matrix operations to each quadrant. In some embodiments, the second matrix is ​​a mapping of 1 bit per cell, and the fourth matrix is ​​a mapping of 1.5 bits per cell or 3 bits per group. The resulting fifth matrix is ​​a mapping of 2.5 bits per cell or 5 bits per group.

[0071] In another example, the second matrix is ​​a standard 3-bit mapping per cell, and the fourth matrix is ​​a mapping of 1.5 bits per cell or 3 bits per group. The resulting fifth matrix is ​​a mapping of 4.5 bits per cell or 9 bits per group. In other words, a matrix mapping of X.5 bits per cell can be generated from A + B.5, where A + B = X.

[0072] In operation 519-3, the processing device generates a new version of the fifth matrix. In some embodiments, the mapping of the fifth matrix is ​​manipulated to create a new version of the fifth matrix, which includes features that allow the processing device to quickly read data stored in the fifth cell group. In some embodiments, a cyclic shift operation is applied to the fifth matrix to generate a new version of the fifth matrix.

[0073] In operation 520, the processing device generates a third matrix representing a third mapping of a charge level sequence to a bit sequence of a third group having two memory cells. Each memory cell in the third group supports six charge levels and represents 2.5 data bits. In some embodiments, the third mapping of the sequence represents the Gray code of the third memory cell group.

[0074] In operation 525, the processing device stores each matrix on a memory device coupled to the processing device. In some embodiments, the processing device stores any combination of the first matrix, the second matrix, the third matrix, the fourth matrix, and the fifth matrix.

[0075] Figure 6 Interaction diagrams are provided illustrating interactions between components of a computing environment in the context of some embodiments, where methods using data allocation techniques on memory devices as described herein are performed. The operations of the methods can be performed by processing logic, which may include hardware (e.g., processing devices, circuit systems, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, the methods are performed by a host system (e.g., host system 120), a memory subsystem controller (e.g., memory subsystem controller 115), a memory device (e.g., memory device 140), or some combination thereof. Although operations are shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be performed in different orders, and some processes may be performed in parallel. Additionally and / or alternatively, one or more processes may be omitted in various embodiments. Therefore, not all processes are used in every embodiment. Figure 6 In the context of the example shown, the host system may include host system 120, the memory subsystem controller may include memory subsystem controller 115, and the memory device may include memory device 140.

[0076] like Figure 6 As shown, in operation 602, the host system sends a memory command associated with a memory cell to the memory subsystem 110. In operation 604, the memory subsystem controller 115 receives a memory command associated with a request to perform a data operation. In operation 606, the memory device provides a mapping that assigns individual charge level sequences to individual bit representation sequences of memory cells in the memory device.

[0077] In response to a memory command received in operation 604, the memory subsystem controller 115 performs the requested data operation. The data operation is performed based on the mapping allocation of the memory device. Based on the mapping, a charge level sequence corresponding to a first charge level sequence is determined.

[0078] In operation 610, based on the received read memory command, the memory device reads the charge level sequence from the memory cell group associated with the memory command and provides the first bit sequence corresponding to the first charge level sequence.

[0079] In operation 612, based on the received write-to-memory command, the memory device causes the memory cell group to store the first charge level sequence.

[0080] In operation 614, after the memory subsystem controller 115 completes the execution of the requested data operation, the host system receives an instruction associated with the execution of the memory command. The host system may decide to repeat steps 602-614 by providing one or more memory commands associated with the memory cell to the memory subsystem controller 115.

[0081] Figure 7 An example machine of computer system 700 is shown, within which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 700 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110) or can be used to perform controller operations (e.g., execute the operating system to perform operations corresponding to...). Figure 1 (Operation of the mapping matrix component 113). In an alternative embodiment, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a client-server network environment as a server or client machine in a cloud computing infrastructure or environment.

[0082] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network appliance, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is shown, the term "machine" should also be considered to include any set of machines that individually or collectively execute a set of instructions (or multiple sets of instructions) to perform any or more of the methods discussed herein.

[0083] Example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0084] Processing device 702 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets or a combination of instruction sets. Processing device 702 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. Computer system 700 may further include a network interface device 708 for communication via network 720.

[0085] Data storage system 718 may include machine-readable storage medium 724 (also referred to as computer-readable medium) on which one or more sets of instructions 728 or software embodying any one or more methods or functions described herein are stored. Instructions 728 may also reside wholly or at least partially within main memory 704 and / or processing device 702 during execution by computer system 700, which also constitute machine-readable storage medium. Machine-readable storage medium 724, data storage system 718, and / or main memory 704 may correspond to... Figure 1 The memory subsystem 110.

[0086] In one embodiment, instruction 726 includes instructions for implementing a component corresponding to a memory cell group (e.g., Figure 1The machine-readable storage medium 724 contains functional instructions for the memory cell group 109 and / or mapping matrix component 113. Although the machine-readable storage medium 724 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of stored instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing a set of instructions executable by a machine or encoding said set of instructions and causing a machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0087] Some parts of the previously described in detail have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce the desired result. An operation is an operation that requires physical manipulation of a physical quantity. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, quantities, etc.

[0088] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient notations applied to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate data represented as physical (electronic) quantities in the registers and memories of the computer system and transform said data into other data similarly represented as physical quantities in the memory or registers or other such information storage systems of the computer system.

[0089] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or the apparatus may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0090] The algorithms and demonstrations presented herein are inherently independent of any particular computer or other device. Various general-purpose systems can be used with programs based on the teachings herein, or it may prove convenient to construct more specialized devices to execute the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It will be understood that the teachings of this disclosure as described herein can be implemented using various programming languages.

[0091] This disclosure can be provided as a computer program product or software, which may include a machine-readable medium on which instructions are stored for programming a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0092] In the foregoing description, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications can be made to the present disclosure without departing from the broader scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be regarded as illustrative rather than restrictive.

Claims

1. A system comprising: A memory device comprising multiple memory cells, each memory cell comprising one or more memory information cells; as well as The memory controller of the memory device is configured to perform operations including the following: A request is received to perform a read operation associated with at least one of the plurality of memory cells, the at least one memory cell comprising a first group of memory cells, each memory cell in the first group of memory cells supporting a specified number of charge levels such that each memory cell having a specified charge level represents a non-integer number of bits, the first group of memory cells representing a first bit sequence based on a first charge level sequence stored in the first group of memory cells, and the first bit sequence comprising an integer number of bits; and The read operation is performed on the at least one memory cell based on mapping information stored in the system, wherein the mapping information maps individual charge level sequences stored in individual memory cell groups to individual bit sequences below a specified Gray code penalty value, and wherein the mapping information includes a mapping assignment matrix that satisfies the constraint: {0, 1, 2, … , } only , in It is a matrix of size L×L, where L is the specified number of charge levels, k is the number of allocations, and performing the read operation includes: Read the first charge level sequence from the first memory cell group; The first bit sequence corresponding to the first charge level sequence is determined based on the mapping assignment matrix; and The first bit sequence is provided in response to the request.

2. The system of claim 1, wherein the first memory cell group comprises two or more memory cells, each memory cell supporting a specific number of charge levels.

3. The system of claim 1, wherein the first memory cell group supports 529 different charge level sequences, the first bit sequence includes 9 data bits, the memory device includes 16KB word lines, and each word line is represented by 9 pages of size 8KB.

4. The system of claim 1, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting three charge levels and representing the individual sequence of 1.5 data bits.

5. The system of claim 1, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting 6 charge levels and representing the individual sequence of 2.5 data bits.

6. The system of claim 1, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting 12 charge levels and representing the individual sequence of 3.5 data bits.

7. The system of claim 1, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting 24 charge levels and representing the individual sequence of 4.5 data bits.

8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing means of a memory device, cause the processing means to perform operations including: A request is received to perform a read operation associated with at least one of a plurality of memory cells in the memory device, the at least one memory cell comprising a first group of memory cells, each memory cell in the first group of memory cells supporting a specified number of charge levels such that each memory cell having a specified charge level represents a non-integer number of bits, the first group of memory cells representing a first bit sequence based on a first charge level sequence stored in the first group of memory cells, and the first bit sequence comprising an integer number of bits; and The read operation is performed on the at least one memory cell based on mapping information, wherein the mapping information maps individual charge level sequences stored in individual memory cell groups to individual bit sequences below a specified Gray code penalty value, and wherein the mapping information includes a mapping allocation matrix that satisfies the constraint: {0, 1, 2, … , } only , in It is a matrix of size L×L, where L is the specified number of charge levels, k is the number of allocations, and performing the read operation includes: Read the first charge level sequence from the first memory cell group; The first bit sequence corresponding to the first charge level sequence is determined based on the mapping assignment matrix; as well as The first bit sequence is provided in response to the request.

9. The non-transitory computer-readable storage medium of claim 8, wherein the first memory cell group comprises two or more memory cells, each memory cell supporting a specific number of charge levels.

10. The non-transitory computer-readable storage medium of claim 8, wherein the first memory cell group supports 529 different charge level sequences, the first bit sequence comprising 9 data bits, the memory device comprising 16KB of word lines, and each word line being represented by 9 pages of size 8KB.

11. The non-transitory computer-readable storage medium of claim 8, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting three charge levels and representing the individual sequence of 1.5 data bits.

12. The non-transitory computer-readable storage medium of claim 8, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting six charge levels and representing the individual sequence of 2.5 data bits.

13. The non-transitory computer-readable storage medium of claim 8, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting 12 charge levels and representing the individual sequence of 3.5 data bits.

14. The non-transitory computer-readable storage medium of claim 8, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting 24 charge levels and representing the individual sequence of 4.5 data bits.

15. A method performed at a memory device, the memory device comprising a plurality of memory cells, each memory cell comprising one or more memory information cells, the method comprising: A request is received to perform a read operation associated with at least one of the plurality of memory cells, the at least one memory cell comprising a first group of memory cells, each memory cell in the first group of memory cells supporting a specified number of charge levels such that each memory cell having a specified charge level represents a non-integer number of bits, the first group of memory cells representing a first bit sequence based on a first charge level sequence stored in the first group of memory cells, and the first bit sequence comprising an integer number of bits; and The read operation is performed on the at least one memory cell based on mapping information, wherein the mapping information maps individual charge level sequences stored in individual memory cell groups to individual bit sequences below a specified Gray code penalty value, and wherein the mapping information includes a mapping allocation matrix that satisfies the constraint: {0, 1, 2, … , } only , in It is a matrix of size L×L, where L is the specified number of charge levels, k is the number of allocations, and performing the read operation includes: Read the first charge level sequence from the first memory cell group; The first bit sequence corresponding to the first charge level sequence is determined based on the mapping assignment matrix; and The first bit sequence is provided in response to the request.

16. The method of claim 15, wherein the first memory cell group comprises two or more memory cells, each memory cell supporting a specific number of charge levels.

17. The method of claim 15, wherein the first memory cell group supports 529 different charge level sequences, the first bit sequence comprising 9 data bits, the memory device comprising 16KB of word lines, and each word line being represented by 9 pages of size 8KB.

18. The method of claim 15, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting three charge levels and representing the individual sequence of 1.5 data bits.

19. The method of claim 15, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting six charge levels and representing the individual sequence of 2.5 data bits.

20. The method of claim 15, wherein the first memory cell group comprises a first memory cell and a second memory cell, each of the first memory cell and the second memory cell supporting 12 charge levels and representing the individual sequence of 3.5 data bits.

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