Secure storage

Abstract

Various embodiments of this disclosure relate to secure memory. The memory includes memory cells arranged in rows and columns, having at least one bit line for each column coupled to the memory cells of that column. Read / write circuitry is coupled to the bit lines and configured to receive binary data to be stored in one memory cell of the column for each column. For each column, the read / write circuitry includes: a latch configured to store a key bit; and encryption circuitry configured to encrypt the received binary data using the key bit to provide encrypted binary data. The read / write circuitry controls the bit lines to store the encrypted binary data.

Description

[0001] priority

[0002] This application claims priority to French patent application No. 2014086, filed on December 23, 2020, the entire contents of which are incorporated herein by reference to the full extent permitted by law. Technical Field

[0003] This disclosure generally relates to electronic circuit memories, and more specifically to methods and systems for protecting memories from attacks. Background Technology

[0004] Data stored in memory may include critical information. Therefore, it is desirable to prevent unauthorized access to such critical data. It is known to use a key to encrypt data stored in memory to prevent unauthorized access. However, the key itself must be inaccessible. Therefore, there is a need to improve the security of critical data stored in memory. Summary of the Invention

[0005] An embodiment provides a memory having memory cells arranged in rows and columns, wherein at least one bit line for each column is coupled to the memory cell of the column; and read / write circuitry coupled to the bit lines and configured to receive binary data to be stored in one memory cell of the column for each column. For each column, the read / write circuitry includes: a latch configured to store a key bit; and encryption circuitry configured to encrypt the received binary data using the key bit, thereby providing encrypted binary data. The read / write circuitry is configured to control the bit lines to store the encrypted binary data.

[0006] The embodiment also provides a data storage method in a memory having memory cells arranged in rows and columns, wherein at least one bit line for each column is coupled to the memory cells of the column. Read / write circuitry is coupled to the bit lines and receives binary data from one memory cell in the column's memory cells for each column. For each column, the read / write circuitry includes a latch storing a key bit and circuitry for encrypting the received binary data with the key bit to deliver encrypted binary data, the bit lines being controlled to store the encrypted binary data.

[0007] According to an embodiment, for each column, the read / write circuit includes circuitry for detecting the logic level of a bit line, configured to deliver read binary data dependent on the logic level. For each column, the operation of reading encrypted binary data from one memory cell stored in the column's memory cells sequentially includes the step of selecting a memory cell, and the step of reading by the detection circuitry of the bit line's level after a first time period has elapsed. For at least one column, the read / write circuitry is configured to store a key bit in a latch associated with the column, the key bit corresponding to binary data provided by the detection circuitry after a second time period has elapsed, the second time period being shorter than the first time period.

[0008] According to an embodiment, for at least one column, the read / write circuitry is configured to store a key bit in a latch associated with the column when the memory is powered on, the key bit corresponding to binary data stored in a memory cell of the column when the memory is powered on.

[0009] According to an embodiment, for each column, the read / write circuit is configured to: decrypt encrypted data in one memory cell of the memory cells in that column upon request, and deliver the decrypted binary data.

[0010] According to an embodiment, for each column, the read / write circuitry is configured to directly deliver encrypted binary data from one of the memory cells stored in that column upon request.

[0011] According to an embodiment, for each column, the read / write circuitry is configured to deliver, upon request, key bits stored in a latch associated with that column.

[0012] According to an embodiment, each column includes a sub-column of memory cells. During a write operation, the binary data received for each column is encrypted, and the encrypted binary data is stored only in the memory cells of one sub-column of the sub-column.

[0013] According to an embodiment, during a write operation, when the sub-column has an odd number of levels, one of the key bits or one of the inverted key bits is used to encrypt the received binary data, and when the sub-column has an even number of levels, the other of the key bit and the inverted key bit is used to encrypt the received binary data.

[0014] According to an embodiment, for each column, the read / write circuitry includes an additional latch configured to store additional key bits. During a write operation, when the sub-column has an odd number of levels, one of the key bits or one of the additional key bits is used to encrypt the received binary data, and when the sub-column has an even number of levels, another is used to encrypt the received binary data.

[0015] According to an embodiment, the rows of memory cells are distributed in a first row and a second row. For each column, the read / write circuitry includes an additional latch configured to store additional key bits. During a write operation, when the sub-column has an odd number of levels and the selected row is one of the first rows, the received binary data is encrypted using one of the key bits or one of the additional key bits or an inverted version of one of the key bits, or an inverted version of one of the additional key bits.

[0016] When the sub-column has an even number of levels and the selected row is one of the first rows, the received binary data is encrypted using another key bit, or another additional key bit, or the inverted form of another key bit, or the inverted form of another additional key bit. When the sub-column has an odd number of levels and the selected row is one of the second rows, the received binary data is encrypted using yet another key bit, or another additional key bit, or the inverted form of another key bit, or the inverted form of another additional key bit. When the sub-column has an even number of levels and the selected row is one of the second rows, the received binary data is encrypted using yet another key bit, or another additional key bit, or the inverted form of another key bit, or the inverted form of another additional key bit, or the inverted form of another additional key bit.

[0017] According to an embodiment, each latch includes a first tri-state inverter, an inverter connected in series with the first tri-state inverter, and a second tri-state inverter connected in antiparallel with the inverter. Attached Figure Description

[0018] The foregoing features and advantages, as well as other features and advantages, will be described in detail below with reference to the accompanying drawings, which are illustrated but not limited to the description of specific embodiments, in which:

[0019] Figure 1 Examples of the random access memory (RAM) described herein are shown in part and schematically.

[0020] Figure 2 This shows the process during a write operation. Figure 1 Timing diagram of the signals in the memory;

[0021] Figure 3 This shows the process during the read operation. Figure 1 Timing diagram of the signals in the memory;

[0022] Figure 4 An embodiment of the secure RAM described herein is shown in part and schematically.

[0023] Figure 5 The following is illustrated during an embodiment of the key generation method. Figure 4 Timing diagram of the signals in the memory;

[0024] Figure 6 Another embodiment of the key generation method is shown. Figure 4 Timing diagram of the signals in the memory;

[0025] Figure 7 Another embodiment of the RAM described herein is shown in part and schematically.

[0026] Figure 8 Another embodiment of the RAM described herein is shown in part and schematically.

[0027] Figure 9 Another embodiment of the RAM described herein is shown in part and schematically.

[0028] Figure 10 This shows the key reading operation. Figure 4 Timing diagram of the signals in the memory;

[0029] Figure 11 A schematic block diagram of an embodiment of the memory circuit described herein is shown;

[0030] Figure 12 It shows Figure 7 A schematic block diagram of a portion of an embodiment of the memory;

[0031] Figure 13 A schematic block diagram of an embodiment of a memory cell for storing key bits as described herein is shown;

[0032] Figure 14 It shows Figure 7 A schematic block diagram of another part of an embodiment of the memory;

[0033] Figure 15 It shows Figure 7 A schematic block diagram of another part of an embodiment of the memory;

[0034] Figure 16 It shows Figure 4 A schematic block diagram of a portion of an embodiment of the memory;

[0035] Figure 17 It shows Figure 4 A schematic block diagram of another part of an embodiment of the memory;

[0036] Figure 18 It shows Figure 4 A schematic block diagram of another part of an embodiment of the memory;

[0037] Figure 19 It shows Figure 4A schematic block diagram of another part of an embodiment of the memory;

[0038] Figure 20 It shows Figure 19 A variant of the schematic block diagram;

[0039] Figure 21 It shows Figure 19 or Figure 20 The timing diagram of the circuit signals;

[0040] Figure 22 It shows Figure 4 A schematic block diagram of another part of an embodiment of the memory; and

[0041] Figure 23 It shows Figure 4 A schematic block diagram of another part of an embodiment of the memory. Detailed Implementation

[0042] In the various figures, the same features are indicated by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference and may be provided with the same structure, dimensions, and material properties.

[0043] For clarity, only the steps and elements useful for understanding the embodiments described herein are described in detail. In particular, methods and systems for protecting memory from attacks are provided.

[0044] Unless otherwise stated, when referring to two elements connected together, it means that there is no direct connection of any intermediate element other than a conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0045] Furthermore, a signal that alternates between a first constant state (e.g., a logic low state, labeled "0") and a second constant state (e.g., a logic high state, labeled "1") is called a "binary signal." The high and low states of different binary signals in the same electronic circuit can be different. In practice, a binary signal can correspond to a voltage or current that may not be perfectly constant in either a high or low state.

[0046] In the following description, when referring to terms that define absolute position, such as “front,” “rear,” “top,” “bottom,” “left,” “right,” or to terms that define relative position, such as “above,” “below,” “upper,” “lower,” etc., or to terms that define direction, such as “horizontal,” “vertical,” etc., they refer to the orientation of the figure or “a…” in its normal position of use.

[0047] Unless otherwise stated, the expressions “about,” “probably,” “basically” and “approximately” indicate within 10%, and preferably within 5%.

[0048] In the following description, the source and drain of a MOS transistor are referred to as the "power terminals" or "conduction terminals" of the MOS transistor.

[0049] Figure 1 A partially simplified embodiment of a random access memory (RAM) 10 is shown. The memory 10 includes: an array 12 of memory cells 14 arranged in rows and columns; for each row, word lines 16 coupled to the memory cells 14 in that row; row control circuitry 18 configured to control the word lines 16, receive a digital row address signal AD, and deliver a binary select signal WL on each word line 16; and for each column, two bit lines 20 and 22 coupled to the memory cells 14 in that column receive binary signals BLT and BLF, respectively.

[0050] The memory 10 also includes: a read / write (R / W) circuit 24 coupled to bit lines 20 and 22 of all columns; a processing circuit 26 that receives a binary clock signal CK, a binary control signal CSN (chip select), WEN (write enable) for read or write operations, and a digital address signal AD, the processing circuit 26 being configured to transmit the digital address signal AD to the row control circuit 18 and to transmit control signals for read or write operations to the read / write circuit 24; a dummy memory cell column 28; and an interface circuit 32 coupled to the processing circuit 26, the read / write circuit 24, and the dummy memory cell column 28, the interface (I / F) circuit 32 being configured to transmit a binary signal SAE (sensor amplifier enable) for read operations to the read / write circuit 24 and a binary signal Reset indicating the end of a read operation to the processing circuit 26.

[0051] The read / write circuit 24 is configured to receive binary data Di for each column of memory cell 14 corresponding to the row of address signal AD, and is configured to control bit lines 20 and 22 according to the binary data Di to store the binary data in the column of memory cell 14 and the row of memory cell 14 corresponding to the address signal AD. The read / write circuit 24 is also configured to deliver binary data Qi read from the row of memory cell 14 corresponding to the address signal AD for each column. For each column, the read / write circuit 24 includes a detection circuit (Det) 34, which is configured to deliver binary data as logic "0" or logic "1" based on the difference between signals BLT and BLF.

[0052] The operation of memory 10 is rated by clock signal CK.

[0053] Figure 2This shows the process during a write operation. Figure 1 The timing diagram of the signals of memory 10. Time intervals tA1, tA2, and tA3 are consecutive.

[0054] Time tA0 corresponds to the rising edge of the clock signal CK. Before time tA0, the binary signal CSN is set to logic "0" and the binary signal WEN is set to logic "1", thereby controlling the write operation. The signal SAE is held at logic "0" for the entire write operation. At time tA0, the processing circuit 26 transmits the address signal AD, specifying the memory row to be written to, to the row control circuit 18. At time tA1, the row control circuit 18 sets the selection signal WL for the row corresponding to the address signal AD to logic "1", while the signal WL for other rows is held at logic "0". For each column, the read / write circuit 24 sets the column BLT / BLF signal to logic "0" or logic "1" according to the binary data Di to be written to each memory cell 14 of the selected row, where the signals BLT and BLF are complementary. At time tA2, the row signal WL associated with the selected row switches to logic "0". At time tA3, the write operation ends.

[0055] Figure 3 This shows the process during the read operation. Figure 1 The timing diagram of the signals of memory 10. Time intervals tB0, tB1, tB2, tB3, and tB4 are consecutive.

[0056] Time tB0 corresponds to the rising edge of signal ck. Before time tB0, binary signal CSN is set to logic "0" and binary signal WEN is set to logic "0", thereby controlling the read operation. Read / write circuit 24 sets signals BLT and BLF for each column to logic "1". At time tB0, processing circuit 26 transmits the address signal AD to row control circuit 18, specifying the memory row from which to perform the read operation. At time tB1, row control circuit 18 sets the selection signal WL for the row corresponding to address signal AD to logic "1", and sets the signal WL for other rows to remain at logic "0".

[0057] For each column, signals BLT and BLF then change according to the binary data stored in the memory cell 14 of the selected row; one signal BLT or BLF switches to logic "0," while the other signal BLT or BLF remains at logic "1." For each column, the detection circuit 34 of the read / write circuit delivers binary data at logic "0" or logic "1" from the interval between signals BLT and BLF, corresponding to the binary data stored in the memory cell 14 of the column and the selected row. This binary data also corresponds to the binary data Qi provided by the read / write circuit 24 at time tB3. The selection signal WL for the selected row switches to logic "0" at time tB4, and signal SAE is set to logic "0." To reduce the duration of the read operation, the detection circuit 34 is configured to deliver binary data at logic "0" or logic "1," even if the two signals BLT and BLF have not yet reached their respective binary states of logic "0" and logic "1." A time window for setting the signal SAE to logic "1" is selected such that, for each column, the interval between signals BLT and BLF is sufficient to ensure that the binary data provided by the detection circuit 34 is correct. Columns of dummy memory cells 28, which may have the same structure as memory cells 14, enable the interface circuit 32 to deliver the signal SAE, taking into account the characteristics of memory cells 14.

[0058] Figure 4 A partially simplified embodiment of RAM40 is shown. RAM40 includes... Figure 1 All elements of the RAM 10 shown have a read / write circuit 24 that also includes an encryption / decryption (CRY) circuit 42, and a processing circuit 26 that also includes a security (SEC) circuit 44.

[0059] According to an embodiment, the encryption / decryption operation uses a key. For each column, the read / write circuitry 24 also includes a memory cell (ck) 46 with key bits stored therein. According to an embodiment, each memory cell 46 includes a flip-flop.

[0060] Processing circuit 26 also receives binary signal RdCry, binary signal GenKey, and signal ReadKey.

[0061] During a write operation, for each column, the encryption / decryption circuit 42 is configured to deliver binary data X obtained by encrypting the binary data Di using a key, based on the binary data Di to be stored. The binary data X is stored in the memory unit 14 of the column and the selected row. Figure 4 The timing diagram of signals CK, AD, CSN, WEN, WL, BLF, BLT, SAE, and Qi of memory 40 during write operations is shown below. Figure 2The timing diagram is the same, except that for each column, the signals BLF and BLT change according to the encrypted binary data X, but not according to the binary data Di, which is stored in the memory unit 14 of the column and the selected row.

[0062] According to an embodiment, the security circuit 44 controls the operation of the encryption / decryption circuit 42 based on the value of the binary signal RdCry during a read operation. During the operation of reading binary data stored in the memory 40 from the row corresponding to the address signal AD, the binary signal RdCry controls whether the read binary data is decrypted or not. During the read operation, Figure 4 The timing diagrams of signals CK, AD, CSN, WEN, WL, BLF, BLT, SAE, and Qi in memory 40 are shown below. Figure 3 The timing diagram is the same, except that for each column, the signals BLF and BLT vary according to the encrypted binary data X, which is stored in memory cell 14 of the column and the selected row. This advantageously enables protection in memory so that it cannot be detected by read operations by encrypting the data stored in memory.

[0063] According to the first operating mode controlled by the signal RdCry, the encrypted binary data stored in memory 40 is decrypted using a key, and the binary data Qi is determined by the encryption / decryption circuit 42. According to the second operating mode controlled by the signal RdCry, the binary data Qi directly corresponds to the encrypted binary data stored in memory 40.

[0064] The generation of new key values ​​is controlled by the GenKey signal.

[0065] Figure 5 An example of generating a new value for the key is shown. Figure 4 The timing diagram of the signals of memory 40. According to this embodiment, the generation of a new key value is based on a modified read operation.

[0066] Figure 5 The timing diagram and Figure 3The timing diagram is the same, except that the signal SAE is set to logic "1" at time tC1, substantially simultaneously with the time tB1 when the selection signal WL is set to logic "1". For each column, the detection circuit 34 of the read / write circuit 24 determines the binary data SENO from the interval between signals BLT and BLF at time tC2 after time tC1. The binary data SENO is stored in the memory cell 46 associated with the column and corresponds to a key bit. For each column, signals BLT and BLF change from time tB1 based on the binary data stored in the memory cells of the column and the selected row. Due to fluctuations in the structure of the memory cells and the detection circuit 34, and due to fluctuations in the signals present in these components, the precise values ​​of signals BLF and BLT shortly after time tB1 cannot be known in advance. The time window for signal SAE to be set to logic "1" is chosen to be close enough to tB1 to ensure that the binary data delivered by the detection circuit 34 cannot be known in advance. Therefore, for each column, the detection circuit 34 randomly delivers the signal SEO at logic "0" or logic "1". This yields a new value for the key.

[0067] Figure 6 Another embodiment based on the new value of the generated key is shown. Figure 4 The timing diagram of the signals of memory 40 is shown. According to this embodiment, the generation of a new key value is based on the operation of reading binary data stored in a memory cell after the memory cell of a row of memory 40 has been powered on but before a write operation has been performed in that row of memory cell. In fact, when RAM 40 is powered on, the binary data stored in each memory cell 14 stabilizes at logic "0" or logic "1" in an unpredictable and unreproducible manner during each power-on cycle of RAM 40.

[0068] Figure 6 The timing diagram and Figure 3 The timing diagram is the same, except that for each column, the detection circuit 34 of the read / write circuit 24 delivers binary data SENO, which corresponds to the data read from the memory cell 14 of the column and the selected row. Figure 6 In the diagram, time tB3 has been shown as a variant following time tB4. The binary data SENO is stored in memory cell 46 associated with the column and corresponds to a key bit. Therefore, a new, unpredictable value for the key is obtained.

[0069] According to an embodiment, the memory cells 46 of the read / write circuit 24 are distributed into a first memory cell and into a second memory cell. According to previous information... Figure 5An embodiment of the described key generation method obtains each bit of a key stored in one of the first memory cells 46, and according to the previous description... Figure 6 An implementation of the described key generation method obtains each bit of a key stored in one of the second memory units 46.

[0070] Figure 7 Another embodiment of RAM 50, partially and schematically illustrated, allows storage of more than one binary data per column per row. Memory 50 comprises all the elements of RAM 40, except that for each row, each column includes more than one memory cell 14, where two columns COL0 and COLN are... Figure 7 The example shown is shown below. As an example, in... Figure 7 The diagram shows sub-columns of four memory cells 14 per column. For each column, read / write circuitry 24 includes a multiplexer (not shown) coupled to bit lines 20 and 22 of the sub-column of memory cells 14. During a read or write operation, for each column, binary data is read from one sub-column of the sub-column or written to another sub-column of the sub-column according to signals used to control the multiplexer associated with the column.

[0071] According to an embodiment, the read / write circuit 24 includes memory cells 46 for each column, and key bits are stored for each column of memory cells (ck) 46. The key bits are used to encrypt / decrypt binary data read from / written to memory cells 14 in odd-numbered sub-columns, and the inversion of the key bits is used to encrypt / decrypt binary data written to / read from memory cells 14 in even-numbered sub-columns.

[0072] Figure 8 Another embodiment of RAM 55, partially and schematically illustrated, allows storage of more than one binary data item per row per column. Memory 55 includes all the elements of memory 50, except that memory circuitry 20 includes first and second memory cells (CK1, CK2) 46 for each column, and a first key bit is stored in the first memory cell 46 and a second key bit is stored in the second memory cell 46. The first key bit is used to encrypt / decrypt binary data written to / read from memory cells in odd-numbered sub-columns, and the second key bit is used to encrypt / decrypt binary data written to / read from memory cells in even-numbered sub-columns.

[0073] Figure 9Another embodiment of RAM 60, partially and schematically shown, allows storage of more than one binary data per column on each row. Memory 60 includes all the elements of memory 55. Rows of memory cells 14 are distributed into a first contiguous row ranging from row WL_FIRST to row WL_MIDDLE, for example, including the first half of the row, and distributed into two contiguous rows, for example, including the second half of the row ranging from row WL_MIDDLE+1 to row WL_LAST.

[0074] The first key bit is used to encrypt / decrypt binary data written to / read from memory cells in the odd-numbered sub-columns of the first row, and the inverted first key bit is used to encrypt / decrypt binary data written to / read from memory cells in the even-numbered sub-columns of the second row. The second key bit is also used to encrypt / decrypt binary data written to / read from memory cells in the odd-numbered sub-columns of the first row, and the inverted second key bit is used to encrypt / decrypt binary data written to / read from memory cells in the even-numbered sub-columns of the second row.

[0075] The reading of the key value is controlled by the ReadKey signal.

[0076] Figure 10 A timing diagram of the signals of memory 40 during a key read operation is shown. During the key read operation, each signal WL, CSN, and WEN is held at logic "0". Time tD0 corresponds to the rising edge of the clock signal CLK and the setting of the signal ReadKey to logic "1". At time tD1, the read / write circuit 20 delivers binary data Qi corresponding to the key bit associated with each column.

[0077] A more detailed embodiment of the read / write circuitry 24 of RAM40 will now be described. These embodiments specifically utilize circuitry MEM to store binary data corresponding to the D latch.

[0078] Figure 11 The left side shows a memory circuit MEM that specifically includes a tri-state inverter, and the right side shows a schematic block diagram of such a memory circuit MEM, which is formed with an insulated gate field-effect transistor, also known as a MOS transistor.

[0079] A tri-state inverter corresponds to a logic circuit that includes an input that receives a binary signal D, an output that delivers a binary signal Q, and an enable node that receives a binary enable signal EN. Typically, a tri-state inverter is illustrated with the following truth table:

[0080] Table 1

[0081] EN D Q 0 0 X 0 1 X 1 0 1 1 1 0

[0082] A tri-state inverter most often also includes a node that receives the enable signal EN and an inverted ENb.

[0083] like Figure 11 As shown in the left portion, the storage circuit MEM includes a tri-state inverter INVT1, which has its input to receive binary data D and its output to deliver binary data Qb, which is the inverted form of binary data Q. The tri-state inverter INVT1 receives an enable signal EN at its enable node (and also receives the inverted form of the enable signal ENb). The storage circuit MEM also includes an inverter INV1 and a tri-state inverter INVT2. Inverter INV1 has its input to receive binary data Qb and its output to deliver binary data Q. Tri-state inverter INVT2 has its input to receive binary data Q and its output is connected to the output of tri-state inverter INVT1. Tri-state inverter INVT2 receives an enable signal ENb at its enable node (and also receives the enable signal EN).

[0084] The storage circuit MEM operates as follows: when the enable signal EN is at logic "0", the output of the storage circuit MEM maintains its state regardless of the state of the binary data D, and when the enable signal EN is at logic "1", the storage circuit MEM copies the state of the binary data D at its output to the binary data Q.

[0085] Figure 11 The right-hand side shows an embodiment of a memory circuit MEM with MOS transistors.

[0086] The first tri-state inverter INVT1 includes: a P-channel MOS transistor T1, having its source connected to a high reference potential VDD and its gate controlled by an enable signal EN; an N-channel MOS transistor T2, having its source connected to a low reference potential GND and its gate controlled by an inverted ENb of the enable signal EN; a P-channel MOS transistor T3, having its source connected to the drain of transistor T1, having its drain connected to the output node of the tri-state inverter INVT1 for delivering binary data Qb, and having its gate connected to the input node of the tri-state inverter INVT1 for receiving binary data D; and an N-channel MOS transistor T4, having its source connected to the drain of transistor T2, having its drain connected to the output node of the tri-state inverter INVT1 for delivering binary data Qb, and having its gate connected to the input node of the tri-state inverter INVT1 for receiving binary data D.

[0087] Inverter INV1 includes: a P-channel MOS transistor T5 having its source connected to a high reference potential VDD, its gate connected to the input node of inverter INV1 that delivers binary data Qb, and its drain connected to the output node of inverter INV1 that delivers binary data Q; and an N-channel MOS transistor T6 having its source connected to a low reference potential GND, its gate connected to the input node of inverter INV1 that receives binary data Qb, and its drain connected to the output node of inverter INV1 that delivers binary data Q.

[0088] The second tri-state inverter INVT2 includes: a P-channel MOS transistor T7, having its source connected to a high reference potential VDD and its gate controlled by the inverted ENb of the enable signal EN; an N-channel MOS transistor T8, having its source connected to a low reference potential GND and its gate controlled by the enable signal EN; a P-channel MOS transistor T9, having its source connected to the drain of transistor T7, having its drain connected to the output node of the tri-state inverter INVT2 for delivering binary data Qb, and having its gate connected to the input node of the tri-state inverter INVT2 for receiving binary data Q; and an N-channel transistor T10, having its source connected to the drain of transistor T8, having its drain connected to the output node of the tri-state inverter INVT2 for delivering binary data Qb, and having its gate connected to the input node of the tri-state inverter INVT2 for receiving binary data Q.

[0089] Figure 12 A more detailed example of some elements of the read / write circuit 24 for writing binary data Di into the memory 40 in memory cell 14 is shown.

[0090] Figure 12 Bit line 20 and bit line 22 of the received signal blt from a sub-column of a column in the memory are shown.

[0091] For each sub-column, the read / write circuit 24 includes: a P-channel MOS transistor T11 having its gate coupled (preferably connected) to bitline 20, its source coupled (preferably connected) to a source at a high reference potential VDD, and its drain coupled (preferably connected) to bitline 22; a P-channel MOS transistor T12 having its gate coupled (preferably connected) to bitline 22, its source coupled (preferably connected) to a source at a high reference potential VDD, and its drain coupled (preferably connected) to bitline 20; an N-channel MOS transistor T13 having one end of its drain coupled (preferably connected) to bitline 20, and its source coupled (preferably connected) to a source at a low reference potential GND; and an inverter INV2 having its output coupled (preferably connected) to the gate of transistor T13, and its input coupled (preferably connected) to node T.

[0092] For each sub-column, the read / write circuit 24 further includes: a P-channel MOS transistor T14 having its source coupled (preferably connected) to a high reference potential VDD, its drain coupled (preferably connected) to node T, and its gate controlled by a binary signal wrt; an N-channel MOS transistor T15 having its drain coupled (preferably connected) to one end of bit line 22, and its source coupled (preferably connected) to a low reference potential GND; an inverter INV3 having its output coupled (preferably connected) to the gate of transistor T15, and its input coupled (preferably connected) to node F; and a P-channel MOS transistor T16 having its source coupled (preferably connected) to a high reference potential VDD, its drain coupled (preferably connected) to node F, and its gate controlled by a binary signal wrrf.

[0093] When each column of RAM40 contains only one sub-column, node T directly receives the inverted wrtb of signal wrt, and node F directly receives the inverted wrfb of signal wrrf. When each column includes multiple sub-columns, for each sub-column, the read / write circuit 24 further includes: a P-channel MOS transistor T17 having its source coupled (preferably connected) to a high reference potential VDD, its drain coupled (preferably connected) to node T, and its gate controlled by a binary signal muxi; an N-channel MOS transistor T18 having its drain coupled (preferably connected) to node T, its source receiving a signal wrtb, and its gate controlled by a signal muxi; a P-channel MOS transistor T19 having its source coupled (preferably connected) to a high reference potential VDD, its drain coupled (preferably connected) to node F, and its gate controlled by a signal muxi; and an N-channel MOS transistor T20 having its drain coupled (preferably connected) to node F, its source receiving a signal wrfb, and its gate controlled by a signal muxi.

[0094] The read / write circuit 24 includes circuitry 62 for delivering binary data DD and DB from binary data Di to be written. Circuitry 62 has... Figure 11 The structure of the storage circuit MEM shown is such that the enable signal EN corresponds to the binary signal ck, the binary data D corresponds to the binary data Di, the binary data Qb corresponds to the binary data DB, and the binary data Q corresponds to the binary data DD.

[0095] The read / write circuit 24 further includes: a P-channel transistor T21 having a source coupled (preferably connected) to a high reference potential VDD, a drain coupled (preferably connected) to node K, and a gate controlled by the inverted ckb of the signal ck; an N-channel transistor T22 having a source coupled (preferably connected) to GND, a drain coupled (preferably connected) to node K, and a gate controlled by the inverted ckb of the signal ck; an N-channel transistor T23 having a source coupled (preferably connected) to node K, a drain delivering a binary signal wrt, and a gate controlled by binary data DB; and a P-channel transistor T24 having a source coupled (preferably connected) to a high reference potential VDD, a drain coupled (preferably connected) to the drain of transistor T23, and a gate controlled by the inverted ckb of the signal ck.

[0096] The read / write circuit 24 further includes: an inverter INV4 having an input that receives the binary signal wrt and an inverted wrtb that delivers the signal wrt; an N-channel transistor T25 having its source coupled (preferably connected) to node K, its drain that delivers the binary signal wrt, and its gate controlled by binary data DD; a P-channel transistor T26 having its source coupled (preferably connected) to a high reference potential VDD, its drain coupled (preferably connected) to the drain of transistor T25, and its gate controlled by the inverted ckb of the signal ck; and an inverter INV5 having an input that receives the binary signal wrt and an inverted wrfb that delivers the signal wrt.

[0097] Signal ck is a binary signal within the memory determined by clock signal CK and binary signal Reset. As an example, signal ck is set to logic "0" on each rising edge of signal CK and to logic "1" on each falling edge of signal Reset. During a write operation of binary data Di, when signal ck is set to logic "1", binary data DD copies binary data Di, and binary data DB is the inverse of binary data Di. As an example, when DD is at logic "1" and DB is at logic "0", transistor 25 is turned on and transistor 23 is turned off. Signal wrt is set to logic "1" and signal wlf is set to logic "0", causing signal blt to be set to logic "0" and signal blf to be set to logic "1".

[0098] Figure 13 A schematic block diagram of a memory cell 46 is shown, enabling a read / write circuit 24 for storing key bits. The memory cell 46 has... Figure 11 The storage circuit MEM shown has an enable signal EN corresponding to the binary signal ckgk, binary data D corresponding to the binary signal SENO, binary data Qb corresponding to the key bit of the key, and binary data Q corresponding to the inverted key bit bkey. Memory cell 46 also receives the inverted signal ckbgk.

[0099] Figure 14 A schematic block diagram of a portion of a read / write circuit 24 for encrypting binary data Di to be written to memory 50 is shown, enabling the implementation of previously mentioned... Figure 7 An example of the described encryption method.

[0100] For each column, the read / write circuit 24 includes two inverters INV6 and INV7 connected in series. The first inverter INV6 receives binary data Di, and the output of the second inverter INV7 is connected to the input node A of the encryption / decryption circuit 64.

[0101] The encryption / decryption circuit 64 includes a basic encryption / decryption circuit 66 between node A and node B and a basic encryption / decryption circuit 68 between node A and node C.

[0102] The basic encryption / decryption circuit 66 includes: a tri-state inverter INVT3, having its input connected to node A and receiving the key bit of the key (and also receiving the inverted bkey of the key bit of the key) at its enable node; an inverter INV8, having its input receiving the output of the tri-state inverter INVT3 and having its output connected to node B; and a tri-state inverter INVT4, having its input connected to node A and receiving the inverted bkey of the key bit of the key (and also receiving the key bit of the key) at its enable node, and having its output connected to node B.

[0103] The basic encryption / decryption circuit 68 has the same structure as the basic encryption / decryption circuit 66, except that the enable node of the tri-state inverter INVT3 receives the inverted key bit bkey of the key, and the enable node of the tri-state inverter INVT4 receives the key bit of the key.

[0104] The encryption / decryption circuit 64 further includes: a tri-state inverter INVT5, having its input connected to node B, receiving a binary signal even (and also receiving the inverted ieven of the signal) at its enable node, and having its output connected to node E; and a tri-state inverter INVT6, having its input connected to node C, receiving a binary signal odd (and also receiving the inverted iodd of the signal) at its enable node, and having its output connected to node D.

[0105] Node E delivers binary data Dii to the input of circuit 62, which delivers binary data DD and DB.

[0106] The basic encryption / decryption circuit 68 has the same structure as the basic encryption / decryption circuit 66, except that the enable node of the tri-state inverter INVT3 receives the inverted key bit bkey of the key, the enable node of the tri-state inverter INVT4 receives the key bit of the key, and the enable node of the tri-state inverter INVT5 receives the binary signal odd (and also receives the inverted iodd of the signal odd) at its enable node.

[0107] When each column of RAM40 comprises a single sub-column, the encryption / decryption circuit 64 includes a basic encryption / decryption circuit 66.

[0108] Signals `even` and `odd` are set to logic "1" to write binary data `Di` into the even-level sub-column, and `even` is set to logic "0" to write binary data `Di` into the odd-level sub-column. As an example, to write data `Di` equal to logic "1" into the even-level sub-column when the key bit is equal to logic "1", node A is set to logic "1". Basic encryption / decryption circuit 66 delivers logic "1" to node B and basic encryption / decryption circuit 68 delivers logic "0" to node C. The state at node E is applied by the tri-state inverter `INVT5`, which is set to logic "0".

[0109] Figure 15 A schematic block diagram of circuits 70 and 72 is shown, which are configured to deliver signals even and odd when each column comprises four sub-columns. Each sub-column has an associated binary signal mux0, mux1, mux2, and mux3, which are at logic "1" when the corresponding sub-column is selected and, conversely, at logic "0".

[0110] Circuit 70 includes: an N-channel MOS transistor T27 having a source coupled (preferably connected) to a low reference potential GND, a drain coupled (preferably connected) to a node G, node G delivering a binary signal ieven, and a gate receiving a binary signal mux0; an N-channel MOS transistor T28 having a source coupled (preferably connected) to a low reference potential GND, a drain coupled (preferably connected) to a node G, and a gate receiving a binary signal mux2; an N-channel MOS transistor T29 having a source coupled (preferably connected) to a node G, and a gate receiving a binary signal mux2; a P-channel MOS transistor T30 having a source coupled (preferably connected) to a high reference potential VDD, a drain coupled (preferably connected) to the drain of transistor T29, and a gate receiving a binary signal mux0; and an inverter INV9 receiving the signal ieven and delivering the signal even.

[0111] Circuit 72 includes: an N-channel MOS transistor T31 having a source coupled (preferably connected) to a low reference potential GND, a drain coupled (preferably connected) to a node H that delivers a binary signal iodd, and a gate that receives a binary signal mux1; an N-channel MOS transistor T32 having a source coupled (preferably connected) to a low reference potential GND, a drain coupled (preferably connected) to a node H, and a gate that receives a binary signal mux3; an N-channel MOS transistor T33 having a source coupled (preferably connected) to a node H, and a gate that receives a binary signal mux3; a P-channel MOS transistor T34 having a source coupled (preferably connected) to a high reference potential VDD, a drain coupled (preferably connected) to the drain of transistor T33, and a gate that receives a binary signal mux1; and an inverter INV10 that receives the signal iodd and delivers the signal odd.

[0112] Figure 16 A schematic block diagram of an embodiment of RAM40 is shown. Figure 16 The memory cell 14 used during a read operation and a portion of the read / write circuitry 24 are shown in the diagram.

[0113] Memory cell 14 includes: two memory nodes NT and NF; an N-channel MOS transistor T35, having one of its power supply terminals connected to bit line 20 to receive signal BLT, another of its power supply terminals connected to node NT, and its gate receiving row select signal WL; an N-channel MOS transistor T36, having one of its power supply terminals connected to bit line 22 to receive signal BLF, another of its power supply terminals connected to node NF, and its gate receiving row select signal WL; and a P-channel MOS transistor T37, having its source connected to a high reference potential VD. The source of transistor D has its drain connected to node NT and its gate connected to node NF; the source of transistor T38 has its source coupled to a low reference potential GND, its drain connected to node NT and its gate connected to node NF; the source of transistor T39 has its source connected to a high reference potential VDD, its drain connected to node NF and its gate connected to node NT; and the source of transistor T40 has its source coupled to a low reference potential GND, its drain connected to node NF and its gate connected to node NT.

[0114] For each column, the read / write circuitry 24 includes a memory cell 74 specifically for reading data stored in the selected memory cell 14 of the column. The memory cell 74 includes: a memory node MEMT that delivers a binary signal PSA and a memory node MEMF that delivers a binary signal NSA; a P-channel MOS transistor T41 having one conductive terminal connected to bit line 20 to receive signal BLT, another conductive terminal connected to node MEMT, and its gate receiving binary signal SAEN; a P-channel MOS transistor T42 having one conductive terminal connected to bit line 22 to receive signal BLF, another conductive terminal connected to node MEMF, and its gate receiving the inverted SAEN of signal SAE; and a P-channel MOS transistor T43 having its source connected to a high reference potential VDD. The transistors T44, T45, T46, T47, and T48 have their drains connected to node MEMT and their gates connected to node MEMF; T48 has its drain connected to node MEMT and its gate connected to node MEMF; T49 has its drain connected to node MEMF and its gate connected to node MEMF; T40 has its drain connected to node MEMF and its gate connected to node MEMF; and T48 has its source connected to low reference potential GND, its drain connected to the sources of transistors T44 and T46, and its gate receiving the inverted SAEN of signal SAE.

[0115] Figure 17 A schematic block diagram of an embodiment of circuit 75 for delivering binary data for column reads of read / write circuit 24 is shown. Circuit 75 includes: a P-channel MOS transistor T48 having its source coupled (preferably connected) to a source at a high reference potential VDD, its drain coupled (preferably connected) to a node receiving a binary signal PSA, and its gate receiving a binary signal PCH; a P-channel MOS transistor T49 having its source coupled (preferably connected) to a source at a high reference potential VDD, its drain coupled (preferably connected) to a node receiving a binary signal NSA, and its gate receiving a binary signal PCH; and a P-channel MOS transistor T50 having its drain or source coupled (preferably connected) to the drain of transistor T48, with another drain or source coupled (preferably connected) to the drain of transistor T49, and its gate receiving a binary signal PCH.

[0116] Circuit 75 further includes: an inverter INV11 having an inverted PSAI having an input receiving signal PSA and an output delivering signal PSA; a P-channel MOS transistor T51 having a source coupled (preferably connected) to a high reference potential VDD, a drain coupled (preferably connected) to a node of the delivering signal SENO, and a gate receiving the binary signal PSAI; an N-channel MOS transistor T52 having a source coupled (preferably connected) to a low reference potential GND, a drain coupled (preferably connected) to a node of the delivering signal SENO, and a gate receiving the binary signal NSA; previously regarding Figure 13 The described memory cell 46 receives signal SEO; and the storage circuit 76 has Figure 11 The structure of the memory circuit MEM shown is such that the enable signal EN corresponds to the binary signal ckbgk, the binary data D corresponds to the binary signal SENO, the binary data Qb corresponds to the binary data Qi, and the binary data Q corresponds to the binary data Q.

[0117] The signal PCH is a binary signal set to logic "1" for a window contained within a window whose signal WL is set to logic "1" during a read operation.

[0118] It can be based on previous information Figure 5 and 6 The generation of key bits for each column of the key in the described embodiment is implemented in Figure 16 and Figure 17 The circuit shown in the figure.

[0119] Figure 18 A schematic block diagram of the read circuit 78 of the read / write circuit 24 is shown. The read circuit 78 includes, for each column: a tri-state inverter INVT7 that receives the binary signal SENO and, at its enable node, the inverted ckbgk of the signal ckgk (and also receives the signal ckgk); a first branch that includes an encryption / decryption circuit 64, as previously described, having its input receiving the output of the tri-state inverter INVT7; and a tri-state inverter INVT8 that has its input receiving the signal provided by the encryption / decryption circuit 64, receiving the signal ckwc (and also receives the inverted ckwoc of the signal ckwc) at its enable node and having its output coupled to node L; a second branch that includes a tri-state inverter INVT9 that has its input receiving the signal provided by the tri-state inverter INVT7, receiving the signal ckwoc (and also receives the inverted ckwc of the signal ckwoc) at its enable node and having its output coupled to node L; and a storage circuit 80, having… Figure 11The structure of the memory circuit MEM shown is such that the enable signal EN corresponds to the binary signal clk, the binary data D corresponds to the binary signal at node L, the binary data Qb corresponds to the binary data Qi, and the binary data Q corresponds to the binary data Q; and the previous information regarding... Figure 17 The described storage circuit 76 has an enable signal EN corresponding to a binary signal ckgk, binary data D corresponding to a binary signal SENO, binary data Qb corresponding to binary data Qi, and binary data Q corresponding to binary data Q.

[0120] For each column, the read circuit 78 further includes: an inverter INV12 having its input connected to the output of the storage circuit 76; a first selection circuit 84 including two input nodes M and N, a NAND gate and a NOR gate NOR1, each having a first input at the input node N to receive a binary signal delivered by the storage circuit 80, and a NAND gate having a second input connected to node M; an inverter INV13 having an input connected to node M and an output connected to the second input of the NOR gate NOR1; and a P-channel MOS transistor 53 having its source coupled (preferably connected) to a high reference potential VDD, its drain coupled to the output node OUT of the circuit 78, and its gate connected to the output of the NAND gate. And an N-channel MOS transistor 54 having a source coupled (preferably connected) to a low reference potential GND, a drain coupled to the output node OUT of circuit 78, and a gate connected to the output of logic gate NOR1; or a NOT logic gate NOR2 having a first input receiving a binary signal IntReadKey and a second input receiving a binary signal IntGenKey, and an output connected to node M; and a second selection circuit 86 having the same structure as the first selection circuit 84, having an input node M receiving a binary signal IntReadKey, an input node N connected to the output of inverter INV12, and an output node connected to the output node of circuit 78.

[0121] For the operation of reading binary data stored in memory using decryption, binary signals IntReadKey and IntGenKey are set to logic "0", binary signal ckwc is set to logic "1", and the inverted form of binary signal ckwc, ckwoc, is therefore set to logic "0". When signal IntReadKey is at logic "0", the two MOS transistors 53 and 54 of the second selection circuit 86 are turned off, so that the second selection circuit 86 has no effect on the state of node OUT. When signal ckwoc is at logic "0", the tri-state inverter INVT9 has no effect on the state of node L. When signal ckbgk switches to logic "1", binary data SENO is decrypted and read in the first branch. When signal CLK is set to logic "1" and copied to output node OUT, the binary data decrypted at node L is propagated to the first selection circuit 84.

[0122] For the operation of reading binary data stored in memory without decryption, the binary signals IntReadKey and IntGenkey are set to logic "0", the binary signal ckwc is set to logic "0", and the inverted binary signal ckwc, ckwoc, is therefore set to logic "1". When the signal IntReadKey is at logic "0", the two MOS transistors 53 and 54 of the second selection circuit 86 are turned off, so that the second selection circuit 86 has no effect on the state of node OUT. When the signal ckwoc is at logic "1", the tri-state inverter INVT8 has no effect on the state of node L. When the signal ckbgk switches to logic "1", the read binary data SENO is transmitted to node L via the second branch. When the signal clk is set to logic "1" and copied to the output node OUT, the undecrypted binary data at node L is propagated to the first selection circuit 84.

[0123] For the operation of reading the key bits of the key, the binary signal IntReadKey is set to logic "1", and the binary signal IntGenkey is set to logic "0". Then, the two MOS transistors 53 and 54 of the first selection circuit 84 are turned off, so that the first selection circuit 84 has no effect on the state of node OUT. When the signal ckgk switches to logic "1", the binary data SENO (which then corresponds to the key bits of the key) is read and transmitted via the second selection circuit 86. When the signal IntReadKey is at logic "1", the second selection circuit 86 copies the key bits of the key to the output node OUT.

[0124] According to one embodiment, the security circuit 44 is configured to control the erasure of binary data and key bits stored in the memory cell 14 of the memory 40.

[0125] Figure 19 A schematic block diagram of a portion of memory 40 is shown.

[0126] According to an embodiment, security circuit 44 (security control) receives binary signals ReadKey, GenKey, and CSN. Security circuit 44 delivers binary signals IntReadKey, IntGenKey, and erasectrl. Security circuit 44 also receives signals representing operations of memory 40. As an example, security circuit 44 receives the digital signal ADX. <odd>and ADY <even>Digital signal ADX <odd>and ADY <even>These represent the odd-numbered bits and even-numbered bits of the address signal AD, respectively, and perform predefined calculations on these bits to determine whether the address signal AD is correct.

[0127] According to one embodiment, the read / write circuit 24 includes a switch 90 controlled by a signal erasectrl, which is inserted between a node GNDi and the source of a low reference potential GND. Node GNDi is coupled to each memory cell 14 of array 12 and corresponds to the source for delivering a low reference potential for each memory cell 14. When the signal erasectrl is at logic "1", switch 90 is turned on and the source of the low reference potential GND is connected to node GNDi for delivering the low reference potential for each memory cell 14. When the signal erasectrl is at logic "0", switch 90 is turned off and node GNDi for delivering the low reference potential for each memory cell 14 remains floating, thereby erasing binary data stored in the memory cell.

[0128] According to an embodiment, switch 90 includes an N-channel MOS transistor 55, the N-channel MOS transistor 55 having its source coupled (preferably connected) to a node GNDi of each memory cell 14, having its gate receiving a signal erasectrl, and having its drain coupled (preferably connected) to a source at a low reference potential GND.

[0129] According to an embodiment, for each column, the read / write circuit 24 includes circuitry 92 for erasing key bits of a key controlled by the signal erasectrl. According to an embodiment, the erase circuitry 92 includes: an inverter INV14 having its input to receive the signal erasectrl; an N-channel MOS transistor 56 having its source coupled (preferably connected) to a low reference potential GND, its drain coupled (preferably connected) to the output of a first tri-state inverter INVT1 of the column's memory cell 46, and its gate connected to the output of inverter INV14; and an N-channel MOS transistor 57 having its source coupled (preferably connected) to a low reference potential GND, its drain coupled (preferably connected) to the input of a second tri-state inverter INVT2 of the memory cell 46, and its gate connected to the output of inverter INV14. Each transistor 56 and 57 is turned off when the signal erasectrl is at logic "1". When the signal erasectrl is at logic "0", each transistor 56 and 57 is turned on, forcing the key bit of the key to be set to logic "0" and the inverted key bit of the key to be set to logic "0".

[0130] Figure 20 It shows Figure 19 A variant of the schematic block diagram, wherein switch 90 further includes a P-channel MOS transistor T58 having its source coupled (preferably connected) to a high reference potential VDD, its gate receiving a signal erasectrl, and its drain coupled (preferably connected) to a node GNDi of each memory cell 14. When the signal erasectrl is at logic "1", transistor T58 is off. When the signal erasectrl is at logic "0", transistor T58 is on and node GNDi is coupled to the source of the high reference potential VDD. This advantageously allows the rise of node GNDi to a sufficiently high potential to erase data stored in the memory cell 14.

[0131] Figure 21 A timing diagram showing the signals indicating the operation of safety circuit 44 is shown. Times tE0, tE1, tE2, and tE3 are continuous.

[0132] In normal operation, i.e., when no intrusion attempt is detected, security circuit 44 maintains signal erasectrl at logic "1", causing switch 90 to be turned on and transistors 56 and 57 to be turned off. At time tE0, signal ADX <odd>It is set to logic "1", and the signal ADX <even>It is set to logic "0". At time tE1, the GenKey or ReadKey signal is set to logic "1" for key generation or key reading operations. This operation is still considered normal by security circuit 44. At time tE2, the ADX signal... <even>Set to logic "1", where signal ADX <odd>It remains at logic "1". At time t3, the signal GenKey or ReadKey is set to logic "1". This operation is considered abnormal by security circuit 44. Then, security circuit 44 sets the signal erasectrl to logic "1", causing switch 90 to open, which causes the binary data stored in all memory cells 14 of memory 40 to be erased, and turns on transistors 56 and 57, which causes the erasure of all key bits of the key.

[0133] Figure 22 and 23 Examples of a portion of the security circuitry during key generation and key reading operations are shown respectively. Now, regarding... Figure 4 The security circuit 44 is described in detail using the key generation operation. The security circuit 44 includes: a P-channel MOS transistor T59, having its source connected to a high reference potential VDD and its gate receiving a binary input signal GenKey; an N-channel MOS transistor T60, having its source connected to a low reference potential GND and its gate receiving a binary signal GenKey; and a first group 94 of N-channel MOS transistors connected in series between the drains of transistor T59 and T60, the first group 94 of N-channel MOS transistors having its gate receiving a first binary control signal. As an example, the first group 94 of N-channel MOS transistors includes... Figure 22 and 23 The three N-channel MOS transistors T61, T62, and T63 are shown in the figure.

[0134] Security circuit 44 further includes: a P-channel MOS transistor T64 having its gate connected to the drain of transistor T59 and having its drain delivery signal IntGenKey; a second group 96 of P-channel MOS transistors connected in series between the source of transistor T64 and the source of the high reference potential VDD, and the second group 96 of P-channel MOS transistors having its gate receiving a second binary control signal. As an example, the second group 96 of P-channel MOS transistors may include, for example... Figure 22 and 23 The two P-channel MOS transistors shown are T65 and T66.

[0135] The safety circuit 44 further includes: an inverter INV15 having an input signal GenKey; an N-channel MOS transistor T67 having a source coupled (preferably connected) to a low reference potential GND, a drain coupled (preferably connected) to the drain of transistor T64, and a gate connected to the output of inverter INV16; a P-channel MOS transistor T68 having a gate connected to the drain of transistor T59; and a P-channel MOS transistor T69 having a source coupled (preferably connected) to a high reference potential VDD, a drain coupled (preferably connected) to the drain of transistor T68, and a gate signal GenKey.

[0136] The safety circuit 44 further includes: a third group 98 of P-channel MOS transistors connected in series between the source of transistor T68 and the source of the high reference potential VDD, the third group 98 of P-channel MOS transistors including the same number of transistors as the second group 96, and having their gates controlled by a second signal for controlling the second group 96; and a fourth group 100 of components 102, the fourth group 100 having the same number of components 102 as the first group 94. Each component 100 includes: an N-channel MOS transistor T70 having its drain coupled (preferably connected) to the drain of transistor T68, and having its gate receiving the signal GenKey; an N-channel MOS transistor T71 having its source coupled (preferably connected) to the source of the low reference potential GND, and having its drain coupled (preferably connected) to the drain of transistor T70; and an inverter INV16 having its input receiving one of the first signals for controlling the first group 94, and having its output connected to the gate of transistor T71.

[0137] The safety circuit 44 further includes a fifth group 104 of components 106, the number of components 106 in the fifth group 104 being the same as the number of transistors in the second group 96. Each component 106 includes: an N-channel MOS transistor T72 having its drain coupled (preferably connected) to the drain of transistor T68 and having its gate receiving the signal GenKey; and an N-channel MOS transistor T73 having its source coupled (preferably connected) to a low reference potential GND, having its drain coupled (preferably connected) to the source of transistor T72, and having its gate receiving one of the second signals for controlling the second group 96.

[0138] The safety circuit 44 further includes: an AND gate having a first input connected to the drain of transistor T68 and a second input receiving the binary signal ReadKeyLock; and an RS flip-flop having its S input receiving the binary signal SetoGInit, its R input connected to the output of the AND gate and its output delivering the signal erasectrl.

[0139] For key generation operations, such as Figure 22 As shown, the first binary signal used to control the first group 94 is signal CNSI, which is the inverted form of signal CNS; signal ADLSB (as an example) is the least significant bit of the digital signal AD; and signal ADMSB (as an example) is the most significant bit of the digital signal AD. The second binary signal used to control the second group 96 is signal ADLSB1, which is the bit following the least significant bit of the digital signal AD; and signal ADMSB1, which is the bit preceding the most significant bit of the digital signal AD. Signal Out1 corresponds to signal IntGenKey.

[0140] As an example, using Figure 22 The circuit shown maintains signal erasectrl at logic "1" when all of the following conditions are met, and switches to logic "0" if one of the following conditions is not met: signal GenKey is at logic "1"; signals CSNI, ADLSB, and ADMSB are at logic "1"; and signals ADLSB1 and ADMSB1 are at logic "0".

[0141] For key reading operations, such as Figure 23 As shown, the safety circuit 44 has a connection with Figure 21 The structure shown is the same as the one shown, except that the binary signal ReadKey replaces the signal GenKey, the signal CNS, which is the inverted signal of signal CSN, replaces the signal CNSI with the signal CNS, and the signal IntGenKey is replaced with the signal IntReadKey.

[0142] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to them. In particular, although embodiments have been described with respect to RAM, it should be clear that embodiments relating to the encryption of data written to memory, the decryption of data read from memory, and the generation of keys can be implemented using ROM.

[0143] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.< / odd> < / even> < / even> < / odd> < / even> < / odd> < / even> < / odd>

Claims

1. A memory, comprising: Memory cells arranged in rows and columns; At least one bit line for each column is coupled to the memory cell of the column; as well as A read / write circuit, coupled to the bit line, includes a detection circuit for each column, the detection circuit being configured to: detect a logic level of the bit line for that column, and deliver read binary data depending on the logic level, wherein the read / write circuit is configured to, for each column, receive binary data to be stored in one memory cell of the memory cells in that column, and wherein, for each column, the operation of reading encrypted binary data stored in one memory cell of the memory cells in that column includes: selecting the one memory cell, and after selecting the memory cell, the detection circuit reading the level of the bit line after a first time period has elapsed; For each column, the read / write circuit includes: A latch is configured to store key bits; and An encryption circuit is configured to encrypt the received binary data using the key bits, thereby providing encrypted binary data; The read / write circuitry is configured to control the bit lines for that column to store the encrypted binary data; For at least one of the columns, the read / write circuit is configured to store the key bit in the latch associated with that column, the key bit corresponding to the read binary data delivered by the detection circuit after a second time period has elapsed, the second time period being shorter than the first time period.

2. The memory of claim 1, wherein for each column, the read / write circuitry is configured to: decrypt encrypted data in one of the memory cells stored in that column upon request, and deliver the decrypted binary data.

3. The memory of claim 1, wherein for each column, the read / write circuitry is configured to: deliver, upon request, the encrypted binary data stored in one of the memory cells in that column.

4. The memory of claim 1, wherein for each column, the read / write circuitry is configured to deliver, upon request, the key bit stored in the latch associated with that column.

5. A memory, comprising: Memory cells arranged in rows and columns; At least one bit line for each column is coupled to the memory cell of the column; as well as A read / write circuit is coupled to the bit line, and the read / write circuit is configured to receive binary data in one of the memory cells to be stored in the column for each column; For each column, the read / write circuit includes: A latch is configured to store key bits; and An encryption circuit is configured to encrypt the received binary data using the key bits, thereby providing encrypted binary data; The read / write circuitry is configured to control the bit lines for that column to store the encrypted binary data; and For at least one of the columns, the read / write circuitry is configured to store the key bit in the latch associated with that column when the memory is powered on, the key bit corresponding to binary data stored in one of the memory cells of that column when the memory is powered on.

6. A memory comprising: Memory cells arranged in rows and columns; At least one bit line for each column is coupled to the memory cell of the column; as well as A read / write circuit is coupled to the bit line, and the read / write circuit is configured to receive binary data in one of the memory cells to be stored in the column for each column; For each column, the read / write circuit includes: A latch is configured to store key bits; and An encryption circuit is configured to encrypt the received binary data using the key bits, thereby providing encrypted binary data; The read / write circuitry is configured to control the bit lines for that column to store the encrypted binary data; and Each column comprises a sub-column of memory cells, wherein during a write operation, the binary data received for each column is encrypted, and the encrypted binary data is stored in a memory cell of one of the sub-columns.

7. The memory of claim 6, wherein during the write operation, the read / write circuitry is configured to: encrypt the received binary data using one of the key bit and its inverted form when the sub-column containing the memory cells has an odd number of levels, and encrypt the received binary data using the other of the key bit and its inverted form when the sub-column containing the memory cells has an even number of levels.

8. The memory of claim 6, wherein for each column, the read / write circuitry includes an additional latch configured to store an additional key bit; and wherein during the write operation, the read / write circuitry is configured to: encrypt the received binary data using one of the key bit and the additional key bit when the sub-column containing the memory cells has an odd number of levels, and encrypt the received binary data using the other of the key bit and the additional key bit when the sub-column containing the memory cells has an even number of levels.

9. The memory according to claim 6, The rows of the memory cells are arranged in a first row and a second row; For each column, the read / write circuitry includes an additional latch configured to store additional key bits; as well as During the write operation, the read / write circuitry includes: The received binary data is encrypted using one of the key bit, the additional key bit, the inverted key bit, and the inverted additional key bit when the sub-column containing the memory cell has an odd number of levels and the selected row is one of the first rows. Using the key bit, the additional key bit, the inverted key bit, and the inverted additional key bit, the received binary data is encrypted when the sub-column containing the memory cell has an even number of levels and the selected row is one of the first rows; Using the key bit, the additional key bit, the inverted key bit, and another of the inverted additional key bit, the received binary data is encrypted when the sub-column containing the memory cell has an odd number of levels and the selected row is one of the second rows; and The received binary data is encrypted using one of the key bit, the additional key bit, the inverted key bit, and the inverted additional key bit, when the sub-column containing the memory cell has an even number of levels and the selected row is one of the second rows.

10. A memory comprising: Memory cells arranged in rows and columns; At least one bit line for each column is coupled to the memory cell of the column; as well as A read / write circuit is coupled to the bit line, and the read / write circuit is configured to receive binary data in one of the memory cells to be stored in the column for each column; For each column, the read / write circuit includes: A latch is configured to store key bits; and An encryption circuit is configured to encrypt the received binary data using the key bits, thereby providing encrypted binary data; The read / write circuitry is configured to control the bit lines for that column to store the encrypted binary data; and Each latch includes a first tri-state inverter, an inverter connected in series with the first tri-state inverter, and a second tri-state inverter connected in antiparallel with the inverter.

11. A method for storing data in a memory, the memory comprising memory cells arranged in rows and columns, at least one bit line coupled to the memory cells for each column, and read / write circuitry coupled to the bit lines, the method comprising: At the read / write circuit, for each column, binary data is stored in one of the memory cells of the column; Store the key bits in a latch for each column; as well as The received binary data is encrypted using the key bits by an encryption circuit device to provide encrypted binary data. For each column, a detection circuit is used to detect the logic level of the bit line for that column in order to deliver read binary data that depends on the logic level; For each column, an operation is performed to read encrypted binary data from one of the memory cells stored in the column, the operation including: selecting the one memory cell in the memory cells, and after selecting the memory cell, using the detection circuit to read the level of the bit line after a first time period has elapsed; as well as For at least one of the columns, a read / write circuit is used to store a key bit in the latch associated with that column, the key bit corresponding to the read binary data delivered by the detection circuit after a second time period has elapsed, the second time period being shorter than the first time period.

12. The method of claim 11, further comprising: For each column, the read / write circuitry is used to decrypt encrypted data in one of the memory cells stored in that column, and the decrypted binary data is delivered.

13. The method of claim 11, further comprising: For each column, the encrypted binary data stored in one of the memory cells in that column is delivered directly using the read / write circuitry upon request.

14. The method of claim 11, further comprising: For each column, the read / write circuitry is used, upon request, to deliver the key bit stored in the latch associated with that column.

15. A method for storing data in a memory, the memory comprising memory cells arranged in rows and columns, at least one bit line coupled to the memory cells for each column, and read / write circuitry coupled to the bit lines, the method comprising: At the read / write circuit, for each column, binary data is stored in one of the memory cells of the column; Store the key bits in a latch for each column; as well as The received binary data is encrypted using the key bits by an encryption circuit device to provide encrypted binary data. and For at least one of the columns, the read / write circuitry stores the key bit in the latch associated with that column when the memory is powered on. The key bit corresponds to binary data stored in one of the memory cells of that column when the memory is powered on.

16. A method for storing data in a memory, the memory comprising memory cells arranged in rows and columns, at least one bit line coupled to the memory cells for each column, and read / write circuitry coupled to the bit lines, the method comprising: At the read / write circuit, for each column, binary data is stored in one of the memory cells of the column; Store the key bits in a latch for each column; as well as The received binary data is encrypted using the key bits via an encryption circuit device to provide encrypted binary data. During the write operation, the binary data received for each column is encrypted, and the encrypted binary data is stored in the memory cells of a sub-column of the memory.

17. The method of claim 16, further comprising: During a write operation, the read / write circuitry encrypts the received binary data using one of the key bit and its inverted form when the sub-column has an odd number of levels, and uses the other of the key bit and its inverted form when the sub-column has an even number of levels.

18. The method of claim 16, further comprising: For each column, an additional latch in the read / write circuit stores an additional key bit; and It also includes: during the write operation, causing the read / write circuit to encrypt the received binary data using one of the key bit and the additional key bit when the sub-column has an odd number of levels, and to encrypt the received binary data using the other of the key bit and the additional key bit when the sub-column has an even number of levels.

19. The method of claim 16, wherein the rows of the memory cells are arranged as a first row and a second row; further comprising: For each column, an additional latch in the read / write circuit stores an additional key bit; as well as It also includes: during a write operation, causing the read / write circuitry to: The received binary data is encrypted using one of the key bit, the additional key bit, the inverted key bit, and the inverted additional key bit when the sub-column has an odd number of levels and the selected row is one of the first rows. The received binary data is encrypted using one of the key bit, the additional key bit, the inverted key bit, and the inverted additional key bit when the sub-column has an even number of levels and the selected row is one of the first rows. Using the key bit, the additional key bit, the inverted key bit, and another of the inverted additional key bit, the received binary data is encrypted when the sub-column has an odd number of levels and the selected row is one of the second rows; and The received binary data is encrypted using one of the key bit, the additional key bit, the inverted key bit, and the inverted additional key bit when the sub-column has an even number of levels and the selected row is one of the second rows.

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