Clock signal generation circuit and data sampling circuit

Abstract

This disclosure provides a clock signal generation circuit and a data sampling circuit. The clock signal generation circuit includes N clock signal processing modules for generating N corresponding target clock signals based on N received phase-correlated initial clock signals. The overlap area between adjacent target clock signals is less than a preset value. Each clock signal processing module includes a delay unit and a clock generation unit. The delay unit receives the initial clock signal and delays it to obtain a first input signal. The clock generation unit generates target clock signals based on the received first and second input signals. The phase of the second input signal differs from the phase of the initial clock signal by 360 degrees / N, where N is a positive integer greater than 1. The second input signal is the initial clock signal received by adjacent clock signal processing modules. The clock signal generation circuit provided by this disclosure can improve the inter-symbol interference problem of data signals.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and in particular to a clock signal generation circuit and a data sampling circuit. Background Technology

[0002] With industrial development, there is a growing desire to further increase the operating speed of electronic devices, i.e., to increase their operating frequency. To achieve this, the signal transmission speed in electronic devices must also be faster. However, at higher operating frequencies, inter-symbol interference (ISI) is more likely to occur during signal transmission, limiting the development of electronic devices. Summary of the Invention

[0003] This disclosure provides a clock signal generation circuit and a data sampling circuit that can improve inter-symbol interference and increase data transmission speed.

[0004] In a first aspect, embodiments of this disclosure provide a clock signal generation circuit, including N clock signal processing modules for generating N corresponding target clock signals based on N received phase-correlated initial clock signals, wherein the overlap area between adjacent target clock signals is less than a preset value; wherein each clock signal processing module includes a delay unit and a clock generation unit; the delay unit is used to receive the initial clock signal and delay the initial clock signal to obtain a first input signal; the clock generation unit is used to generate target clock signals based on the received first input signal and second input signal; wherein the phase of the second input signal differs from the phase of the initial clock signal by 360 degrees / N, where N is a positive integer greater than 1, and the second input signal is the initial clock signal received by adjacent clock signal processing modules.

[0005] In some embodiments, the delay unit is further configured to receive a control signal and control the delay unit to be in an open or closed state based on the control signal.

[0006] In some embodiments, the control signal includes a first control signal and a second control signal, wherein the levels of the first control signal and the second control signal are opposite; the delay unit is further configured to control the delay unit to open when the first control signal is at a first level and the second control signal is at a second level, thereby delaying the initial clock signal to obtain the first input signal.

[0007] In some embodiments, the delay unit in the clock signal processing module includes a transmission gate.

[0008] In some embodiments, the clock generation unit in the clock signal processing module includes a first arithmetic unit.

[0009] In some embodiments, the clock generation unit further includes a second arithmetic unit, wherein the input terminal of the second arithmetic unit is connected to the output terminal of the first arithmetic unit, and the output terminal of the second arithmetic unit outputs the target clock signal.

[0010] In some embodiments, the N phase-associated initial clock signals include: an initial clock signal associated with a first phase, an initial clock signal associated with a second phase, an initial clock signal associated with a third phase, and an initial clock signal associated with a fourth phase.

[0011] In some embodiments, the first phase is 0 degrees, the second phase is 90 degrees, the third phase is 180 degrees, and the fourth phase is 270 degrees.

[0012] In some embodiments, the overlap region being smaller than a preset value includes: the length T of the clock cycle corresponding to the overlap region. overlap Less than the first preset value.

[0013] In some embodiments, the overlap region being smaller than a preset value includes: the voltage level V corresponding to the overlap region. overlap Less than the second preset value.

[0014] In some embodiments, the delay unit is further configured to receive a first code and determine a delay parameter based on the first code, so that the overlap area between adjacent target clock signals is less than a preset value; wherein the first code includes at least one of the following: manufacturing process, power supply voltage, temperature; and / or, the delay unit is further configured to receive a mode encoding signal and determine a delay parameter based on the mode encoding signal, so that the overlap area between adjacent target clock signals is less than a preset value; wherein the mode encoding signal is used to characterize the data transmission rate of the electronic device.

[0015] In a second aspect, embodiments of this disclosure provide a data sampling circuit, the data sampling circuit including a data selector and a clock signal generation circuit as described in the first aspect; wherein: the clock signal generation circuit is used to receive an initial clock signal to generate a target clock signal; the data selector includes N data processing modules; used to receive an initial data signal and the initial clock signal, and sequentially output corresponding target data signals based on the target clock signal.

[0016] In some embodiments, each of the data processing modules includes: a register module and a switch module; the register module is used to receive the initial data signal and the initial clock signal, shift the initial data signal, and generate the target data signal; the switch module is used to control the sequential output of the target data signal based on the target clock signal.

[0017] In some embodiments, the N data processing modules include a first data processing module, a second data processing module, a third data processing module, and a fourth data processing module, wherein: the first data processing module includes a first register module and a first switch module, the first register module being used to receive a first initial data signal and a first initial clock signal, and the first switch module being used to control the output of a first target data signal based on a first target clock signal; the second data processing module includes a second register module and a second switch module, the second register module being used to receive a second initial data signal and a second initial clock signal, and the second switch module being used to control the output of a second target data signal based on a second target clock signal; the third data processing module includes a third register module and a third switch module, the third register module being used to receive a third initial data signal and a third initial clock signal, and the third switch module being used to control the output of a third target data signal based on a third target clock signal; the fourth data processing module includes a fourth register module and a fourth switch module, the fourth register module being used to receive a fourth initial data signal and a fourth initial clock signal, and the fourth switch module being used to control the output of a fourth target data signal based on a fourth target clock signal.

[0018] In some embodiments, the first initial clock signal and the second initial clock signal are the same, the third initial clock signal and the fourth initial clock signal are the same, and the phase difference between the first initial clock signal and the third initial clock signal is 180 degrees.

[0019] This embodiment of the present disclosure includes a delay unit and a clock generation unit in each clock signal processing module. Based on the received N phase-correlated initial clock signals, it generates N corresponding target clock signals, thereby reducing the overlap between the N target clock signals and thus reducing the occurrence of inter-symbol interference during data transmission. Attached Figure Description

[0020] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0021] Figure 1 This is a schematic diagram of the overlapping region of the target clock signal generated by a current clock signal generation circuit.

[0022] Figure 2a A schematic diagram of the framework of a clock signal generation circuit provided in an embodiment of this disclosure;

[0023] Figure 2b A timing diagram of N phase-correlated initial clock signals provided for embodiments of this disclosure;

[0024] Figure 2c A schematic diagram of the overlapping region of a target clock signal generated by a clock signal generation circuit according to an embodiment of this disclosure;

[0025] Figure 3a A schematic diagram of another clock signal generation circuit provided in an embodiment of this disclosure;

[0026] Figure 3b A timing diagram of an initial clock signal, a first input signal, and a target clock signal provided for embodiments of this disclosure;

[0027] Figure 3c A schematic diagram of another clock signal generation circuit provided in an embodiment of this disclosure;

[0028] Figure 3d A timing diagram of another target clock signal provided in an embodiment of this disclosure;

[0029] Figure 4a A schematic diagram of the framework of a data sampling circuit provided in an embodiment of this disclosure;

[0030] Figure 4b A schematic diagram of the framework of a data processing module in a data sampling circuit provided in an embodiment of this disclosure;

[0031] Figure 4c A schematic diagram of the framework of another data sampling circuit provided in an embodiment of this disclosure;

[0032] Figure 5a A schematic diagram of the framework of another data sampling circuit provided in an embodiment of this disclosure;

[0033] Figure 5b A timing diagram of a parallel output data signal;

[0034] Figure 5c A timing diagram of a sequentially output target data signal provided in an embodiment of this disclosure. Detailed Implementation

[0035] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0037] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0038] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or parts, these elements, components, areas, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part. When a second element, component, region, layer, or portion is discussed, it does not imply that a first element, component, region, layer, or portion necessarily exists in this disclosure.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0041] The English abbreviations used in the embodiments of this disclosure are explained.

[0042] DRAM (Dynamic Random Access Memory): Dynamic random access memory;

[0043] SRAM (Static Random-Access Memory): Static random access memory;

[0044] SDRAM (Synchronous Dynamic Random Access Memory): Synchronous dynamic random access memory;

[0045] DDR (Double Data Rate SDRAM): Double Data Rate SDRAM;

[0046] DDR4: The fourth version of the DDR technical specification;

[0047] DDR5: The fifth version of the DDR technical specification;

[0048] Mbps (Million bits per second): megabits per second;

[0049] 4-1MUX: A four-to-one data selector;

[0050] ISI (Inter-Symbol Interference): Inter-symbol interference;

[0051] PVT (Process Voltage and Temperature): Process voltage and temperature;

[0052] V CC Power supply voltage;

[0053] PMOS (Positive Channel Metal Oxide Semiconductor): P-channel metal-oxide semiconductor;

[0054] NMOS (Negative Channel Metal Oxide Semiconductor): N-channel metal oxide semiconductor.

[0055] DDR is a core memory device in electronic devices. Compared to DDR4, DDR5 increases data transfer speed from 3200Mbps to 6400Mbps. Because the DDR5 interface (transmitter and receiver) uses high frequency and high speed, it can achieve high-speed data transmission, thus halving the operating speed of DDR5. However, the internal circuitry of DDR5 still operates at the DDR4 speed, which leads to the problem of converting between high-frequency and low-frequency data. Currently, inter-symbol interference (ISI) occurs when using data selectors (such as 4-1MUX) to convert between high-frequency and low-frequency data.

[0056] Currently, reference Figure 1 The clock period T of the overlapping region of the target clock signal ICLK_N and the target clock signal QCLK_N generated by the clock signal generation circuit. overlap The level value V in the longer and overlapping regions is relatively long. overlap The signal is relatively large, which makes it easy for the transmitted data to be subject to inter-symbol interference (ISI) in subsequent use (e.g., using the generated target clock signal for a data selector).

[0057] This disclosure provides a clock signal generation circuit, with reference to... Figure 2aThe clock signal generation circuit 20 includes N clock signal processing modules 201, used to generate N corresponding target clock signals based on N received phase-correlated initial clock signals. The overlap area between adjacent target clock signals is less than a preset value. Each clock signal processing module 201 includes a delay unit 2011 and a clock generation unit 2012. The delay unit 2011 receives the initial clock signal and delays it to obtain a first input signal. The clock generation unit 2012 generates target clock signals based on the received first and second input signals. The phase of the second input signal differs from the phase of the initial clock signal by 360 degrees (°) / N, where N is a positive integer greater than 1. The second input signal is the initial clock signal received by the adjacent clock signal processing module. By including a delay unit and a clock generation unit in each clock signal processing module, and generating N corresponding target clock signals based on the received N phase-correlated initial clock signals, the overlap between the N target clock signals is reduced, thereby reducing inter-symbol interference during data transmission.

[0058] Here, the input terminal of the delay unit in each clock signal processing module corresponds to an initial clock signal. The phase difference between the initial clock signals can be 360° / n, where n is the number of initial clock signals. For example, if the number of initial clock signals is 4, then the phase difference between two adjacent initial clock signals can be 90°.

[0059] In some embodiments, the N phase-associated initial clock signals include: an initial clock signal associated with a first phase, an initial clock signal associated with a second phase, an initial clock signal associated with a third phase, and an initial clock signal associated with a fourth phase. That is, the embodiments of this application include 4 initial clock signals.

[0060] In some embodiments, the first phase is 0°, the second phase is 90°, the third phase is 180°, and the fourth phase is 270°. (See reference) Figure 2bIf the initial clock signal associated with the first phase is denoted as ICLK, the initial clock signal associated with the second phase as QCLK, the initial clock signal associated with the third phase as IBCLK, and the initial clock signal associated with the fourth phase as QBCLK, then the initial clock signals ICLK and QCLK are 90° out of phase, the initial clock signals QCLK and IBCLK are 90° out of phase, and the initial clock signals IBCLK and QBCLK are 90° out of phase. In other words, the phase difference between any two adjacent initial clock signals is 90°. The overlap area between the N target clock signals ultimately generated by this clock signal generation circuit is less than a preset value. It is understandable that, theoretically, clock signals that are 90 degrees apart should have their rising and falling edges aligned. However, due to process variations or parasitic effects in the design circuit, there may be an overlap between the rising and falling edges of a clock signal. For example, when transmitting the parallel-to-serial data signal "1011", the falling edge of the sampling clock signal corresponding to the first data signal "1" overlaps with the rising edge of the sampling clock signal corresponding to the second data signal "0", which may cause the second data signal "0" to be misjudged. Therefore, it is necessary to solve ISI.

[0061] In some embodiments, the overlap region being smaller than a preset value includes: the length T of the clock cycle corresponding to the overlap region. overlap The delay time can be adjusted to change the length of the clock cycle corresponding to the overlapping area, making the clock cycle of the overlapping area smaller than the first preset value, thereby reducing or even completely eliminating inter-symbol interference (ISI) between transmitted data signals.

[0062] In some embodiments, the overlap region being smaller than a preset value includes: the voltage level V corresponding to the overlap region. overlap Less than the second preset value.

[0063] refer to Figure 2c and Figure 1 Compared to the clock period and level value corresponding to the overlapping area of ​​the target clock signal ICLK_N and target clock signal QCLK_N generated by the current clock signal generation circuit, it can be seen that the clock period corresponding to the overlapping area of ​​the target clock signal ICLK_N and target clock signal QCLK_N generated by the clock signal generation circuit 20 in this embodiment is shorter, and the level value corresponding to the overlapping area is also smaller. Therefore, the probability of misjudgment caused by the corresponding level is smaller, thereby reducing the possibility of inter-symbol interference (ISI) during data transmission.

[0064] In some embodiments, the delay unit is further configured to receive a first code and determine delay parameters based on the first code, so that the overlap region between adjacent target clock signals is less than a preset value; wherein the first code includes at least one of the following: manufacturing process, power supply voltage, and temperature. That is, the clock period and level value corresponding to the overlap region can be adjusted according to different PVT values, because different manufacturing processes, power supply voltages, and temperatures will cause delays of different durations. For example, a higher operating voltage corresponds to a higher V... CC The higher the value, the longer the corresponding delay time. Therefore, during implementation, the PVT can be adjusted and combined with the delay unit to output the required N target clock signals.

[0065] In other embodiments, the clock period and level value corresponding to the overlapping area can be adjusted according to the frequency required for actual use. The delay unit is also used to receive the mode-coded signal and determine delay parameters based on the mode-coded signal, so that the overlapping area between adjacent target clock signals is less than a preset value; wherein, the mode-coded signal is used to characterize the data transmission rate of the electronic device. For example, in scenarios with higher frequencies (from 3200Mbps to 6400Mbps), the delay is greater, resulting in a smaller level value and clock period corresponding to the overlapping area; in scenarios with higher frequencies (from 3200Mbps to 4200Mbps), the delay is less, resulting in a slightly larger level value and clock period corresponding to the overlapping area. Thus, different mode-coded signals can be set according to actual needs, thereby generating target clock signals for the corresponding overlapping areas to meet different requirements.

[0066] In some embodiments, reference Figure 2b The waveforms of the N initial clock signals are trapezoidal. In other embodiments, the waveforms of the N initial clock signals can be rectangular, square, bell-shaped, etc.

[0067] The first input signal is the signal output by the delay unit after the initial clock signal is delayed; that is, the signal obtained after the initial clock signal is delayed. The first input signal can be 180° out of phase with the corresponding initial clock signal, meaning that the initial clock signal can be delayed by half a clock cycle to obtain the corresponding first input signal. Each delay unit outputs a first input signal; in other words, each clock generation unit receives a first input signal. In other embodiments, the initial clock signal can be delayed by a certain clock cycle to obtain the first input signal according to actual needs and application scenarios; this disclosure does not limit this.

[0068] The second input signal can be the initial clock signal received by the adjacent clock signal processing module, and the phase difference between the second input signal and the initial clock signal is 360° / N. For example, when N=4, for the clock generation unit in the first clock signal processing module, the second input signal can be the initial clock signal QCLK; for the clock generation unit in the second clock signal processing module, the second input signal can be the initial clock signal IBCLK; for the clock generation unit in the third clock signal processing module, the second input signal can be the initial clock signal QBCLK; and for the clock generation unit in the fourth clock signal processing module, the second input signal can be the initial clock signal ICLK. In implementation, it is only necessary to ensure that the phase difference between the second input signal received by the clock generation unit in the clock signal processing module and the initial clock signal received by the delay unit is 360° / 4 = 90°.

[0069] It should be noted that the clock signal generation circuit 20 in this embodiment may include 2, 3, or 4 clock signal processing modules, etc., and the number of clock signal processing modules is not limited in this embodiment. This embodiment mainly uses the example of 4 clock signal processing modules generating 4 target clock signals for explanation and illustration.

[0070] The clock signal generation circuit can be applied to various types of electronic devices, such as smartphones, tablets, PDAs, mobile terminals, etc. The embodiments disclosed herein are for illustrative purposes only and do not constitute any limitation.

[0071] For example, when a memory (e.g., DRAM, SRAM, or SRAM) in an electronic device needs to read data from its internal memory to an external port, a parallel-to-serial converter can be used to output only one set of data signals at a time. The clock signal generation circuit in this embodiment can be used to generate a target clock signal. The initial clock signal and initial data signal are received by the data selector, and the target data signal is output sequentially based on the target clock signal. In this way, by shifting the initial data signal, the data signal transmission performance is improved, thereby mitigating the inter-symbol interference problem between data signals.

[0072] In some embodiments, the delay unit is further configured to receive a control signal and control the delay unit to be in an open or closed state based on the control signal.

[0073] In some embodiments, the control signal includes a first control signal and a second control signal, wherein the levels of the first control signal and the second control signal are opposite. The delay unit is further configured to, when the first control signal is at a first level and the second control signal is at a second level, control the delay unit to turn on, delaying the initial clock signal to obtain the first input signal. Therefore, the delay time of the first input signal output by the delay unit can be adjusted by the control signal to meet different requirements.

[0074] The foregoing embodiments have provided a detailed description of the control logic and signal processing logic of the clock signal generation circuit 20. A specific clock signal generation circuit 20 can be formed by combining various basic electrical components. The following provides an exemplary structure of a clock signal generation circuit 20, but this does not constitute a limitation on the embodiments of this disclosure.

[0075] In some embodiments, reference Figure 3a The delay unit 2011 in the clock signal processing module 201 may include a transmission gate 2011a.

[0076] In other embodiments, the delay unit may include an RC circuit or other circuits that can perform the delay function, such as a circuit formed by connecting a resistor and a Zener diode, and then connecting a capacitor in parallel with them at their connection point.

[0077] In some embodiments, the clock generation unit in the clock signal processing module includes a first arithmetic unit. For example, refer to Figure 3a The first arithmetic unit includes a NAND gate 2012a, which is used to perform NAND operation on the first input signal output by the transmission gate 2011a.

[0078] For example, the first arithmetic unit may include an AND gate for performing an AND operation on the first input signal output by the transmission gate. It is understood that, depending on the type of enable signal required by subsequent circuitry, a NOT gate (inverter) or similar device may be connected in series after the AND gate to meet the requirements.

[0079] Among them, reference Figure 3a The transmission gate 2011a can be formed by connecting a pair of PMOS and NMOS transistors together. The first terminal of the PMOS is the gate (G), the second terminal is the drain (D), and the third terminal is the source (S); the first terminal of the NMOS is the gate (G), the second terminal is the drain (D), and the third terminal is the source (S). The drains of the PMOS and NMOS are connected together as the input terminal, and the sources of the PMOS and NMOS are connected together as the output terminal. The gates of the PMOS and NMOS serve as a pair of complementary control signals C (the first control signal) and... (Second control signal). During the operation of the transmission gate, the first control signal C and the second control signal... It is always at the opposite level. For example, when C=1 (first level), At the second level, both the PMOS and NMOS transistors are turned on, resulting in a low-impedance connection between the input and output terminals, equivalent to a switch being turned on. The initial clock signal can then reach the output terminal through the transmission gate. For example, when C = 0, At this time, both transistors are in the off state, and their turn-off resistance is very large. Therefore, the input and output terminals are disconnected.

[0080] The initial clock signals input to the input terminals of the transmission gates in the four clock signal processing modules 201 are ICLK, QCLK, IBCLK, and QBCLK, respectively. After being delayed by their respective transmission gates, the initial clock signals ICLK, QCLK, IBCLK, and QBCLK yield the first input signals ICLK_O, QCLK_O, IBCLK_O, and QBCLK_O, respectively. The clock generation units in the four clock signal processing modules 201 perform calculations on the first and second input signals to obtain the target clock signals ICLK_N, QCLK_N, IBCLK_N, and QBCLK_N.

[0081] For example, see reference Figure 3b The initial clock signals ICLK, QCLK, IBCLK, and QBCLK are all 90° out of phase with each other. The first input signals ICLK_O, QCLK_O, IBCLK_O, and QBCLK_O are also 90° out of phase with each other, and the delay time t between the first input signal ICLK_O and the initial clock signal ICLK (or the first input signal QCLK_O and the initial clock signal QCLK, or the first input signal IBCLK_O and the initial clock signal IBCLK, or the first input signal QBCLK_O and the initial clock signal QBCLK) is also 90°. d It is half a clock cycle; the phase difference between any two adjacent target clock signals in the target clock signals ICLK_N, QCLK_N, IBCLK_N, and QBCLK_N is 90°.

[0082] It should be noted that, Figure 3bThe target clock signals ICLK_N, QCLK_N, IBCLK_N, and QBCLK_N are the initial clock signals ICLK, QCLK, IBCLK, and QBCLK, respectively, after... Figure 3a The clock signal generated by the circuit shown is the target clock signal, which is obtained by passing the initial clock signal through a transmission gate and a NAND gate.

[0083] In some embodiments, reference Figure 3c The clock generation unit 2012 further includes a second arithmetic unit. In implementation, the second arithmetic unit may include an inverter 2012b. The input of the inverter 2012b is connected to the output of the first arithmetic unit, such as a NAND gate 2012a, and the output of the inverter 2012b outputs the target clock signal.

[0084] In implementation, the inverters can be configured according to the needs of subsequent circuitry. For example, if a high-level enable is required, an inverter can be connected to the output of the clock generation unit; if a low-level enable is required, two inverters can be connected to the output of the clock generation unit, or no inverters can be used. Taking the requirement of a high-level enable in subsequent circuitry as an example, the target clock signal output can be referenced... Figure 3d It can be observed that within one clock cycle, the pulse width of the target clock signal ICLK_N is τ. k .contrast Figure 3d and Figure 3b ,because Figure 3d The target clock signal is obtained by passing the initial clock signal through a transmission gate, a NAND gate, and an inverter, so it can be seen that... Figure 3b and Figure 3d The corresponding target clock signal levels are reversed. Additionally, the pulse width τ of the target clock signal ICLK_N can be observed. k The pulse width τ is less than the initial clock signal ICLK. j This means the duty cycle of the target clock signal decreases. It can also be seen that the pulse widths of the target clock signals QCLK_N, IBCLK_N, and QBCLK_N are all τ. k And they are all smaller than the pulse widths τ of the initial clock signals QCLK, IBCLK, and QBCLK, respectively. j Within one clock cycle, the target clock signals ICLK_N, QCLK_N, IBCLK_N, and QBCLK_N do not have overlapping regions.

[0085] This disclosure also provides a data sampling circuit, referenced in embodiments thereof. Figure 4a The data sampling circuit includes a data selector 30 and a clock signal generation circuit 20. The clock signal generation circuit 20 receives an initial clock signal and generates a target clock signal. The data selector 30 includes N data processing modules 301, which receive the initial data signal and the initial clock signal, and sequentially output the corresponding target data signals based on the target clock signal. Thus, the N data processing modules can sequentially output the parallel initial data signals based on the target clock signal generated by the clock signal generation circuit, thereby reducing inter-symbol interference (ISI) during data transmission.

[0086] In some embodiments, the data selector 30 may be a two-to-one data selector, a four-to-one data selector, etc. m Select 1 data selector, where m is a positive integer greater than or equal to 0. Correspondingly, 2... m One initial clock signal and 2 m Initial data signals are provided. For example, if data selector 30 is a 4-to-1 data selector, then four initial clock signals and four sets of initial data signals D0, D1, D2, and D3 are required. In some embodiments, the first initial clock signal can be the same as the second initial clock signal, and the third initial clock signal can be the same as the fourth initial clock signal. Data selector 30 receives the aforementioned initial clock signals and initial data signals, and sequentially outputs the corresponding target data signals based on the target clock signal generated by the clock signal generation circuit.

[0087] In some embodiments, reference Figure 4b Each data processing module 301 includes a register module 3011 and a switch module 3012. The register module 3011 receives an initial data signal and an initial clock signal, shifts the initial data signal, and generates a target data signal. The switch module 3012 controls the sequential output of the target data signal based on the target clock signal. Here, the target clock signal serves as the enable signal for the switch module, controlling the switch module to open when it is high or low, so that the target data signal is output sequentially.

[0088] In some embodiments, reference Figure 4c The N data processing modules include a first data processing module 302, a second data processing module 303, a third data processing module 304, and a fourth data processing module 305, wherein:

[0089] The first data processing module 302 includes a first register module 3021 and a first switch module 3022. The first register module 3021 is used to receive a first initial data signal D0 and a first initial clock signal ICLK. The first switch module 3022 is used to control the output of the first target data signal D0′ based on the first target clock signal ICLK_N.

[0090] The second data processing module 303 includes a second register module 3031 and a second switch module 3032. The second register module is used to receive the second initial data signal D1 and the second initial clock signal QCLK. The second switch module is used to control the output of the second target data signal D1′ based on the second target clock signal QCLK_N.

[0091] The third data processing module 304 includes a third register module 3041 and a third switch module 3042. The third register module 3041 is used to receive the third initial data signal D2 and the third initial clock signal IBCLK. The third switch module 3042 is used to control the output of the third target data signal D2′ based on the third target clock signal IBCLK_N.

[0092] The fourth data processing module 305 includes a fourth register module 3051 and a fourth switch module 3052. The fourth register module 3051 is used to receive the fourth initial data signal D3 and the fourth initial clock signal QBCLK. The fourth switch module 3052 is used to control the output of the fourth target data signal D3′ based on the fourth target clock signal QBCLK_N.

[0093] In some embodiments, the first initial clock signal and the second initial clock signal are the same, the third initial clock signal and the fourth initial clock signal are the same, and the phase difference between the first initial clock signal and the third initial clock signal is 180 degrees.

[0094] This disclosure also provides a data sampling circuit, referenced in embodiments thereof. Figure 5a The 4-to-1 data selector 50 includes four register modules and four switch modules, wherein the register modules can be D flip-flops (DFFs).

[0095] The 4-to-1 data selector receives four sets of parallel initial data signals, such as D0 / D4 / D8 / D12, D1 / D5 / D9 / D13, D2 / D6 / D10 / D14, and D3 / D7 / D11 / D15. (Reference) Figure 5bDuring clock cycle T1, the 4-to-1 data selector samples data signals D0 and D1 at the rising edge of the initial clock signal ICLK; during clock cycle T2, the 4-to-1 data selector samples data signals D4 and D5 at the rising edge of the initial clock signal ICLK; during clock cycle T3, the 4-to-1 data selector samples data signals D8 and D9 at the rising edge of the initial clock signal ICLK; and during clock cycle T4, the 4-to-1 data selector samples data signals D12 and D13 at the rising edge of the initial clock signal ICLK.

[0096] Similarly, during clock cycles T1 to T4, the 4-to-1 data selector samples data signals D2 and D3, D6 and D7, D10 and D11, and D14 and D15 sequentially, starting from the rising edge of the initial clock signal IBCLK. That is, the 4-to-1 data selector samples two sets of data signals simultaneously, corresponding to one set of switches outputting each set. However, because the overlap between IBCLK_N and QBCLK_N is greater than a preset value (see reference...), the data selector will not output the corresponding data signals. Figure 1 Therefore, the inter-symbol interference between the output data is quite severe.

[0097] In this embodiment, the 4-to-1 data selector receives parallel initial data signals D0, D1, D2, D3, D4, D5…D15. During clock cycle T1, the 4-to-1 data selector samples data signals D0 and D1 at the rising edge of the initial clock signal ICLK. That is, D0 and D1 are sampled simultaneously at the rising edge of the same initial clock signal, but D0' and D1' are output respectively at the rising edges of ICLK_N / QCLK_N. Since the overlap area between ICLK_N and QCLK_N is less than a preset value (reference value...), the data selector... Figure 2c This reduces inter-symbol interference between output data. (Reference) Figure 5c During clock cycle T1, the 4-to-1 data selector outputs the target data signal D0' on the rising edge of the target clock signal ICLK_N.

[0098] Similarly, during clock cycle T1, the 4-to-1 data selector outputs target data signal D1' on the rising edge of the target clock signal QCLK_N; the 4-to-1 data selector outputs target data signal D2' on the rising edge of the target clock signal IBCLK_N; and the 4-to-1 data selector outputs target data signal D3' on the rising edge of the target clock signal QBCLK_N. In other words, based on the target clock signals ICLK_N, QCLK_N, IBCLK_N, and QBCLK_N, the 4-to-1 data selector will sequentially output four target data signals within one clock cycle, thereby reducing or even eliminating data interference problems.

[0099] In the several embodiments provided in this disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple units or components may be combined, or integrated into another system, or some features may be ignored or not executed. In addition, the various components shown or discussed are coupled or directly coupled to each other.

[0100] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0101] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0102] The above descriptions are merely some embodiments of this disclosure, but the protection scope of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this disclosure should be included within the protection scope of this disclosure. Therefore, the protection scope of this disclosure should be determined by the scope of the claims.

Claims

1. A clock signal generation circuit, characterized in that, It includes N clock signal processing modules, which are used to generate N corresponding target clock signals based on the received N phase-correlated initial clock signals. The phase difference between adjacent initial clock signals is 360° / N, and the level overlap area between adjacent target clock signals is less than a preset value. The clock signal processing module includes a delay unit and a clock generation unit. The delay unit is used to receive the initial clock signal, delay the initial clock signal, and obtain the first input signal; The clock generation unit is used to perform logical operations based on the received first input signal and second input signal to generate a target clock signal; wherein the phase of the second input signal differs from the phase of the initial clock signal by 360 degrees / N, where N is a positive integer greater than 1, and the second input signal is the initial clock signal received by the adjacent clock signal processing module.

2. The circuit according to claim 1, characterized in that, The delay unit is also used to receive control signals and control the delay unit to be in an open or closed state based on the control signals.

3. The circuit according to claim 2, characterized in that, The control signal includes a first control signal and a second control signal, wherein the levels of the first control signal and the second control signal are opposite. The delay unit is further configured to control the delay unit to open when the first control signal is at a first level and the second control signal is at a second level, so as to delay the initial clock signal to obtain the first input signal.

4. The circuit according to any one of claims 1 to 3, characterized in that, The delay unit in the clock signal processing module includes a transmission gate.

5. The circuit according to any one of claims 1 to 3, characterized in that, The clock generation unit in the clock signal processing module includes a first arithmetic unit.

6. The circuit according to claim 5, characterized in that, The clock generation unit further includes a second arithmetic unit, the input of which is connected to the output of the first arithmetic unit, and the output of the second arithmetic unit outputs the target clock signal.

7. The circuit according to any one of claims 1 to 3, characterized in that, The N phase-associated initial clock signals include: an initial clock signal associated with the first phase, an initial clock signal associated with the second phase, an initial clock signal associated with the third phase, and an initial clock signal associated with the fourth phase.

8. The circuit according to claim 7, characterized in that, The first phase is 0 degrees, the second phase is 90 degrees, the third phase is 180 degrees, and the fourth phase is 270 degrees.

9. The circuit according to any one of claims 1 to 3, characterized in that, The overlap region being less than a preset value includes: the length of the clock cycle corresponding to the overlap region, Toverlap, being less than a first preset value.

10. The circuit according to any one of claims 1 to 3, characterized in that, The overlap region being less than a preset value includes: the voltage level Voverlap corresponding to the overlap region being less than a second preset value.

11. The circuit according to any one of claims 1 to 3, characterized in that, The delay unit is further configured to receive a first code and determine delay parameters based on the first code, so that the overlap area between adjacent target clock signals is less than a preset value; wherein the first code includes at least one of the following: manufacturing process, power supply voltage, and temperature; And / or, the delay unit is further configured to receive a pattern-coded signal and determine a delay parameter based on the pattern-coded signal, so that the overlap area between adjacent target clock signals is less than a preset value; wherein the pattern-coded signal is used to characterize the data transmission rate of the electronic device.

12. A data sampling circuit, characterized in that, The data sampling circuit includes a data selector and a clock signal generation circuit as described in claim 1; wherein: The clock signal generation circuit is used to receive the initial clock signal and generate the target clock signal; The data selector includes N data processing modules; It is used to receive the initial data signal and the initial clock signal, and to output the corresponding target data signal sequentially based on the target clock signal.

13. The data sampling circuit according to claim 12, characterized in that, Each of the data processing modules includes: a register module and a switch module; The register module is used to receive the initial data signal and the initial clock signal, shift the initial data signal, and generate the target data signal. The switching module is used to control the sequential output of the target data signal based on the target clock signal.

14. The data sampling circuit according to claim 13, characterized in that, The N data processing modules include a first data processing module, a second data processing module, a third data processing module, and a fourth data processing module, wherein: The first data processing module includes a first register module and a first switch module. The first register module is used to receive a first initial data signal and a first initial clock signal. The first switch module is used to control the output of the first target data signal based on the first target clock signal. The second data processing module includes a second register module and a second switch module. The second register module is used to receive a second initial data signal and a second initial clock signal, and the second switch module is used to control the output of the second target data signal based on the second target clock signal. The third data processing module includes a third register module and a third switch module. The third register module is used to receive a third initial data signal and a third initial clock signal. The third switch module is used to control the output of the third target data signal based on the third target clock signal. The fourth data processing module includes a fourth register module and a fourth switch module. The fourth register module is used to receive a fourth initial data signal and a fourth initial clock signal. The fourth switch module is used to control the output of the fourth target data signal based on the fourth target clock signal.

15. The data sampling circuit according to claim 14, characterized in that, The first initial clock signal is the same as the second initial clock signal, the third initial clock signal is the same as the fourth initial clock signal, and the phase difference between the first initial clock signal and the third initial clock signal is 180 degrees.

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