Memory device performing erase operations to maintain data reliability

Abstract

A memory device can include a memory block and a control circuit. The memory block can include first and second sub-blocks connected between a common source line and a plurality of bit lines and can be vertically stacked. The control circuit can be configured to select one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on locations of the first and second sub-blocks, and perform an erase operation on the first and second sub-blocks in units of sub-blocks.

Description

[0001] Cross-reference to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2020-0181181, filed with the Korean Intellectual Property Office on December 22, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to storage devices, and more specifically, to storage devices comprising a three-dimensional array of memory cells for performing erase operations on a sub-block basis. Background Technology

[0004] Semiconductor memory devices with three-dimensional array structures have been studied to improve their integration density, and techniques for performing memory operations in sub-block units have been proposed to effectively manage memory blocks larger than those in existing two-dimensional array structures. Recently, a semiconductor memory device has been proposed to support local erase operations performed in sub-block units.

[0005] Using erase voltage to boost the channel voltage of the sub-block targeted for erasure may be interrupted by other sub-blocks. In addition, data stored in other blocks may be degraded due to the erase voltage, resulting in a deterioration in data reliability. Summary of the Invention

[0006] This disclosure provides a storage device with a three-dimensional array of storage cells and a storage device capable of ensuring data reliability by performing effective erasure operations based on the location of sub-blocks.

[0007] According to one aspect of the present invention, a storage device is provided, the storage device comprising: a storage block including a first sub-block and a second sub-block, the first sub-block and the second sub-block being connected between a common source line and a plurality of bit lines and stacked vertically; and a control circuit configured to select one of the common source line and the plurality of bit lines as the transmission path of an erase voltage based on the positions of the first sub-block and the second sub-block, and to perform an erase operation on the first sub-block and the second sub-block on a sub-block basis.

[0008] According to another aspect of the present invention, a memory device is provided, the memory device comprising: a lower chip including a peripheral circuit region; and a first upper chip stacked on the lower chip and connected to the lower chip according to a bonding method, and including a first cell region, wherein the first cell region includes: a first metal layer formed adjacent to the lower chip and connected to a plurality of first bit lines; a first substrate formed at a horizontal height higher than the first metal layer and having a lower surface on which a first common source line is formed; and at least two first sub-blocks connected between the plurality of first bit lines and the first common source line and stacked vertically, and the peripheral circuit region including control circuitry configured to: select one of the plurality of first bit lines and the first common source line as the transmission path of an erase voltage based on the position of the at least two first sub-blocks, and perform an erase operation on the at least two first sub-blocks.

[0009] According to another aspect of the present invention, a memory device is provided, the memory device comprising: a lower chip including a peripheral circuit region; and a first upper chip stacked on the lower chip, connected to the lower chip according to a bonding method, and including a first cell region; and a second upper chip stacked on the first upper chip, connected to the first upper chip according to the bonding method, and including a second cell region, wherein the first cell region comprises: a first substrate adjacent to the second upper chip and having a lower surface on which a first common source line is formed; and a first metal layer, the first metal layer being connected to the lower chip. The lower chip is adjacent to and connected to multiple first bit lines; and a first sub-block, the first sub-block comprising a plurality of vertically stacked first memory cells, the second cell region comprising: a second substrate having a lower surface on which a second common source line is formed; a second metal layer adjacent to the first upper chip and connected to multiple second bit lines; and a second sub-block, the second sub-block comprising a plurality of vertically stacked second memory cells, and the direction in which the erase voltage boosts the channel of the first sub-block during an erase operation of the first sub-block is different from the direction in which the erase voltage boosts the channel of the second sub-block during an erase operation of the second sub-block. Attached Figure Description

[0010] Embodiments of this disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram of a storage device according to an example embodiment;

[0012] Figure 2Ayes Figure 1 A diagram of the storage cell array; Figure 2B and Figure 2C It is used for explanation Figure 2A A diagram showing the configuration of one of the storage blocks; Figure 2D This is a diagram illustrating a storage device having a COP structure according to an example embodiment;

[0013] Figure 3 yes Figure 2B The circuit diagram of the memory block;

[0014] Figure 4 This is a flowchart of an operation method of a storage device according to an example embodiment;

[0015] Figure 5 It is a diagram of a string of cells included in a storage block according to an example embodiment;

[0016] Figure 6A and Figure 6B This is an illustration based on the example embodiment. Figure 5 A diagram showing the erase operation performed on the first sub-block in the unit string;

[0017] Figure 7A and Figure 7B This is an illustration based on the example embodiment. Figure 5 A diagram showing the erase operation performed on the second sub-block in the unit string;

[0018] Figure 8A and Figure 8B This is an illustration based on the example embodiment. Figure 5 A diagram showing the erase operation performed on the second sub-block in the unit string;

[0019] Figures 9A to 9C This is a diagram illustrating an example of a sub-block included in a storage block to which an erasure operation is performed, according to an exemplary embodiment;

[0020] Figure 10 This is a flowchart of an operation method of a storage device according to an example embodiment;

[0021] Figure 11A and 11B This is a diagram illustrating an erasing method for a second sub-block according to an example embodiment;

[0022] Figure 12 This is a flowchart of an operation method of a storage system according to an example embodiment;

[0023] Figure 13 This is a block diagram of a solid-state drive (SSD) system according to an example embodiment;

[0024] Figure 14 This is for illustrative purposes based on example embodiments. Figure 1 Cross-sectional view of an example storage device; and

[0025] Figures 15A to 15D This is based on the example embodiment. Figure 1 Examples of memory devices all have a chip-to-chip (C2C) structure. Cross-sectional view of the memory device. Detailed Implementation

[0026] One or more embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0027] In the following description, one or more embodiments of this disclosure may be described with reference to NAND flash memory. However, the spirit of the inventive concept is not limited to NAND flash memory. The spirit of the inventive concept can be applied to various non-volatile memory devices, such as electrically erasable programmable ROM (EEPROM), NOR flash memory devices, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM).

[0028] Figure 1 This is a block diagram of a storage device 100 according to an example embodiment.

[0029] refer to Figure 1 The storage device 100 may include a memory cell array 110, a page buffer circuit 120, control logic 130, a voltage generator 140, a row decoder 150, and data input / output circuitry 160. Hereinafter, the control logic 130 may be referred to as a control circuit. According to the example embodiment described below, the control logic 130 may include an erase control module 132 for controlling erase operations. Although Figure 1 Although not shown, the storage device 100 may also include various functional blocks related to storage operations. The erase control module 132 may be implemented as hardware logic, software logic, or a combination of hardware and software logic. The erase control module 132 may also be implemented as one or more logic circuits.

[0030] The memory cell array 110 may include strings (or clusters) of cells arranged on a substrate along row and column directions. Each string of cells may include memory cells stacked in a direction perpendicular to the substrate. That is, memory cells may be stacked in a direction perpendicular to the substrate to form a three-dimensional structure. Each memory cell may be, for example, a single-level cell, a multi-level cell, a triple-level cell, a quadruple-level cell, etc. The spirit of the present invention can be flexibly applied to memory cells of various cell types. A memory block of the memory cell array 110 may include a first sub-block SB1 and a second sub-block SB2. Hereinafter, a sub-block may be a memory cell in which the memory cells included in the memory block are logically or physically divided, and may be defined as a specific cell in the memory block in which a partial erase operation can be performed. Control logic 130 may operate the first sub-block SB1 and the second sub-block SB2 in a memory block.

[0031] In an example embodiment, the cell types of the first sub-block SB1 and the second sub-block SB2 may be the same or different from each other. Furthermore, the number of memory cells included in the first sub-block SB1 may be the same as or different from the number of memory cells included in the second sub-block SB2. In some embodiments, the number of word lines connected to the first sub-block SB1 may be the same as or different from the number of memory cells included in the second sub-block SB2.

[0032] The memory cells of the memory cell array 110 can be connected to the row decoder 150 via the word line WL, the serial select line SSL, the ground select line GSL, the bit line BL, the first gate-induced drain-leakage (GIDL) select line GIDL_SL1, and the second GIDL select line GIDL_SL2, and can be connected to the page buffer circuit 120 via the bit line BL. A voltage with a controlled level can be applied to the first GIDL select line GIDL_SL1 and the second GIDL select line GIDL_SL2, thereby enabling the operation according to the example embodiment to be performed during an erase operation. A voltage with a fixed level can be applied during operations other than the erase operation.

[0033] Page buffer circuit 120 can temporarily store data to be programmed into memory cell array 110 and data to be read from memory cell array 110. Page buffer circuit 120 may include page buffers (or latches). For example, each page buffer may include latches corresponding to bit lines BL and may store data in units of pages. Page buffer circuit 120 may include sense latches, and sense latches may include sense latches corresponding to bit lines BL. In addition, each sense latch may be connected to a sense node that detects data through the corresponding bit line.

[0034] Control logic 130 can control all operations of storage device 100. For example, control logic 130 can program data in memory cell array 110 based on command CMD, address ADDR and control signal CTRL received from memory controller (not shown), read data from memory cell array 110, or output various internal control signals for erasing data stored in memory cell array 110.

[0035] The internal control signals output from control logic 130 can be provided to page buffer circuit 120, voltage generator 140, and row decoder 150. Specifically, control logic 130 can provide a voltage control signal CS_vol to voltage generator 140. Voltage generator 140 may include one or more pumps (not shown) and can generate voltages VWL with different levels based on pump operation according to the voltage control signal CS_vol. Furthermore, control logic 130 can provide row address X_ADD to row decoder 150 and column address Y_ADD to page buffer circuit 120. The operation of erase control module 132 is described below, and control logic 130 can generate internal control signals related to the operation of erase control module 132 and output these internal control signals to function blocks of memory device 100. Furthermore, the operation of erase control module 132 can be defined as the operation of control logic 130.

[0036] In the example embodiment, the erase control module 132 can select either the bit line BL or the common source line (not shown) as the transmission path for the erase voltage based on the positions of the first sub-block SB1 and the second sub-block SB2, and the erase control module 132 can perform erase operations on the first sub-block SB1 and the second sub-block SB2 on a sub-block basis. In the following text, for better understanding, it is assumed that the second sub-block SB2 is stacked on top of the first sub-block SB1 and is therefore closer to the bit line BL than the first sub-block SB1.

[0037] In an example embodiment, the erase control module 132 can select a common source line (not shown) as the transmission path for the erase voltage during the erase operation. Therefore, the channels of the first sub-block SB1 and the second sub-block SB2 can be sequentially boosted due to the erase voltage applied through the common source line (not shown).

[0038] In the example embodiment, during the erase operation performed on the second sub-block SB2, the erase control module 132 can select the bit line BL as the transmission path for the erase voltage. Therefore, due to the erase voltage applied through the bit line BL, the channels of the second sub-block SB2 and the first sub-block SB1 can be boosted sequentially.

[0039] In some embodiments, during an erase operation performed on at least one of the first sub-block SB1 and the second sub-block SB2, the erase control module 132 can select all common source lines (not shown) and bit lines BL as transmission paths for the erase voltage. Therefore, the channels of the first sub-block SB1 and the second sub-block SB2 can be boosted due to the erase voltage applied through the bit lines BL and the common source lines (not shown).

[0040] As described above, the erase control module 132 can select different transmission paths for the erase voltage based on the location of the target sub-block, i.e., whether the target sub-block is adjacent to the common source line (not shown) or the bit line BL.

[0041] However, Figure 1 The illustrations are merely examples, and one or more embodiments are not limited thereto. In addition to the first sub-block SB1 and the second sub-block SB2, the memory cell array 110 may also include more sub-blocks, and the erase control module 132 may select the transmission path of the erase voltage based on the location of the sub-blocks and perform the erase operation on a sub-block basis.

[0042] In the example embodiments, the storage device 100 may have any of a stacked structure, a chip-on-periphery (COP) structure, and a bonding structure, and the erasure method according to the example embodiments can be applied to sub-blocks included in the various embodiments. (Refer to...) Figure 2C A detailed description of embodiments of the stacked structure will be provided by referring to Figure 2D A detailed description of embodiments of the COP structure will be provided by referring to Figure 14 and Figures 15A to 15D A detailed description of an embodiment of the joining structure is provided.

[0043] Figure 2A yes Figure 1 A diagram of the storage cell array 110. Figure 2B and Figure 2C It is used for explanation Figure 2A A diagram showing the configuration of one of the storage blocks. Figure 2D This is a diagram illustrating a storage device with a COP structure according to an example embodiment.

[0044] refer to Figure 1 and Figure 2AThe memory cell array 110 may include memory blocks BLK1 to BLKz (where z is a natural number greater than 1). Memory blocks BLK1 to BLKz may each have a three-dimensional structure (vertical structure). For example, each of memory blocks BLK1 to BLKz may include a structure extending upwards in a first direction to a third direction. Each of memory blocks BLK1 to BLKz may include a string of cells (not shown) extending in a second direction. The string of cells (not shown) may be separated from each other in the first and third directions. The string of cells (not shown) of a memory block is connected to a bit line BL, a string select line SSL, a word line WL, one or more ground select lines GSL, and a common source line (not shown). The string of cells (not shown) of memory blocks BLK1 to BLKz may share the bit line BL. For example, the bit line BL may extend in the second direction and may be shared by memory blocks BLK1 to BLKz.

[0045] Storage blocks BLK1 to BLKz can be accessed Figure 1 The row decoder 150 shown is selected. For example, the row decoder 150 can select the memory block corresponding to the received address ADDR from memory blocks BLK1 to BLKz. Programming and reading operations can be performed on the selected memory block. In addition, an erase operation according to the example embodiment can be performed on selected sub-blocks included in the selected memory block.

[0046] Further reference Figure 2B , Figure 2A Storage blocks BLKn, from BLK1 to BLKz, are formed along a direction perpendicular to the substrate SUB. A common source line CSL is disposed on the substrate SUB, and gate electrode GE and insulating layer IL are alternately stacked on the substrate SUB. Furthermore, a charge storage layer CS may be formed between the gate electrode GE and the insulating layer IL.

[0047] When alternatingly stacked gate electrodes GE and insulating layer IL are vertically patterned, a V-shaped pillar P is formed. The pillar P is connected to the substrate SUB through the gate electrodes GE and insulating layer IL. The outer surface O of the pillar P may include a semiconductor material and serve as a channel, while the inner surface I of the pillar P may include an insulating material such as silicon oxide.

[0048] The gate electrode GE of the memory block BLKn may include a first GIDL select line GIDL_SL1, a ground select line GSL, first word lines WL1 to sixth word lines WL6, a serial select line SSL, and a second GIDL select line GIDL_SL2. The pillar P of the memory block BLKn may be connected to bit lines BL1 to BL3. Furthermore, memory cells connected to the first word lines WL1 to the third word lines WL3 may form a first sub-block SB1, and memory cells connected to the fourth word lines WL4 to the sixth word lines WL6 may form a second sub-block SB2. The memory block BLKn can be applied to... Figure 2A The memory blocks BLK1 to BLKz are shown below. For convenience, sub-blocks are illustrated as including word lines and memory cells connected thereto. However, a sub-block can be defined as including at least one of the following: a GIDL select line, a transistor connected to the GIDL select line, a ground select line, a transistor connected to the ground select line, a serial select line, and a transistor connected to the serial select line.

[0049] However, Figure 2B The storage block BLKn is merely an example for illustrative purposes, and one or more embodiments are not limited thereto. It is understood that the spirit of the inventive concept can be applied to various embodiments of the storage block BLKn.

[0050] Figure 2C Sub-blocks SB1 and SB2 in a memory block BLKn' are shown, formed according to a method different from that applied to memory block BLKn. (Reference) Figure 2C The channel CH of memory block BLKn' can include a lower channel CHa and an upper channel CHb. The lower channel CHa can be located between the upper channel CHb and the substrate SUB. For example, the lower channel CHa can be formed by an etching process and a polysilicon deposition process before the upper channel CHb is formed. After the lower channel CHa is formed, the upper channel CHb can be formed on the lower channel CHa by an additional etching process and a polysilicon deposition process. In this case, the memory cell corresponding to the lower channel CHa can be defined as the first sub-block SB1, and the memory cell corresponding to the upper channel CHb can be defined as the second sub-block SB2.

[0051] The channel widths of the lower channel CHa and the upper channel CHb can have the same profile. For example, the diameter d1 of the upper channel CHb corresponding to the sixth character line WL6 can be substantially the same as or similar to the diameter d3 of the lower channel CHa corresponding to the third character line WL3. Furthermore, the diameter d2 of the upper channel CHb corresponding to the fifth character line WL5 can be substantially the same as or similar to the diameter d4 of the lower channel CHa corresponding to the second character line WL2. Moreover, at the position where the first sub-block SB1 contacts the second sub-block SB2, the diameter of the lower channel CHa of the first sub-block SB1 can be larger than the diameter of the upper channel CHb of the second sub-block SB2.

[0052] However, Figure 2C The storage block BLKn' is just an example. As more channels are formed in stages, more channel stacks can be formed, and the storage block BLKn' can include sub-blocks corresponding to the channels respectively.

[0053] refer to Figure 2DA memory device MC according to an example embodiment may include a peripheral circuit region PCR forming peripheral circuitry, a memory cell region MCR, and input / output pads IOPAD. The peripheral circuit region PCR may include a semiconductor substrate SUB, peripheral circuitry (not shown) formed on the upper surface of the semiconductor substrate SUB, and a lower insulating layer LIF covering the peripheral circuitry. The memory cell region MCR may include a substrate layer BASE formed on the upper surface of the lower insulating layer LIF, a memory cell array (not shown) formed on the upper surface of the substrate layer BASE, and an upper insulating layer UIF covering the memory cell array. Input / output pads IOPAD may be formed on the lower surface of the semiconductor substrate SUB. In the memory device MC, the peripheral circuitry may be formed on the semiconductor substrate SUB, and the size of the memory device MC can be reduced by employing a COP structure in which the memory cell array is stacked on the peripheral circuitry.

[0054] At least one memory block can be formed in the memory cell region (MCR), the at least one memory block including sub-blocks to which an erase operation according to the example embodiment is performed. Furthermore, in order to select the transmission path of the erase voltage, an erase transistor controlled to be turned on / off can be formed in the peripheral circuit region (PCR).

[0055] Figure 3 yes Figure 2B The circuit diagram of the storage block BLKn.

[0056] refer to Figure 3 The storage block BLKn can be a vertical NAND flash memory and can include cell strings CSTR11, CSTR21, CSTR31, CSTR12, CSTR22, CSTR32, CSTR13, CSTR23 and CSTR33, first word lines WL1 to sixth word lines WL6, bit lines BL1 to BL3, ground select line GSL, string select lines SSL1 to SSL3, common source line CSL, first GIDL select line GIDL_SL1 and second GIDL select line GIDL_SL2. Here, the number of cell strings, the number of word lines, the number of bit lines, the number of ground select lines, the number of string select lines, the number of first and second GIDL select lines, and the connections between these lines can vary according to the example embodiment.

[0057] Cell strings CSTR11, CSTR21, CSTR31, CSTR12, CSTR22, CSTR32, CSTR13, CSTR23, and CSTR33 can be connected between bit lines BL1 to BL3 and the common source line CSL. Each cell string (e.g., cell string CSTR11) may include a first GIDL select transistor GIDL_ST1 and a second GIDL select transistor GIDL_ST2, a string select transistor SST, first memory cells MC1 to sixth memory cells MC6, and a ground select transistor GST connected in series. First memory cells MC1 to third memory cells MC3 can form a first sub-block SB1, and fourth memory cells MC4 to sixth memory cells MC6 can form a second sub-block SB2. The memory device can perform a partial erase operation on each of the first sub-block SB1 and the second sub-block SB2. Figure 3 The diagram illustrates a storage block BLKn comprising two sub-blocks, such as a first sub-block SB1 and a second sub-block SB2, but this is merely an example. A storage block BLKn may contain more than two sub-blocks.

[0058] In an example embodiment, the first GIDL selection transistor GIDL_ST1 and the second GIDL selection transistor GIDL_ST2 may have a configuration for intentionally causing GIDL during the erase operation, and the erase voltage can be effectively transmitted to the channels of the first subblock SB1 and the second subblock SB2 through the first GIDL selection transistor GIDL_ST1 and the second GIDL selection transistor GIDL_ST2.

[0059] The string select transistor SST can be connected to string select lines SSL1 to SSL3. Memory cells MC1 to MC6 can be connected to first word lines WL1 to sixth word lines WL6, respectively. The ground select transistor GST can be connected to the ground select line GSL. In the example embodiment, in the first GIDL select transistor GIDL_ST1, the gate can be connected to the first GIDL select line GIDL_SL1, and the source can be connected to the common source line CSL. In the second GIDL select transistor GIDL_ST2, the gate can be connected to the second GIDL select line GIDL_SL2, and the drain can be connected to the corresponding bit lines BL1 to BL3.

[0060] Word lines of the same height (e.g., word line WL1) can be connected together, and string select lines SSL1 to SSL3 can be separate. When a memory cell connected to the first word line WL1 and included in the cell strings CSTR11, CSTR12, and CSTR13 is programmed, the first word line WL1 and the first string select line SSL1 can be selected.

[0061] According to the embodiment, the storage device can select the transmission path of the erase voltage based on the positions of the first sub-block SB1 and the second sub-block SB2, and can perform the erase operation by using the selected transmission path.

[0062] Figure 4 This is a flowchart of an operation method of a storage device according to an example embodiment.

[0063] refer to Figure 4 In operation S100, the storage device can identify the location of the target sub-block as the erase target. For example, the storage device can identify whether the target sub-block is adjacent to a bit line or to a common source line. As another example, the storage device can identify whether the target sub-block is adjacent to a string select line or to a ground select line. In some embodiments, the storage device can identify the location of the target sub-block by referring to pre-stored location information about each sub-block. In operation S110, the storage device can select an erasure method based on the location of the target sub-block. In operation S120, the storage device can perform an erasure operation on the target sub-block according to the selected erasure method. For example, when the target sub-block is adjacent to a bit line, the storage device can select the bit line as the transmission path for the erasure voltage and perform an erasure operation on the target sub-block. When the target sub-block is adjacent to a common source line, the storage device can select the common source line as the transmission path for the erasure voltage and perform an erasure operation on the target sub-block. In some embodiments, the storage device may select bit lines and common source lines as transmission paths for the erase voltage regardless of the location of the target sub-block, and may perform an erase operation on the target sub-block.

[0064] Figure 5 This is a diagram of a cell string (CSTR) included in a storage block according to an example embodiment.

[0065] refer to Figure 5 The cell string CSTR may include a first GIDL selection transistor GIDL_ST1 and a ground selection transistor GST for controlling the electrical connection between the common source line CSL and the cell string CSTR, and may include a second GIDL selection transistor GIDL_ST2 and a string selection transistor SST for controlling the electrical connection between the bit line BL and the cell string CSTR, and may include a memory cell MC. Specifically, the first GIDL transistor GIDL_ST1 may be coupled between the common source line CSL and the ground selection transistor GST, and the second GIDL transistor GIDL_ST2 may be coupled between the bit line BL and the string selection transistor SST.

[0066] The cell string CSTR can be coupled to a first erase transistor E_TR1, which is controlled to be turned on / off according to a first gate voltage VG_ER1 to selectively apply an erase voltage to the common source line CSL. The first erase transistor E_TR1 can be coupled to a first terminal T1 to which the erase voltage is applied. The cell string CSTR can be coupled to a second erase transistor E_TR2, which is controlled to be turned on / off according to a second gate voltage VG_ER2 to selectively apply an erase voltage to the bit line BL. The second erase transistor E_TR2 can be connected to a second terminal T2 to which the erase voltage is applied.

[0067] In some embodiments, when a memory block comprising a cell string (CSTR) has a COP structure, the memory block can be stacked on peripheral circuitry. For example, in the peripheral circuitry, a [structure / structure] can be formed. Figure 1 The system includes a page buffer circuit 120, control logic 130, voltage generator 140, row decoder 150, and data input / output circuit 160. Furthermore, a first erase transistor E_TR1 and a second erase transistor E_TR2 can be formed in the region where the peripheral circuitry is formed (hereinafter referred to as the peripheral circuitry region). A detailed description of this is provided below.

[0068] Figure 5 The arrangement of the first erase transistor E_TR1 and the second erase transistor E_TR2 is merely an example, and one or more embodiments are not limited thereto. Various arrangements can be applied to the cell string CSTR, thereby enabling the selection of at least one of the common source line CSL and the bit line BL as the transmission path for the erase voltage.

[0069] Figure 6A and Figure 6B This is an illustration based on the example embodiment. Figure 5 The diagram shows the erase operation performed on the first sub-block SB1 in the cell string CSTR.

[0070] refer to Figure 6A When performing an erase operation on the first sub-block SB1, based on the position of the first sub-block SB1 adjacent to the common source line CSL, the common source line CSL can be selected as the transmission path for the erase voltage V_ERS. Further reference will follow. Figure 6B Describe the detailed operation.

[0071] Further reference Figure 6BThe erase voltage V_ERS can be applied from a first time point t1 to the first terminal T1 and the second terminal T2. The first gate voltage VG_ER1 can be applied from the first time point t1 to the gate of the first erase transistor E_TR1, wherein the first gate voltage VG_ER1 can increase from 0V (or low level) to a specific threshold voltage V from the first time point t1 to the third time point t3. th The level of the erase voltage V_ERS is applied. Therefore, the first erase transistor E_TR1 can be turned on. For example, the erase voltage V_ERS can be approximately 18V, and the threshold voltage V... th The voltage can be approximately 3V. A second gate voltage VG_ER2 with a voltage of 0V (or low level) can be applied to the gate of the second erase transistor E_TR2, thus turning off the second erase transistor E_TR2. The common source line CSL can be selected as the transmission path for the erase voltage V_ERS, and the voltage of the common source line CSL can increase from 0V (or low level) to the level of the erase voltage V_ERS from the first time point t1 to the third time point t3. From the first time point t1 to the second time point t2, a voltage of 0V (or low level) can be applied to the ground source line GSL and the first GIDL select line GIDL_SL1, and the ground source line GSL and the first GIDL select line GIDL_SL1 can be floated starting from the second time point t2. In the following text, the control ground select line GSL and the first GIDL select line GIDL_SL1 have a float start timing (second time point t2) that is later than the float start timing (first time point t1) of the bit line BL, the second GIDL select line GIDL_SL2, the serial select line SSL, and the fourth word lines WL4 to WL6. This is achieved by inducing a voltage difference between the first time point t1 and the second time point t2, thereby effectively providing an erase voltage V_ERS to the channel of the second sub-block SB2. The ground source line GSL and the first GIDL select line GIDL_SL1 may have a float voltage whose level is obtained by subtracting the GIDL voltage V_GIDL from the erase voltage V_ERS. The GIDL voltage V_GIDL is generated by the GIDL of the first GIDL selection transistor GIDL_ST1, and effectively provides the erase voltage V_ERS to the channel of the second sub-block SB2 by inducing a voltage difference between the channels of the first sub-block SB1 and the second sub-block SB2 even after the third time point t3.

[0072] Because the first sub-block SB1 is the erase target sub-block, a voltage of 0V (or low level) can be applied to the first word line WL1 through the third word line WL3. Because the second sub-block SB2 is not the erase target sub-block, the fourth word line WL4 through the sixth word line WL6 can be floated from the erase voltage V_ERS from the first time point t1. Similarly, the serial select line SSL, the second GIDL select line GIDL_SL2, and the bit line BL can be floated from the erase voltage V_ERS from the first time point t1.

[0073] Through the above operations, the channels of the first sub-block SB1 and the second sub-block SB2 can be sequentially boosted to the erase voltage V_ERS in the direction from the common source line CSL to the bit line BL, and the memory cell MC of the first sub-block SB1 can be erased.

[0074] The start time (first time point t1) at which the erase voltage is applied to the first terminal T1 and the second terminal T2 can be the same as the float start timing (first time point t1) of the bit line BL, the second GIDL select line GIDL_SL2, the serial select line SSL, and the fourth word line WL4 to the sixth word line WL6.

[0075] Figure 7A and Figure 7B This is an illustration based on the example embodiment. Figure 5 A diagram showing the erase operation performed on the second sub-block SB2 in the cell string CSTR. This will be discussed in the following description. Figure 7A and Figure 7B Before providing an example embodiment, a comparative example is first described. In the comparative example, it is assumed that when the second sub-block SB2 is erased, the erase voltage V_ERS is transmitted through the common source line CSL, as follows. Figure 6A and Figure 6B As shown. In the comparative example, when 0V (or a low level) is applied to the ground select line GSL and the first GIDL select line GIDL_SL1 from the first time point t1 to the second time point t2 to effectively transmit the erase voltage V_ERS to the channel of the second sub-block SB2, the voltage difference between the ground select line GSL and the first GIDL select line GIDL_SL1, which are applied with voltages increased to near the erase voltage V_ERS, and other lines may be relatively large. Therefore, the charge stored in the memory cell MC of the first sub-block SB1 may be lost. The loss of charge will lead to a deterioration in the data reliability of the memory device and may be applied to… Figure 7A and Figure 7B The embodiments described herein address the problems illustrated in the comparative examples. References are omitted below. Figure 6A and Figure 6B The description provided.

[0076] refer to Figure 7AWhen performing an erase operation on the second sub-block SB2, based on the position of the second sub-block SB2 adjacent to the bit line BL, the bit line BL can be selected as the transmission path for the erase voltage V_ERS. (Refer to...) Figure 7B Describe the detailed operation.

[0077] Further reference Figure 7B The second gate voltage VG_ER2 can be increased from 0V (or low level) to a specific threshold voltage V from the first time point t1 to the third time point t3. th When the erase voltage V_ERS is applied, the second gate voltage VG_ER2 can be applied to the gate of the second erase transistor E_TR2, thus turning on the second erase transistor E_TR2. A first gate voltage VG_ER1 of 0V (or low level) can be applied to the gate of the first erase transistor E_TR1, turning it off. Bit line BL can be selected as the transmission path for the erase voltage V_ERS, and the voltage on bit line BL can increase from 0V (or low level) to the erase voltage V_ERS from the first time point t1 to the third time point t3. A voltage of 0V (or low level) can be applied from the first time point t1 to the second time point t2 to the serial select line SSL and the second GIDL select line GIDL_SL2, and the serial select line SSL and the second GIDL select line GIDL_SL2 can float from the second time point t2. The serial select line SSL and the second GIDL select line GIDL_SL2 can have a floating voltage level obtained by subtracting the GIDL voltage V_GIDL from the erase voltage V_ERS. The GIDL voltage V_GIDL can be generated due to the GIDL of the second GIDL select transistor GIDL_ST2.

[0078] Because the second sub-block SB2 is the erase target sub-block, a voltage of 0V (or low level) can be applied to the fourth word line WL4 through the sixth word line WL6. Because the first sub-block SB1 is not the erase target sub-block, the first word line WL1 through the third word line WL3 can be floated to the erase voltage V_ERS from the first time point t1. Similarly, the ground select line GSL, the first GIDL select line GIDL_SL1, and the common source line CSL can be floated to the erase voltage V_ERS from the first time point t1.

[0079] Through the above operations, the channels of the second sub-block SB2 and the first sub-block SB1 can be sequentially boosted to the erase voltage V_ERS in the direction from the bit line BL to the common source line CSL, and the memory cell MC of the second sub-block SB2 can be erased.

[0080] Figure 8A and Figure 8B This is an illustration based on the example embodiment. Figure 5 The diagram shows the erase operation performed on the second sub-block SB2 in the cell string CSTR.

[0081] refer to Figure 8A When performing an erase operation on the second sub-block SB2, the common source line CSL and the bit line BL can be selected as the transmission path for the erase voltage V_ERS. Further reference is available. Figure 8B To describe the detailed operation.

[0082] Further reference Figure 8B From time point t1 to time point t3, the first gate voltage VG_ER1 and the second gate voltage VG_ER2, which increase from 0V (or low level) to the level at which the erase voltage V_ERS is added to a specific threshold voltage Vth, can be applied to the gates of the first erase transistor E_TR1 and the second erase transistor E_TR2. Therefore, the first erase transistor E_TR1 and the second erase transistor E_TR2 can be turned on. The common source line CSL and the bit line BL can be selected as the transmission path for the erase voltage V_ERS, and the voltages of the common source line CSL and the bit line BL can increase from 0V (or low level) to the level of the erase voltage V_ERS from time point t1 to time point t3. A voltage of 0V (or low level) can be applied from time point t1 to time point t2 to the serial select line SSL and the second GIDL select line GIDL_SL2, and the serial select line SSL and the second GIDL select line GIDL_SL2 can be floated starting from time point t2. The serial select line SSL and the second GIDL select line GIDL_SL2 can have a floating voltage, which has a level obtained by subtracting the GIDL voltage V_GIDL from the erase voltage V_ERS. The GIDL voltage V_GIDL can be generated due to the GIDL of the second GIDL select transistor GIDL_ST2.

[0083] Because the second sub-block SB2 is the erase target sub-block, a voltage of 0V (or low level) can be applied to the fourth word line WL4 through the sixth word line WL6. Because the first sub-block SB1 is not the erase target sub-block, the first word line WL1 through the third word line WL3 can be floated to the erase voltage V_ERS starting from the first time point t1. Similarly, the ground select GSL and the first GIDL select line GIDL_SL1 can be floated to the erase voltage V_ERS starting from the first time point t1.

[0084] Through the above operations, in both the direction from the common source line CSL to the bit line BL and the direction from the bit line BL to the common source line CSL, i.e. in both directions, the channels of the first sub-block SB1 and the second sub-block SB2 can be boosted to the erase voltage V_ERS, and the memory cell MC of the second sub-block SB2 can be erased.

[0085] When performing the erase operation on the first sub-block SB1, the following can be applied: Figure 8A and Figure 8B The embodiments are described herein, and their detailed description will be omitted.

[0086] Figures 9A to 9C This is a diagram of an example of a sub-block included in a storage block to which an erasure operation is performed, according to an example embodiment.

[0087] refer to Figure 9A A memory block BLKn_a may include a first sub-block SB1 and a second sub-block SB2. For example, the first sub-block SB1 and the second sub-block SB2 may each be coupled to the same number of word lines. As another example, the number of memory cells included in the first sub-block SB1 may be the same as the number of memory cells included in the second sub-block SB2. The first sub-block SB1 may be coupled to three word lines WL1 to WL3 (first word line WL1 to third word line WL3), and the second sub-block SB2 may be coupled to three word lines (fourth word line WL4 to sixth word line WL6). The second sub-block SB2 may be adjacent to the bit line BL, and the position of the second sub-block SB2 may be defined as adjacent to the bit line BL. The first sub-block SB1 may be adjacent to the common source line CSL, and the position of the first sub-block SB1 may be defined as adjacent to the common source line CSL. Hereinafter, for consistency, the position of each sub-block is described with respect to the bit line BL or the common source line CSL, but one or more embodiments are not limited thereto. The location of a sub-block can be described using the string select line or string select transistor instead of the bit line BL and the ground select line or ground select transistor instead of the common source line CSL.

[0088] refer to Figure 9B A memory block BLKn_b may include sub-blocks SB1 to SBk (where k is a natural number greater than 2). That is, a memory block BLKn_b may include three or more sub-blocks SB1 to SBk. Sub-blocks SB1 to SBk may be coupled to the same number of word lines, and the number of memory cells included in sub-blocks SB1 to SBk may be the same for each other. However, this is merely an example, and various embodiments can be made. For example, the number of word lines connected to sub-blocks SB1 to SBk may be different for each other, and the number of memory cells included in sub-blocks SB1 to SBk may be different for each other. The location of each sub-block SB1 to SBk may be defined with respect to the bit line BL or the common source line CSL. For example, the first sub-block SB1 to the j-th sub-block SBj (where j is a natural number less than k-1) may be defined as adjacent to the common source line CSL, and the (j+1)-th sub-block SB(j+1) to the k-th sub-block SBk may be defined as adjacent to the bit line BL.

[0089] Information regarding the locations of sub-blocks SB1 to SBk can be predetermined through memory test operations, and this information can be updated periodically or irregularly depending on the operating environment of the storage device for effective erase operations. In an example embodiment, the information regarding the locations of sub-blocks SB1 to SBk may include information about the selected transmission path of the erase voltage during an erase operation performed on each of the sub-blocks SB1 to SBk.

[0090] refer to Figure 9C The storage block BLKn_c may include a first sub-block SB1 and a second sub-block SB2 connected to different numbers of word lines. For example, the first sub-block SB1 may be connected to p word lines WL1 to WLp, and the second sub-block SB2 may be connected to q word lines WL(p+1) to WL(p+q). For example, the ratio of the number of word lines in the first sub-block SB1 to the number of word lines in the second sub-block SB2 may vary, such as "40:60", "50:50", "60:40", etc.

[0091] Figure 10 This is a flowchart of an operation method of a storage device according to an example embodiment.

[0092] refer to Figure 10 In operation S200, the storage device can identify the location of the target sub-block as the erase target sub-block. When the target sub-block is at a certain location, for example, when the target sub-block is between a bit line and a common source line, the storage block can perform operation S210. In operation S210, the storage device can identify the cell types of the adjacent sub-blocks of the target sub-block. In operation S220, the storage device can select an erasure method for the target sub-block based on the location of the target sub-block and the cell types of the adjacent sub-blocks. In operation S230, the storage device can perform an erasure operation on the target sub-block according to the selected erasure method.

[0093] Figure 11A and Figure 11B This is a diagram illustrating the erasure method of the second sub-block SB2 according to an example embodiment.

[0094] refer to Figure 11AThe memory block may include first sub-blocks SB1 to third sub-blocks SB3, second sub-block SB2 may be stacked on top of first sub-block SB1, and third sub-block SB3 may be stacked on top of second sub-block SB2. When an erase operation is performed on second sub-block SB2, the memory device can identify the cell types of the first sub-block SB1 and third sub-block SB3 adjacent to second sub-block SB2 to select the transmission path of the erase voltage. For example, the cell type of first sub-block SB1 may be higher than that of third sub-block SB3. Specifically, the memory cells of first sub-block SB1 are multi-level cells storing two bits of data, while the memory cells of third sub-block SB3 may be single-level cells storing one bit of data. The memory device can select the transmission path of the erase voltage based on the cell types of first sub-block SB1 and third sub-block SB3.

[0095] The third sub-block SB3, operating as a single-order unit operation, can have a larger gap between threshold voltage discretenesses than the first sub-block SB1, operating as a multi-order unit operation. Therefore, due to the difference in voltages generated during the erase operation, the degradation of the data in the third sub-block SB3 can be relatively less than the degradation of the data in the first sub-block SB1. Thus, by considering the relatively smaller degradation of the third sub-block SB3 due to the erase operation, the memory device can select the bit line BL adjacent to the third sub-block SB3 as the transmission path for the erase voltage V_ERS and can perform the erase operation on the second sub-block SB2.

[0096] refer to Figure 11B ,and Figure 11A Unlike the diagram, the cell type of the first sub-block SB1 can have a lower level than the cell type of the third sub-block SB3. Specifically, the memory cells of the first sub-block SB1 can operate as single-level cells and store one bit of data, while the memory cells of the third sub-block SB3 can operate as multi-level cells and store two bits of data. The storage device can select the transmission path of the erase voltage based on the cell types of the first sub-block SB1 and the third sub-block SB3. By considering the relatively small degree of degradation of the first sub-block SB1 due to the erase operation, the storage device can select the common source line CSL adjacent to the first sub-block SB1 as the transmission path of the erase voltage V_ERS and can perform the erase operation on the second sub-block SB2.

[0097] Figure 11A and Figure 11B The cell types of the first sub-block SB1 and the third sub-block SB3 are merely examples, and one or more embodiments are not limited thereto. The spirit of the inventive concept can be applied when the first sub-block SB1 and the third sub-block SB3 have different cell types, such as three-level cell and four-level cell types.

[0098] In some embodiments, when the memory block comprises three or more sub-blocks, the transmission path for the erase voltage selected when each sub-block is designated as the target erase sub-block can be determined based on sub-block operation information, which indicates the cell type and location of each sub-block. Therefore, the transmission path can be pre-stored in the memory device as sub-block erase information. When the memory device performs an erase operation, the transmission path for the erase voltage matching the target sub-block can be quickly selected by referring to the sub-block erase information.

[0099] Figure 12 This is a flowchart of an operation method of a storage system according to an example embodiment.

[0100] refer to Figure 12 The storage system may include a storage controller 300 and a storage device 310. In operation S300, the storage controller 300 may send sub-block operation information of a storage block of the storage device 310 to the storage device 310. The sub-block operation information may indicate the cell type of each sub-block. In some embodiments, the storage controller 300 may change the cell type of a sub-block in the storage block by considering requests from the host, the operating environment of the storage system, etc., and may send sub-block operation information including information about the changed cell type to the storage device 310. In operation S310, the storage device 310 may update sub-block erase information based on the sub-block operation information. As described above, when each sub-block is selected as the target sub-block for erasure, the sub-block erase information may indicate the transmission path of the erase voltage selected for the erase operation. In operation S320, the storage controller 300 may send an erase command about the target sub-block to the storage device 310. In operation S330, the storage device 310 may perform an erase operation on the target sub-block in response to the erase command by using the updated sub-block erase information.

[0101] Figure 13 This is a block diagram of a solid-state drive (SSD) system 400 according to an example embodiment.

[0102] refer to Figure 13 The SSD system 400 may include a host 410 and an SSD 420. The SSD 420 can exchange signals with the host 410 via a signal connector and can receive power via a power connector. The SSD 420 may include an SSD controller 421, an auxiliary power supply 422, and first storage devices 423_1 to s-th storage devices 423_s (i.e., NAND1, NAND2, ..., NANDs, where s is a natural number greater than 1). Each of the first storage devices 423_1 to s-th storage devices 423_s may include one or more previously disclosed storage devices. In some examples, the first storage device 423_1 may employ... Figure 1One or more storage devices. In this case, Figure 1 , Figures 2A to 2D , Figures 3 to 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figures 9A to 9C , Figure 10 , Figure 11A , Figure 11B and Figure 12 The embodiments can be applied to first storage devices 423_1 to s-th storage devices 423_s. For example, first storage devices 423_1 to s-th storage devices 423_s may include first sub-block erase information ERS_Info.1 to s-th sub-block erase information ERS_Info.s, which indicates the transmission path of the erase voltage selected during an erase operation performed on each sub-block of the storage block included in each of the first storage devices 423_1 to s-th storage devices 423_s. As described above, the transmission path of the erase voltage selected during an erase operation on each sub-block can be determined by considering at least one of the location of the sub-block and the cell type of adjacent sub-blocks. First storage devices 423_1 to s-th storage devices 423_s can perform an erase operation on a target sub-block using first sub-block erase information ERS_Info.1 to s-th sub-block erase information ERS_Info.s.

[0103] Figure 14 This is for illustrative purposes based on example embodiments. Figure 1 A cross-sectional view of a storage device 2400, an example of a storage device 100.

[0104] refer to Figure 14 The memory device 2400 may have a chip-to-chip (C2C) structure. The C2C structure may indicate that an upper chip including cell regions (CELL) is fabricated on a first wafer, and a lower chip including peripheral circuit regions (PERI) is fabricated on a second wafer different from the first wafer. The upper and lower chips are then connected to each other according to a bonding method. For example, the bonding method may indicate a method in which bonding metal formed on the uppermost metal layer of the upper chip is electrically connected to bonding metal formed on the uppermost metal layer of the lower chip. For example, when the bonding metal includes copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may include aluminum or tungsten.

[0105] The peripheral circuit area PERI and cell area CELL of the storage device 2400 may each include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0106] The Peripheral Circuit Region (PERI) may include a first substrate 2210, an interlayer insulating layer 2215, circuit elements 2220a, 2220b, and 2220c formed on the first substrate 2210, first metal layers 2230a, 2230b, and 2230c respectively connected to the circuit elements 2220a, 2220b, and 2220c, and second metal layers 2240a, 2240b, and 2240c formed on the first metal layers 2230a, 2230b, and 2230c. Each of the circuit elements 2220a, 2220b, and 2220c may correspond to one or more transistors. In an embodiment, the first metal layers 2230a, 2230b, and 2230c may include tungsten with relatively high resistance, and the second metal layers 2240a, 2240b, and 2240c may include copper with relatively low resistance.

[0107] In this disclosure, only first metal layers 2230a, 2230b, and 2230c and second metal layers 2240a, 2240b, and 2240c are shown, but one or more embodiments are not limited thereto. At least one metal layer may be further formed on the second metal layers 2240a, 2240b, and 2240c. At least a portion of at least one metal layer formed on the second metal layers 2240a, 2240b, and 2240c may include aluminum, which has a lower resistivity than copper included in the second metal layers 2240a, 2240b, and 2240c.

[0108] Interlayer insulating layer 2215 may be formed on first substrate 2210 to cover circuit elements 2220a, 2220b and 2220c, first metal layers 2230a, 2230b and 2230c and second metal layers 2240a, 2220b and 2220c, and may include insulating material such as silicon oxide or silicon nitride.

[0109] The lower bonding metals 2271b and 2272b can be formed on the second metal layer 2240b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 2371b and 2372b of the cell region CELL according to the bonding method, and the lower bonding metals 2271b and 2272b and the upper bonding metals 2371b and 2372b can both include aluminum, copper, tungsten, etc.

[0110] A cell region (CELL) can provide at least one memory block. The cell region (CELL) may include a second substrate 2310 and a first common source line 2320. On the second substrate 2310, word lines 2333 to 2336 (WL1 to WL4) may be stacked in a direction perpendicular to the upper surface of the second substrate 2310 (Z-axis direction). A serial select line 2337 (SSL) and a ground select line 2332 (GSL) may be arranged above and below the word lines 2333 to 2336 (WL1 to WL4), respectively. The serial select line 2337 (SSL), the ground select line 2332 (GSL), and the word lines 2333 to 2336 (WL1 to WL4) may be arranged between the first GIDL select line 2331 and the second GIDL select line 2338 (GIDL_SL1 and GIDL_SL2).

[0111] In the bit line bonding area BLBA, the channel structure CHS can extend in a direction perpendicular to the second substrate 2310 and can penetrate word lines 2333 to 2336 (WL1 to WL4), the first GIDL select line 2331 and the second GIDL select line 2338 (GIDL_SL1 and GIDL_SL2), the serial select line 2337 (SSL), and the ground select line 2332 (GSL). The channel structure CHS may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer can be electrically connected to the first metal layer 2350c and the second metal layer 2360c. For example, the first metal layer 2350c can be a bit line contact, and the second metal layer 2360c can be the first bit line. In an embodiment, the first bit line 2360c can extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 2310.

[0112] exist Figure 14 In the illustrated embodiment, the area where the channel structure CHS, the first bit line 2360c, etc., are arranged can be defined as the bit line bonding area BLBA. The first bit line 2360c can be electrically connected in the bit line bonding area BLBA to the circuit element 2220c that provides the page buffer 2393 in the peripheral circuit area PERI. For example, the first bit line 2360c can be connected to the upper bonding metals 2371c and 2372c in the cell area CELL, and the upper bonding metals 2371c and 2372c can be connected to the lower bonding metals 2271c and 2272c that are connected to the circuit element 2220c of the page buffer 2393.

[0113] In the word line bonding area WLBA, word lines 2332 to 2337 (WL1 to WL6) can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 2310 and can be connected to cell contact plugs 2341 to 2347 (2340). Word lines 2332 to 2337 (WL1 to WL6) and cell contact plugs 2340 can be connected to pads provided as at least some of word lines 2333 to 2336 (WL1 to WL4) extending at different lengths in the second direction. A first metal layer 2350b and a second metal layer 2360b can be sequentially connected to the upper portion of the cell contact plugs 2340 connected to the word lines 2333 to 2336 (WL1 to WL4). In the word line bonding area WLBA, the cell contact plug 2340 can be connected to the peripheral circuit area PERI via the upper bonding metals 2371b and 2372b of the cell area CELL and the lower bonding metals 2271b and 2272b of the peripheral circuit area PERI.

[0114] The cell contact plug 2340 can be electrically connected to circuit element 2220b that provides row decoder 2394 in the peripheral circuitry region PERI. In an embodiment, the operating voltage of circuit element 2220b providing row decoder 2394 can be different from the operating voltage of circuit element 2220c providing page buffer 2393. For example, the operating voltage of circuit element 2220c providing page buffer 2393 can be greater than the operating voltage of circuit element 2220b providing row decoder 2394.

[0115] In the external pad bonding region PA, a common source line contact plug 2380 may be disposed. The common source line contact plug 2380 may comprise a conductive material such as a metal, a metal compound, or polysilicon, and may be electrically connected to the common source line 2320. A first metal layer 2350a and a second metal layer 2360a may be sequentially stacked on the common source line contact plug 2380. For example, the region in which the common source line contact plug 2380, the first metal layer 2350a, and the second metal layer 2360a are disposed may be defined as the external pad bonding region PA.

[0116] Input / output pads 2205 and 2305 can be placed in the external pad bonding area PA. (See reference) Figure 14A lower insulating layer 2201 covering the lower surface of the first substrate 2210 may be formed on the lower portion of the first substrate 2210, and a first input / output pad 2205 may be formed on the lower insulating layer 2201. The first input / output pad 2205 can be connected to at least one of the circuit elements 2220a, 2220b, and 2220c arranged in the peripheral circuit region PERI via a first input / output contact plug 2203, and can be separated from the first substrate 2210 by the lower insulating layer 2201. Furthermore, a side insulating layer may be arranged between the first input / output contact plug 2203 and the first substrate 2210 and can electrically isolate the first input / output contact plug 2203 from the first substrate 2210.

[0117] refer to Figure 14 An upper insulating layer 2301 covering the upper surface of the second substrate 2310 may be formed on the upper part of the second substrate 2310, and a second input / output pad 2305 may be disposed on the upper insulating layer 2301. The second input / output pad 2305 may be connected to at least one of the circuit elements 2220a, 2220b and 2220c disposed in the peripheral circuit region PERI via a second input / output contact plug 2303.

[0118] According to the example embodiment, the second substrate 2310, the first common source line 2320, etc., may not be arranged in the area where the second input / output contact plug 2303 is arranged. Furthermore, the second input / output pad 2305 may not overlap with word lines 2333 to 2336 (WL1 to WL4) in the third direction (Z-axis direction). Reference Figure 14 The second input / output contact plug 2303 can be separated from the second substrate 2310 in a direction parallel to the upper surface of the second substrate 2310, and can be connected to the second input / output pad 2305 by penetrating the interlayer insulating layer 2315 in the cell region.

[0119] According to embodiments, the first input / output pad 2205 and the second input / output pad 2305 can be selectively formed. For example, the storage device 2400 may include only the first input / output pad 2205 disposed on the first substrate 2210 or only the second input / output pad 2305 disposed on the second substrate 2310. Alternatively, the storage device 2400 may include both the first input / output pad 2205 and the second input / output pad 2305.

[0120] In the external pad bonding area PA and bit line bonding area BABA, which are respectively included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the top metal layer can be a dummy pattern, or the top metal layer can be omitted.

[0121] In the external pad bonding area PA, the lower metal pattern 2273a of the peripheral circuit area PERI, which is electrically connected to the upper bonding metals 2371a and 2372a of the cell area CELL, can correspond to the upper metal pattern 2372a formed on the uppermost metal layer of the cell area CELL, which is formed on the uppermost metal layer of the peripheral circuit area PERI. The lower metal pattern 2273a formed on the uppermost metal layer of the peripheral circuit area PERI may not be connected to a separate contact in the peripheral circuit area PERI. As described above, in the external pad bonding area PA, an upper metal pattern (e.g., 2373a) having the same shape as the lower metal pattern (e.g., 2273a) in the peripheral circuit area PERI can correspond to the lower metal pattern (e.g., 2273a) formed on the uppermost metal layer of the peripheral circuit area PERI, which is formed on the upper metal layer of the cell area CELL.

[0122] In the external pad bonding area PA, the upper metal pattern 2373a of the cell area CELL can be electrically connected to the lower bonding metals 2271a and 2272a of the peripheral circuit area PERI.

[0123] Lower bonding metals 2271b and 2272b can be formed on the second metal layer 2240b of the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 2271b and 2272b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 2371b and 2372b of the cell region CELL according to the bonding method.

[0124] Furthermore, in the bit line bonding region BLBA, an upper metal pattern 2392 having the same shape as the lower metal pattern 2252 of the peripheral circuit region PERI can be formed on the uppermost metal layer of the cell region CELL, corresponding to the lower metal pattern 2252 formed on the uppermost metal layer of the peripheral circuit region PERI. No contact may be formed on the upper metal pattern 2392 formed on the uppermost metal layer of the cell region CELL.

[0125] In an example embodiment, the first subblock SB1 may be adjacent to the first common source line CSL (2320) or the second substrate 2310 and may include memory cells MC connected to the first word line 2333 and the second word line 2334 (WL1 and WL2). The second subblock SB2 may be adjacent to the first bit line 2360c or the peripheral circuit region PERI and may include memory cells MC connected to the third word line 2335 and the fourth word line 2336 (WL3 and WL4). However, this is merely an example, and one or more embodiments are not limited thereto. The first subblock SB1 and the second subblock SB2 may also include memory cells connected to a greater number of word lines.

[0126] When the storage device 2400 performs an erase operation, and when the target sub-block is the first sub-block SB1, the first common source line 2320 can be selected as the transmission path for the erase voltage, and when the target sub-block is the second sub-block SB2, the first bit line 2360c can be selected as the transmission path for the erase voltage. One or more embodiments of the present invention can be applied to the storage device 2400.

[0127] In the example embodiment, reference Figure 1 , Figures 2A to 2D and Figure 3 The described array or block of storage cells can be included within a cell area (CELL). (Reference) Figure 1 The described peripheral circuitry (e.g., page buffer circuitry 120, control logic 130, voltage generator 140, row decoder 150, and data input / output circuitry 160) can be included in the peripheral circuitry region PERI.

[0128] Figures 15A to 15D This is based on the example embodiment. Figure 1 Cross-sectional views of storage devices 3400a to 3400c having a C2C structure, examples of storage devices 100.

[0129] refer to Figure 15A ,and Figure 14 Compared to memory device 2400, memory device 3400a may include two or more upper chips comprising cell regions. Specifically, memory device 3400a may have a structure in which a first upper chip including a first cell region CELL1, a second upper chip including a second cell region CELL2, and a lower chip including a peripheral circuit region PER1 are connected according to a bonding method. However, the number of upper chips is not limited to this. A description of the first cell region CELL1 and the second cell region CELL2 has been referenced... Figure 14 The provided description will not be repeated. In the following text, cell region CELL may refer to at least one of first cell region CELL1 and second cell region CELL2.

[0130] In the bitline bonding area (BLBA), the cell region (CELL) may include a lower channel (LCH) and an upper channel (UCH) that are interconnected. The lower channel (LCH) and upper channel (UCH) can be interconnected and can form a channel structure (CHS). That is, with... Figure 14Unlike other channel structures, the channel structure CHS in Figure 15 can be formed using processes for the upper channel UCH and the lower channel LCH. In the first cell region CELL1, the lower channel LCH can extend in a direction perpendicular to the upper surface of the third substrate 3610 and can penetrate the second common source line 3620, the first GIDL select line 3631, the second ground select line 3632, and the second lower word lines 3633 and 3634. The lower channel LCH may include a data storage layer, a channel layer, a buried insulating layer, etc., and can be connected to the upper channel UCH. The upper channel UCH can penetrate the second upper word lines 3635 and 3636, the second string select line 3637, and the second GIDL select line 3638. The upper channel UCH may include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer of the upper channel UCH can be electrically connected to the third metal layer 3650c and the fourth metal layer 3660c. Due to manufacturing processes, the longer the channel length, the more difficult it is to form a channel with a uniform width. The memory device 3400a can achieve improved uniformity in channel width by forming a lower channel (LCH) and an upper channel (UCH) according to a sequential process.

[0131] The second string selection line 3637 and the second ground selection line 3632 can be arranged above and below the second lower digit lines 3633 and 3634 and the second upper digit lines 3635 and 3636. The second digit lines 3633 to 3636, the second string selection line 3637 and the second ground selection line 3632 can be arranged between the first GIDL selection line 3631 and the second GIDL selection line 3638.

[0132] In an example embodiment, the storage device 3400a may further include a word line adjacent to the second string select line 3637 and a dummy word line adjacent to the second ground select line 3632. In some embodiments, the storage device 3400a may further include dummy word lines disposed on the boundary between the lower channel LCH and the upper channel UCH.

[0133] In the bit line bonding area (BLBA), the first cell region CELL1 may include a first through electrode THV1, and the second cell region CELL2 may include a second through electrode THV2. The second through electrode THV2 may penetrate the second common source line 3620 and word lines 3633 to 3636. The second through electrode THV2 may include a conductive material. Alternatively, the second through electrode THV2 may include a conductive material surrounded by an insulating material. The first through electrode THV1 may include the same material as the second through electrode THV2. The first through electrode THV1 and the second through electrode THV2 may be electrically connected to each other via a first through upper metal pattern 3672b and a second through lower metal pattern 3771d. The first through upper metal pattern 3672b may be formed on the upper end of the second upper chip including the second cell region CELL2, and the second through lower metal pattern 3771d may be formed on the lower end of the first upper chip including the first cell region CELL1. The second through electrode THV2 may be electrically connected to a third metal layer 3650c and a fourth metal layer 3660c. The first through-path 3671b can be formed between the fourth metal layer 3660c and the first through-mounted metal pattern 3672b, and the second through-path 3772d can be formed between the first through-electrode THV1 and the second through-mounted lower metal pattern 3771d. The first through-mounted metal pattern 3672b and the second through-mounted lower metal pattern 3771d can be connected to each other according to a bonding method.

[0134] According to an embodiment, a first upper metal pattern 3672a may be formed on the upper part of the second cell region CELL2, and a first lower metal pattern 3771e may be formed on the lower part of the first cell region CELL1. The first upper metal pattern 3672a of the second cell region CELL2 and the first lower metal pattern 3771e of the first cell region CELL1 may be connected to each other in the external pad bonding area PA according to a bonding method. A second upper metal pattern 3772a may be formed on the upper part of the first cell region CELL1, and a second lower metal pattern 3873a may be formed on the upper part of the peripheral circuit region PERI. The second upper metal pattern 3772a of the first cell region CELL1 and the second lower metal pattern 3873a of the peripheral circuit region PERI may be connected to each other in the external pad bonding area PA according to a bonding method. The fourth metal layer 3660c may be a second bit line.

[0135] In an example embodiment, the first cell region CELL1 may include a first sub-block SB1, which includes memory cells connected to first word lines 3733 to 3736. The second cell region CELL2 may include a second sub-block SB2, which includes memory cells connected to second word lines 3633 to 3636.

[0136] In the example embodiment, the direction of the erase voltage boost in the channel of the first sub-block SB1 during an erase operation on the first sub-block SB1 of the first cell region CELL1 may differ from the direction of the erase voltage boost in the channel of the second sub-block SB2 during an erase operation on the second sub-block SB2 of the second cell region CELL2. For example, during the erase operation on the first sub-block SB1, the first bit line 3760c may be selected as the transmission path for the erase voltage, and the channel of the first sub-block SB1 may be boosted from the first bit line 3760c toward the first common source line 3720 due to the erase voltage. During the erase operation on the second sub-block SB2, the second common source line 3620 may be selected as the transmission path for the erase voltage, and the channel of the second sub-block SB2 may be boosted from the second common source line 3620 to the second bit line 3660c due to the erase voltage. As another example, during the erase operation of the first sub-block SB1, the first common source line 3720 can be selected as the transmission path for the erase voltage, and the channel of the first sub-block SB1 can be boosted in the direction from the first common source line 3720 to the first bit line 3760c due to the erase voltage. During the erase operation of the second sub-block SB2, the second bit line 3660c can be selected as the transmission path for the erase voltage, and the channel of the second sub-block SB2 can be boosted in the direction from the second bit line 3660c to the second common source line 3620 due to the erase voltage.

[0137] However, this is merely an example, and one or more embodiments are not limited thereto. The direction in which the erase voltage is boosted in the channel of the first sub-block SB1 during an erase operation can be the same as the direction in which the erase voltage is boosted in the channel of the second sub-block SB2 during an erase operation. For example, during an erase operation on the first sub-block SB1, the first bit line 3760c can be selected as the transmission path for the erase voltage, and during an erase operation on the second sub-block SB2, the second bit line 3660c can be selected as the transmission path for the erase voltage. Therefore, the aforementioned directions can be the same for each other.

[0138] Further reference Figure 15B In an example embodiment, the first cell region CELL1 may include a first sub-block SB1 and a second sub-block SB2. The first sub-block SB1 includes memory cells connected to word lines 3733 and 3734, and the second sub-block SB2 includes memory cells connected to word lines 3735 and 3736. The second cell region CELL2 may include a third sub-block SB3 and a fourth sub-block SB4. The third sub-block SB3 includes memory cells connected to word lines 3633 and 3634, and the fourth sub-block SB4 includes memory cells connected to word lines 3635 and 3636.

[0139] In the example embodiment, by considering the positions of the first sub-block SB1 and the second sub-block SB2 in the first cell region CELL1, the first common source line 3720 can be selected as the transmission path for the erase voltage during the erase operation of the first sub-block SB1, and the first bit line 3760c can be selected as the transmission path for the erase voltage during the erase operation of the second sub-block SB2. By considering the positions of the third sub-block SB3 and the fourth sub-block SB4 in the second cell region CELL2, the second common source line 3620 can be selected as the transmission path for the erase voltage during the erase operation of the third sub-block SB3, and the second bit line 3660c can be selected as the transmission path for the erase voltage during the erase operation of the fourth sub-block SB4.

[0140] Further reference Figure 15C In an example embodiment, the first cell region CELL1 may include a first sub-block SB1 and a second sub-block SB2. The first sub-block SB1 includes memory cells connected to word lines 3733 and 3734, and the second sub-block SB2 includes memory cells connected to word lines 3735 and 3736. The second cell region CELL2 may include a third sub-block SB3, which includes memory cells connected to word lines 3633 to 3636.

[0141] In the example embodiment, by considering the positions of the first sub-block SB1 and the second sub-block SB2 within the first cell region CELL1, the first common source line 3720 can be selected as the transmission path for the erase voltage during the erase operation of the first sub-block SB1, and the first bit line 3760c can be selected as the transmission path for the erase voltage during the erase operation of the second sub-block SB2. During the erase operation of the third sub-block SB3, at least one of the second bit line 3660c and the second common source line 3620 can be selected as the transmission path for the erase voltage.

[0142] Further reference Figure 15D In an example embodiment, the first cell region CELL1 may include a first sub-block SB1, which includes memory cells connected to word lines 3733 to 3736. The second cell region CELL2 may include a second sub-block SB2 and a third sub-block SB3, where the second sub-block SB2 includes memory cells connected to word lines 3633 and 3634, and the third sub-block SB3 includes memory cells connected to word lines 3635 and 3636.

[0143] In the example embodiment, during the erase operation of the first sub-block SB1, at least one of the first bit line 3760c and the first common source line 3670 can be selected as the transmission path for the erase voltage. Taking into account the positions of the second sub-block SB2 and the third sub-block SB3 within the second cell region CELL2, the second common source line 3620 can be selected as the transmission path for the erase voltage during the erase operation of the second sub-block SB2, and the second bit line 3660c can be selected as the transmission path for the erase voltage during the erase operation of the third sub-block SB3.

[0144] While the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A storage device, the storage device comprising: A memory block, comprising a first sub-block and a second sub-block, wherein the first sub-block and the second sub-block are connected between a common source line and multiple bit lines and are stacked vertically; as well as A control circuit is configured to select one of the common source line and the plurality of bit lines as the transmission path for the erase voltage based on the positions of the first sub-block and the second sub-block, and to perform an erase operation on the first sub-block and the second sub-block on a sub-block basis. The storage block further includes a third sub-block stacked between the first sub-block and the second sub-block, and The control circuit is further configured to select one of the common source line and the plurality of bit lines as the transmission path of the erase voltage based on the cell types of the first sub-block and the second sub-block, and to perform an erase operation on the third sub-block.

2. The storage device according to claim 1, wherein, The second sub-block is stacked on top of the first sub-block and is closer to the multiple bit lines than the first sub-block, and The control circuit is configured as follows: During the erase operation on the second sub-block, the plurality of bit lines are selected as the transmission path for the erase voltage, and During the erase operation on the first sub-block, the common source line is selected as the transmission path for the erase voltage.

3. The storage device according to claim 2, wherein, At the position where the first sub-block contacts the second sub-block, the channel diameter of the first sub-block is larger than the channel diameter of the second sub-block.

4. The storage device according to claim 2, wherein, The control circuit is configured to select the plurality of bit lines as the transmission path of the erase voltage during the erase operation on the third sub-block when the cell type of the first sub-block has a higher order than the cell type of the second sub-block.

5. The storage device according to claim 1, wherein, The number of word lines connected to the first sub-block is different from the number of word lines connected to the second sub-block.

6. The storage device according to claim 1, wherein, The storage block also includes: A plurality of first gate-sensing drain-leaking transistors, the plurality of first gate-sensing drain-leaking transistors being coupled to the common source line; Multiple ground selection transistors, each of which is coupled to a plurality of first gate-sensing drain leakage transistors; A plurality of second gate-sensing drain-leaking transistors, wherein the plurality of second gate-sensing drain-leaking transistors are respectively coupled to the plurality of bit lines; and Multiple string select transistors, each of which is coupled to a plurality of second gate-sensing drain-leak transistors.

7. The storage device according to claim 6, wherein, The storage block also includes: A first erase transistor, configured to select the common source line as the transmission path for the erase voltage; and A second erase transistor is configured to select the plurality of bit lines as the transmission path for the erase voltage.

8. The storage device according to claim 6, wherein, The control circuit is configured such that, when the plurality of bit lines are selected as the transmission path of the erase voltage, the first floating start timing of controlling the plurality of gates of the plurality of second gate-sensor-drain-leakage transistors and the plurality of gates of the plurality of string-select transistors is later than the second floating start timing of the plurality of gates of the plurality of first gate-sensor-drain-leakage transistors and the plurality of gates of the plurality of ground-select transistors.

9. The storage device according to claim 8, wherein, The second float start timing is the same as the timing at which the erase voltage is first applied to the multiple bit lines.

10. The storage device according to claim 8, wherein, The floating voltage levels of the plurality of gates of the plurality of second gate-sensing drain-leakage transistors and the plurality of gates of the plurality of string select transistors are lower than the floating voltage levels of the plurality of gates of the plurality of first gate-sensing drain-leakage transistors and the plurality of gates of the plurality of ground select transistors.

11. A storage device, the storage device comprising: The lower chip includes a peripheral circuit area; as well as A first upper chip, stacked on the lower chip and connected to the lower chip according to a bonding method, includes a first unit region. The first unit region includes: A first metal layer is formed adjacent to the lower chip and connected to a plurality of first bit lines; A first substrate is formed at a horizontal height higher than the first metal layer and has a lower surface on which a first common source line is formed. At least two first sub-blocks, the at least two first sub-blocks being connected between the plurality of first bit lines and the first common source line and stacked vertically; and The second sub-block is stacked between the at least two first sub-blocks, and The peripheral circuit region includes a control circuit, which is configured as follows: Based on the positions of the at least two first sub-blocks, one of the plurality of first bit lines and the first common source line is selected as the transmission path for the erase voltage, and An erase operation is performed on the at least two first sub-blocks, and The control circuit is further configured to: select one of the plurality of first bit lines and the first common source line as the transmission path of the erase voltage based on the cell type of each of the at least two first sub-blocks, and perform an erase operation on the second sub-block.

12. The storage device according to claim 11, wherein, The at least two first sub-blocks are respectively connected to a different number of word lines.

13. The storage device according to claim 11, wherein, The at least two first sub-blocks include: First-first sub-block, the first-first sub-block being adjacent to the plurality of first-position lines; and The second-first sub-block is adjacent to the first common source line, and The control circuit is configured as follows: During the erase operation on the first-first sub-block, the plurality of first bit lines are selected as the transmission path for the erase voltage, and During the erase operation on the second-first sub-block, the first common source line is selected as the transmission path for the erase voltage.

14. The storage device according to claim 11, wherein, The peripheral circuit area also includes: A first erase transistor, configured to select the plurality of first bit lines as the transmission path of the erase voltage; and A second erase transistor is configured to select the first common source line as the transmission path for the erase voltage.

15. The storage device of claim 11, further comprising: The second upper chip, stacked on top of the first upper chip, is connected to the first upper chip according to the bonding method, and includes a second unit region. The second unit region includes: A second metal layer is adjacent to the first upper chip and connected to multiple second bit lines; A second substrate, formed at a horizontal height higher than the second metal layer and having a lower surface on which a second common source line is formed; and At least two third sub-blocks, said at least two third sub-blocks being connected between the plurality of second bit lines and the second common source line, and The control circuit is configured as follows: Based on the positions of the at least two third sub-blocks, one of the plurality of second bit lines and the second common source line is selected as the transmission path of the erase voltage, and An erase operation is performed on the at least two third sub-blocks.

16. The storage device according to claim 15, wherein, The control circuit is also configured to operate as if the at least two first sub-blocks and the at least two third sub-blocks were included in a single storage block.

17. A storage device, the storage device comprising: A memory block, comprising a first sub-block and a second sub-block, wherein the first sub-block and the second sub-block are connected between a common source line and multiple bit lines and are stacked vertically; as well as A control circuit is configured to select one of the common source line and the plurality of bit lines as the transmission path for the erase voltage based on the positions of the first sub-block and the second sub-block, and to perform an erase operation on the first sub-block and the second sub-block on a sub-block basis. The storage block further includes: A plurality of first gate-sensing drain-leaking transistors, the plurality of first gate-sensing drain-leaking transistors being coupled to the common source line; Multiple ground selection transistors, each of which is coupled to a plurality of first gate-sensing drain leakage transistors; A plurality of second gate-sensing drain-leaking transistors, wherein the plurality of second gate-sensing drain-leaking transistors are respectively coupled to the plurality of bit lines; and Multiple string select transistors, each of which is coupled to a plurality of second gate-sensor drain-leak transistors, and The control circuit is configured such that, when the plurality of bit lines are selected as the transmission path of the erase voltage, the first floating start timing of the plurality of gates of the plurality of second gate-sensor-drain-leakage transistors and the plurality of gates of the plurality of string select transistors is later than the second floating start timing of the plurality of gates of the plurality of first gate-sensor-drain-leakage transistors and the plurality of gates of the plurality of ground select transistors.

18. The storage device according to claim 17, wherein, The second sub-block is stacked on top of the first sub-block and is closer to the multiple bit lines than the first sub-block, and The control circuit is configured as follows: During the erase operation on the second sub-block, the plurality of bit lines are selected as the transmission path for the erase voltage, and During the erase operation on the first sub-block, the common source line is selected as the transmission path for the erase voltage.

19. The storage device according to claim 18, wherein, At the position where the first sub-block contacts the second sub-block, the channel diameter of the first sub-block is larger than the channel diameter of the second sub-block.

20. The storage device according to claim 18, wherein, The storage block also includes a third sub-block stacked between the first sub-block and the second sub-block, and The control circuit is configured to select one of the common source line and the plurality of bit lines as the transmission path of the erase voltage based on the cell types of the first sub-block and the second sub-block, and to perform an erase operation on the third sub-block.

21. The storage device according to claim 20, wherein, The control circuit is configured to select the plurality of bit lines as the transmission path of the erase voltage during the erase operation on the third sub-block when the cell type of the first sub-block has a higher order than the cell type of the second sub-block.

22. The storage device according to claim 17, wherein, The number of word lines connected to the first sub-block is different from the number of word lines connected to the second sub-block.

23. The storage device according to claim 17, wherein, The storage block also includes: A first erase transistor, configured to select the common source line as the transmission path for the erase voltage; and A second erase transistor is configured to select the plurality of bit lines as the transmission path for the erase voltage.

24. The storage device according to claim 17, wherein, The second float start timing is the same as the timing at which the erase voltage is first applied to the multiple bit lines.

25. The storage device according to claim 17, wherein, The floating voltage levels of the plurality of gates of the plurality of second gate-sensing drain-leakage transistors and the plurality of gates of the plurality of string select transistors are lower than the floating voltage levels of the plurality of gates of the plurality of first gate-sensing drain-leakage transistors and the plurality of gates of the plurality of ground select transistors.

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