Method for manufacturing semiconductor device, semiconductor device, memory, and storage system

Abstract

Embodiments of the present application disclose a semiconductor device manufacturing method, a semiconductor device, a memory and a storage system. The method comprises: providing a stack layer and a plurality of word line contact structures, the stack layer comprising a plurality of alternately stacked gate layers and interlayer insulating layers, the plurality of word line contact structures being electrically connected to the plurality of gate layers one by one, and the word line contact structure penetrating a film layer on the corresponding gate layer, the word line contact structure comprising a word line contact connected to the corresponding gate layer; and forming a lead contact on the stack layer, the lead contact being connected to the word line contact, and a lateral cross-sectional area of the lead contact being greater than a top surface area of the word line contact, the lateral direction being parallel to a top surface of the stack layer. Embodiments of the present application can increase a process window of the connection contact, and improve stability of electrical connection of the semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor device, a semiconductor device, a memory, and a storage system. Background Technology

[0002] After word line contacts are formed on the gate layer of a semiconductor device, connection holes (V0) are formed on the word line contacts, and connection contacts are filled in the connection holes to electrically connect the gate layer to peripheral devices through the word line contacts and connection contacts. However, the top surface area of ​​the word line contacts is small, which makes the loading window of the connection contacts small and difficult to align with the word line contacts. If alignment deviation occurs, it can easily lead to unstable electrical connections. Summary of the Invention

[0003] This invention provides a method for fabricating a semiconductor device, a semiconductor device, a memory, and a storage system, which can increase the process window of the interconnection points and improve the stability of the electrical connections of the semiconductor device.

[0004] This invention provides a method for fabricating a semiconductor device, comprising:

[0005] A stacked layer and multiple word line contact structures are provided. The stacked layer includes multiple alternately stacked gate layers and interlayer insulating layers. The multiple word line contact structures are electrically connected to the multiple gate layers one by one, and the word line contact structures penetrate the film layer located on their corresponding gate layers. The word line contact structures include word line contacts connected to the corresponding gate layers.

[0006] A conductive contact is formed on the stack layer, the conductive contact is connected to the word line contact, and the lateral cross-sectional area of ​​the conductive contact is larger than the top surface area of ​​the word line contact, wherein the lateral direction is parallel to the top surface of the stack layer.

[0007] Optionally, the step of forming conductive contacts on the stack layer includes:

[0008] A dielectric layer is formed on the stack layer;

[0009] A mask layer is formed on the dielectric layer;

[0010] A first opening is formed in the dielectric layer through the mask layer to expose the word line contact;

[0011] The conductive contact point is filled into the first opening to connect the conductive contact point to the word line contact point.

[0012] Optionally, the method further includes:

[0013] A cover layer is provided on the stack layer, the dielectric layer is located on the cover layer, and the word line contact structure further includes a dielectric layer located between the word line contact and the cover layer;

[0014] The step of forming a first opening in the dielectric layer through the mask layer to expose the word line contact includes:

[0015] The first opening is formed in the dielectric layer and the cover layer through the mask layer to expose the dielectric layer;

[0016] Remove the dielectric layer to expose the word line contacts.

[0017] Optionally, the method further includes:

[0018] Provide a storage channel structure that runs through the stack layer;

[0019] A second opening is formed in the dielectric layer through the mask layer to expose the storage channel structure;

[0020] A channel contact is formed in the second opening, so that the channel contact is connected to the storage channel structure.

[0021] Optionally, the method further includes:

[0022] A connecting contact point is formed on the conductive contact point, and the connecting contact point is connected to the conductive contact point.

[0023] Accordingly, embodiments of the present invention also provide a semiconductor device, comprising:

[0024] The stacked layer comprises multiple alternately stacked gate layers and interlayer insulating layers;

[0025] Multiple word line contact structures are electrically connected to multiple gate layers one by one, and the word line contact structures penetrate the film layer located on their corresponding gate layers. The word line contact structures include word line contacts connected to the corresponding gate layers.

[0026] A conductive contact point is located on the stack layer, the conductive contact point is connected to the word line contact point, and the lateral cross-sectional area of ​​the conductive contact point is larger than the top surface area of ​​the word line contact point, the lateral direction being parallel to the top surface of the stack layer.

[0027] Optionally, the word line contact structure includes a first insulating layer, a word line layer disposed around the periphery of the first insulating layer, and a second insulating layer disposed around the periphery of the word line layer;

[0028] The word line layer includes the word line contacts and sacrificial layers located on opposite sides of the word line contacts.

[0029] Optionally, the semiconductor device further includes a gate gap structure;

[0030] The grid gap structure extends through the word line contact, so that the word line contact forms multiple word line sub-contacts.

[0031] Optionally, the word line sub-contacts are respectively connected to the corresponding gate layer and the conductive contact;

[0032] The lateral cross-sectional area of ​​the conductive contact point is greater than the sum of the top surface areas of the plurality of word line sub-contact points.

[0033] Optionally, the orthographic projection of the conductive contact point on the stack layer covers the top surface of the word line contact.

[0034] Optionally, the conductive contact point includes a plurality of conductive sub-contacts;

[0035] The plurality of conductive sub-contacts are connected one-to-one with the plurality of word line sub-contacts, and the lateral cross-sectional area of ​​the conductive sub-contact is greater than the top surface area of ​​the corresponding word line sub-contact.

[0036] Optionally, the semiconductor device further includes:

[0037] Storage channel structure penetrating the stack layer;

[0038] The channel contact is located on the stack layer and is connected to the storage channel structure. The channel contact and the conductive contact are disposed on the same layer.

[0039] Optionally, the semiconductor device further includes:

[0040] A connecting contact point located on the conductive contact point, and the connecting contact point is connected to the conductive contact point.

[0041] This invention also provides a memory, including a memory array structure and a peripheral structure electrically connected to the memory array structure;

[0042] The memory array structure includes the aforementioned semiconductor devices.

[0043] This invention also provides a storage system, including the aforementioned memory and a controller electrically connected to the memory.

[0044] The beneficial effects of this invention are as follows: It provides a stacked layer and a plurality of word line contact structures corresponding one-to-one with a plurality of gate layers in the stacked layer. The word line contact structures penetrate the film layer located on the corresponding gate layer, and the word line contact structures include word line contacts connected to the corresponding gate layer. Conductive contacts are formed on the stacked layer, so that the conductive contacts are connected to the word line contacts. The lateral cross-sectional area of ​​the conductive contacts is larger than the top surface area of ​​the word line contacts, so as to reduce the alignment difficulty when forming connection contacts on the conductive contacts, increase the process window of the connection contacts, and improve the stability of the electrical connection. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0047] Figures 2a to 2h A schematic diagram of a structure corresponding to the method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the first structure of the conductive contact in the method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0049] Figure 4 This is a second structural schematic diagram of the conductive contact in the method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0050] Figure 5 This is a third structural schematic diagram of the conductive contact in the method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0051] Figure 6 This is a fourth structural schematic diagram of the conductive contact point in the method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0052] Figure 7 This is a fifth structural schematic diagram of the conductive contact in the method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0053] Figure 8 This is a sixth structural schematic diagram of the conductive contact in the method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0054] Figure 9This is a seventh structural schematic diagram of the conductive contact in the method for fabricating a semiconductor device provided in an embodiment of the present invention;

[0055] Figure 10 A schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0056] Figure 11 A cross-sectional view of a semiconductor device provided in an embodiment of the present invention;

[0057] Figure 12 Another cross-sectional view of the semiconductor device provided in an embodiment of the present invention;

[0058] Figure 13 A schematic diagram of the structure of a memory provided in an embodiment of the present invention;

[0059] Figure 14 This is a schematic diagram of a storage system provided in an embodiment of the present invention. Detailed Implementation

[0060] The specific structural and functional details disclosed herein are merely representative and are intended to describe exemplary embodiments of the invention. However, embodiments of the invention may be implemented in many alternative forms and should not be construed as being limited solely to the embodiments set forth herein.

[0061] In the description of the embodiments of the present invention, it should be understood that the terms "center," "lateral," "upper," "lower," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing the embodiments of the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the embodiments of the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" and "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present invention, unless otherwise stated, "a plurality of" means two or more. Additionally, the term "comprising" and any variations thereof are intended to cover non-exclusive inclusion.

[0062] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of the present invention based on the specific circumstances.

[0063] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms “a” and “an” as used herein are also intended to include the plural. It should also be understood that the terms “comprising” and / or “including” as used herein specify the presence of the stated features, integers, steps, operations, units, and / or components, without excluding the presence or addition of one or more other features, integers, steps, operations, units, components, and / or combinations thereof.

[0064] See Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor device provided in an embodiment of the present invention.

[0065] like Figure 1 As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention includes steps 101 to 102, as detailed below:

[0066] Step 101: Provide a stack layer and multiple word line contact structures. The stack layer includes multiple alternately stacked gate layers and interlayer insulating layers. The multiple word line contact structures are electrically connected to the multiple gate layers one by one. The word line contact structures penetrate the film layer located on their corresponding gate layers. The word line contact structures include word line contacts connected to the corresponding gate layers.

[0067] In embodiments of the present invention, such as Figure 2a As shown, a substrate 1 can be provided first, with a stacked layer 2 located on the substrate 1. The substrate 1 can include a substrate, or it can include multiple stacked film layers, such as a substrate including an insulating layer on the substrate, a sacrificial layer on the insulating layer, a barrier layer on the sacrificial layer, and a stop layer on the barrier layer. The substrate can be a silicon substrate, or a substrate including other elemental semiconductors or compound semiconductors. The insulating layer can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The sacrificial layer can be a semiconductor layer such as polycrystalline silicon. The barrier layer can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The stop layer can be a semiconductor layer such as polycrystalline silicon.

[0068] Stack layer 2 may include multiple vertically alternating interlayer insulating layers 21 and gate layers 22, where vertical refers to the direction perpendicular to the top surface of substrate 1 (i.e., the surface of substrate 1 closest to stack layer 2). The number of stacked interlayer insulating layers 21 and gate layers 22 is not limited, and can be, for example, 48 layers, 64 layers, 128 layers, etc. Interlayer insulating layers 21 may be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and gate layers 22 may be tungsten, cobalt, copper, aluminum, doped silicon, or doped silicides.

[0069] The semiconductor device includes a core region A and a non-core region B, and stack layer 2 is located in both core region A and non-core region B. For example... Figure 2b and Figure 2c As shown, Figure 2b for Figure 2a Cross-sectional view at the dashed line MM'. Figure 2c for Figure 2a A cross-sectional schematic diagram at the dashed line NN'. The core region A includes multiple memory channel structures 3, which penetrate the stack layer 2 and extend into the substrate 1. Specifically, the memory channel structure 3 includes an isolation layer 31, a channel layer 32 surrounding the isolation layer 31, and a memory dielectric layer 33 surrounding the channel layer 32. The memory dielectric layer 33 includes a tunnel layer (not shown) surrounding the channel layer 32, a charge storage layer (not shown) surrounding the tunnel layer, and a charge blocking layer (not shown) surrounding the charge storage layer. The isolation layer 31 can be an oxide such as silicon oxide, the channel layer 32 can be a semiconductor layer such as polysilicon, the tunnel layer can be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride, the charge storage layer can be an insulating layer containing quantum dots or nanocrystals or compounds containing nitrogen and silicon, and the charge blocking layer can be an oxide such as silicon oxide.

[0070] The storage channel structure 3 also includes a plug 34 located on the side of the storage channel structure 3 facing away from the substrate 1. Specifically, the plug 34 is located on the side of the isolation layer 31 facing away from the substrate 1, and the channel layer 32 is also disposed around the plug 34 to connect with the plug 34. The material of the plug 34 can be the same as the material of the channel layer 32, that is, the plug 34 can be polysilicon or the like.

[0071] The non-core region B includes multiple word line contact structures 4, which are electrically connected one-to-one with multiple gate layers 22 in the stack layer 2. The stack layer 2 of the non-core region B no longer has a stepped structure, so that each word line contact structure 4 passes through a film layer (which includes an interlayer insulating layer 21 and a gate layer 22) located on its corresponding gate layer 22 to connect with its corresponding gate layer 22.

[0072] Specifically, in combination Figure 2a , Figure 2b and Figure 2cAs shown, the word line contact structure 4 includes a first insulating layer 41, a word line layer 42 surrounding the first insulating layer 41, and a second insulating layer 43 surrounding the periphery of the word line layer 42. The word line layer 42 includes word line contacts 44 and sacrificial layers 45, with the sacrificial layers 45 located on opposite sides of the word line contacts 44, meaning the word line contacts 44 and sacrificial layers 45 together surround the first insulating layer 41. The word line contacts 44 penetrate the film layer on their corresponding gate layer 22 and are connected to their corresponding gate layer 22. Specifically, the word line contacts 44 may include a conductive layer 441 on their corresponding gate layer 22, and multiple word line sub-contacts 442 penetrating the film layer on their corresponding gate layer 22 and connected to the conductive layer 441. The word line sub-contacts 442 are connected to their corresponding gate layer 22 through the conductive layer 441. The conductive layer 441 and the word line sub-contacts 442 can be made of tungsten, cobalt, copper, aluminum, doped silicon, or doped silicides, etc. The first insulating layer 41, the second insulating layer 43, and the sacrificial layer 45 can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0073] like Figure 2a As shown, the semiconductor device also includes a first gate gap structure 51. The first gate gap structure 51 is located in the core region A and the non-core region B, and it penetrates the stack layer 2 and extends into the substrate 1. The semiconductor device also includes a gate gap structure, namely a second gate gap structure 52. The second gate gap structure 52 is located in the non-core region B, and it penetrates the word line contact structure 4 and the stack layer 2, extending into the substrate 1. Specifically, the second gate gap structure 52 penetrates the first insulating layer 41, the word line contact 44, and the second insulating layer 43 in the word line contact structure 4. It should be noted that there can be multiple second gate gap structures 52, and each second gate gap structure 52 can correspond to multiple word line contact structures 4, such that each second gate gap structure 52 penetrates its corresponding multiple word line contact structures 4.

[0074] Specifically, such as Figure 2c As shown, the second gate gap structure 52 may include a semiconductor layer 521 that penetrates the word line contact structure 4 and the stacked layer 2 and extends into the substrate 1, as well as a barrier layer 522 disposed around the semiconductor layer 521. The first gate gap structure 51 may be the same as or different from the second gate gap structure 52, and no specific limitation is made here.

[0075] In some embodiments, the stack layer 2 further includes a cover layer (not shown) that covers the memory channel structure 3 and the word line contact structure 4. The word line contact structure 4 also includes a dielectric layer (not shown) located around the word line contact 44, specifically between the word line contact 44 and the first insulating layer 41, between the word line contact 44 and the second insulating layer 43, and between the word line contact 44 and the cover layer. The cover layer can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The dielectric layer can be titanium nitride to improve the adhesion of the word line contact 44.

[0076] Step 102: Form a conductive contact point on the stack layer. The conductive contact point is connected to the word line contact point, and the lateral cross-sectional area of ​​the conductive contact point is greater than the top surface area of ​​the word line contact point. The lateral direction is parallel to the top surface of the stack layer.

[0077] Since the word line contact 44 and the sacrificial layer 45 are both arranged around the first insulating layer 41, the top surface area of ​​the word line contact 44 (i.e., the surface area of ​​the word line contact 44 on the side away from the substrate 1) is relatively small. If a connecting contact is formed directly on the word line contact 44, the process window for the connecting contact will be small. Therefore, in this embodiment, without changing the word line contact 44, a conductive contact is formed on the word line contact 44, so that the lateral cross-sectional area of ​​the conductive contact is larger than the top surface area of ​​the word line contact 44. Subsequently, a connecting contact is formed on the conductive contact, which can increase the process window for the connecting contact and improve the stability of the electrical connection between the connecting contact and the word line contact 44. Here, lateral refers to the direction parallel to the top surface of the stack layer 2 (i.e., the surface of the stack layer 2 on the side away from the substrate 1).

[0078] Specifically, the step 102 of forming conductive contact points on the stack layer includes:

[0079] A dielectric layer is formed on the stack layer;

[0080] A mask layer is formed on the dielectric layer;

[0081] A first opening is formed in the dielectric layer through the mask layer to expose the word line contact;

[0082] The conductive contact point is filled into the first opening to connect the conductive contact point to the word line contact point.

[0083] exist Figure 2b On the basis of, such as Figure 2dAs shown, a dielectric layer 6 is formed on stacked layer 2 using a thin-film deposition process. Dielectric layer 6 is located in the core region A and the non-core region B. The thin-film deposition process can be physical vapor deposition, chemical vapor deposition, atomic layer deposition, laser-assisted deposition, etc. After forming dielectric layer 6, chemical mechanical polishing (CMP) can be performed on dielectric layer 6 to make the surface of dielectric layer 6 facing away from stacked layer 2 flush. Dielectric layer 6 can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0084] like Figure 2e As shown, a mask layer 7 is formed on the dielectric layer 6. The mask layer 7 has a first mask opening 71, which corresponds to the position of the top surface of the word line contact 44, and the lateral cross-sectional area of ​​the first mask opening 71 is larger than the top surface area of ​​the word line contact 44. Specifically, the mask layer 7 may include a hard mask layer (not shown in the figure), an anti-reflection layer (not shown in the figure), and a photoresist layer (not shown in the figure) sequentially located on the dielectric layer 6. The material of the hard mask layer can be amorphous carbon, etc., and the material of the anti-reflection layer can be silicon oxynitride (SiON), etc.

[0085] Since there can be multiple word line contacts 44, there can be multiple first mask openings 71 in the mask layer 7, and multiple first mask openings 71 correspond one-to-one with multiple word line contacts 44.

[0086] The shape and size of the first mask opening 71 corresponding to different word line contacts 44 can be the same or different. For example, this embodiment describes the first mask opening 71 with different shapes and sizes, but in other embodiments, the shape and size of the first mask opening 71 can also be the same.

[0087] like Figure 2f As shown, the dielectric layer 6 is etched through the first mask opening 71 in the mask layer 7 using an etching process to form the first opening 61 in the dielectric layer 6. The first opening 61 corresponds to the position of the top surface of the word line contact 44 to expose the word line contact 44, and the lateral cross-sectional area of ​​the first opening 61 is larger than the top surface area of ​​the word line contact 44.

[0088] Since there can be multiple first mask openings 71 in the mask layer 7, there can also be multiple first openings 61 in the dielectric layer 6, and each of the multiple first openings 61 corresponds one-to-one with a multiple word line contact 44. The shape and size of the first openings 61 corresponding to different word line contacts 44 can be the same or different.

[0089] In some embodiments, the stack layer 2 further includes a cover layer, the word line contact structure 4 further includes a dielectric layer located between the word line contact 44 and the cover layer, and the dielectric layer 6 is located on the cover layer. The step of forming a first opening in the dielectric layer through the mask layer to expose the word line contact includes:

[0090] The first opening is formed in the dielectric layer and the cover layer through the mask layer to expose the dielectric layer;

[0091] Remove the dielectric layer to expose the word line contacts.

[0092] After forming a mask layer 7 on the dielectric layer 6, the dielectric layer 6 and the capping layer are etched through the first mask opening 71 in the mask layer 7 to form a first opening 61 in the dielectric layer 6 and the capping layer, i.e., the first opening 61 penetrates the dielectric layer 6 and the capping layer. Since there is a dielectric layer between the word line contact 44 and the capping layer, the dielectric layer is exposed after the first opening 61 is formed in the dielectric layer 6 and the capping layer. The exposed dielectric layer is then removed to expose the word line contact 44.

[0093] The mask layer 7 also has a second mask opening 72, which corresponds to the position of the storage channel structure 3. While the first opening 61 is formed in the dielectric layer 6, the second opening 62 is formed in the dielectric layer 6 through the second mask opening 72. The second opening 62 corresponds to the position of the storage channel structure 3, exposing the plug 34 in the storage channel structure 3. In this embodiment, the first opening 61 and the second opening 62 in the dielectric layer 6 are formed simultaneously to ensure that the manufacturing process and cost are not increased.

[0094] Then, as Figure 2g As shown, remove mask layer 7. Figure 2h As shown, conductive contacts 8 are filled into the first opening 61. These conductive contacts 8 are connected to word line contacts 44, allowing them to connect to the corresponding gate layer 22 via the word line contacts 44. The lateral cross-sectional area of ​​the conductive contacts 8 is larger than the top surface area of ​​the word line contacts 44, thereby increasing the process window for subsequent connection contacts to the word line contacts 44. Multiple conductive contacts 8 can be present, with each contact corresponding to a different word line contact 44. The shape and size of the lateral cross-sections of different conductive contacts 8 can be the same or different.

[0095] The storage channel structure 3 also has channel contacts, and the channel contacts and the conductive contacts 8 are formed simultaneously.

[0096] Specifically, the method further includes:

[0097] A second opening is formed in the dielectric layer through the mask layer to expose the storage channel structure;

[0098] A channel contact is formed in the second opening, so that the channel contact is connected to the storage channel structure.

[0099] like Figure 2h As shown, when the conductive contact 8 is filled into the first opening 61, the channel contact 9 is formed in the second opening 62. The channel contact 9 is connected to the plug 34 in the storage channel structure 3, so that the channel contact 9 is connected to the channel layer 32 through the plug 34. In this embodiment, the conductive contact 8 and the channel contact 9 are formed simultaneously to ensure that the manufacturing process and cost are not increased.

[0100] After forming the conductive contact 8 and the channel contact 9, the method further includes:

[0101] A connecting contact point is formed on the conductive contact point, and the connecting contact point is connected to the conductive contact point.

[0102] Since the lateral cross-sectional area of ​​the conductive contact 8 is larger than the top surface area of ​​the word line contact 44, by setting the conductive contact 8 so that the connecting contact (not shown in the figure) is connected to the word line contact 44 through the conductive contact 8, the process window of the connecting contact can be increased, the alignment difficulty of the connecting contact can be reduced, and the stability of the electrical connection between the connecting contact and the word line contact can be improved.

[0103] Additionally, a channel connecting contact (not shown in the figure) can also be formed on the channel contact 9, and the channel connecting contact is connected to the channel contact 9. The channel connecting contact and the connecting contact are formed simultaneously to ensure that the manufacturing process and cost are not increased.

[0104] The conductive contact 8 can be a single, integral structure. When the word line contact 44 is an integral structure, the lateral cross-sectional area of ​​the conductive contact 8 is greater than the top surface area of ​​the word line contact 44. When the word line contact 44 includes multiple word line sub-contacts 442, the lateral cross-sectional area of ​​the conductive contact 8 is greater than the sum of the top surface areas of the multiple word line sub-contacts 442. The lateral cross-section of the conductive contact 8 can be rectangular, U-shaped, X-shaped, or other shapes; no specific limitation is made here. Furthermore, the orthographic projection of the conductive contact 8 onto the stack layer 2 can cover the top surface of the word line contact 44.

[0105] like Figure 3 As shown, the word line contact 44 may include four word line sub-contacts 442 arranged in two rows and two columns. The transverse cross-section of the guide contact 8 may be rectangular, so that the positions of the four word line sub-contacts 442 correspond one-to-one with the four corners of the guide contact 8. The orthographic projection of the guide contact 8 on the stack layer 2 covers the top surface of the four word line sub-contacts 442, making the transverse cross-sectional area of ​​the guide contact 8 greater than the sum of the top surface areas of the four word line contacts 442, thereby increasing the process window for subsequent connection contacts to connect to the word line contact 44.

[0106] like Figure 4As shown, the word line contact 44 may include four word line sub-contacts 442 arranged in two rows and two columns. The transverse cross-section of the guide contact 8 may be U-shaped, so that the positions of the four word line sub-contacts 442 correspond one-to-one with the four corners of the guide contact 8. The orthographic projection of the guide contact 8 on the stack layer 2 can completely cover the top surface of the four word line sub-contacts 442, so that the transverse cross-sectional area of ​​the guide contact 8 is greater than the sum of the top surface areas of the four word line sub-contacts 442, thereby increasing the process window for subsequent connection contacts to connect to the word line contact 44.

[0107] like Figure 5 As shown, the word line contact 44 may include four word line sub-contacts 442 arranged in two rows and two columns. The transverse cross-section of the conductive contact 8 may be X-shaped, so that the positions of the four word line sub-contacts 442 correspond one-to-one with the four ends of the conductive contact 8. The orthographic projection of the conductive contact 8 on the stack layer 2 can completely cover the top surface of the four word line sub-contacts 442, so that the transverse cross-sectional area of ​​the conductive contact 8 is greater than the sum of the top surface areas of the four word line sub-contacts 442, thereby increasing the process window for subsequent connection contacts to connect to the word line contact 44.

[0108] When the word line contact 44 includes multiple word line sub-contacts 442, the multiple word line sub-contacts 442 can be spaced apart, so that the conductive contact 8 can include multiple spaced conductive sub-contacts, each conductive sub-contact can be connected to at least one word line sub-contact 442, and the cross-sectional area of ​​each conductive sub-contact is greater than the sum of the top surface areas of its corresponding at least one word line sub-contact 442.

[0109] like Figure 6 As shown, the conductive contact 8 may include multiple first conductive sub-contacts 81a, which are connected one-to-one with multiple word line sub-contacts 442. The orthographic projection of each first conductive sub-contact 81a on the stack layer 2 can completely cover the top surface of its corresponding word line sub-contact 442, so that the lateral cross-sectional area of ​​each first conductive sub-contact 81a is larger than the top surface area of ​​its corresponding word line sub-contact 442, thereby increasing the process window for subsequent connection contacts to connect to the word line contacts 44. The top surface of the word line sub-contact 442 can be rectangular, so that the lateral cross-section of the first conductive contact 81a can also be rectangular. The lateral cross-section of the first conductive contact 81a can also be other shapes, which are not specifically limited here.

[0110] like Figure 7 and Figure 8As shown, the word line contact 44 may include four word line sub-contacts 442, and the conductive contact 8 may include a second conductive sub-contact 81b and a third conductive sub-contact 81c. The second conductive sub-contact 81b is connected to two of the four word line sub-contacts 442 respectively. The orthographic projection of the second conductive sub-contact 81b on the stack layer 2 can completely cover the top surface of the two word line sub-contacts 442, such that the lateral cross-sectional area of ​​the second conductive sub-contact 81b is greater than the sum of the top surface areas of the two word line sub-contacts 442. The third conductive sub-contact 81c is connected to the other two word line sub-contacts 442 respectively. The orthographic projection of the third conductive sub-contact 81c on the stack layer 2 can completely cover the top surface of the other two word line sub-contacts 442, such that the lateral cross-sectional area of ​​the third conductive sub-contact 81c is greater than the sum of the top surface areas of the other two word line sub-contacts 442. In this embodiment, the four word line sub-contacts 442 can be arranged in two rows and two columns, so that the transverse cross-sections of the second conductor sub-contact 81b and the third conductor sub-contact 81c can both be rectangular. The transverse cross-sections of the second conductor contact 81b and the third conductor contact 81c can also be other shapes, which are not specifically limited here.

[0111] like Figure 9 As shown, the word line contact 44 may include four word line sub-contacts 442, and the conductive contact 8 may include a fourth conductive sub-contact 81d and a fifth conductive sub-contact 81e. The fourth conductive sub-contact 81d is connected to three of the four word line sub-contacts 442 respectively. The orthographic projection of the fourth conductive sub-contact 81d on the stack layer 2 can completely cover the top surface of the three word line sub-contacts 442, such that the lateral cross-sectional area of ​​the fourth conductive sub-contact 81d is greater than the sum of the top surface areas of the three word line sub-contacts 442. The fifth conductive sub-contact 81e is connected to another word line sub-contact 442 of the four word line sub-contacts 442. The orthographic projection of the fifth conductive sub-contact 81e on the stack layer 2 can completely cover the top surface of the other word line sub-contact 442, such that the lateral cross-sectional area of ​​the fifth conductive sub-contact 81e is greater than the top surface area of ​​the other word line sub-contact 442. In this embodiment, the four word line sub-contacts 442 can be arranged in two rows and two columns, so that the transverse cross-section of the fourth conductor sub-contact 81d can be L-shaped and the transverse cross-section of the fifth conductor sub-contact 81e can be rectangular. The transverse cross-sections of the fourth conductor sub-contact 81d and the fifth conductor contact 81e can also be other shapes, which are not specifically limited here.

[0112] As can be seen from the above, the semiconductor device fabrication method provided by the embodiments of the present invention can provide a stacked layer and a plurality of word line contact structures corresponding one-to-one with a plurality of gate layers in the stacked layer. The word line contact structures penetrate the film layer located on the corresponding gate layer, and the word line contact structures include word line contacts connected to the corresponding gate layers. Conductive contacts are formed on the stacked layer, so that the conductive contacts are connected to the word line contacts. The lateral cross-sectional area of ​​the conductive contacts is larger than the top surface area of ​​the word line contacts, so as to reduce the alignment difficulty when forming connection contacts on the conductive contacts, increase the process window of the connection contacts, and improve the stability of the electrical connection.

[0113] Accordingly, embodiments of the present invention also provide a semiconductor device that can be fabricated using the above-described semiconductor device fabrication method.

[0114] like Figure 10 , Figure 11 and Figure 12 As shown, this embodiment provides a semiconductor device, including a stack layer 2, multiple word line contact structures 4, and multiple conductive contacts 8.

[0115] The semiconductor device may also include a substrate 1, with a stacked layer 2 located on the substrate 1. The stacked layer 2 may include multiple vertically alternating interlayer insulating layers 21 and gate layers 22, where vertical refers to the direction perpendicular to the top surface of the substrate 1 (i.e., the surface of the substrate 1 closest to the stacked layer 2). The number of stacked interlayer insulating layers 21 and gate layers 22 is not limited, for example, 48 layers, 64 layers, 128 layers, etc. The interlayer insulating layers 21 include, but are not limited to, any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride, and the gate layers 22 include, but are not limited to, tungsten, cobalt, copper, aluminum, doped silicon, or doped silicides.

[0116] The semiconductor device includes a core region A and a non-core region B, and stack layer 2 is located in both core region A and non-core region B. For example... Figure 11 and Figure 12 As shown, Figure 11 for Figure 10 Cross-sectional view at the dashed line PP'. Figure 12 for Figure 10A cross-sectional schematic diagram at the dashed line QQ'. Core region A includes multiple memory channel structures 3, which penetrate the stack layer 2 and extend into the substrate 1. Specifically, the memory channel structure 3 includes an isolation layer 31, a channel layer 32 surrounding the isolation layer 31, and a memory dielectric layer 33 surrounding the channel layer 32. The memory dielectric layer 33 includes a tunnel layer (not shown) surrounding the channel layer 32, a charge storage layer (not shown) surrounding the tunnel layer, and a charge blocking layer (not shown) surrounding the charge storage layer. The isolation layer 31 can be an oxide such as silicon oxide, the channel layer 32 can be a semiconductor layer such as polysilicon, the tunnel layer can be an oxide such as silicon oxide, silicon nitride, or silicon oxynitride, the charge storage layer can be an insulating layer containing quantum dots or nanocrystals or compounds containing nitrogen and silicon, and the charge blocking layer can be an oxide such as silicon oxide.

[0117] The storage channel structure 3 also includes a plug 34 located on the side of the storage channel structure 3 facing away from the substrate 1. Specifically, the plug 34 is located on the side of the isolation layer 31 facing away from the substrate 1, and the channel layer 32 is also disposed around the plug 34 to connect with the plug 34. The material of the plug 34 can be the same as the material of the channel layer 32, that is, the plug 34 can be polysilicon or the like.

[0118] The non-core region B includes multiple word line contact structures 4, which correspond one-to-one with multiple gate layers 22 in the stack layer 2. The stack layer 2 of the non-core region B no longer has a stepped structure, so that each word line contact structure 4 passes through a film layer (which includes an interlayer insulating layer 21 and a gate layer 22) located on its corresponding gate layer 22 to connect with its corresponding gate layer 22.

[0119] Specifically, in combination Figure 10 , Figure 11 and Figure 12 As shown, the word line contact structure 4 includes a first insulating layer 41, a word line layer 42 surrounding the first insulating layer 41, and a second insulating layer 43 surrounding the periphery of the word line layer 42. The word line layer 42 includes word line contacts 44 and a sacrificial layer 45, meaning the word line contacts 44 and the sacrificial layer 45 are together disposed around the first insulating layer 41. The word line contacts 44 penetrate the film layer on their corresponding gate layer 22 and are connected to their corresponding gate layer 22. Specifically, the word line contacts 44 may include a conductive layer 441 on their corresponding gate layer 22, and a plurality of word line sub-contacts 442 penetrating the film layer on their corresponding gate layer 22 and connected to the conductive layer 441. The word line sub-contacts 442 are connected to their corresponding gate layer 22 through the conductive layer 441. The conductive layer 441 and the word line sub-contacts 442 can be made of tungsten, cobalt, copper, aluminum, doped silicon, or doped silicide, etc. The first insulating layer 41, the second insulating layer 43, and the sacrificial layer 45 can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride.

[0120] like Figure 12 As shown, the semiconductor device also includes a first gate gap structure 51. The first gate gap structure 51 is located in the core region A and the non-core region B, and it penetrates the stack layer 2 and extends into the substrate 1. The semiconductor device also includes a gate gap structure, namely a second gate gap structure 52. The second gate gap structure 52 is located in the non-core region B, and it penetrates the word line contact structure 4 and the stack layer 2, extending into the substrate 1. Specifically, the second gate gap structure 52 penetrates the first insulating layer 41, the word line contact 44, and the second insulating layer 43 in the word line contact structure 4. It should be noted that there can be multiple second gate gap structures 52, and each second gate gap structure 52 can correspond to multiple word line contact structures 4, such that each second gate gap structure 52 penetrates its corresponding multiple word line contact structures 4.

[0121] Specifically, such as Figure 12 As shown, the second gate gap structure 52 may include a semiconductor layer 521 that penetrates the word line contact structure 4 and the stacked layer 2 and extends into the substrate 1, as well as a barrier layer 522 disposed around the semiconductor layer 521. The first gate gap structure 51 may be the same as or different from the second gate gap structure 52, and no specific limitation is made here.

[0122] In some embodiments, such as Figure 11 As shown, the semiconductor device further includes a capping layer 10, which is located on the stack layer 2 and covers the memory channel structure 3 and the word line contact structure 4. The word line contact structure 4 further includes a dielectric layer 46, which is located around the word line contact 44, specifically between the word line contact 44 and the first insulating layer 41, and between the word line contact 44 and the second insulating layer 43. The capping layer 10 can be any one or more combinations of silicon oxide, silicon nitride, and silicon oxynitride. The dielectric layer 46 can be titanium nitride to improve the adhesion of the word line contact 44.

[0123] The semiconductor device also includes a dielectric layer 6, which is located on the capping layer 10. Multiple conductive contacts 8 penetrate the dielectric layer 6 and the capping layer 10, and are connected one-to-one with multiple word line contacts 44. The lateral cross-sectional area of ​​each conductive contact 8 is larger than the top surface area of ​​its corresponding word line contact 44. The lateral direction is parallel to the top surface of the stack layer 2 (i.e., the surface of the stack layer 2 facing away from the substrate 1), increasing the process window for subsequent connection contacts.

[0124] The semiconductor device also includes a channel contact 9, which penetrates the dielectric layer 6 and the capping layer 10, and is connected to a plug 34 in the storage channel structure 3, so that the channel contact 9 is connected to the channel layer 32 through the plug 34. The channel contact 9 and the conductive contact 8 are disposed in the same layer, that is, the channel contact 9 and the conductive contact 8 can be formed using the same manufacturing process, so as not to increase the manufacturing process and cost of the semiconductor device.

[0125] The semiconductor device may also include interconnect contacts (not shown in the figure) and channel interconnect contacts (not shown in the figure). The interconnect contacts are located on and connected to the conductive contact 8, such that the interconnect contacts are connected to the word line contacts 44 through the conductive contact 8. Since the lateral cross-sectional area of ​​the conductive contact 8 is larger than the top surface area of ​​the word line contacts 44, connecting the interconnect contacts to the word line contacts 44 through the conductive contact 8 can increase the process window of the interconnect contacts, reduce the alignment difficulty of the interconnect contacts, and improve the stability of the electrical connection between the interconnect contacts and the word line contacts.

[0126] The channel connection contact is located on and connected to the channel contact 9. The channel connection contact and the connection contact are arranged in the same layer, that is, the channel connection contact and the connection contact can be formed using the same manufacturing process, so as not to increase the manufacturing process and cost of the semiconductor device.

[0127] The conductive contact 8 can be a single, integral structure. When the word line contact 44 is an integral structure, the lateral cross-sectional area of ​​the conductive contact 8 is greater than the top surface area of ​​the word line contact 44. When the word line contact 44 includes multiple word line sub-contacts 442, the lateral cross-sectional area of ​​the conductive contact 8 is greater than the sum of the top surface areas of the multiple word line sub-contacts 442. The lateral cross-section of the conductive contact 8 can be rectangular, U-shaped, X-shaped, or other shapes; no specific limitation is made here.

[0128] like Figure 3 As shown, the word line contact 44 may include four word line sub-contacts 442 arranged in two rows and two columns. The transverse cross-section of the guide contact 8 may be rectangular, so that the positions of the four word line sub-contacts 442 correspond one-to-one with the four corners of the guide contact 8. The orthographic projection of the guide contact 8 on the stack layer 2 covers the top surface of the four word line sub-contacts 442, making the transverse cross-sectional area of ​​the guide contact 8 greater than the sum of the top surface areas of the four word line contacts 442, thereby increasing the process window for subsequent connection contacts to connect to the word line contact 44.

[0129] like Figure 4As shown, the word line contact 44 may include four word line sub-contacts 442 arranged in two rows and two columns. The transverse cross-section of the guide contact 8 may be U-shaped, so that the positions of the four word line sub-contacts 442 correspond one-to-one with the four corners of the guide contact 8. The orthographic projection of the guide contact 8 on the stack layer 2 can completely cover the top surface of the four word line sub-contacts 442, so that the transverse cross-sectional area of ​​the guide contact 8 is greater than the sum of the top surface areas of the four word line sub-contacts 442, thereby increasing the process window for subsequent connection contacts to connect to the word line contact 44.

[0130] like Figure 5 As shown, the word line contact 44 may include four word line sub-contacts 442 arranged in two rows and two columns. The transverse cross-section of the conductive contact 8 may be X-shaped, so that the positions of the four word line sub-contacts 442 correspond one-to-one with the four ends of the conductive contact 8. The orthographic projection of the conductive contact 8 on the stack layer 2 can completely cover the top surface of the four word line sub-contacts 442, so that the transverse cross-sectional area of ​​the conductive contact 8 is greater than the sum of the top surface areas of the four word line sub-contacts 442, thereby increasing the process window for subsequent connection contacts to connect to the word line contact 44.

[0131] When the word line contact 44 includes multiple word line sub-contacts 442, the multiple word line sub-contacts 442 can be spaced apart, so that the conductive contact 8 can include multiple spaced conductive sub-contacts, each conductive sub-contact can be connected to at least one word line sub-contact 442, and the cross-sectional area of ​​each conductive sub-contact is greater than the sum of the top surface areas of its corresponding at least one word line sub-contact 442.

[0132] like Figure 6 As shown, the conductive contact 8 may include multiple first conductive sub-contacts 81a, which are connected one-to-one with multiple word line sub-contacts 442. The orthographic projection of each first conductive sub-contact 81a on the stack layer 2 can completely cover the top surface of its corresponding word line sub-contact 442, so that the lateral cross-sectional area of ​​each first conductive sub-contact 81a is larger than the top surface area of ​​its corresponding word line sub-contact 442, thereby increasing the process window for subsequent connection contacts to connect to the word line contacts 44. The top surface of the word line sub-contact 442 can be rectangular, so that the lateral cross-section of the first conductive contact 81a can also be rectangular. The lateral cross-section of the first conductive contact 81a can also be other shapes, which are not specifically limited here.

[0133] like Figure 7 and Figure 8As shown, the word line contact 44 may include four word line sub-contacts 442, and the conductive contact 8 may include a second conductive sub-contact 81b and a third conductive sub-contact 81c. The second conductive sub-contact 81b is connected to two of the four word line sub-contacts 442 respectively. The orthographic projection of the second conductive sub-contact 81b on the stack layer 2 can completely cover the top surface of the two word line sub-contacts 442, such that the lateral cross-sectional area of ​​the second conductive sub-contact 81b is greater than the sum of the top surface areas of the two word line sub-contacts 442. The third conductive sub-contact 81c is connected to the other two word line sub-contacts 442 respectively. The orthographic projection of the third conductive sub-contact 81c on the stack layer 2 can completely cover the top surface of the other two word line sub-contacts 442, such that the lateral cross-sectional area of ​​the third conductive sub-contact 81c is greater than the sum of the top surface areas of the other two word line sub-contacts 442. In this embodiment, the four word line sub-contacts 442 can be arranged in two rows and two columns, so that the transverse cross-sections of the second conductor sub-contact 81b and the third conductor sub-contact 81c can both be rectangular. The transverse cross-sections of the second conductor contact 81b and the third conductor contact 81c can also be other shapes, which are not specifically limited here.

[0134] like Figure 9 As shown, the word line contact 44 may include four word line sub-contacts 442, and the conductive contact 8 may include a fourth conductive sub-contact 81d and a fifth conductive sub-contact 81e. The fourth conductive sub-contact 81d is connected to three of the four word line sub-contacts 442 respectively. The orthographic projection of the fourth conductive sub-contact 81d on the stack layer 2 can completely cover the top surface of the three word line sub-contacts 442, such that the lateral cross-sectional area of ​​the fourth conductive sub-contact 81d is greater than the sum of the top surface areas of the three word line sub-contacts 442. The fifth conductive sub-contact 81e is connected to another word line sub-contact 442 of the four word line sub-contacts 442. The orthographic projection of the fifth conductive sub-contact 81e on the stack layer 2 can completely cover the top surface of the other word line sub-contact 442, such that the lateral cross-sectional area of ​​the fifth conductive sub-contact 81e is greater than the top surface area of ​​the other word line sub-contact 442. In this embodiment, the four word line sub-contacts 442 can be arranged in two rows and two columns, so that the transverse cross-section of the fourth conductor sub-contact 81d can be L-shaped and the transverse cross-section of the fifth conductor sub-contact 81e can be rectangular. The transverse cross-sections of the fourth conductor sub-contact 81d and the fifth conductor contact 81e can also be other shapes, which are not specifically limited here.

[0135] The semiconductor device provided in this embodiment of the invention provides a conductive contact point on the word line contact, which connects the conductive contact point to the word line contact. The lateral cross-sectional area of ​​the conductive contact point is larger than the top surface area of ​​the word line contact, thereby reducing the alignment difficulty when forming connecting contacts on the conductive contact point, increasing the process window of the connecting contacts, and improving the stability of the electrical connection.

[0136] See Figure 13 This is a schematic diagram of the memory structure provided in an embodiment of the present invention.

[0137] like Figure 13 As shown, the memory includes a memory array structure 100 and a peripheral structure 200 connected to the memory array structure 100. The memory array structure 100 can be a non-volatile memory array structure, such as NAND flash memory or NOR flash memory. Specifically, the memory array structure 100 may include the semiconductor devices described in the above embodiments, which will not be elaborated further here.

[0138] The peripheral structure 200 may include devices such as CMOS (Complementary Metal-Oxide-Semiconductor), SRAM (Static Random Access Memory), DRAM (Dynamic Random Access Memory), FPGA (Field Programmable Gate Array), CPU (Central Processing Unit), and Xpoint chip.

[0139] Specifically, the peripheral structure 200 can be located on the storage array structure 100, and the peripheral structure 200 is connected to the storage array structure 100. The storage array structure 100 and the peripheral structure 200 can also adopt other architectural forms, such as the peripheral structure 200 being located below the storage array structure 100, i.e., a PUC (periphery under core array) architecture, or the peripheral structure 200 being arranged side by side with the storage array structure 100, i.e., a PNC (periphery near core array) architecture, etc., without specific limitations here.

[0140] The memory provided in this embodiment of the invention can improve the stability of the electrical connection of semiconductor devices, thereby improving the electrical performance of the memory.

[0141] See Figure 14 This is a schematic diagram of the storage system provided in an embodiment of the present invention.

[0142] like Figure 14 As shown in the figure, this embodiment of the invention also provides a storage system, which includes a memory 300 and a controller 400. The memory 300 and the controller 400 are electrically connected, and the controller 400 is used to control the memory 300 to store data. The memory 300 is the memory in the above embodiment, and will not be described in detail here.

[0143] The storage system can be applied to terminal products such as computers, televisions, set-top boxes, and vehicles.

[0144] In summary, although the embodiments of the present invention have been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the embodiments of the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention shall be determined by the scope defined in the claims.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A stacked layer and multiple word line contact structures are provided. The stacked layer includes multiple alternately stacked gate layers and interlayer insulating layers. The multiple word line contact structures are electrically connected to the multiple gate layers one-to-one. Each word line contact structure penetrates a film layer located on its corresponding gate layer and contacts the film layer. The film layer includes multiple alternately stacked gate layers and interlayer insulating layers. Each word line contact structure includes a word line contact connected to the corresponding gate layer. A conductive contact is formed on the stack layer, the conductive contact is connected to the word line contact, and the lateral cross-sectional area of ​​the conductive contact is larger than the top surface area of ​​the word line contact, wherein the lateral direction is parallel to the top surface of the stack layer.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The step of forming conductive contact points on the stack layer includes: A dielectric layer is formed on the stack layer; A mask layer is formed on the dielectric layer; A first opening is formed in the dielectric layer through the mask layer to expose the word line contact; The conductive contact point is filled into the first opening to connect the conductive contact point to the word line contact point.

3. The method for fabricating a semiconductor device according to claim 2, characterized in that, The method further includes: A cover layer is provided on the stack layer, the dielectric layer is located on the cover layer, and the word line contact structure further includes a dielectric layer located between the word line contact and the cover layer; The step of forming a first opening in the dielectric layer through the mask layer to expose the word line contact includes: The first opening is formed in the dielectric layer and the cover layer through the mask layer to expose the dielectric layer; Remove the dielectric layer to expose the word line contacts.

4. The method for fabricating a semiconductor device according to claim 2, characterized in that, The method further includes: Provide a storage channel structure that runs through the stack layer; A second opening is formed in the dielectric layer through the mask layer to expose the storage channel structure; A channel contact is formed in the second opening, so that the channel contact is connected to the storage channel structure.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The method further includes: A connecting contact point is formed on the conductive contact point, and the connecting contact point is connected to the conductive contact point.

6. A semiconductor device, characterized in that, include: The stacked layer comprises multiple alternately stacked gate layers and interlayer insulating layers; Multiple word line contact structures are electrically connected to multiple gate layers one by one, and each word line contact structure penetrates a film layer located on its corresponding gate layer. The word line contact structure contacts the film layer, and the film layer includes multiple alternately stacked gate layers and interlayer insulating layers. Each word line contact structure includes a word line contact connected to the corresponding gate layer. A conductive contact point is located on the stack layer, the conductive contact point is connected to the word line contact point, and the lateral cross-sectional area of ​​the conductive contact point is larger than the top surface area of ​​the word line contact point, the lateral direction being parallel to the top surface of the stack layer.

7. The semiconductor device according to claim 6, characterized in that, The word line contact structure includes a first insulating layer, a word line layer disposed around the periphery of the first insulating layer, and a second insulating layer disposed around the periphery of the word line layer; The word line layer includes the word line contacts and sacrificial layers located on opposite sides of the word line contacts.

8. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes a gate gap structure; The grid gap structure extends through the word line contact, so that the word line contact forms multiple word line sub-contacts.

9. The semiconductor device according to claim 8, characterized in that, The word line sub-contacts are respectively connected to the corresponding gate layer and the conductive contact; The lateral cross-sectional area of ​​the conductive contact point is greater than the sum of the top surface areas of the plurality of word line sub-contact points.

10. The semiconductor device according to claim 6, characterized in that, The orthographic projection of the conductive contact point on the stack layer covers the top surface of the word line contact point.

11. The semiconductor device according to claim 8, characterized in that, The conductive contact point includes multiple conductive sub-contacts; The plurality of conductive sub-contacts are connected one-to-one with the plurality of word line sub-contacts, and the lateral cross-sectional area of ​​the conductive sub-contact is greater than the top surface area of ​​the corresponding word line sub-contact.

12. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes: Storage channel structure penetrating the stack layer; The channel contact is located on the stack layer and is connected to the storage channel structure. The channel contact and the conductive contact are disposed on the same layer.

13. The semiconductor device according to claim 6, characterized in that, The semiconductor device further includes: A connecting contact point located on the conductive contact point, and the connecting contact point is connected to the conductive contact point.

14. A memory, characterized in that, It includes a storage array structure and peripheral structures connected to the storage array structure; The memory array structure includes a semiconductor device as described in any one of claims 6 to 13.

15. A storage system, characterized in that, It includes the memory as described in claim 14, and a controller electrically connected to the memory.

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