Device providing multiple threshold voltages and method of manufacturing the same

Abstract

The present disclosure relates to devices providing multiple threshold voltages and methods of manufacturing the same. One method includes forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, and performing a first thermal drive-in operation at a first temperature to form a diffusion feature in a first portion of the dielectric layer underlying the first patterned layer. The method also includes forming a second patterned layer of a second dipole material, where a first section of the second patterned layer is on the diffusion feature and a second section of the second patterned layer is offset from the diffusion feature. The method further includes performing a second thermal drive-in operation at a second temperature, where the second temperature is lower than the first temperature. The method additionally includes forming a gate electrode layer on the dielectric layer.

Description

Technical Field

[0001] This application relates generally to the field of semiconductor technology, and more specifically to devices that provide multiple threshold voltages and methods of manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded several generations of ICs, each with smaller and more complex circuitry than the previous one. Throughout IC development, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process typically benefits production efficiency and reduces associated costs. However, this scaling down also increases the complexity of IC fabrication and manufacturing, and similar advancements in IC processes and manufacturing are needed to achieve these progresses.

[0003] For example, nanosheet-based devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCE). Nanosheet-based devices comprise multiple channel layers stacked together to form transistor channels joined by a gate structure. Nanosheet-based devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, allowing these devices to be aggressively scaled down while maintaining gate control and mitigating SCE. However, achieving certain functions (such as providing multiple threshold voltages) without sacrificing other performance characteristics can be challenging due to the complex device structure and reduced spacing between features. Therefore, while conventional techniques are often sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0004] According to one aspect of this application, a method is provided, comprising: forming a dielectric layer on a semiconductor workpiece; forming a first patterned layer of a first dipole material on the dielectric layer; performing a first thermal drive-in operation at a first temperature to form a diffusion feature in a first portion of the dielectric layer located below the first patterned layer; forming a second patterned layer of a second dipole material, a first segment of the second patterned layer located on the diffusion feature, and a second segment of the second patterned layer offset from the diffusion feature; performing a second thermal drive-in operation at a second temperature, wherein the second temperature is lower than the first temperature; and forming a gate electrode layer on the dielectric layer.

[0005] According to another aspect of this application, a method is provided, comprising: forming a dielectric layer on a semiconductor workpiece; forming a first patterned layer of a first dipole material on the dielectric layer; performing a first thermal drive-in operation for a first duration to drive a subset of the first dipole material into the dielectric layer; performing a first etching operation to remove remaining portions of the first dipole material; forming a second patterned layer of a second dipole material on the dielectric layer, a first portion of the second patterned layer disposed on a first portion of the dielectric layer without the first dipole material, and a second portion of the second patterned layer disposed on a second portion of the dielectric layer having the first dipole material; performing a second thermal drive-in operation for a second duration, wherein the second duration is greater than the first duration; and performing a second etching operation to remove remaining portions of the first dipole material, wherein performing the first etching operation comprises: recessing a mixed region of the dielectric layer including the first dipole material.

[0006] According to another aspect of this application, a semiconductor device is provided, comprising: a semiconductor substrate; a first transistor on the semiconductor substrate, the first transistor having: a first channel, a first junction layer, a first gate dielectric layer on the first channel, and a first gate electrode layer on the first gate dielectric layer and bordering the first gate dielectric layer; and a second transistor on the semiconductor substrate, the second transistor having: a second channel, a second junction layer, a second gate dielectric layer on the second channel, and a second gate electrode layer on the second gate dielectric layer and bordering the second gate dielectric layer, wherein the first gate electrode layer and the second gate electrode layer have the same composition, wherein the first gate dielectric layer includes a first dipole material component having a maximum concentration at half-thickness line of the first gate dielectric layer, and wherein the second gate dielectric layer includes a second dipole material component having a maximum concentration at the junction between the second gate dielectric layer and the second junction layer. Attached Figure Description

[0007] The various aspects of this disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features can be arbitrarily enlarged or reduced.

[0008] Figure 1 and Figure 14 This is a flowchart illustrating a method for manufacturing a device according to some embodiments of the present disclosure.

[0009] Figure 2A and Figure 15This is a plan view of an embodiment of the device of this disclosure according to some embodiments of this disclosure.

[0010] Figure 2B This is a three-dimensional (3D) view of a nanosheet-based transistor of an embodiment of the device of this disclosure constructed according to some embodiments of this disclosure.

[0011] Figure 2C According to some embodiments of this disclosure Figure 2B A cross-sectional view of a nanosheet-based transistor along line A-A'.

[0012] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 16 , Figure 17 , Figure 18 , Figure 19 , Figure 20 and Figure 21 These are cross-sectional views of embodiments of the device or a portion thereof constructed at various manufacturing stages according to some embodiments of the present disclosure.

[0013] Figure 13 , Figure 22 , Figure 23A , Figure 23B , Figure 23C , Figure 24 , Figure 25A , Figure 25B , Figure 26A and Figure 26B This refers to data illustrating various aspects of embodiments of this disclosure. Detailed Implementation

[0014] This disclosure is best understood from the following detailed description (when read in conjunction with the accompanying drawings). It should be emphasized that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the various features may be increased or decreased arbitrarily for clarity of discussion.

[0015] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not in itself prescribe a relationship between the various embodiments and / or configurations discussed.

[0016] Furthermore, for ease of description, spatially relative terms such as “below,” “under,” “lower than,” “above,” “above,” etc., may be used herein to describe the relationship of an element or feature to one or more other elements or features shown in the figures. In addition to the orientation depicted in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatially relative descriptive terms used herein may be interpreted accordingly in a similar manner. Furthermore, when numbers or ranges of numbers are described using terms such as “about,” “approximately,” etc., unless otherwise stated, the term is intended to cover numbers within + / - 10% of the number described. For example, the term “about 5 nm” covers a size range from 4.5 nm to 5.5 nm.

[0017] This disclosure generally relates to ICs and semiconductor devices and methods of forming them. More specifically, this disclosure relates to semiconductor devices having multiple threshold voltages (Vt) (hereinafter referred to as multi-Vt devices). Developing such multi-Vt devices becomes increasingly challenging as advanced technology nodes continue to scale down. Typically, various additional material layers may be required to design the device to provide multiple threshold voltages. These material layers occupy specific spaces (and / or volumes) on the semiconductor chip, hindering the scaling mission. In some examples, the device may not have sufficient space to accommodate such additional material layers. For example, nanosheet-based devices (sometimes referred to as gate all-around (GAA) devices, multi-bridge channel (MBC) devices, or other similar names) comprise multiple channel layers stacked vertically. The gate stack is formed in a very narrow spacing between adjacent channel layers in the vertical direction, where additional material layers sometimes cannot be reliably formed. Furthermore, the volume of these additional material layers can further adversely affect device performance, such as causing channel resistance (Rt) to increase. chTherefore, this disclosure provides processes and methods that allow the formation of multi-Vt devices without size requirements. The devices presented herein may be complementary metal-oxide-semiconductor (CMOS) devices, p-type metal-oxide-semiconductor (PMOS) devices, or n-type metal-oxide-semiconductor (NMOS) devices. Those skilled in the art will recognize other examples of semiconductor devices that can benefit from the aspects of this disclosure. Furthermore, while this disclosure uses nanosheet-based devices as examples, those skilled in the art will recognize other examples of semiconductor devices that can benefit from the aspects of this disclosure. For example, other types of metal-oxide-semiconductor field-effect transistors (MOSFETs), such as planar MOSFETs, fin FETs, and other multi-gate FETs, can benefit from the aspects of this disclosure.

[0018] Figure 1 This is a flowchart of an embodiment of the method 1000 of the present disclosure for preparing the multi-Vt device 10 (or simply device 10) of the present disclosure. Figure 2A This is a plan view of device 10 according to an embodiment of the present disclosure. Figure 2B This is a three-dimensional (3D) perspective view of a nanosheet-based transistor 100 according to some embodiments of the present disclosure, the transistor representing Figure 2A The components of device 10. Figure 2C According to some embodiments of this disclosure Figure 2B A cross-sectional view of the nanosheet-based transistor 100 along line A-A'. Figures 3-12 These are cross-sectional views or enlarged cross-sectional views of the device 10 (or a portion thereof) at various manufacturing stages according to embodiments of the present disclosure.

[0019] refer to Figure 1 Box 1010 and reference Figures 2A-2CA nanosheet-based example multi-Vt device 10 is received. Device 10 includes a plurality of nanosheet-based transistors (or simply transistors), such as transistors 100A-100D and 100A'-100D'. In the depicted embodiment, transistors 100A and 100A' are formed in substrate region 102A of semiconductor substrate 102; transistors 100B and 100B' are formed in substrate region 102B of semiconductor substrate 102; transistors 100C and 100C' are formed in substrate region 102C of semiconductor substrate 102; and transistors 100D and 100D' are formed in substrate region 102D of semiconductor substrate 102. Furthermore, in the depicted embodiment, transistors 100A-100D may be configured as n-type transistors, while transistors 100A'-100D' may be configured as p-type transistors. In some embodiments, transistors 100A-100D each have a different threshold voltage; and transistors 100A'-100D' each have a different threshold voltage. Therefore, device 10 provides both n-type and p-type transistors, each providing four (4) different threshold voltages. As described later, these total eight (8) threshold voltages can be achieved by different configurations of the gate dielectric layer with respect to the dipole element. Transistors 100A-100D and 100A'-100D' can include similar or different device structures. In the depicted embodiments, transistors 100A-100D and 100A'-100D' are both nanosheet-based transistors and have similar device structures, for example... Figure 2B and Figure 2C The device structure of transistor 100 shown. Figures 2A-2C This has been abbreviated to provide an overview of device 10 and does not include all details. For example, Figures 2A-2C The shapes, sizes, and relative positions of the transistors shown have been simplified and / or conceptualized and are not intended to be limiting. Additional details are described in conjunction with the following figures.

[0020] refer to Figure 2B and Figure 2C Nanosheet-based transistor 100 (or simply transistor 100) can represent Figure 2A One or more of transistors 100A-100D and 100A'-100D'. In other words, Figure 2B and Figure 2C The diagram shows Figure 2AAs shown, transistor 100 includes a semiconductor substrate 102 (or simply substrate 102). Substrate 102 contains semiconductor materials such as bulk silicon (Si), germanium (Ge), silicon-germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb) or combinations thereof. Substrate 102 may also include a semiconductor-on-insulator substrate, such as silicon-on-insulator (SOI), silicon-germanium-on-insulator (SGOI), or germanium-on-insulator (GOI) substrates. Fin structures (or fins) 104 are formed on substrate 102, each fin extending horizontally longitudinally in the X direction and horizontally spaced apart from each other in the Y direction. The X and Y directions are perpendicular to each other, and the Z direction is perpendicular (or orthogonal) to the horizontal XY plane defined by the X and Y directions. The top surface of substrate 102 may be parallel to the XY plane. As described above, substrate 102 includes substrate regions 102A-102D.

[0021] Each fin structure 104 has a source region 104a and a drain region 104a arranged along the X direction. The source region 104a and the drain region 104a are collectively referred to as source / drain regions 104a. An epitaxial source / drain feature 500 is formed in or on the source / drain regions 104a of the fin structure 104. In some embodiments, the epitaxial source / drain feature 500 is configured as part of a PMOS transistor. Therefore, the epitaxial source / drain feature 500 can include any suitable p-type semiconductor material, such as Si, SiGe, Ge, SiGeC, or combinations thereof. In some embodiments, the epitaxial source / drain feature 500 is configured as part of an NMOS transistor. Therefore, the epitaxial source / drain feature 500 can include any suitable n-type semiconductor material, such as Si. The epitaxial source / drain feature 500 can also be doped in situ or out-of-situ. For example, the epitaxially grown SiGe source / drain features of a PMOS can be doped with boron (B) to form Si:Ge:B source / drain features; and the epitaxially grown Si source / drain features of an NMOS can be doped with carbon to form silicon:carbon (Si:C) source / drain features, doped with phosphorus to form silicon:phosphorus (Si:P) source / drain features, or with both carbon and phosphorus to form silicon-carbon phosphor (Si:C:P) source / drain features. Multiple processes, including etching and growth processes (e.g., epitaxial processes), can be used to grow the epitaxial source / drain features 500. One or more annealing processes can be performed to activate the dopants in the epitaxial source / drain features 500. In some embodiments, the epitaxial source / drain features 500 can be fused together, for example, along the Y direction, between adjacent fin structures 104 to provide a larger lateral width than individual epitaxial source / drain features.

[0022] Each fin structure 104 also has a channel region 104b disposed between and connecting the source / drain regions 104a. Each fin structure 104 includes a stack of channel layers 120 (which may also be interchangeably referred to as "semiconductor layer 120", "suspended semiconductor layer 120", or "suspended channel layer 120"). The stack of channel layers 120 occupies the channel region 104b of the fin structure 104 and extends from the substrate 102 in a vertical direction (e.g., along the Z direction). Each of the channel layers 120 connects to a pair of epitaxial source / drain features 500. Each of the channel layers 120 may have one of many different shapes, such as a wire (or nanowire), sheet (or nanosheet), rod (or nanorod) and / or other suitable shapes, and may be spaced apart from each other. In the depicted embodiment, there are three channel layers 120 in the stack. However, there may be any suitable number of layers in the stack, such as 2 to 10 layers. In some embodiments, the channel layer 120 is at the nanoscale (e.g., having at least one dimension of about 1 nm to about 100 nm). Therefore, the channel layer 120 is referred to as a nanostructure, and the transistor is referred to as a transistor based on a nanostructure (or nanosheet).

[0023] In some embodiments, the fin structure 104 can be formed by first forming a layer stack on a substrate 102. The layer stack may include alternating semiconductor layers 110 and 120. The material composition of semiconductor layers 110 and 120 is configured such that they are etch-selective in a subsequent etching process. For example, in some embodiments, semiconductor layer 110 comprises silicon germanium (SiGe), while semiconductor layer 120 comprises silicon (Si). The layer stack (and, in some embodiments, the substrate portion beneath it) is then collectively patterned into the fin structure 104, such that each fin structure 104 extends longitudinally in the X direction. Patterning can be performed by any suitable method. For example, one or more photolithography processes can be used to pattern the fins, including dual patterning or multi-patterning processes. Typically, dual patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns with, for example, smaller pitches than that achievable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to pattern the fins. Patterning can be performed using multiple etching processes, which may include dry etching and / or wet etching. The fin structures 104 may have the same or different lateral widths along the Y direction.

[0024] Semiconductor layer 110 is subsequently removed and is therefore also referred to as sacrificial semiconductor layer 110. Meanwhile, patterned semiconductor layer 120 is later used as the channel for the transistor and is therefore also referred to as channel layer 120. Each channel layer 120 can be bonded to a single gate structure 250. Gate structure 250 includes a gate dielectric layer 246 and a gate electrode layer 248. In the depicted embodiment, gate structure 250 also includes an interface layer 242. However, in some other embodiments, the interface layer 242 may be omitted. Note that gate structure 250 in… Figure 2B The features shown are transparent to illustrate the features (e.g., channel layer 120) covered by gate structure 250. Gate structures 250 may be configured to extend longitudinally parallel to each other, for example, each along the Y direction. In some embodiments, gate structures 250 each surround the top and side surfaces of each of the fin structures 104. In some embodiments, as described later, gate structure 250 is first formed with a dummy gate stack of different materials (e.g., polysilicon), which is then replaced by gate dielectric layer 246 and gate electrode layer 248 (and, in some embodiments, boundary layer 242). The dummy gate stack 240 may be formed by processes including deposition, photolithography, patterning, and etching. Deposition processes may include chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), other suitable methods, or combinations thereof. Gate structure 250 also includes gate spacers. Gate spacers may comprise a single-layer or multi-layer structure. For example, in the depicted embodiment, a gate spacer layer 201 is formed on the top surface of the device, and a gate spacer layer 202 is formed on the gate spacer layer 201. Gate spacer layers 201 and 202 may each comprise silicon nitride (Si3N4), silicon oxide (SiO2), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbonitrile (SiOCN), carbon-doped oxide, nitrogen-doped oxide, porous oxide, or combinations thereof.

[0025] Transistor 100 also includes an isolation feature 150 within or on substrate 102 that spaces adjacent fin structures 104 from each other. Isolation feature 150 may be a shallow trench isolation (STI) feature. In some examples, forming isolation feature 150 includes etching trenches into substrate 102 between active electrode regions (where the fin structures are formed) and filling these trenches with one or more dielectric materials (e.g., silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof). Any suitable method, such as CVD, ALD, PVD, plasma-enhanced CVD (PECVD), plasma-enhanced ALD (PEALD), and / or combinations thereof, may be used to deposit isolation feature 150. Isolation feature 150 may have a multilayer structure, such as a thermal oxide liner layer over substrate 102 and a fill layer (e.g., silicon nitride or silicon oxide) over the thermal oxide liner layer. Alternatively, isolation feature 150 may be formed using any other isolation technique. Figure 2B As shown, the fin structure 104 is located above the top surface of the isolation feature 150. In the depicted embodiment, the transistor 100 further includes: an internal spacer 206 between the gate structure 250 and the source / drain feature 500; a contact etch stop layer 220 on the epitaxial source / drain feature 500; and an interlayer dielectric (ILD) layer 230 on the epitaxial source / drain feature 500 and on the contact etch stop layer 220. Figure 2B and Figure 2C The image has been abbreviated to provide an overview of transistor 100 and does not include all details. Additional details of the gate structure 250 are described in conjunction with the following figures.

[0026] As described above, transistor 100 is formed by replacing the dummy gate stack of gate structure 250 with a gate dielectric layer 246 and a gate electrode layer 248 (and an interface layer 242 in some embodiments). Details for forming the gate dielectric layer 246 are described below. Return to Reference Figure 1 Box 1010 and reference Figure 3 The workpiece (or simply workpiece 10) for device 10 is received. Figure 3 Only a portion of workpiece 10 is shown, which was subsequently machined into Figure 2B and Figure 2C Transistor 100 (e.g., one of transistors 100A-100D and 100A'-100D'). In other words, Figure 3 The figure shows the ratio Figure 2B and Figure 2C The transistor 100 is a transistor from an earlier process stage. More specifically, the transistor 100 at this process stage includes those described above. Figure 2B and Figure 2CAll features described except that the gate structure 250 includes a dummy gate stack 240 instead of a gate dielectric layer 246, a gate electrode layer 248, or an interface layer 242. The dummy gate stack 240 may include any suitable material, such as polysilicon. In some embodiments, the dummy gate stack 240 may include a multilayer structure. For example, in some embodiments, the dummy gate stack may include a dummy gate dielectric layer and a dummy gate electrode layer.

[0027] refer to Figure 4 The dummy gate stack 240 is selectively removed from the gate structure 250 to form openings. The etching process can be a dry etching process, a wet etching process, or a combination thereof. The etching process can be tuned such that the dummy gate stack 240 is removed without (or only minimally) etching other features of the transistor 100. Furthermore, after the dummy gate stack 240 is removed (exposing the sidewall surfaces of the fin structure 104), the remaining portion of the sacrificial semiconductor layer 110 is selectively removed to form additional openings. These openings collectively form a gate trench 241. The gate trench 241 exposes portions of these channel layers 120 at 360° and further exposes the top surface of the substrate 102.

[0028] Figure 5 The figure shows an enlarged view of transistor 100, specifically a portion of the gate trench 241 of transistor 100. (Reference) Figure 5 Method 1000 continues to form an interface layer 242 in the gate trench 241 and on the channel layer 120. In some embodiments, the interface layer 242 is formed on the exposed surface of the channel layer 120. In some embodiments, the interface layer 242 improves the adhesion between the subsequently formed gate dielectric layer 246 and the channel layer 120. In some embodiments, the interface layer 242 has a thickness in the range of about 5 angstroms to about 15 angstroms. In embodiments, the interface layer 242 comprises a dielectric material, such as SiO2, HfSiO, SiON, other silicon-containing dielectric materials, other suitable dielectric materials, or combinations thereof. The interface layer 242 is formed by any suitable process, such as thermal oxidation, chemical oxidation, ALD, CVD, other suitable processes, or combinations thereof.

[0029] refer to Figure 1 Box 1020 and reference Figure 5 A gate dielectric layer 246 is formed on the interface layer 242, for example, directly on and in contact with (e.g., at the interface with) the interface layer 242. Furthermore, the gate dielectric layer 246 may be further formed on other surfaces exposed in the gate trench 241. The gate dielectric layer 246 may include a high-k dielectric material, such as HfO2, HfSiO, HfSiO4, HfSiON, HfLaO, HfTaO, HfTiO, HfZrO, or HfAlO.x The gate dielectric layer 246 may be formed by any of the processes described herein, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof. For example, the gate dielectric layer 246 may be conformally deposited on the interface layer 242 by an ALD process, such that the gate dielectric layer 246 has a substantially uniform thickness and partially fills the gate trench 241. The gate dielectric layer 246 may be disposed on the sidewall surface of the inner spacer 206 and surround the channel layer 120. In some embodiments, the gate dielectric layer 246 has a thickness of about 1 nm to about 3 nm. The gate dielectric layer 246 is formed to surround the exposed portion of the channel layer 120 and reduces the size of the gate trench 241. The gate dielectric layer 246 separates the channel layer 120 from the subsequently formed gate electrode layer and is crucial for determining the threshold voltage of the transistor.

[0030] refer to Figure 1 Box 1030 and reference Figure 6A dipole layer 302 is deposited in the gate trench 241 or in some of the gate trenches 241 as described later. As described above, each of the gate trenches 241 surrounds a portion of the channel layer 120 (e.g., those surrounded by the gate dielectric layer 246) at 360° and also over a portion of the topmost channel layer 120 and a portion of the substrate 102. Thus, the dipole layer 302 is formed on and around the gate dielectric layer 246 such that the dipole layer 302 directly contacts the exposed surface of the gate dielectric layer 246. The dipole layer 302 can be deposited by ALD, CVD, PVD, thermal oxidation deposition, or other suitable methods, and can be deposited at temperatures ranging from about 100°C to about 450°C and pressures ranging from about 1 Torr to about 100 Torr. The dipole layer 302 can comprise any suitable material. In some embodiments, the dipole layer 302 can comprise an n-type dipole material or a precursor of an n-type dipole material. n-type dipole materials may include germanium oxide (GeO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium oxide (SrO), other suitable n-type dipole materials, or combinations thereof. In some embodiments, dipole layer 302 may include a p-type dipole material or a precursor of a p-type dipole material. p-type dipole materials may include aluminum oxide (Al2O3), gallium oxide (Ga2O3), magnesium oxide (MgO), hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), zinc oxide (ZnO), other suitable p-type dipole materials, or combinations thereof. Figure 6 As shown, in this process stage, the dipole layer 302 is separated from the channel layer 120 and the gate dielectric layer 246. As will be discussed, the dipole material of the dipole layer 302 will be thermally driven into the corresponding gate dielectric layer 246 in a subsequent step, such that these dipole materials are distributed across the gate dielectric layer 246 and around the boundary between the gate dielectric layer 246 and the junction layer 242. Therefore, the dipole material of the dipole layer 302 can thus be distributed closer to or closer to the surface of the channel layer 120. In NMOS, n-type dipole materials configured in this way are used to lower the threshold voltage of the NMOS; while in PMOS, n-type dipole materials configured in this way are used to increase the threshold voltage of the PMOS. Similarly, in PMOS, p-type dipole materials configured in this way are used to lower the threshold voltage of the PMOS; while in NMOS, p-type dipole materials configured in this way are used to increase the threshold voltage of the NMOS. Furthermore, the amount and distribution of these dipole materials further affect the magnitude of the threshold voltage variation. Therefore, the threshold voltage of the transistor can be fine-tuned by simply designing the presence or absence, chemical properties, and distribution of the dipole material in the gate dielectric layer 246.

[0031] In some embodiments, the material of the dipole layer 302 can be designed based on the desired amplitude (or amount) of threshold voltage tuning. For example, using materials such as La2O3, Y2O3, or TiO2, the threshold voltage of transistor 100 can be tuned up (for p-type transistors) or down (for n-type transistors) in the range of about 20 mV to about 450 mV. Furthermore, the thickness of the dipole layer 302 can be further adjusted based on the desired amplitude of threshold voltage tuning. In some embodiments, a thicker dipole layer 302 typically allows (all other things being equal) more dipole material into the gate dielectric layer 246 and results in a larger variation in the transistor threshold voltage. In some embodiments, the dipole layer 302 can be deposited to a substantially uniform thickness, ranging from about 0.5 angstroms to about 10 angstroms in various embodiments, for example, from about 3 angstroms to about 5 angstroms. If the thickness is too small (e.g., less than 0.5 angstroms), the dipole layer 302 may be too weak for Vt tuning in certain cases. If the thickness is too large (e.g., greater than 10 angstroms), the dipole layer 302 may be too strong for Vt tuning and may have side effects, such as reduced mobility in the channel layer 120.

[0032] Furthermore, as described above, device 10 includes a plurality of NMOS transistors and PMOS transistors. Each transistor may have the same characteristics as described above. Figures 2B-2C and Figures 3-6 The device structure of the described transistor 100 is similar to that of a typical device structure, except that only a subset of the transistors includes a dipole layer 302. Therefore, each transistor includes a corresponding gate trench 241 and, where appropriate, can receive deposition of a corresponding portion of the dipole layer 302 on a corresponding portion of the gate dielectric layer. In other words, each of transistors 100A-100D and 100A'-100D' may include portions 200A-200D (corresponding to...) Figure 6 Part 200), which includes the gate dielectric layer 246 and the remaining portion of the gate trench 241. Furthermore, some of parts 200A-200D may include a dipole layer 302, as described in detail later. In this respect, Figure 7 For the purpose of clearly illustrating various aspects of the embodiments, portions 200A-200D of NMOS transistors 100A-100D are illustrated. Although portions 200A-200D are depicted as discontinuous, it should be understood that these portions may instead be arranged one after another. Furthermore, although they are depicted side-by-side in a particular order, it should be understood that this disclosure anticipates any alternative relative positions. Additionally, although not explicitly stated below, transistors 100A'-100D' may include gate dielectric portions and dipole layers 302 similar to those of NMOS transistors 100A-100D, and undergo similar process steps.

[0033] refer to Figure 7Each of portions 200A-200D includes a corresponding portion of gate dielectric layer 246, referred to as gate dielectric portions 246A-246D respectively. Dipole layer 302 is shown herein as representative. Figure 6 The collection of circles representing the chemical composition of the dipole layer 302. The number of circles does not necessarily represent the concentration or amount of the chemical composition. Although not explicitly described in Figure 7 In this process, a dipole layer 302 is also formed on the sidewall surface and bottom surface of the gate dielectric portions 246A-246D, similar to the formation of the dipole layer 302 on... Figure 6 The gate dielectric layer 246 is formed on the sidewall and bottom surfaces. In the depicted embodiment, the dipole layer 302 is formed on a subset of the surfaces of the gate dielectric portions 246A-246D, rather than on all of the entire surfaces. At this stage of the process, the gate dielectric portions 246B and 246D may each have thicknesses d1B and d1D, which may be from about 1 nm to about 3 nm. In some embodiments, the thicknesses d1B and d1D may be similar to the thicknesses d1A and d1C of the corresponding gate dielectric portions 246A and 246C. If the thicknesses d1A-d1D are too small, for example less than about 1 nm, tunneling through the gate dielectric portions 246A-246D may increase dramatically, leading to leakage. If the thicknesses d1A-d1D are too large, for example greater than about 3 nm, the gate capacitance may not be optimized.

[0034] refer to Figure 1 Box 1040 and reference Figure 8Process 402 is performed to form diffusion features within the gate dielectric layer 246 in regions configured for a subset of transistors 100A-100D. In some embodiments, process 402 includes a thermal drive-in operation (alternatively referred to as an annealing process). In some embodiments, the dipole material of the dipole layer 302 (e.g., dipole material La2O3) or the dipole elements of the dipole layer 302 (e.g., La and O elements of the dipole layer 302 having dipole material La2O3) are at least partially driven into the gate dielectric layer 246. For example, the thermal drive-in operation provides thermal energy to the workpiece 10, causing a significant increase in the mobility of the dipole material and the diffusion of the dipole elements into regions that intersect with them (e.g., into the gate dielectric portions 246B and 246D that intersect with the dipole layer 302). In one embodiment, the heat-driven entry operation is a soaking annealing process performed in an environment of O2, N2, or a mixture of O2 and N2 at a temperature range of about 600°C to about 1000°C (e.g., about 700°C to about 800°C). In another embodiment, the heat-driven entry operation is a furnace tube annealing process performed in an environment of O2, N2, or a mixture of O2 and N2 at a temperature range of about 300°C to about 600°C for about 1 second to about 30 minutes. In yet another embodiment, the heat-driven entry operation is a spike annealing process. In still another embodiment, the heat-driven entry operation is a laser annealing process or a microwave annealing process performed using O2, N2, NH3, H2, or a mixture thereof at a temperature range of about 800°C to about 1200°C for about 1 millisecond to about 10 seconds. The temperature range described above is chosen such that the thermal drive-in operation does not adversely affect the existing structure and features of device 10, and is also sufficient to allow the dipole elements to migrate (or diffuse) from dipole layer 302 to the gate dielectric layer 246 beneath it. In some embodiments, dipole elements (e.g., La and O) diffuse into gate dielectric layer 246 while maintaining their stoichiometry as in dipole layer 302 (e.g., [La]:[O] of La₂O₃ is 2:3). In other words, the stoichiometry of the dipole elements in gate dielectric layer 246 (e.g., the ratio of the increase in La atom concentration to the increase in O atom concentration) is substantially the same as that in dipole layer 302. In some other embodiments, dipole elements diffuse into gate dielectric layer 246 but do not maintain the same stoichiometry. Therefore, the ratio of dipole elements within gate dielectric layer 246 (e.g., the ratio of the increase in La atom concentration to the increase in O atom concentration) may differ from the ratio of dipole elements in dipole layer 302. As will be described in detail later, the chemical properties, amount (or concentration), and distribution of the dipole element can be further adjusted to achieve the desired threshold voltage.

[0035] The thermal drive-in operation of process 402 causes a portion of the dipole material of layer 302 to diffuse into the gate dielectric portions 246B and 246D in a specific manner. As a result, gate dielectric portions 246B and 246D each include a specific dipole material composition 2002. Therefore, it can be said that gate dielectric portions 246B and 246D include a diffusion characteristic (or simply diffusion characteristic 2002) of the dipole material composition 2002. As will be discussed in more detail below, the configuration of the dipole material composition 2002 in terms of the chemical properties, concentration, and / or distribution of the dipole material (or dipole element, without maintaining stoichiometry) differs from the dipole material composition in other gate dielectric portions. This provides tunability for threshold voltages that are independent of each other and may differ from each other for the individual transistors. Although in Figure 8 Not explicitly shown, in some embodiments, the thermal drive-in operation of process 402 is configured to form a hybrid layer at the boundary between the remaining portion of dipole layer 302 and modified gate dielectric portions 246B and 246D (e.g., modified with dipole material composition 2002). For example, the hybrid layer is formed on the modified gate dielectric portions 246B and 246D, each modified gate dielectric portion including the dipole material of dipole layer 302, the concentration of which is from about 40% to about 60%. In other words, the hybrid layer includes the properties of both gate dielectric layer 246 and dipole layer 302 (e.g., etch resistance). In some embodiments, the concentration of dipole material in each hybrid layer is greater than the concentration of dipole material in gate dielectric portions 246B and 246D. On the other hand, gate dielectric portions 246A and 246C do not include such a hybrid layer.

[0036] As described above, a significant portion of the dipole layer 302 was not driven into the gate dielectric portions 246B and 246D at the end of the thermal drive-in operation of process 402, and thus remained on the surfaces of the gate dielectric portions 246B and 246D (e.g., on the surface of the mixed layer on the surfaces of the gate dielectric portions 246B and 246D). Still referring to... Figure 1 Block 1040 and reference Figure 8Process 402 continues by removing the remaining portions of the dipole layer 302 in an etching operation, thereby exposing the surfaces of the modified gate dielectric portions 246B and 246D (or doped gate dielectric portions 246B and 246D). In some embodiments, the exposed surfaces of the modified gate dielectric portions 246B and 246D each comprise a dipole material of the dipole layer 302 at a concentration of less than about 40% to about 60%. The etching operation of process 402 may include one or more etching processes (or stripping processes), which may be dry etching processes, wet etching processes, reactive ion etching processes, or other etching processes, and have high etch selectivity for the dipole layer 302 (relative to the gate dielectric layer 246). In some embodiments, the etching operation of process 402 is a wet etching operation. It is worth noting that the removal of the remaining portion of dipole layer 302 frees up the limited space within gate trench 241, allowing additional gate layers to be formed within gate trench 241, such as another dipole layer (e.g., dipole layer 304 described later), another gate dielectric layer (e.g., gate dielectric layer 246' described later), or other gate or auxiliary layers that are needed for or beneficial to the normal or improved function of the transistor. Therefore, embodiments implementing the etching operation of process 402 provide improved devices compared to methods that do not implement such a process.

[0037] Following process 402, gate dielectric portions 246A-246D each have thicknesses d2A-d2D. As described above, since the etching operation is configured to have etching selectivity for the dipole layer 302 (relative to the gate dielectric layer 246 (or the unmodified gate dielectric portions 246A and 246C)), thicknesses d2A and d2C are approximately the same as thicknesses d1A and d1C. However, due to the presence of a large amount of dipole material, the etching operation may cause the mixed layer on the modified gate dielectric portions 246B and 246D to be recessed. Therefore, after the etching operation, the thicknesses d2B and d2D of gate dielectric portions 246B and 246D are reduced compared to thicknesses d1B and d1D, and compared to thicknesses d2A and d2C, respectively. As will be described in detail later, the reduction in the thickness of gate dielectric portions 246B and 246D reduces the channel resistance R of transistors 100B and 100D, respectively. ch Furthermore, as described later, the amount of mixed layer removed can be tuned by adjusting the etching parameters of the etching operation in process 402, thereby tuning the remaining thicknesses d2B and d2D, and consequently tuning the channel resistance R. ch .

[0038] Following process 402, gate dielectric portions 246A and 246C, as well as gate dielectric portions 246B and 246D, are exposed in gate trench 241. Furthermore, gate dielectric portions 246B and 246D may be thinner than gate dielectric portions 246A and 246C. In other words, the surfaces of the gate dielectric portions in different substrate regions are uneven (or stepped). Additionally, gate dielectric portions 246B and 246D now have a different composition than gate dielectric portions 246A and 246C because they include dipole material component 2002, while gate dielectric portions 246A and 246C do not. As described above, this difference alone (e.g., the presence or absence of dipole material component 2002) causes transistors 100B / 100D to have a different threshold voltage than transistors 100A / 100C, even if other aspects of the transistors are the same.

[0039] refer to Figure 1 Box 1050 and reference Figure 9The method continues to form another dipole layer in the gate dielectric layer in regions configured for certain transistors. For example, another dipole layer 304 is formed over a subset of gate dielectric portions 246A-246D. In some embodiments, dipole layer 304 may similarly comprise an n-type dipole material (e.g., GeO2, Y2O3, La2O3, SrO, other suitable n-type dipole materials or combinations thereof) or a precursor of an n-type dipole material, a p-type dipole material (e.g., Al2O3, Ga2O3, MgO, HfO2, TiO2, ZrO2, ZnO, other suitable p-type dipole materials or combinations thereof) or a precursor of a p-type dipole material. In some embodiments, dipole layer 304 comprises the same dipole material as dipole layer 302. Having dipole layers 302 and 304 with the same dipole material simplifies processing and reduces costs. Alternatively, in some embodiments, dipole layer 304 may comprise a different dipole material than dipole layer 302. Having dipole layers 302 and 304 with different dipole materials provides opportunities for further tuning of the threshold voltage of the individual transistors and potentially improves functionality. In some embodiments, dipole layer 304 may be deposited to a generally uniform thickness, ranging from about 0.5 angstroms to about 10 angstroms in various embodiments, for example from about 3 angstroms to about 5 angstroms. If the thickness is too small (e.g., less than 0.5 angstroms), dipole layer 304 may be too weak for Vt tuning in some cases. If the thickness is too large (e.g., greater than 10 angstroms), dipole layer 304 may be too strong for Vt tuning and may have side effects, such as reduced mobility in channel layer 120. In some embodiments, a thicker dipole layer 304 results in a larger variation in the threshold voltage of the transistor. In some embodiments, the thickness of dipole layer 304 may be less than the thickness of dipole layer 302. For example, in some embodiments, dipole layer 302 may have a thickness t1 and dipole layer 304 may have a thickness t2. The difference between the thicknesses (t1-t2) can be from about 0.1 angstroms to about 2 angstroms, for example, from about 0.3 angstroms to about 1 angstrom. In some embodiments, this thickness difference provides greater freedom in adjusting the amount of dipole material subsequently diffused from the dipole layer 304 into the gate dielectric portions 246C and 246D. If the difference is too small, the final dipole material composition between the gate dielectric portions 246C / 246D and the gate dielectric portions 246A / 246B may not be sufficiently different. If the difference is too large, the additional material may not bring about a significant difference in diffusion behavior. Alternatively, in some embodiments, the thickness t1 is smaller than the thickness t2 to meet certain specific design needs (e.g., creating a specific threshold voltage cascade).

[0040] As described above, the dipole layer 304 is formed only on a subset of the gate dielectric portions 246A-246D (in other words, only for a subset of transistors 100A-100D). In some embodiments, the dipole layer 304 is first formed on all transistors 100A-100D and then removed from certain transistor regions, such as the regions configured for transistors 100A and 100B. Therefore, the dipole layer 304 remains only on the gate dielectric portions 246C and 246D, and not on the gate dielectric portions 246A and 246B. The removal process may change the thickness of some gate dielectric portions. Therefore, at this stage of the process, the gate dielectric portions may each have their own thicknesses d3A-d3D. In some embodiments, thicknesses d3A and d3B may be similar to thicknesses d2A and d2B (due to good etch selectivity); while thicknesses d3C and d3D may be approximately the same as thicknesses d2C and d2D. In the depicted embodiment, the dipole layer 304 directly intersects with the gate dielectric portion 246C without forming the dipole material component 2002 therein. Furthermore, the dipole layer 304 also directly intersects with the gate dielectric portion 246D, where the dipole material component 2002 is formed. In other words, when the dipole layer 304 comprises a material different from that of the dipole layer 302, the top surface of the gate dielectric portion 246D can include two different dipole materials.

[0041] refer to Figure 1 Box 1060 and reference Figure 10 Then, another process 404 is performed. In some embodiments, process 404 includes a thermal drive-in operation. The thermal drive-in operation of process 404 can be similar to the above-described process. Figure 8The thermal drive-in operation of process 402 is described. In some embodiments, the thermal drive-in operation of process 404 may implement the same or different parameters as the thermal drive-in operation of process 402. In some embodiments, the thermal drive-in operation may be implemented at a lower temperature than the thermal drive-in operation of process 402. For example, the thermal drive-in operation of process 402 may achieve a homogenization temperature T1, and the thermal drive-in operation of process 404 may achieve a homogenization temperature T2. The difference between the homogenization temperatures (T1-T2) may be about 50°C to about 250°C, for example, about 100°C to about 200°C. Using a higher annealing temperature during process 402 and a lower annealing temperature during process 404 allows for better control of the diffusion behavior of the dipole material, and thus provides more precise control over the distribution of the dipole material in the respective gate dielectric portions. As a result, better tuning of the threshold voltage is achieved. If the temperature difference (T1-T2) is too small, this benefit may be lost; while if the difference is too large, either diffusion in the thermal drive-in operation becomes difficult to control or diffusion in the thermal drive-in operation becomes insufficient. In some alternative embodiments, temperature T2 may be higher than temperature T1. For example, in some embodiments, implementing a higher temperature T2 may facilitate a greater amount of dipole material driven into dipole layer 304 than into dipole material driven into dipole layer 302 and / or a wider distribution than that of dipole layer 302. In some embodiments, this greater amount and / or wider distribution may be advantageous for achieving a specific threshold voltage configuration. Furthermore, in some embodiments, the duration of the thermal drive-in operation of process 404 may be implemented to be greater or less than the duration of the thermal drive-in operation of process 402, such that the dipole material of dipole layer 304 may migrate deeper or shallower into gate dielectric portions 246C and / or 246D compared to those dipole materials of dipole layer 302 entering gate dielectric portions 246B and / or 246D. In some embodiments, the thermal drive-in operation of process 404 is configured to drive the dipole material of dipole layer 304 deeper into the corresponding gate dielectric (compared to the thermal drive-in operation of dipole material composition 2002 at this stage of process 402), despite the use of a lower annealing temperature and / or in the case of a thinner dipole layer (compared to dipole layer 302). In some embodiments, the thermal drive-in operation of process 402 may have a duration τ1; the thermal drive-in operation of process 404 may have a duration τ2. In some embodiments, the duration τ2 may be greater than the duration τ1. For example, the difference (τ2-τ1) may be from about 1 second to about 30 minutes, for example from about 30 seconds to about 10 minutes. If the time difference is too small, the dipole material of dipole layer 304 may not reach the desired depth; if the time difference is too large, the dipole material may diffuse too deep to reach channel layer 120, thereby adversely affecting device performance.

[0042] The thermal drive-in operation of process 404 has two main effects. The first effect is that the dipole material composition 2002 (see [reference]) already present in the gate dielectric portions 246B and 246D is optimized. Figure 12 The dipole material further migrates deeper into the channel layer 120, allowing the dipole material composition to be distributed closer to the channel layer 120. A second effect is the diffusion of the dipole material from the dipole layer 304 into the gate dielectric portions 246C and 246D. As a result, both gate dielectric portions 246C and 246D include a specific dipole material composition 2004. The dipole material composition 2004 can differ from the dipole material composition 2002 in its chemical properties or concentration configuration. For example, dipole material composition 2002 may include La₂O₃, while dipole material composition 2004 may include Y₂O₃. Alternatively or additionally, dipole material compositions 2002 and 2004 may include corresponding dipole materials of different concentrations (the same or different from each other). These parameters can be adjusted to adjust the threshold voltage differences between transistors.

[0043] In the gate dielectric portion 246D, the dipole material composition 2002 (see...) Figure 8 As the dipole material diffuses further from the dipole layer 304, it is modified to form a dipole material composition 2042 (or diffusion feature 2042). Dipole material composition 2042 can resemble a combination of dipole material compositions 2002 and 2004. When the materials of dipole layers 302 and 304 are different, dipole material composition 2042 comprises a mixture of the materials in the gate dielectric portion 246D. When the materials of dipole layers 302 and 304 are the same, dipole material compositions 2002, 2004, and 2042 each comprise the same dipole material, although at different concentrations and with different distribution profiles. Dipole material composition 2042 can include a highest concentration of dipole material, which can resemble the sum of the concentrations in dipole material compositions 2002 and 2004. Furthermore, in some embodiments, the dipole material component 2002 may be distributed more deeply than the dipole material component 2004 (because it has undergone two thermal drive-in operations, compared to one for the dipole material component 2004); while the dipole material component 2042 may have a wider distribution than both dipole material components 2002 and 2004.

[0044] Still referencing Figure 1 Box 1060 and reference Figure 10 After the thermal drive-in operation is completed, the remaining portion of the dipole layer 304 on the gate dielectric layer is selectively removed during the etching operation of process 404, similar to the etching operation of process 402 described above. Therefore, the valuable space of the gate trench 241 is not occupied by the dipole layer 304. Similar to the above... Figure 8As described, the thermal drive-in operation of process 404 can be configured to create a mixed layer between the remaining portion of dipole layer 304 and gate dielectric portions 246C and 246D, which is absent in gate dielectric portions 246A and 246B. Therefore, the etching operation can be configured to have good etch selectivity for dipole layer 304 (relative to gate dielectric layer 246). However, the presence of the mixed layer allows the etching operation to recess the top surfaces of gate dielectric portions 246C and 246D. This reduces the thickness and channel resistance of the respective gate dielectric portions in transistors 100C and 100D. For example, after the etching operation of process 404, gate dielectric portions 246A-246D can each have thicknesses d4A-d4D. Due to etch selectivity, thicknesses d4A and d4B can be approximately the same as thicknesses d3A and d3B; while due to the removal of the mixed layer, thicknesses d4C and d4D can be less than thicknesses d3C and d3D, respectively. In some embodiments, thickness d4C can be configured to be less than thickness d4B. This allows for a decreasing trend in thickness from gate dielectric portions 246A, 246B, 246C to 246D. Consequently, as described later, the channel resistance also exhibits a decreasing trend. This can be beneficial for applications where continuous resistance adjustment is important. The relative magnitude of thickness d4C to thickness d4B can be controlled by controlling parameters of process 404 compared to process 402. For example, the thermal drive-in operation of process 404 can be configured to be performed at a higher temperature than that of process 402 or for a longer duration than that of process 402. Therefore, the mixed layer formed on gate dielectric portion 246C can be thicker than the mixed layer formed on gate dielectric portion 246B. As a result, in the etching operation of process 404, the thicker portion of gate dielectric portion 246C (compared to that portion of gate dielectric portion 246B in the etching operation of process 402). In some embodiments, thickness d4B can be less than thickness d4C. This configuration provides a sawtooth trend in the channel resistance of adjacent transistors 100A-100D and can help control the total resistance offset to keep it within a certain threshold.

[0045] In this process stage, gate dielectric portions 246A-246D are each configured differently from one another. For example, gate dielectric portion 246A does not include a dipole material; gate dielectric portion 246B includes dipole material composition 2002; gate dielectric portion 246C includes dipole material composition 2004; and gate dielectric portion 246D includes dipole material composition 2042 (or a combination of dipole materials 2002 and 2004). The dipole material compositions 2002, 2004, and 2042 differ from one another in terms of chemical properties, concentration, and / or distribution within their respective gate dielectric portions. Because each of these parameters affects the threshold voltage of the transistor thus formed, transistors 100A-100D incorporating these gate dielectric portions can provide different threshold voltages, even if they include the same gate electrode layer. Furthermore, thickness d4A can be approximately similar to thickness d1A and can be greater than thicknesses d4B-d4D; thickness d4D can be less than thicknesses d4B and d4C.

[0046] In some embodiments, reference Figure 1 Box 1070 and reference Figure 11 Process 406 is performed to further adjust the position and / or distribution of the dipole material within the gate dielectric portions 246A-246D. In some embodiments, process 406 includes a thermal operation (or annealing operation). For example, device 10 is annealed in an environment of O2, N2, or a mixture of O2 and N2 at a temperature of about 600°C to about 1000°C (e.g., about 700°C to about 800°C). In another embodiment, process 406 is a furnace tube annealing process performed in an environment of O2, N2, or a mixture of O2 and N2 at a temperature ranging from about 300°C to about 600°C for about 1 second to about 30 minutes. In yet another embodiment, process 406 is a spike annealing process. In still another embodiment, process 406 is a laser annealing process or a microwave annealing process performed in an environment of O2, N2, NH3, H2, or a mixture thereof at a temperature ranging from about 800°C to about 1200°C for about 1 millisecond to about 10 seconds. In some embodiments, process 406 is configured to cause the dipole material to migrate further into the channel layer 120. This can improve the effectiveness of threshold voltage tuning, as described later. In some embodiments, process 406 can be configured to randomize and normalize the dipole material within the gate dielectric portion to achieve a normalized distribution (as opposed to a tailing distribution), thereby improving control over the threshold voltage. In some embodiments, although not specifically described, process 406 is performed instead between processes 402 and 404. In some embodiments, although not specifically described, process 406 is performed both between processes 402 and 404 and after process 404. In some embodiments, process 406 is omitted.

[0047] In some embodiments, an additional dipole layer is formed over a subset of the gate dielectric portion, and additional thermal drive-in and etching operations are performed to form a transistor with an additionally different threshold voltage. In some embodiments, such an additional dipole layer is omitted. In some embodiments (see reference) Figure 1 (Branch A), Method 1000 continues to form gate electrode layer 248 ( Figure 1 The frame 1080 is constructed and the gate structure 250 is fabricated. However, in some other embodiments, reference is made to... Figure 1 The "B" branch and reference Figure 12 In some embodiments, another gate dielectric layer 246' is formed over the gate dielectric layer 246. The gate dielectric layer 246' may be similar to the gate dielectric layer 246 described above. In some embodiments, the gate dielectric layer 246' may include the same or different materials as the gate dielectric layer 246 and undergo the same or different processes. For example, different portions of the gate dielectric layer 246' may be configured to include different dipole material compositions. In the depicted embodiments, the gate dielectric layer 246' is configured in the same way as the gate dielectric layer 246. For example, the gate dielectric layer 246' of transistor portion 200A may not include a dipole material; the gate dielectric layer 246' of transistor portion 200B may include a dipole material composition 2002', which may be similar to the above description. Figure 10 The described dipole material composition 2002; the gate dielectric layer 246' of the transistor portion 200C may include a dipole material 2004', which may be similar to the above description regarding Figure 10 The described dipole material 2004; the gate dielectric layer 246' of the transistor portion 200D may include a dipole material 2042', which may be similar to the above description regarding Figure 10 The described dipole material 2042. Therefore, in relation to already discussed... Figures 7-10 Following processes similar to those described above, the processed gate dielectric layer 246' can be used in conjunction with the processes described above. Figure 10 The processed gate dielectric layer 246 described is similar or identical. In other words, the processed gate dielectric layers 246 and 246' can be considered as sublayers of a thicker gate dielectric structure. Additional gate dielectric layers can be further formed, and Figure 1 The processing cycles of boxes 1020-1070 can be repeated until the desired total thickness of the gate dielectric layer is achieved.

[0048] In some embodiments, forming the gate dielectric structure using a layer-by-layer approach allows for thinner layers (e.g., layers 246 and 246') to achieve better processability. Furthermore, this approach allows for better tuning of the distribution and profile of the dipole material within the gate dielectric structure, thereby improving the tunability and reliability of the threshold voltage. For example, the threshold voltage can be progressively adjusted to provide better control precision. Alternatively, the gate dielectric layer 246' may comprise a different material and / or employ a different dipole material configuration than the gate dielectric layer 246. In such embodiments, more substrate regions with different dipole configurations can be provided, offering greater opportunities to create multi-Vt products. In some embodiments, an additional gate dielectric layer may be formed on top of the gate dielectric layer 246' and in a manner similar to that described above. Figures 7-11 The process is described in a specific way.

[0049] refer to Figure 1 The frame is 1080 and referenced. Figure 12 Method 1000 forms a gate electrode layer 248 over one or more treated gate dielectric layers. The gate electrode layer 248 is formed on the top surface of the gate dielectric layer 246' (or an additional gate dielectric layer formed thereon). Return to Reference Figure 2B and Figure 2CA gate electrode layer 248 surrounds a gate dielectric layer 246 above each channel layer 120. In various embodiments, the gate electrode layer 248 may completely or partially fill the gate trench 241. The combination of the gate electrode layer 248 and the gate dielectric layer is designed to provide a suitable threshold voltage for various NMOS and PMOS transistors. In some embodiments, the gate electrode layer 248 of the NMOS transistors 100A-100D comprises any suitable n-type work function metal material, such as titanium nitride (TiN), ruthenium (Ru), iridium (Ir), osmium (Os), rhodium (Rh), or combinations thereof. The gate electrode layer 248 of the PMOS transistors 100A'-100D' comprises any suitable p-type work function metal material, such as titanium (Ti), aluminum (Al), tantalum (Ta), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbide nitride (TaCN), silicon tantalum nitride (TaSiN), or combinations thereof. Although not explicitly shown, the gate electrode layer 248 of the NMOS and / or PMOS transistors may also include a filler metal layer. The filler metal layer may include any suitable material, such as aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), nickel (Ni), platinum (Pt), ruthenium (Ru), or combinations thereof. The conductive metal layer fills the remaining space of the gate trench 241. In some embodiments, a chemical mechanical polishing operation is performed to expose the top surface of the ILD layer 230. Therefore, the gate dielectric layer 246 and the gate electrode layer 248 together form a high-k metal gate stack in place of the original dummy gate stack 240. The high-k metal gate stack, together with the gate spacer layers 201 and 202, forms a new gate structure 250. The gate structure 250 is coupled with a plurality of channel layers 120 to form a plurality of gate channels. Reference Figure 1 Following frame 1090, method 1000 continues to complete the fabrication of the device. For example, silicide features, contact features, via features, metal lines, passivation layers, etc., can be formed.

[0050] In this embodiment, the differences in the threshold voltages of the transistors can be fully tuned by the dipole material doping discussed above, allowing the common gate electrode layer 248 to be used for all NMOS transistors (e.g., transistors 100A-100D) or all PMOS transistors (e.g., transistors 100A'-100D'). This avoids the need to use different work function metal layers (or different gate electrode layers) to achieve a wide variety of threshold voltages. Therefore, embodiments of this disclosure enable the use of thinner (compared to other methods) (one or more) work function metal layers for device 10 and are suitable for miniaturized multi-gate devices, such as nanosheet-based devices. Note that the gate electrode layer 248 may include multiple sublayers, but it remains a common layer for multiple transistors (e.g., transistors 100A-100D or transistors 100A'-100D'). In some embodiments, transistors 100A-100D (or transistors 100A'-100D') may each include different gate electrode layers to provide a further (or greater) threshold voltage tuning amplitude. In some embodiments, this disclosure may also be implemented such that transistors of different conductivity types (e.g., NMOS and PMOS) can use the same gate electrode layer.

[0051] The embodiments provided above allow for effective tuning of the threshold voltage. Figure 13A graph illustrating the Vt tuning capability according to an embodiment of the method is shown. In this embodiment, the transistors in the device (e.g., device 10) have four different threshold voltages. In this example, by doping dipole material component 2002 in transistor 100B, the threshold voltage is adjusted by -40 mV compared to transistor 100A without any dipole material. By doping dipole material component 2004 in transistor 100C, the threshold voltage is adjusted by -76 mV compared to transistor 100A. Furthermore, by doping dipole material component 2042 in transistor 100D, the threshold voltage is adjusted by -114 mV compared to transistor 100A. Moreover, these tuning capabilities match well with target threshold voltage values ​​of -40 mV, -80 mV, and -120 mV, respectively. In other words, multi-Vt devices can be reliably implemented with tuning capabilities up to -120 mV by simply tuning the presence and / or configuration (e.g., chemical properties, concentration, and distribution) of the dipole material component in the gate dielectric layer. Furthermore, the NMOS device formed in this manner exhibits a reduced channel resistance loss of approximately +0.03 kΩ per fin (compared to +0.1 kΩ per fin using some other methods). Meanwhile, the channel resistance loss of the PMOS device formed in this manner is negligible (compared to +0.2 to +0.3 kΩ per fin using some other methods). In other words, this method provides good Vt linearity, comparable leakage current (Igi), and low channel resistance loss compared to other methods. Therefore, device improvements are achieved through the method described herein.

[0052] The embodiments of this disclosure can be adapted to provide a wider threshold voltage tuning capability without significantly increasing processing complexity. For example, Figure 14 A flowchart of an alternative embodiment of the method (method 2000) of this disclosure for manufacturing device 20 is provided. Figure 15 Plan views of embodiments of devices (e.g., device 20) of the present disclosure are provided according to some embodiments of the present disclosure. Figures 16-21 Provided according to Figure 14 The flowchart shows a cross-sectional view of device 20 at different process stages. Method 2000 enables the fabrication of device 20 having six (6) NMOS transistors with different threshold voltages and another six (6) PMOS transistors with different threshold voltages. This is in Figure 15 As shown, device 20 is generally similar to Figure 1 Device 10, except that it comprises six NMOS transistors 100A-100F and six PMOS transistors 100A'-100F'. Note that for simplicity and clarity, the reference numerals are repeated in the following description.

[0053] refer to Figure 14The box 2020, method 2000 begins by receiving a workpiece on which various transistors are formed, each transistor having a stack of dummy gates (similar to the above regarding...). Figure 2B and Figure 2C The described dummy gate stack 240 is bonded to a channel layer. Method 2000 continues to remove the dummy gate stack 240 to form a gate trench 241, similar to... Figure 4 . refer to Figure 14 The box 2030 and reference Figure 16 A gate dielectric layer 246 is formed in the gate trench 241 surrounding each channel layer 120, similar to the above. Figure 5 The described gate dielectric layer. Furthermore, refer to... Figure 14 Box 2040 and reference Figure 16 A dipole layer is formed on each gate dielectric portion 246A-246F. For example... Figure 16 As shown, the dipole layers are configured differently in different regions 100A-100F. For example, no dipole layers are formed on gate dielectric portions 246A and 246B; gate dielectric portions 246C and 246D have dipole layers 304 thereon; and gate dielectric portions 246E and 246F have dipole layers 302 and 304 thereon. Therefore, at this stage of the process, the surfaces of transistor portions 100A-100F have uneven surfaces. In other words, the material layer surrounding gate dielectric portions 246E-246F in transistor portions 200E-200F is thicker than the material layer surrounding gate dielectric portions 246C-246D in transistor portions 200C-200D, and the material layer surrounding gate dielectric portions 246C-246D in transistor portions 200C-200D is thicker than the material layer surrounding dielectric portions 246A-246B in transistor portions 200A-200B. Dipole layer 302 may be similar to the dipole layer 302 described above, for example, comprising the same material and having the same thickness. Dipole layer 304 may comprise the same or different material as dipole layer 302. Furthermore, dipole layers 302 and 304 may be conformal and have thicknesses adjusted based on the desired threshold voltage of the transistor, as described above. In the depicted embodiment, dipole layer 304 has a greater thickness than dipole layer 302 in order to provide a higher concentration of dipole material in the gate dielectric portion at the junction with the dipole layers, as described in detail below.

[0054] Any suitable method can be used to achieve this. Figure 16The configuration of dipole layers 302 and 304 is shown. For example, dipole layer 302 may first be formed blanket-like and / or conformally on all device regions 100A-100F, and then partially removed (e.g., patterned) such that the dipole layer only covers device regions 100A, 100B, 100E, and 100F. In other words, the surfaces of gate dielectric portions 246C and 246D in transistor portions 200C and 200D are exposed in gate trench 241. Dipole layer 304 is then formed on all exposed surfaces (including, for example, on the surface (or around) of dipole layer 302 on gate dielectric portions 246A-246B and 246E-246F, and on the surface (or around) of gate dielectric portions 246C and 246D). Therefore, dipole layer 304 is spaced apart from the gate dielectric layer 246 in transistor portions 200A, 200B, 200E, and 200F, but directly contacts the gate dielectric layer 246 in transistor portions 200C and 200D. Dipole layers 302 and 304 in device regions 100A-100B are then removed, while dipole layers in device regions 100C-100F are retained, for example, by covering device regions 100C-100F with mask elements, thus exposing device regions 100A and 100B. Alternatively, any other suitable method may be used.

[0055] refer to Figure 14 The box 2050 and reference Figure 17 Process 502 is then performed. Process 502 can be similar to the above-mentioned processes. Figure 8Process 402 is described. For example, process 502 includes a thermal drive-in operation that causes the dipole material of dipole layer 302 and dipole material of dipole layer 304 to diffuse into the corresponding gate dielectric portion below them. This thermal drive-in operation can be similar to the thermal drive-in operation of process 402. For example, parameters of the thermal drive-in operation of process 502 can be adjusted to tune the amount of dipole material of dipole layer 302 and / or dipole material of dipole layer 304 to be driven into gate dielectric layer 246. Parameters may include annealing temperature and duration. These parameters (along with the chemical properties of the dipole materials of dipole layers 302 and 304) and the thicknesses of dipole layers 302 and 304 are configured to provide an appropriate dipole material composition within the corresponding gate dielectric portion, similar to the dipole material composition already discussed for device 10. In some embodiments, because dipole layer 302 directly intersects with gate dielectric portions 246E and 246F, while dipole layer 304 is spaced apart from gate dielectric portions 246E and 246F, a larger portion of dipole layer 302 (compared to dipole layer 304) diffuses into gate dielectric portions 246E and 246F. Furthermore, because there is more dipole material on gate dielectric portions 246E and 246F than on gate dielectric portions 246C and 246D (e.g., both dipole layers 302 and 304), a larger total amount (including dipole material from dipole layers 302 and 304) diffuses into gate dielectric portions 246E and 246F (compared to the amount entering gate dielectric portions 246C and 246D).

[0056] After the thermal drive-in operation, gate dielectric portions 246A and 246B do not contain any dipole material. Gate dielectric portions 246C and 246D include dipole material from dipole layer 304 but not from dipole layer 302. This combination of dipole materials is referred to as dipole material composition 2040. Gate dielectric portions 246E and 246F include dipole material from dipole layer 304 and dipole material from dipole layer 302. This combination of dipole materials is referred to as dipole material 2042. When dipole layers 302 and 304 comprise different materials, dipole material composition 2040 may be a single dipole material composition, while dipole material 2042 comprises a mixture. When dipole layers 302 and 304 comprise the same material, dipole material composition 2040 and dipole material composition 2042 may comprise the same material, although at different concentrations. Similar to the above regarding... Figure 8 As described, at the end of the thermal drive-in operation of process 502, a portion of dipole layer 302 and a portion of dipole layer 304 remain on the surface of gate dielectric layer 246. Subsequently, still referring to... Figure 14 The remaining portions of frame 2050 are removed during the etching operation of process 502, similar to the above regarding... Figure 8The etching operation of process 402 is described.

[0057] Therefore, at this stage of the process, the portions of the gate dielectric layer 246 in different substrate regions comprise different dipole material compositions. This difference alone enables device 20 to provide three (3) different threshold voltages for each transistor type. Furthermore, similar to process 402, the thermal drive-in operation of process 502 similarly creates a mixed layer at the interface between the gate dielectric layer and dipole layers 302 and / or 304. In some embodiments, this mixed layer is recessed or removed during the etching operation of process 502, similar to the case in the etching operation of process 402. As a result, the thickness of the individual gate dielectric portions can be reduced. For example, after process 502, gate dielectric portions 246A-246F each have corresponding thicknesses d3A-d3F. Due to the etch selectivity implemented during the etching operation of process 502, thicknesses d3A and d3B can be compared with thicknesses d2A and d2B (compare). Figure 16 The thicknesses are roughly the same. However, since the mixing layer is removed, the thicknesses d3C-d3F can each be smaller than the thicknesses d2C-d2F.

[0058] refer to Figure 14 Box 2060 and reference Figure 18 Another dipole layer 306 is formed on gate dielectric portions 246A-246F. In the depicted embodiments, dipole layer 306 is formed on gate dielectric portions 246B, 246D, and 246F, but not on gate dielectric portions 246A, 246C, and 246E. Dipole layer 306 may be similar to dipole layers 302 and / or 304. For example, dipole layer 306 may comprise a material similar to or different from the material of dipole layers 302 and / or 304. In some embodiments, the thickness of dipole layer 306 is less than the thickness of dipole layer 304, which in turn is less than the thickness of dipole layer 302, for reasons similar to those described above. Figure 8 Those discussed. Any suitable method can be used to achieve this. Figure 18 The configuration provided in [the document / reference]. For example, the dipole layer 306 can be conformally formed across all device regions 100A-100F, and formed in [the configuration / reference] such as [the configuration / reference]. Figure 17 The modified gate dielectric layer 246 is seen on the surface. Subsequently, for example by performing a patterning operation, the dipole layer 306 is removed from the surface portions of the gate dielectric portions 246A, 246C, and 246E. The bottom surface of the remaining dipole layer 306 may intersect with gate dielectric portions having different dipole material compositions. For example, the dipole layer 306 directly intersects with the gate dielectric portion 246B that does not contain a dipole material; the dipole layer 306 directly intersects with the gate dielectric portion 246D that includes dipole material composition 2040; and the dipole layer 306 directly intersects with the gate dielectric portion 246F that includes dipole material composition 2042.

[0059] refer to Figure 14 Box 2070 and reference Figure 19 Then, another process 504 is performed. In some embodiments, process 504 includes a heat-drive operation similar to that of process 404. In some embodiments, the heat-drive operation may be implemented with parameters that are the same as or different from those of the heat-drive operation of process 502. In some embodiments, the heat-drive operation of process 504 may achieve a lower temperature than the heat-drive operation of process 502. For example, the heat-drive operation of process 502 may achieve a soaking temperature T1, and the heat-drive operation of process 504 may achieve a soaking temperature T2. The difference between the soaking temperatures (T1-T2) may be about 50°C to about 250°C, for example, about 100°C to about 200°C. Using a higher annealing temperature during process 502 and a lower annealing temperature during process 504 allows for better control of the diffusion behavior of the dipole material and subsequently provides more precise control over the distribution of the dipole material in the respective gate dielectric portions. Therefore, better tuning of the threshold voltage is obtained. If the temperature difference (T1-T2) is too small, this benefit may be lost; while if the difference is too large, either the diffusion in the heat-driven operation becomes difficult to control or the diffusion in the heat-driven operation becomes insufficient.

[0060] Furthermore, in some embodiments, the duration of the thermal drive-in operation of process 504 may be greater than or less than the duration of the thermal drive-in operation of process 502, such that the dipole material of dipole layer 306 may migrate deeper or shallower into gate dielectric portions 246B, 246D, and / or 246F compared to those dipole materials that enter gate dielectric portions 246C and / or 246E during the thermal drive-in operation of process 502 (see [link to documentation]). Figure 17 In some embodiments, the thermal drive-in operation of process 502 may have a duration τ1; the thermal drive-in operation of process 504 may have a duration τ2. In some embodiments, the duration τ2 may be greater than the duration τ1. For example, the difference (τ2-τ1) may be about 1 second to about 30 minutes, for example, about 30 seconds to about 10 minutes. In some embodiments, the thermal drive-in operation of process 504 is configured to drive the dipole material of dipole layer 306 deeper (compared to the thermal drive-in operation of process 502) into the corresponding gate dielectric portion, despite the use of a lower annealing temperature and / or on a thinner dipole layer (compared to dipole layer 302). If the time difference is too small, the dipole material of dipole layer 304 may not reach the desired depth; if the time difference is too large, the dipole material may diffuse too deep to reach channel layer 120, thereby adversely affecting device performance.

[0061] Regardless, because the dipole material components 2040 and 2042 in the gate dielectric portions 246C and 246E undergo two thermal drive-in operations, they can migrate to a deeper region of the overall gate dielectric portion and closer to the channel layer 120. Other parameters of the thermal drive-in operation of process 504 can be further adjusted based on the desired tuning range of the threshold voltage. When the thermal drive-in operation of process 504 is completed, gate dielectric portion 246A does not include dipole material; gate dielectric portion 246B includes material from dipole layer 306 but not material from dipole layers 302 or 304. This dipole material component is referred to as dipole material component 2600. Gate dielectric portion 246C is unaffected by the formation of dipole layer 306 or the thermal drive-in operation of process 504, thus maintaining the dipole material component 2040 as described above. Gate dielectric portion 246D includes dipole material composition 2040 prior to the formation of dipole layer 306 and the thermal drive-in operation of process 504, and further receives diffusion of material from dipole layer 306. Therefore, gate dielectric portion 246D includes material from the original dipole layer 304 and material from dipole layer 306. This composition is referred to as dipole material composition 2640. Gate dielectric portion 246E is unaffected by the formation of dipole layer 306 or the thermal drive-in operation of process 504, such that it retains the dipole material composition 2042 as described above. Gate dielectric portion 246F includes dipole material composition 2042 prior to the formation of dipole layer 306 and the thermal drive-in operation of process 504, and further receives diffusion of material from dipole layer 306. Therefore, gate dielectric portion 246F includes material from the original dipole layers 302 and 304 and material from dipole layer 306. This composition is referred to as dipole material composition 2642.

[0062] Still referencing Figure 14 Box 2070 and reference Figure 19 After the thermal drive-in operation is completed, another etching operation is performed, similar to the etching operations of processes 404 and / or 502. The etching operation of process 504 not only removes the additional dipole material above the gate dielectric layer, but also causes the thickness of the gate dielectric portions 246A-246F to vary within themselves. For example, after the etching operation of process 504, the gate dielectric portions 246A-246F may each have thicknesses d4A-d4F. In some embodiments, thicknesses d4A, d4C, and d4E remain approximately the same as thicknesses d3A, d3C, and d3E, respectively; although thicknesses d4B, d4D, and d4F may be smaller than thicknesses d3B, d3D, and d3F, respectively. As mentioned above, this may be due to the formation of a mixed layer at the interface between the gate dielectric layer 246 and the dipole layer 306 in the relevant substrate region. Also as mentioned above, this reduction in the layer thickness of the gate dielectric portions reduces the channel resistance R. ch.

[0063] In some embodiments, dipole layers 302, 304, and 306 differ from each other in terms of chemical properties and / or layer thickness. Furthermore, as described above, the parameters of the thermal drive-in operation of processes 502 and 504 can differ from each other. Therefore, dipole materials 2600, 2040, 2640, 2042, and 2642 differ from each other in terms of chemical properties, concentration, and / or distribution within various portions of the gate dielectric layer 246. As a result, when combined with the gate electrode layer, these portions each provide a unique threshold voltage that differs from each other and further from the threshold voltage of transistor 100A (excluding such dipole materials), regardless of whether the gate electrode layers are the same or different.

[0064] refer to Figure 14 The frame 2080 and reference Figure 20 Process 506 is performed to further adjust the position and / or distribution of the dipole material within the gate dielectric portions 246A-246F. In some embodiments, process 506 includes a thermal operation (or annealing operation). For example, device 20 is annealed in an environment of O2, N2, or a mixture of O2 and N2 at a temperature of about 600°C to about 1000°C (e.g., about 700°C to about 800°C). In another embodiment, process 506 is a furnace tube annealing process performed in an environment of O2, N2, or a mixture of O2 and N2 at a temperature ranging from about 300°C to about 600°C for about 1 second to about 30 minutes. In yet another embodiment, process 506 is a spike annealing process. In still another embodiment, process 506 is a laser annealing process or a microwave annealing process performed in an environment of O2, N2, NH3, H2, or a mixture thereof at a temperature ranging from about 800°C to about 1200°C for about 1 millisecond to about 10 seconds. In some embodiments, process 506 is configured to cause further migration of the dipole material into channel layer 120. This can improve the effectiveness of threshold voltage tuning, as described later. In some embodiments, process 506 can be configured to randomize and normalize the dipole material within the gate dielectric portion to achieve a normalized distribution (as opposed to a tailing distribution), thereby improving control over the threshold voltage. In some embodiments, although not specifically described, process 506 is performed instead between processes 502 and 504. In some embodiments, although not specifically described, process 506 is performed both between processes 502 and 504 and after process 504. In some embodiments, process 506 is omitted.

[0065] In some embodiments, an additional dipole layer is formed over a subset of the gate dielectric portion, and additional thermal drive-in and etching operations are performed to form a transistor with an additionally different threshold voltage. In some embodiments, such an additional dipole layer is omitted. Reference Figure 14In branch "A", in some embodiments, method 2000 proceeds to block 2090 to form the gate electrode layer. In other embodiments, refer to... Figure 14 Branch "B", method 2000 returns to block 2030 to repeat the formation of another gate dielectric layer 246'. In such an embodiment, refer to Figure 21 An additional gate dielectric layer 246' can be formed on the top surface of the gate dielectric layer 246, similar to that described above with respect to device 10. Furthermore, refer to... Figure 14 Box 2090 and reference Figure 21 A gate electrode layer 248 is formed on the top surface of a gate dielectric layer 246' (or an additional gate dielectric layer formed thereon). In some embodiments, the portions of the gate electrode layer 248 that intersect with the gate dielectric portions 246A-246F are identical, for example, having the same material composition.

[0066] refer to Figure 14 Following frame 2100, method 2000 continues to complete the fabrication of the device. For example, silicide features, contact features, via features, metal lines, passivation layers, etc., can be formed.

[0067] Figure 22 A graph illustrating the Vt tuning capability according to an embodiment of the method is shown. In this embodiment, the transistors in the device (e.g., device 20) have six different threshold voltages. In this example, by doping transistor 100B with dipole material 2600, the threshold voltage is adjusted by -48 mV compared to transistor 100A without any dipole material. By doping transistor 100C with dipole material component 2040, the threshold voltage is adjusted by -88 mV compared to transistor 100A. Furthermore, by doping transistor 100D with dipole material component 2640, the threshold voltage is adjusted by -121 mV compared to transistor 100A; by adding dipole material component 2042 to transistor 100E, the threshold voltage is adjusted by -174 mV compared to transistor 100A; and by doping transistor 100F with dipole material component 2642, the threshold voltage is adjusted by -214 mV compared to transistor 100A. Furthermore, these tuning capabilities are matched to target values ​​of -40mV, -80mV, -120mV, -160mV, and -200mV, respectively. In other words, multi-Vt devices can be reliably realized with tuning capabilities up to -200mV by simply tuning the presence and / or configuration (e.g., chemical properties, concentration, and / or distribution) of the dipole material in the gate dielectric layer. Moreover, by implementing this disclosure, the channel resistance R of the PMOS transistor... chBy implementing the method disclosed herein, the voltage drop per fin is reduced from approximately +0.2 kΩ to approximately 0.3 kΩ to approximately +0.1 kΩ, compared to the method not implemented herein. This method offers good Vt linearity, comparable leakage current, and reduced channel resistance losses compared to some other methods, all of which contribute to device improvements.

[0068] Figures 23A-23C More details are provided regarding the diffusion and distribution of the dipole material as a result of thermally driven operations of 402A and 404A or 502A and 504. Figure 23A This is a schematic diagram showing the distribution of the dipole material in the gate dielectric layer 246. Line 702 depicts the boundary between the gate dielectric layer 246 and the junction layer 242; line 708 represents the boundary between the junction layer 242 and the channel layer 120; line 710 depicts the top surface of the gate dielectric layer 246 (which is also the boundary between the gate dielectric layer and the subsequently formed gate electrode layer 248); line 704 represents the center line 704 (or half-thickness line 704) of the gate dielectric layer 246; and region 706 depicts a region with a thickness of approximately 1 nm to approximately 2 nm centered on junction 702. In some embodiments, the dipole material has different distributions in different transistors. For example, as... Figure 23A As shown, the dipole material of transistor 100D has a wider distribution profile than that of the dipole material of transistor 100E. Specifically, the amount of dipole material distributed near the top surface 710 of the gate dielectric portion 246D can be greater than that in the case of the gate dielectric portion 246E; and the amount of dipole material distributed in region 706 of the gate dielectric portion 246D can be less than that in the case of the gate dielectric portion 246E. Figure 23B The figure illustrates an example distribution of the dipole material as a function of its position within the gate dielectric layer 246, the boundary layer 242, and other adjacent layers. Figure 23B It may have been simplified or conceptualized. Figure 23B The vertical axis represents the measured dose of the dipole material. In some embodiments, these thermally driven-in operations are designed to allow some dipole material to migrate through the gate dielectric layer 246 and reach the junction layer 242. Furthermore, although not explicitly described, in some embodiments, some dipole material may further diffuse into the junction layer 242. For example, at least a portion of the dipole material is distributed in region 706. In some embodiments, bringing the dipole material closer to the channel layer 120 allows for greater threshold voltage tuning capability, even without increasing the dipole moment. However, bringing the dipole material too close to the channel layer may adversely affect other device characteristics. In some embodiments, the dipole material within a narrow region 706 has the maximum tuning efficiency to the threshold voltage. In other words, the threshold voltage is more sensitive to the dipole material within region 706 than to the dipole material outside region 706. Reference Figure 23CFor the HfO2 gate dielectric layer doped with La2O3 disclosed herein, the threshold voltage (ΔV) fb The linear fit between the variation curve of lanthanum and hafnium and the ratio of lanthanum to hafnium at the boundary 702 provides the coefficient determination value (R). 2 The threshold voltage is approximately 0.98. Therefore, the threshold voltage responds not only to the chemical properties and concentration of the dipole material, but also to the physical position of the dipole material relative to the interface 702. This relationship enables additional tuning capability. Note that this disclosure further provides a control over ΔV compared to other methods not implemented herein. f Stricter controls. For example, with Figure 23C Curves similar to those not implementing the methods described here provide R. 2 Less than 0.95.

[0069] refer to Figures 23A-23C And refer to Figure 24 As described above, the parameters of dipole layers 302, 304, and 306, as well as the parameters of the thermally driven operations 502A and 504A, can be adjusted to control the position and distribution of the diffused dipole material. In some embodiments, the materials of dipole layers 302, 304, and 306 are identical to each other. Therefore, dipole materials 2600, 2040, 2640, 2042, and 2642 are also identical, although in different amounts. In some embodiments, it is desirable to configure adjacent transistors with alternating (rather than continuously increasing or decreasing) dipole material concentrations. For example, refer to... Figure 24 It may be necessary to configure the concentration (or dosage) of the dipole material to increase in the order of gate dielectric portions 246A < 246C < 246B < 246E < 246D < 246F. In some embodiments, this configuration maximizes processing efficiency and control precision. On the other hand, it may be necessary to configure the threshold voltages of adjacent transistors to vary continuously (rather than alternately). In some embodiments, this allows for easier adjustment and selection of the threshold voltage during operation. In other words, it may be necessary to configure the threshold voltage tuning capability to increase in the order of gate dielectric portions 246A < 246B < 246C < 246D < 246E < 246F. In some embodiments, this can be achieved by configuring the distribution of the dipole material in gate dielectric portions 246B, 246D, and 246F differently than the distribution in gate dielectric portions 246C and 246E. For example, see specific references. Figure 23BThe distribution of dipole material within gate dielectric portions 246C and 246E is configured to reach a peak (e.g., have the highest concentration) at or near the boundary line 702 (see peak values ​​of curves 246C / 246E relative to line 702). In some embodiments, the distribution of dipole material within gate dielectric portions 246C and 246E is configured to reach a peak within region 706. On the other hand, the distribution of dipole material within gate dielectric portions 246B, 246D, and 246F is configured to have a peak at or near the center line 704 (or half-thickness line 704) of the gate dielectric layer 246. Furthermore, the distribution of dipole material within gate dielectric portions 246A-246F is configured to have an increasing concentration at the boundary line 702 in the order 246A < 246B < 246C < 246D < 246E < 246F. Therefore, since the threshold voltage is most sensitive to the dipole material in the region 706 surrounding the boundary 702, the threshold voltage tuning capability is configured sequentially, even though the total concentration of the dipole material is configured in an alternating manner. In some embodiments, the above-mentioned dipole material distribution is achieved by using a smaller layer thickness for the dipole layer 306 than for the dipole layer 304 (the dipole layer 304 has a smaller layer thickness than the dipole layer 302), making the annealing temperature (T2) of the heat-driven operation 504A lower than that of the heat-driven operation 502A (T1), or making the annealing duration (t2) of the heat-driven operation 504A longer than that of the heat-driven operation 502A (t2), as described above. In some embodiments (not depicted), the concentration of the dipole material in the gate dielectric portion 246D is less than the concentration of the dipole material in the gate dielectric portion 246E.

[0070] As described above, due to the presence of the hybrid layer, etching processes 402B, 404B, 502B and / or 504B remove a portion of the relevant gate dielectric portion. Figure 25A The figure illustrates that after etching operation 504B (which removes the remainder of the dipole layer 306 and the mixed layer on these gate dielectric portions 246B, 246D, and 246F), the thickness of the gate dielectric portions is significantly reduced compared to other methods that do not implement the methods of this disclosure. For example, the thickness of both gate dielectric portions 246C and 246E is reduced by about 1 angstrom to about 2 angstroms compared to other methods. This reduction in the thickness of the gate dielectric portions results in a decrease in the channel resistance R. ch The reduction. (Reference) Figure 25B Compared to other methods, embodiments of this disclosure provide reduced R... ch For example, this reduction in channel resistance of an NMOS transistor can be from approximately 0.1 kΩ to approximately 0.3 kΩ per fin. Furthermore, the reduced gate dielectric portion allows for a larger processing window and easier fabrication.

[0071] In some embodiments, the etching parameters (e.g., etching temperature, etching solution concentration, etching time, other suitable wet etching parameters, or combinations thereof) of various etching operations (402B, 404B, 502B and / or 504B) can be adjusted to provide different thinning rates for the respective gate dielectric portions. Figure 26A and Figure 26B The figure illustrates the effect of etching duration on etching operation 504B. In the depicted example, etching condition 1 is performed for an etching duration of 105 s; while etching condition 2 is performed for an etching duration of 210 s. As shown, etching condition 2 results in a further reduction in the La dose. Furthermore, compared to etching condition 1, the channel resistance of the transistor with etching condition 2 is further reduced by approximately 0.03 kΩ per fin to approximately 1.0 kΩ per fin, for example, approximately 0.05 kΩ per fin to approximately 0.08 kΩ per fin.

[0072] While not intended to be limiting, one or more embodiments of this disclosure provide numerous benefits for semiconductor devices and their fabrication. For example, this disclosure provides a method for designing transistors with threshold voltage tuning capability using dipole materials, in some cases without requiring an additional gate electrode layer (or work function metal layer). The threshold voltage tuning range reaches approximately 180 mV to approximately 220 mV. This represents an improvement of approximately 100 mV to approximately 150 mV compared to other methods. Furthermore, since any additional dipole material is removed after a thermal drive-in operation, no additional volume or space is required compared to other methods. In other words, this can be referred to as a “volume-free” method. In some embodiments, by using the methods provided herein, the need for patterning (one or more) work function metal layers is eliminated, making it highly suitable for nanoscale transistors and enabling continuous scaling down. Compared to methods that use work function metal when tuning the threshold voltage (in which case the metal is typically retained in the finished device), R ch Losses are mitigated. Furthermore, in some embodiments, the high threshold voltage tuning capability of the devices 10 or 20 presented herein allows for the fabrication of PMOS transistors with ultra-low threshold voltages, such as those conventionally available only for silicon-germanium (SiGe) channel layers. Therefore, in some embodiments, this disclosure can be implemented in PMOS devices without a SiGe channel layer (e.g., with only a Si channel layer). In some embodiments, the formation of a SiGe channel layer requires more complex device processing. Therefore, this disclosure makes it easier and more cost-effective to fabricate devices with similar threshold voltage tuning capabilities. In other embodiments, the invention can be implemented with a SiGe channel layer to provide even stronger threshold voltage tuning capability. Furthermore, this embodiment can be readily integrated into existing CMOS manufacturing processes.

[0073] Methods 1000 and 2000 are merely examples and are not intended to limit this disclosure to the content explicitly illustrated. For example, while the above disclosure describes a dielectric layer 246 formed as part of a gate replacement process, in some alternative embodiments, the gate dielectric layer 246 may be formed at an earlier process stage, such as before the formation of a dummy gate stack. Additional steps may be provided before, during, or after method 1000 or 2000, and some of the described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein.

[0074] In one example aspect, this disclosure relates to a method. The method includes: forming a dielectric layer on a semiconductor workpiece, forming a first patterned layer of a first dipole material on the dielectric layer, and performing a first thermal drive-in operation at a first temperature to form a diffusion feature in a first portion of the dielectric layer located below the first patterned layer. The method further includes: forming a second patterned layer of a second dipole material, wherein a first segment of the second patterned layer is over the diffusion feature and a second segment of the second patterned layer is offset from the diffusion feature. The method further includes: performing a second thermal drive-in operation at a second temperature, wherein the second temperature is lower than the first temperature. The method further includes: forming a gate electrode layer on the dielectric layer.

[0075] In some embodiments, a first thermal drive-in operation is performed for a first duration, a second thermal drive-in operation is performed for a second duration, and the first duration is less than the second duration. In some embodiments, a first patterned layer has a first thickness, a second patterned layer has a second thickness, and the first thickness is greater than the second thickness. In some embodiments, performing the first thermal drive-in operation includes configuring the first thermal drive-in operation to form a first hybrid layer at the interface between a dielectric layer and the first patterned layer. In some embodiments, the method further includes removing the remaining portion of the first patterned layer and the first hybrid layer after performing the first thermal drive-in operation. In some embodiments, performing the second thermal drive operation includes configuring the second thermal drive operation to form a second hybrid layer at the interface between a first segment of the second patterned layer and the dielectric layer, and to form a third hybrid layer at the interface between a second segment of the second patterned layer and the dielectric layer. The method further includes removing the remaining portion of the second patterned layer, the second hybrid layer, and the third hybrid layer after performing the second thermal drive-in operation. In some embodiments, the dielectric layer is a first dielectric layer, and the method further includes: after performing a second thermal drive-in operation, forming a second dielectric layer on the first dielectric layer, forming a third patterned dipole layer on the second dielectric layer, and performing a third thermal drive-in operation. In some embodiments, forming the first patterned layer includes: forming a patterned sublayer that covers a first region of the dielectric layer and exposes a second region of the dielectric layer; forming another sublayer on the patterned sublayer in the first region and on the dielectric layer in the second region, the other sublayer being adjacent to the dielectric layer in the second region; and jointly patterning the patterned sublayer and the other sublayer to expose a subset of the dielectric layer in the first region, thereby forming the first patterned layer. In some embodiments, the semiconductor workpiece includes a plurality of channel layers stacked vertically on a semiconductor substrate, and a dielectric layer is formed around these channel layers.

[0076] In one example aspect, this disclosure relates to a method. The method includes: forming a dielectric layer on a semiconductor workpiece; forming a first patterned layer of a first dipole material on the dielectric layer; performing a first thermal drive-in operation to drive a subset of the first dipole material into the dielectric layer; and performing a first etching operation to remove the remaining portion of the first dipole material. The method further includes: forming a second patterned layer of a second dipole material on the dielectric layer, wherein a first portion of the second patterned layer is disposed on a first portion of the dielectric layer without the first dipole material, and a second portion of the second patterned layer is disposed on a second portion of the dielectric layer having the first dipole material. The method further includes: performing a second thermal drive-in operation for a second duration, wherein the second temperature is lower than the first temperature. The method further includes: performing a second etching operation to remove the remaining portion of the first dipole material, wherein performing the first etching operation includes: recessing a mixed region of the dielectric layer including the first dipole material.

[0077] In some embodiments, the method further includes: forming a gate electrode layer on a dielectric layer, wherein the gate electrode layer and the dielectric layer surround a plurality of channel layers. In some embodiments, performing a second etching operation includes: recessing a mixed region of the dielectric layer comprising a second dipole material. In some embodiments, performing a second etching operation includes: recessing a mixed region comprising both a first dipole material and a second dipole material of the dielectric layer. In some embodiments, performing a first thermal drive-in operation includes performing it at a first temperature, performing a second thermal drive-in operation includes performing it at a second temperature, and the first temperature is greater than the second temperature. In some embodiments, the difference between the first temperature and the second temperature is about 100°C to about 200°C.

[0078] In one example aspect, this disclosure relates to a semiconductor device. The semiconductor device includes a semiconductor substrate, a first transistor on the semiconductor substrate, and a second transistor on the semiconductor substrate. The first transistor includes: a first channel, a first junction layer, a first gate dielectric layer on the first channel, and a first gate electrode layer on the first gate dielectric layer and bordering the first gate dielectric layer. The second transistor includes: a second channel, a second junction layer, a second gate dielectric layer on the second channel, and a second gate electrode layer on the second gate dielectric layer and bordering the second gate dielectric layer. The first gate electrode layer and the second gate electrode layer have the same composition. The first gate dielectric layer includes a first dipole material component, which has a maximum concentration at half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material component, which has a maximum concentration at the junction between the second gate dielectric layer and the second junction layer.

[0079] In some embodiments, the dipole material includes one of germanium oxide (GeO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium oxide (SrO), magnesium oxide (MgO), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), and aluminum oxide (Al2O3). In some embodiments, the second dipole material composition includes a first dipole material composition and a third dipole material composition. In some embodiments, the first channel is one of a plurality of first channels of the first transistor, and the second channel is one of a plurality of second channels of the second transistor. In some embodiments, the semiconductor device further includes a third transistor having a third gate dielectric layer. The third gate dielectric layer does not contain the first dipole material composition and does not contain the second dipole material composition.

[0080] Below are some specific examples.

[0081] Example 1. A method for fabricating a semiconductor device, comprising:

[0082] Forming a dielectric layer on a semiconductor workpiece;

[0083] A first patterned layer of a first dipole material is formed on the dielectric layer;

[0084] A first thermal drive-in operation is performed at a first temperature to form a diffusion feature in a first portion of the dielectric layer located below the first patterned layer;

[0085] A second patterned layer of a second dipole material is formed, wherein a first segment of the second patterned layer is located on the diffusion feature, and a second segment of the second patterned layer is offset from the diffusion feature;

[0086] A second thermal drive operation is performed at a second temperature, wherein the second temperature is lower than the first temperature; and

[0087] A gate electrode layer is formed on the dielectric layer.

[0088] Example 2. The method as described in Example 1, wherein the first heat drive-in operation is performed for a first duration, the second heat drive-in operation is performed for a second duration, and the first duration is less than the second duration.

[0089] Example 3. The method as described in Example 1, wherein the first patterned layer has a first thickness, the second patterned layer has a second thickness, and the first thickness is greater than the second thickness.

[0090] Example 4. The method as described in Example 1, wherein performing the first thermal drive-in operation includes: configuring the first thermal drive-in operation to form a first hybrid layer at the interface between the dielectric layer and the first patterned layer.

[0091] Example 5. The method as described in Example 4 further includes: after performing the first thermal drive-in operation, removing the remaining portion of the first patterned layer and the first hybrid layer.

[0092] Example 6. The method as described in Example 1, wherein performing the second heat-drive-in operation comprises: configuring the second heat-drive-in operation to form a second hybrid layer at the interface between the first segment of the second patterned layer and the dielectric layer, and to form a third hybrid layer at the interface between the second segment of the second patterned layer and the dielectric layer, and

[0093] The method further includes: after performing the second thermal drive-in operation, removing the remaining portion of the second patterned layer, the second mixing layer, and the third mixing layer.

[0094] Example 7. The method as described in Example 1, wherein the dielectric layer is a first dielectric layer, the method further comprising:

[0095] After performing the second thermal drive-in operation, a second dielectric layer is formed on the first dielectric layer;

[0096] A third patterned dipole layer is formed on the second dielectric layer; and

[0097] Perform the third hot drive operation.

[0098] Example 8. The method as described in Example 1, wherein the formation of the first patterned layer includes:

[0099] A patterned sublayer is formed, which covers a first region of the dielectric layer while exposing a second region of the dielectric layer;

[0100] Another sublayer is formed on the patterned sublayer in the first region and on the dielectric layer in the second region, the other sublayer intersecting with the dielectric layer in the second region; and

[0101] The patterned sublayer and the other sublayer are patterned together to expose the dielectric layer in a subset of the first region, thereby forming the first patterned layer.

[0102] Example 9. The method as described in Example 1, wherein the semiconductor workpiece includes a plurality of channel layers stacked on a semiconductor substrate in a vertical direction, and wherein the dielectric layer is formed around these channel layers.

[0103] Example 10. A method for fabricating a semiconductor device, comprising:

[0104] Forming a dielectric layer on a semiconductor workpiece;

[0105] A first patterned layer of a first dipole material is formed on the dielectric layer;

[0106] Perform a first thermal drive-in operation for a first duration to drive a subset of the first dipole material into the dielectric layer;

[0107] Perform a first etching operation to remove the remaining portion of the first dipole material;

[0108] A second patterned layer of a second dipole material is formed on the dielectric layer, a first portion of the second patterned layer is disposed on a first portion of the dielectric layer that does not contain the first dipole material, and a second portion of the second patterned layer is disposed on a second portion of the dielectric layer that contains the first dipole material.

[0109] The second thermal drive operation is performed for a second duration, wherein the second duration is greater than the first duration; and

[0110] A second etching operation is performed to remove the remaining portion of the first dipole material.

[0111] The first etching operation includes: recessing the mixed region of the dielectric layer, which includes the first dipole material.

[0112] Example 11. The method according to Example 10 further includes: forming a gate electrode layer on the dielectric layer, wherein the gate electrode layer and the dielectric layer surround a plurality of channel layers.

[0113] Example 12. The method according to Example 10, wherein performing the second etching operation includes: recessing the mixed region of the dielectric layer comprising the second dipole material.

[0114] Example 13. The method according to Example 10, wherein performing the second etching operation includes: recessing a mixed region of the dielectric layer comprising both the first dipole material and the second dipole material.

[0115] Example 14. The method as described in Example 10, wherein performing the first heat drive-in operation includes performing it at a first temperature, and performing the second heat drive-in operation includes performing it at a second temperature, and wherein the first temperature is greater than the second temperature.

[0116] Example 15. The method according to Example 14, wherein the difference between the first temperature and the second temperature is about 100°C to about 200°C.

[0117] Example 16. A semiconductor device comprising:

[0118] Semiconductor substrate;

[0119] The first transistor on the semiconductor substrate, the first transistor having: a first channel, a first junction layer, a first gate dielectric layer on the first channel, and a first gate electrode layer on the first gate dielectric layer and junction therewith; and

[0120] The second transistor on the semiconductor substrate has: a second channel, a second junction layer, a second gate dielectric layer on the second channel, and a second gate electrode layer on the second gate dielectric layer and junction therewith.

[0121] The first gate electrode layer and the second gate electrode layer have the same composition.

[0122] The first gate dielectric layer includes a first dipole material component, which has the highest concentration at half-thickness line of the first gate dielectric layer.

[0123] The second gate dielectric layer includes a second dipole material component, which has the highest concentration at the interface between the second gate dielectric layer and the second junction layer.

[0124] Example 17. The semiconductor device according to Example 16, wherein the dipole material comprises one of germanium oxide (GeO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium oxide (SrO), magnesium oxide (MgO), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), and aluminum oxide (Al2O3).

[0125] Example 18. The semiconductor device according to Example 16, wherein the second dipole material composition includes the first dipole material composition and the third dipole material composition.

[0126] Example 19. A semiconductor device as described in Example 16, wherein the first channel is one of a first plurality of channels of the first transistor, and the second channel is one of a second plurality of channels of the second transistor.

[0127] Example 20. The semiconductor device of Example 16 further includes a third transistor having a third gate dielectric layer, wherein the third gate dielectric layer does not contain the first dipole material component and does not contain the second dipole material component.

[0128] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for fabricating a semiconductor device, comprising: Forming a dielectric layer on a semiconductor workpiece; A first patterned layer of a first dipole material is formed on the dielectric layer; A first thermal drive-in operation is performed at a first temperature to form a diffusion feature in a first portion of the dielectric layer located below the first patterned layer; A second patterned layer of a second dipole material is formed, wherein a first segment of the second patterned layer is located on the diffusion feature, and a second segment of the second patterned layer is offset from the diffusion feature; A second thermal drive operation is performed at a second temperature, wherein the second temperature is lower than the first temperature; and A gate electrode layer is formed on the dielectric layer.

2. The method as described in claim 1, wherein, The first heat drive-in operation is performed for a first duration, the second heat drive-in operation is performed for a second duration, and the first duration is less than the second duration.

3. The method as described in claim 1, wherein, The first patterned layer has a first thickness, the second patterned layer has a second thickness, and the first thickness is greater than the second thickness.

4. The method of claim 1, wherein, Performing the first thermal drive-in operation includes: configuring the first thermal drive-in operation to form a first hybrid layer at the interface between the dielectric layer and the first patterned layer.

5. The method of claim 4, wherein, The method further includes removing the remaining portion of the first patterned layer and the first hybrid layer after performing the first heat-drive operation, which forms the remaining portion of the first patterned layer.

6. The method of claim 1, wherein, Performing the second thermal drive-in operation includes: configuring the second thermal drive-in operation to form a second hybrid layer at the interface between the first segment of the second patterned layer and the dielectric layer, and to form a third hybrid layer at the interface between the second segment of the second patterned layer and the dielectric layer. The second thermal drive operation forms the remaining portion of the second patterned layer, and The method further includes: after performing the second thermal drive-in operation, removing the remaining portion of the second patterned layer, the second mixing layer, and the third mixing layer.

7. The method of claim 1, wherein, The dielectric layer is a first dielectric layer, and the method further includes: After performing the second thermal drive-in operation, a second dielectric layer is formed on the first dielectric layer; A third patterned dipole layer is formed on the second dielectric layer; and Perform the third hot drive operation.

8. The method of claim 1, wherein, The formation of the first patterned layer includes: A patterned sublayer is formed, which covers a first region of the dielectric layer while exposing a second region of the dielectric layer; Another sublayer is formed on the patterned sublayer in the first region and on the dielectric layer in the second region, the other sublayer intersecting with the dielectric layer in the second region; and The patterned sublayer and the other sublayer are patterned together to expose the dielectric layer in a subset of the first region, thereby forming the first patterned layer.

9. The method of claim 1, wherein, The semiconductor workpiece includes a plurality of channel layers stacked on a semiconductor substrate in a vertical direction, wherein the dielectric layer is formed around these channel layers.

10. A method for fabricating a semiconductor device, comprising: Forming a dielectric layer on a semiconductor workpiece; A first patterned layer of a first dipole material is formed on the dielectric layer; A first thermal drive-in operation is performed for a first duration to drive a subset of the first dipole material into the dielectric layer, thereby forming the remaining portion of the first dipole material and a first mixed region of the dielectric layer including the first dipole material. Perform a first etching operation to remove the remaining portion of the first dipole material; A second patterned layer of a second dipole material is formed on the dielectric layer, a first portion of the second patterned layer is disposed on a first portion of the dielectric layer that does not contain the first dipole material, and a second portion of the second patterned layer is disposed on a second portion of the dielectric layer that contains the first dipole material. A second thermal drive operation is performed for a second duration, thereby forming the remaining portion of the second dipole material, wherein the second duration is greater than the first duration; and A second etching operation is performed to remove the remaining portion of the second dipole material. The first etching operation includes: recessing the first mixed region of the dielectric layer, which includes the first dipole material.

11. The method of claim 10, further comprising: A gate electrode layer is formed on the dielectric layer, wherein the gate electrode layer and the dielectric layer surround a plurality of channel layers.

12. The method according to claim 10, wherein, Performing the second thermal drive-in operation forms a second hybrid region of the dielectric layer, including the second dipole material, and The second etching operation includes: recessing the second mixed region of the dielectric layer, which includes the second dipole material.

13. The method of claim 10, wherein, Performing the first heat drive-in operation includes performing it at a first temperature, and performing the second heat drive-in operation includes performing it at a second temperature, wherein the first temperature is greater than the second temperature.

14. The method according to claim 13, wherein, The difference between the first temperature and the second temperature is approximately 100°C to approximately 200°C.

15. A semiconductor device, comprising: Semiconductor substrate; The first transistor on the semiconductor substrate has: a first channel, a first junction layer, a first gate dielectric layer on the first channel, and a first gate electrode layer on the first gate dielectric layer and junction with the first gate dielectric layer. as well as The second transistor on the semiconductor substrate has: a second channel, a second junction layer, a second gate dielectric layer on the second channel, and a second gate electrode layer on the second gate dielectric layer and junction therewith. The first gate electrode layer and the second gate electrode layer have the same composition. The first gate dielectric layer includes a first dipole material component, which has the highest concentration at half-thickness line of the first gate dielectric layer. The second gate dielectric layer includes a second dipole material component, which has the highest concentration at the interface between the second gate dielectric layer and the second junction layer.

16. The semiconductor device according to claim 15, wherein, The first dipole material and the second dipole material each include one of germanium oxide (GeO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), strontium oxide (SrO), magnesium oxide (MgO), hafnium oxide (HfO2), zirconium oxide (ZrO2), titanium oxide (TiO2), and aluminum oxide (Al2O3).

17. The semiconductor device according to claim 15, wherein, The second dipole material composition includes the first dipole material composition and the third dipole material composition.

18. The semiconductor device of claim 15, wherein, The first channel is one of a first plurality of channels of the first transistor, and the second channel is one of a second plurality of channels of the second transistor.

19. The semiconductor device of claim 15, further comprising a third transistor having a third gate dielectric layer, wherein, The third gate dielectric layer contains neither the first dipole material nor the second dipole material.

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