CMOS devices and their manufacturing methods

Abstract

This invention provides a CMOS device and its manufacturing method, applicable to the field of semiconductor technology. In the manufacturing method of the CMOS device provided by this invention, unlike existing technologies that require widening the reserved boundary region (NP) to avoid double etching between the NMOS and PMOS regions, the manufacturing method of this invention allows the reserved boundary region (NP) to have a certain width of double etch, i.e., forming the opening. Then, by filling with a second protective layer, the opening caused by the double etch during the formation of the source / drain regions is filled in. This avoids the increased difficulty of subsequent processes caused by the double etch opening, while reducing the width of the existing reserved boundary region (NP) and avoiding the problem of the large width of the existing reserved boundary region (NP) adversely affecting subsequent CMOS processes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a CMOS device and its manufacturing method. Background Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have spawned several generations of ICs, each with smaller and more complex circuits than the previous generation. In the development of ICs, as geometric dimensions (e.g., using the smallest components or lines that manufacturing processes can produce) shrink, functional density (e.g., the number of interconnected devices per chip area) typically increases. Size reduction processes generally offer benefits by increasing production efficiency and reducing associated costs.

[0003] Such size reduction also increases the complexity of processing and manufacturing integrated circuits, and it is understandable that these advancements require similar developments in integrated circuit processing and manufacturing. For example, planar transistors have been replaced by three-dimensional fin-like field-effect transistors (FinFETs). In FinFETs, with the continuous development of integrated circuit manufacturing technology, the requirements for chip integration density are constantly increasing. In chips fabricated using CMOS process platforms, the source / drain of the device is grown epitaxially, which requires opening trenches to form the source / drain of NMOS and PMOS regions respectively. However, with the development of process technology, the number of transistors per unit area is increasing, and the process window at the boundary between NMOS (N) and PMOS (P) formed on the fin structure semiconductor substrate is becoming smaller and smaller. Coupled with the influence of photolithography OVL, CD, and other factors, the process window left at the NP junction is also becoming smaller and smaller. Therefore, when forming the source / drain trenches of NMOS and PMOS respectively, double etch is likely to occur at the NP boundary, which in turn causes a groove to appear on the top of the polysilicon gate at the NP boundary, thus exposing the gate polysilicon and causing device failure.

[0004] To address this issue, existing technologies control the source / drain trenches (CD) of NMOS and PMOS to reserve a portion of the area at the NP boundary to avoid double etching of the gate polysilicon. However, this reserved area often adversely affects subsequent processes; for example, during EPI deposition of the source / drain trenches, it can cause a significant increase in film thickness in the reserved area at the NP boundary. Summary of the Invention

[0005] The purpose of this invention is to provide a CMOS device and its manufacturing method to increase the process window of the NP boundary between NMOS and PMOS transistors in the CMOS device (reducing the width of the NP boundary), thereby ensuring the device performance of the CMOS device.

[0006] In a first aspect, to solve the above-mentioned technical problems, the present invention provides a method for manufacturing a CMOS device, comprising at least the following steps:

[0007] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a PMOS region, an NMOS region and a reserved boundary region located between the PMOS region and the NMOS region, a plurality of discrete fin structures and gate structures spanning the plurality of fin structures and surrounding the sidewalls and top surface of the fin structures are respectively formed on the semiconductor substrate of the PMOS region and the NMOS region, the gate structure including a gate dielectric layer, a gate material layer and a gate isolation layer stacked sequentially;

[0008] Step S2: Etch the semiconductor substrate and form the source and drain regions in the fin structures located on both sides of the gate structure in the PMOS and NMOS regions, respectively, and at the same time form an opening on the reserved boundary region that exposes at least part of the gate isolation layer at the bottom.

[0009] Step S3: Sequentially deposit a first protective layer and a second protective layer on the semiconductor substrate, wherein the first protective layer at least fills the source region and the drain region, and the second protective layer at least fills the opening;

[0010] Step S4: Remove the first protective layer.

[0011] Furthermore, the gate isolation layer can be a single-layer film structure or a double-layer film structure, and the material of the gate isolation layer can include silicon nitride or silicon oxide.

[0012] Furthermore, the material of the first protective layer is different from the materials of the gate material layer, the gate isolation layer, and the gate dielectric layer. The material of the first protective layer can be spin-coated organic carbon, photoresist, or anti-reflective coating material.

[0013] Furthermore, the material of the second protective layer can be a low-temperature oxide.

[0014] Furthermore, step S2, which involves forming source and drain regions in the fin structures located on both sides of the gate structure in the PMOS and NMOS regions respectively, and simultaneously forming an opening on the reserved boundary region that exposes at least a portion of the gate isolation layer at its bottom, may include:

[0015] A first patterned photoresist is formed to mask the NMOS region and expose the PMOS region and the reserved boundary region. Using the first patterned photoresist as a mask, a portion of the fin structure on both sides of the gate structure in the PMOS region and the reserved boundary region is etched away to form a first trench in the PMOS region for forming the source and / or drain, and at the same time, a first opening is formed on the reserved boundary region.

[0016] Remove the first patterned photoresist and form a second patterned photoresist to mask the PMOS region and expose the NMOS region and the reserved boundary region. Using the second patterned photoresist as a mask, etch away a portion of the fin structure on both sides of the gate structure in the NMOS region and the reserved boundary region to form a second trench in the NMOS region for forming the source and / or drain. At the same time, continue etching along the bottom of the first opening to deepen the depth of the first opening.

[0017] Remove the second patterned photoresist and use the deepened first opening as the opening.

[0018] Furthermore, after forming the gate structures of the PMOS region and the NMOS region in step S1, sidewalls can also be formed on the sidewalls of the gate structures.

[0019] Furthermore, after removing the first protective layer in step S4, the manufacturing method provided by the present invention may further include:

[0020] Using the sidewall and the gate structure as masks, epitaxial material layers are deposited in the first trench and the second trench to form the source and drain.

[0021] Furthermore, the material of the epitaxial material layer may include germanium silicide or silicon phosphide.

[0022] Furthermore, in step S3, the second protective layer can not only fill the opening, but also simultaneously cover the top surface of the gate structure and the surface of the first protective layer.

[0023] Secondly, based on the same inventive concept as the manufacturing method of the CMOS device, the present invention also provides a CMOS device, which can be specifically fabricated using the CMOS device manufacturing method described above.

[0024] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0025] In the CMOS device manufacturing method provided by this invention, unlike the prior art, it is not necessary to widen the reserved boundary region (NP) to avoid double etch in the reserved boundary region (NP) located between the NMOS region and the PMOS region. The manufacturing method provided by this invention allows the reserved boundary region (NP) to have a certain width of double etch, i.e., forming the opening. Then, by filling the second protective layer, the opening caused by the double etch of the reserved boundary region (NP) during the formation of the source / drain region is filled in. This avoids the opening caused by double etch increasing the difficulty of subsequent processes, while reducing the width of the existing reserved boundary region (NP) and avoiding the problem that the large width of the existing reserved boundary region (NP) has an adverse effect on subsequent CMOS processes.

[0026] Furthermore, since the present invention reduces the width of the reserved boundary region (NP) between the NMOS region and the PMOS region, the CMOS device formed using the manufacturing method provided by the present invention is more in line with the development trend of modern miniaturized and integrated circuits. Attached Figure Description

[0027] Figure 1 This is a schematic flowchart of a method for manufacturing a CMOS device according to an embodiment of the present invention;

[0028] Figures 2a to 2g This is a schematic diagram of the fabrication process of a CMOS device according to an embodiment of the present invention.

[0029] The reference numerals in the attached figures are as follows:

[0030] 100 - Semiconductor substrate; 110 - Fin structure;

[0031] N-NMOS region; P-PMOS region;

[0032] NP - Reserved boundary region; 251 - Gate structure;

[0033] 120 - Gate dielectric layer; 130 - Gate material layer;

[0034] 140 - Gate isolation layer; 141 - Silicon nitride film layer;

[0035] 142 - Silica film layer; 150 - Sidewall / Sidewall material layer;

[0036] 160 - First patterned photoresist; 102 - Opening;

[0037] 170 - Second patterned photoresist; 101 - First opening;

[0038] 180 - First protective layer; 102 - First opening after deepening;

[0039] 190 - Second protective layer. Detailed Implementation

[0040] As described in the background section, with the continuous development of integrated circuit manufacturing technology, the requirements for chip integration are constantly increasing. In chips fabricated using CMOS process platforms, the source / drain electrodes of devices are grown epitaxially, which requires opening trenches to form the source / drain electrodes of NMOS and PMOS regions respectively. However, with the development of process technology, the number of transistors per unit area is increasing, and the process window at the boundary between NMOS (N) and PMOS (P) formed on the finned semiconductor substrate is becoming smaller and smaller. In addition, the process window left at the NP junction is becoming smaller and smaller due to the influence of photolithography OVL, CD, and other factors. Therefore, when forming the source / drain trenches of NMOS and PMOS respectively, double etch is likely to occur at the NP boundary, which in turn causes a groove to appear on the top of the polysilicon gate at the NP boundary, thus exposing the gate polysilicon and causing device failure.

[0041] To address this issue, existing technologies control the source-drain trenches (CD) of NMOS and PMOS to reserve a portion of the area at the NP boundary to avoid double etching of the gate polysilicon. However, this reserved area often adversely affects subsequent processes; for example, the raised area can impact the process during subsequent ILD CMP.

[0042] To address the problems existing in the prior art, the researchers of this invention propose whether it is possible to reduce the width of the reserved area at the NP boundary while avoiding, to some extent, the adverse effects of double etch and the large width of the reserved area at the NP boundary on subsequent CMOS processes. Therefore, the researchers of this invention propose allowing the reserved boundary region (NP) to have a certain width of double etch, i.e., forming the opening. Then, by filling a second protective layer, the opening caused by the double etch during the formation of the source / drain region caused by the reserved boundary region (NP) is filled in. This avoids the opening caused by the double etch increasing the difficulty of subsequent processes, while reducing the width of the existing reserved boundary region (NP) and avoiding the problem of the large width of the existing reserved boundary region (NP) having an adverse effect on subsequent CMOS processes.

[0043] Based on this, the present invention provides a method for manufacturing a CMOS device to increase the process window of the NP boundary between the NMOS transistor and the PMOS transistor in the CMOS device (reducing the width of the NP boundary), thereby ensuring the device performance of the CMOS device.

[0044] For details, please refer to... Figure 1 , Figure 1 This is a schematic flowchart of the manufacturing method of the CMOS device provided in an embodiment of the present invention; as shown. Figure 1 As shown, the method for manufacturing the CMOS device may include the following steps:

[0045] Step S1: Provide a semiconductor substrate, the semiconductor substrate including a PMOS region, an NMOS region and a reserved boundary region located between the PMOS region and the NMOS region, a plurality of discrete fin structures and gate structures spanning the plurality of fin structures and surrounding the sidewalls and top surface of the fin structures are respectively formed on the semiconductor substrate of the PMOS region and the NMOS region, the gate structure including a gate dielectric layer, a gate material layer and a gate isolation layer stacked sequentially;

[0046] Step S2: Etch the semiconductor substrate and form the source and drain regions in the fin structures located on both sides of the gate structure in the PMOS and NMOS regions, respectively, and at the same time form an opening on the reserved boundary region that exposes at least part of the gate isolation layer at the bottom.

[0047] Step S3: Sequentially deposit a first protective layer and a second protective layer on the semiconductor substrate, wherein the first protective layer at least fills the source region and the drain region, and the second protective layer at least fills the opening;

[0048] Step S4: Remove the first protective layer.

[0049] That is, in the CMOS device manufacturing method provided by the present invention, it is not necessary to widen the reserved boundary region (NP) to avoid double etch in the reserved boundary region (NP) located between the NMOS region and the PMOS region, as in the prior art. The manufacturing method provided by the present invention allows the reserved boundary region (NP) to have a certain width of double etch, i.e., forming the opening. Then, by filling the second protective layer, the opening caused by the double etch of the reserved boundary region (NP) during the formation of the source / drain region is filled in. This avoids the opening caused by double etch increasing the difficulty of subsequent processes, while reducing the width of the existing reserved boundary region (NP) and avoiding the problem that the large width of the existing reserved boundary region (NP) has an adverse effect on subsequent CMOS processes.

[0050] The CMOS device and its manufacturing method proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of this invention. Many specific details are set forth in the following description to provide a thorough understanding of this invention; however, this invention may be practiced in other ways different from those described herein, and therefore this invention is not limited to the specific embodiments disclosed below.

[0051] As shown in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" do not specifically refer to the singular and may also include the plural. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements. In detailing the embodiments of the present invention, for ease of explanation, the cross-sectional views showing the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0052] For details, please refer to... Figures 2a to 2g , Figures 2a to 2g This is a schematic diagram of the fabrication process of a CMOS device according to an embodiment of the present invention.

[0053] In step S1, please refer to the following for details. Figure 2a As shown, a semiconductor substrate 100 is provided. The semiconductor substrate 100 includes a PMOS region P, an NMOS region N, and a reserved boundary region NP located between the PMOS region P and the NMOS region N. Multiple discrete fin structures 110 are formed on the semiconductor substrate 100 of the PMOS region P and the NMOS region N, respectively, and gate structures 251 are formed across the multiple fin structures 110 and surrounding the sidewalls and top surface of the fin structures 110. The gate structure 251 includes a gate dielectric layer 120, a gate material layer 130, and a gate isolation layer 140 stacked sequentially. The gate isolation layer 140 can be a single-layer film structure, such as a silicon dioxide layer or a silicon nitride layer. Alternatively, the gate isolation layer 140 can also be a double-layer or multi-layer film structure. For example, in the embodiments of the present invention... Figure 2a The diagram shows a schematic of the gate isolation layer 140 as a double-layer film structure. Specifically, the gate isolation layer 140 may include a silicon nitride film layer 141 and a silicon dioxide film layer 142.

[0054] Furthermore, the semiconductor substrate 100 can be any suitable substrate known in the art, such as at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III / V compound semiconductors, including multilayer structures composed of these semiconductors, or silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), or it can also be a double-sided polished wafer (DSP), or a ceramic substrate such as alumina, a quartz or glass substrate, etc. For example, in this embodiment, the semiconductor substrate 100 is, for example, a silicon wafer.

[0055] It should be noted that a CMOS device can be composed of multiple PMOS transistors and multiple NMOS transistors, and the specific number of PMOS transistors and NMOS transistors required can be determined according to actual needs. The CMOS device manufacturing method provided by this invention is a CMOS device formed on a fin structure. Therefore, multiple fin structures 110 can be formed on the PMOS region P and NMOS region N provided by this invention. For example, to simplify the drawing process, this invention only shows a portion of the fin structures.

[0056] In this embodiment, a plurality of N-type wells (not shown) for subsequently forming the PMOS region P in the CMOS device and P-type wells (not shown) for forming the NMOS region N can be formed within the semiconductor substrate 100. Furthermore, based on the characteristics of the fin field-effect transistor, the gate structure 251 formed on the PMOS region P and the NMOS region N is a shared gate structure.

[0057] Subsequently, after forming the gate structures 251 required for each of the PMOS and NMOS regions in step S1, sidewalls 150 may also be formed on the sidewalls of the gate structures 251. Due to the appendix provided by the present invention... Figure 2a This is a schematic diagram of a vertical cross-section of a CMOS device formed on the fin structure 110. Therefore, for ease of observation, the present invention includes... Figure 2a The sidewall 150 is a material layer deposited before the sidewall material layer is etched into the sidewall. In this invention, it is referred to as 150 to distinguish it from other film layers. However, in actual applications, after the sidewall is formed by the sidewall etching process, the sidewall only covers the two sidewalls of the gate structure.

[0058] In step S2, please refer to the following for details. Figure 2dAs shown, the semiconductor substrate 100 is etched, and the source region (not shown) and drain region (not shown) in the fin structure 110 located on both sides of the gate structure 251 are formed in the PMOS region P and the NMOS region N, respectively. At the same time, an opening 102 is formed on the reserved boundary region NP, with at least part of the gate isolation layer 140 exposed at the bottom.

[0059] In this embodiment, the source and drain regions in the fin structures 110 located on both sides of the gate structure 251 in the PMOS region P and the NMOS region N are formed by step-by-step etching. During the step-by-step etching process to form the source and drain regions of the PMOS region P and the NMOS region N respectively, the narrower reserved boundary region NP between them will exhibit a double-etching problem of the gate structure in this region. This results in a recessed opening 101 on the top surface of the gate structure 251 in the reserved boundary region NP. If this recessed opening 101 is not addressed, its aspect ratio will affect the process window of the subsequent CMOS process, leading to the film layer size CD formed in the subsequent CMOS process not meeting the expected design requirements, ultimately causing the formed CMOS device to fail. This problem can be effectively solved using step S3 as described below, for details.

[0060] It is understood that the depth of the opening 102 formed during the double etch process may vary depending on the etching parameters. For example, the bottom of the opening 102 may expose a portion of the silicon dioxide film 142 in the gate isolation layer 140, such as... Figure 2e In a1, a portion of the silicon nitride film 141 in the gate isolation layer 140 may also be exposed, such as Figure 2e a2 in the text, and the gate material layer 130 that can expose the gate isolation layer 140, such as Figure 2e a3 in the middle.

[0061] Furthermore, there are attached Figures 2a-2d 2g and attached Figure 2e The comparison shows that the appendix Figures 2a-2d 2g and attached Figure 2e The method for manufacturing the CMOS device provided by the present invention is shown along two different and mutually perpendicular directions.

[0062] Furthermore, the present invention provides a specific implementation method in which source and drain regions are formed in the fin structures 110 located on both sides of the gate structure 251 in the PMOS region P and NMOS region N respectively in step S2, and an opening 102 with at least part of the gate isolation layer 140 exposed at the bottom is formed on the reserved boundary region NP, which may include the following steps:

[0063] Step S2.1, please refer to the following for details. Figure 2b A first patterned photoresist 160 is formed to mask the NMOS region N and expose the PMOS region P and the reserved boundary region NP. Using the first patterned photoresist 160 as a mask, a portion of the fin structure 110 on both sides of the gate structure 251 in the PMOS region P and the reserved boundary region NP is etched away to form a first trench (not shown) in the PMOS region P for forming the source and / or drain, and at the same time, a first opening 101 is formed on the reserved boundary region NP.

[0064] Step S2.2, for details please refer to Figure 2c The first patterned photoresist 160 is removed, and a second patterned photoresist 170 is formed to mask the PMOS region P and expose the NMOS region N and the reserved boundary region NP. Using the second patterned photoresist 170 as a mask, a portion of the fin structure 110 on both sides of the gate structure 251 in the NMOS region N and the reserved boundary region NP is etched away to form a second trench (not shown) in the NMOS region N for forming the source and / or drain. At the same time, the bottom of the first opening 101 is etched along the first opening 101 to deepen the depth of the first opening 101, forming a deepened first opening 102.

[0065] Step S2.3, please refer to [link / reference] for details. Figure 2d As shown, the second patterned photoresist 170 is removed, and the deepened first opening 102 is used as the opening 102.

[0066] In this embodiment, during step S2.1, when the NMOS region N is masked to etch the PMOS region P and the reserved boundary region NP to form the first opening 101 and the first trench required for forming the source and / or drain of the PMOS region P, a portion of the silicon dioxide film layer 142 in the sidewalls (sidewall material layer) 150 of the PMOS region P and the reserved boundary region NP and the gate isolation layer 140 is simultaneously removed. At this time, the removed film layer regions are connected together. Therefore, for ease of display and understanding, the present invention is illustrated in the appendix. Figure 2b and attached Figure 2c The first opening 101 and the first opening 102, which is deepened in depth, are marked by dashed lines.

[0067] Understandably, this appendix Figure 2b and 2cThis example only shows a partial exposure of the silicon nitride film layer 141 in the gate isolation layer 140 at the bottom of the formed opening 102 or the deepened first opening 102. In practical applications, due to the influence of etching process parameters, it is very likely that the bottom of the opening 101 or the deepened first opening 102 will expose the gate material layer 130 in the gate structure 251. The material of the gate material layer 130 can be polysilicon or a metal gate material. If this problem occurs, it will directly lead to the top of the gate structure of the CMOS device being exposed, which will easily cause CMOS device failure in subsequent CMOS processes such as forming metal plugs, and defects in the gate structure during source-drain epitaxial growth. To address this problem, the present invention provides a solution by filling the opening 102 with a second protective layer with an etching selectivity different from all the materials of the gate isolation layer 140, thereby expanding the process window of the reserved boundary region NP.

[0068] In step S3, please refer to the following for details. Figure 2e As shown, a first protective layer 180 and a second protective layer 190 are sequentially deposited on the semiconductor substrate 100. The first protective layer 180 at least fills the source region (not shown) and the drain region (not shown). The second protective layer 190 at least fills the opening 102 (or is a deepened version of the first opening 102) and extends to cover the top surface and part of the sidewalls of the gate structure 251.

[0069] It should be noted that the appendix provided by this invention Figure 2e a1, a2, and a3 in the diagram are merely schematic diagrams of three different residual gate structures 251 for different depths of the opening 102 caused by different etching parameters. Figure 2e The diagram simply shows all three scenarios in one figure. In actual applications, one or more scenarios may occur due to the loading between different structures.

[0070] In this embodiment, for Figure 2d The structure shown is provided for ease of understanding. The present invention provides a structure along the attached... Figure 2d Cross-sectional view of the section formed by cutting along the AA' direction (attached) Figure 2e According to the appendix Figure 2e As can be seen, since the gate structure 251 spans the sidewalls and top surface of the plurality of fin structures 110, therefore, from the attached Figure 2e From the cross-sectional angle shown, only the first protective layer 180 can be seen filling the gaps on both sides of the gate structure 251, while the plurality of fin structures 110 are located on the adjacent side. Figure 2eThe gate structure 251 is located in front of or behind the gate structure 251 and is perpendicular to the gate structure 251.

[0071] The material of the first protective layer 180 is different from the materials of the gate material layer 130, the gate isolation layer 140, and the gate dielectric layer 120. The material of the first protective layer 180 is spin-coated organic carbon. Furthermore, the material of the second protective layer 190 is a low-temperature oxide.

[0072] Further reference Figure 2e It is understood that in step S3, the second protective layer 190 not only fills the opening 102, but also covers the top surface of the gate structure 251 and the surface of the first protective layer 180.

[0073] In step S4, please refer to the following for details. Figure 2f As shown, the first protective layer 180 is removed.

[0074] In this embodiment, due to the special nature of the material of the first protective layer 180, the different etching selectivity of the first protective layer 180 compared to other materials such as the gate isolation layer 140 can be utilized to selectively remove the first protective layer 180 and part of the second protective layer 190, while retaining the second protective layer 190 located on the top surface of the gate structure 251, i.e., in the opening 102. Figure 2g As shown, this achieves the objective of the present invention.

[0075] Furthermore, after removing the first protective layer 180 in step S4 of the manufacturing method of the CMOS device provided by the present invention, the manufacturing method may further include:

[0076] Using the sidewall 150 and the gate structure 251 as masks, epitaxial material layers (not shown) are deposited in the first trench (not shown) and the second trench (not shown) to form the source and drain.

[0077] The epitaxial material layer may be made of germanium silicide or silicon phosphide. It is understood that, based on the different characteristics of PMOS and NMOS transistors in CMOS devices, different epitaxial material layers can be used to fill the trenches used to form the source / drain of the PMOS and NMOS transistors. This is prior art and will not be elaborated upon in this invention.

[0078] Furthermore, based on the manufacturing method of the CMOS device described above, the present invention also provides a CMOS device. In this CMOS device, the width of the reserved boundary region (NP) located between the NMOS region and the PMOS region is smaller than the width of the reserved boundary region (NP) in the prior art; and, in the CMOS device provided by the present invention, an opening 102 is formed on the reserved boundary region (NP) between the NMOS region and the PMOS region, and the opening 102 is filled with the second protective layer 190.

[0079] In summary, the CMOS device manufacturing method provided by this invention does not require widening the reserved boundary region (NP) to avoid double etching as in the prior art. The manufacturing method provided by this invention allows the reserved boundary region (NP) to have a certain width of double etch, i.e., forming the opening. Then, by filling with a second protective layer, the opening caused by double etching during the formation of the source / drain region is filled in. This avoids the opening caused by double etching increasing the difficulty of subsequent processes, while reducing the width of the existing reserved boundary region (NP) and avoiding the problem of the large width of the existing reserved boundary region (NP) adversely affecting subsequent CMOS processes.

[0080] Furthermore, since the present invention reduces the width of the reserved boundary region (NP) between the NMOS region and the PMOS region, the CMOS device formed using the manufacturing method provided by the present invention is more in line with the development trend of modern miniaturized and integrated circuits.

[0081] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of protection of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the scope of protection of the present invention.

[0082] Furthermore, it should be understood that although the terms "first," "second," etc., may be used herein to describe different elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion. Therefore, without departing from the teachings of exemplary embodiments according to the present invention, the first element, component, region, layer, or portion discussed below may also be referred to as the second element, component, region, layer, or portion.

[0083] For ease of description, spatial relative terms such as “below,” “above,” “under,” “above,” “upper,” and “lower” are used herein to describe the spatial positional relationship of an element or feature as shown in the figures to other elements or features. It should be understood that spatial relative terms are intended to encompass different orientations in use or operation beyond the orientation depicted in the figures. For example, if the device in the figures were inverted, an element described as “below” or “under” other elements or features would later be positioned as “above” or “above” other elements or features. Thus, the exemplary term “below” can include both “above” and “below” orientations. The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein will be interpreted accordingly.

[0084] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms “comprising” and / or “including” are used in this specification, they indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or combinations thereof.

[0085] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A method for manufacturing a CMOS device, characterized in that, It should include at least the following steps: Step S1: Provide a semiconductor substrate, the semiconductor substrate including a PMOS region, an NMOS region and a reserved boundary region located between the PMOS region and the NMOS region, a plurality of discrete fin structures and gate structures spanning the plurality of fin structures and surrounding the sidewalls and top surface of the fin structures are respectively formed on the semiconductor substrate of the PMOS region and the NMOS region, the gate structure including a gate dielectric layer, a gate material layer and a gate isolation layer stacked sequentially; Step S2: Etch the semiconductor substrate and form the source and drain regions in the fin structures located on both sides of the gate structure in the PMOS and NMOS regions, respectively, and at the same time form an opening on the reserved boundary region that exposes at least part of the gate isolation layer at the bottom. Step S3: Sequentially deposit a first protective layer and a second protective layer on the semiconductor substrate, wherein the first protective layer at least fills the source region and the drain region, and the second protective layer at least fills the opening; Step S4: Remove the first protective layer and retain the second protective layer located on the top surface of the gate structure.

2. The method for manufacturing a CMOS device as described in claim 1, characterized in that, The gate isolation layer is a single-layer film structure or a double-layer film structure, and the material of the gate isolation layer includes silicon nitride or silicon oxide.

3. The method for manufacturing a CMOS device as described in claim 2, characterized in that, The material of the first protective layer is different from the materials of the gate material layer, the gate isolation layer and the gate dielectric layer. The material of the first protective layer includes spin-coated organic carbon, photoresist or anti-reflective coating material.

4. The method for manufacturing a CMOS device as described in claim 1, characterized in that, The material of the second protective layer includes low-temperature oxides.

5. The method for manufacturing a CMOS device as described in claim 1, characterized in that, Step S2, which involves forming source and drain regions in the fin structures located on both sides of the gate structure in the PMOS and NMOS regions respectively, and simultaneously forming an opening on the reserved boundary region that exposes at least a portion of the gate isolation layer at its bottom, includes: A first patterned photoresist is formed to mask the NMOS region and expose the PMOS region and the reserved boundary region. Using the first patterned photoresist as a mask, a portion of the fin structure on both sides of the gate structure in the PMOS region and the reserved boundary region is etched away to form a first trench in the PMOS region for forming the source and / or drain, and at the same time, a first opening is formed on the reserved boundary region. Remove the first patterned photoresist and form a second patterned photoresist to mask the PMOS region and expose the NMOS region and the reserved boundary region. Using the second patterned photoresist as a mask, etch away a portion of the fin structure on both sides of the gate structure in the NMOS region and the reserved boundary region to form a second trench in the NMOS region for forming the source and / or drain. At the same time, continue etching along the bottom of the first opening to deepen the depth of the first opening. Remove the second patterned photoresist and use the deepened first opening as the opening.

6. The method for manufacturing a CMOS device as described in claim 5, characterized in that, After forming the gate structures of the PMOS region and the NMOS region in step S1, a sidewall is formed on the sidewall of the gate structure.

7. The method for manufacturing a CMOS device as described in claim 6, characterized in that, After removing the first protective layer in step S4, the manufacturing method further includes: Using the sidewall and the gate structure as masks, epitaxial material layers are deposited in the first trench and the second trench to form the source and drain.

8. The method for manufacturing a CMOS device as described in claim 7, characterized in that, The epitaxial material layer is made of germanium silicide or silicon phosphide.

9. The method for manufacturing a CMOS device as described in claim 1, characterized in that, In step S3, the second protective layer not only fills the opening but also covers the top surface of the gate structure and the surface of the first protective layer.

10. A CMOS device, characterized in that, It is prepared using the CMOS device manufacturing method according to any one of claims 1 to 9.

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