Method for forming semiconductor device and semiconductor device

Abstract

Embodiments of the present application provide a semiconductor device forming method and a semiconductor device; wherein the method comprises: providing a substrate, the substrate comprising a well region and a non-well region; forming spaced-apart conductive layer stacks on the well region and the non-well region; forming a conductive connecting layer on the conductive layer stacks, the conductive connecting layer connecting the conductive layer stacks of the well region, and the conductive connecting layer not connecting the conductive layer stacks of the non-well region; wherein the well region, the conductive layer stacks and the conductive connecting layer form a test structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and to, but is not limited to, a method for forming a semiconductor device and a semiconductor device. Background Technology

[0002] With the development of the semiconductor industry, the critical dimensions of Dynamic Random Access Memory (DRAM) devices are constantly decreasing. The plasma damage mechanism caused by the plasma etching process of metals in DRAM devices has an increasingly significant impact on the reliability of the devices. Summary of the Invention

[0003] In view of the above, embodiments of this application provide a method for forming a semiconductor device and a semiconductor device.

[0004] In a first aspect, embodiments of this application provide a method for forming a semiconductor device, the method comprising:

[0005] A substrate is provided, the substrate comprising a well region and a non-well region;

[0006] A conductive stacked structure arranged at intervals is formed on the well region and the non-well region;

[0007] A conductive connection layer is formed on the conductive stacked structure, the conductive connection layer connecting the conductive stacked structure of the well region, and the conductive connection layer not connecting to the conductive stacked structure of the non-well region; wherein, the well region, the conductive stacked structure, and the conductive connection layer form a test structure.

[0008] In some embodiments, the method further includes:

[0009] A transistor is formed in the well region;

[0010] A conductive stacked structure arranged at intervals is formed on the well region and the non-well region, including:

[0011] Simultaneously, a first conductive stack structure connected to the gate of the transistor is formed on the transistor, and a second conductive stack structure spaced apart from the first conductive stack structure is formed on the non-well region. The conductive connection layer is connected to the transistor through the first conductive stack structure.

[0012] In some embodiments, the method further includes:

[0013] An active region with inverse doping to the well region is formed in the well region;

[0014] The conductive stacked structure, arranged at intervals, is formed on the well region and the non-well region, and further includes:

[0015] A third conductive stack structure, spaced apart from the second conductive stack structure, is formed on the active region, and the conductive connection layer is connected to the active region through the third conductive stack structure.

[0016] In some embodiments, the well region includes a first well region and a second well region arranged at intervals, the transistor is formed in the first well region, and the active region is formed in the second well region; an isolation structure is provided between the transistor and the active region.

[0017] In some embodiments, a conductive stack structure arranged at intervals is formed on the well region and the non-well region, including:

[0018] A first dielectric layer is formed on the substrate, the first dielectric layer covering the transistor, the active region and the non-well region;

[0019] The first dielectric layer is patterned, and at least two first vias are formed in the first dielectric layer on the well region, the first vias exposing the gate of the transistor and the active region, respectively;

[0020] A first initial conductive layer is formed on the first dielectric layer, and the first initial conductive layer is patterned to form a first gate conductive layer, a first active conductive layer and a first non-well conductive layer, wherein the first gate conductive layer is connected to the gate of the transistor through a first via, and the first active conductive layer is connected to the active region through a first via.

[0021] A second dielectric layer is formed on the first gate conductive layer, the first active conductive layer and the first non-well conductive layer, and the second dielectric layer is patterned. A plurality of second vias are formed in the second dielectric layer, and the second vias expose the first gate conductive layer, the first active conductive layer and the first non-well conductive layer respectively.

[0022] A second initial conductive layer is formed on the second dielectric layer, and the second initial conductive layer is patterned to form a second gate conductive layer connected to the first gate conductive layer through the second via, a second active conductive layer connected to the first active conductive layer, and a second non-well conductive layer connected to the first non-well conductive layer.

[0023] A third dielectric layer is formed on the second gate conductive layer, the second active conductive layer and the second non-well conductive layer, and the third dielectric layer is patterned. A plurality of third vias are formed in the third dielectric layer, and the third vias expose the second gate conductive layer, the second active conductive layer and the second non-well conductive layer respectively.

[0024] A third initial conductive layer is formed on the third dielectric layer. The third initial conductive layer is patterned to form a third gate conductive layer that is connected to the second gate conductive layer through the third via, a third active conductive layer that is connected to the second active conductive layer, and a third non-well conductive layer that is connected to the second non-well conductive layer.

[0025] The first gate conductive layer, the second gate conductive layer, and the third gate conductive layer connected to the gate of the transistor constitute the first conductive stack structure; the first active conductive layer, the second active conductive layer, and the third active conductive layer connected to the active region constitute the third conductive stack structure; and the first non-well conductive layer, the second non-well conductive layer, and the third non-well conductive layer constitute the second conductive stack structure.

[0026] In some embodiments, the method further includes:

[0027] After forming the first initial conductive layer, the first initial conductive layer on the well region is partially removed. After forming the second initial conductive layer, the second initial conductive layer on the well region is partially removed. After forming the third initial conductive layer, the third initial conductive layer on the well region is partially removed, such that in the direction perpendicular to the substrate, the height of the second conductive stack is greater than the heights of the first conductive stack and the third conductive stack.

[0028] In some embodiments, a conductive stack structure arranged at intervals is formed on the well region and the non-well region, including:

[0029] A first dielectric layer is formed on the substrate, the first dielectric layer covering the transistor, the active region and the non-well region;

[0030] The first dielectric layer is patterned, and at least two first vias are formed in the first dielectric layer on the well region, the first vias exposing the gate of the transistor and the active region, respectively;

[0031] A first initial dielectric layer is formed on the first dielectric layer, the first initial dielectric layer is patterned, and a plurality of first grooves are formed in the first initial dielectric layer. The first grooves on the well region expose the first via, and the first grooves on the non-well region expose the first dielectric layer.

[0032] The first groove and the first through hole are filled to form a first gate conductive layer connected to the gate of the transistor, a first active conductive layer connected to the active region, and a first non-well conductive layer, respectively.

[0033] A second dielectric layer is formed on the first gate conductive layer, the first active conductive layer and the first non-well conductive layer, and the second dielectric layer is patterned. A plurality of second vias are formed in the second dielectric layer. The second vias on the well region expose the first gate conductive layer and the first active conductive layer, respectively. The second vias on the non-well region expose the first non-well conductive layer.

[0034] A second initial dielectric layer is formed on the second dielectric layer, and the second initial dielectric layer is patterned to form a plurality of second grooves that expose the second through holes respectively;

[0035] The second groove and the second through hole are filled to form a second gate conductive layer, a second active conductive layer and a second non-well conductive layer, respectively;

[0036] A third dielectric layer is formed on the second gate conductive layer, the second active conductive layer and the second non-well conductive layer, and the third dielectric layer is patterned. A plurality of third vias are formed in the third dielectric layer, and the third vias expose the second gate conductive layer, the second active conductive layer and the second non-well conductive layer respectively.

[0037] A third initial dielectric layer is formed on the third dielectric layer, the third initial dielectric layer is patterned, and a plurality of third grooves are formed, the third grooves exposing the third through holes respectively;

[0038] The third groove and the third via are filled to form a third gate conductive layer, a third active conductive layer and a third non-well conductive layer;

[0039] The first gate conductive layer, the second gate conductive layer, and the third gate conductive layer connected to the gate of the transistor constitute the first conductive stack structure; the first active conductive layer, the second active conductive layer, and the third active conductive layer connected to the active region constitute the third conductive stack structure; and the first non-well conductive layer, the second non-well conductive layer, and the third non-well conductive layer constitute the second conductive stack structure.

[0040] In some embodiments, the method further includes:

[0041] After forming the first gate conductive layer and the first active conductive layer, the first gate conductive layer and the first active conductive layer are partially removed. After forming the second gate conductive layer and the second active conductive layer, the second gate conductive layer and the second active conductive layer are partially removed. After forming the third gate conductive layer and the third active conductive layer, the third gate conductive layer and the third active conductive layer are partially removed, such that in the direction perpendicular to the substrate, the height of the second conductive stack structure is greater than the height of the first conductive stack structure and the third conductive stack structure.

[0042] In some embodiments, the test structure includes at least a first test structure and a second test structure;

[0043] The transistor, the first conductive stack-up structure, and the conductive interconnect layer form the first test structure;

[0044] The active region, the third conductive stack structure, and the conductive connection layer form the second test structure.

[0045] In some embodiments, a conductive interconnect layer is formed on the conductive stack structure, including:

[0046] An insulating dielectric layer is formed on the first conductive stacked structure, the second conductive stacked structure and the third conductive stacked structure;

[0047] At least two connection holes are formed in the insulating dielectric layer on the well region, and the connection holes are respectively connected to the first conductive stacked structure and the third conductive stacked structure.

[0048] An initial conductive connection layer is formed on the insulating dielectric layer, and the initial conductive connection layer is patterned to form a first conductive connection layer connecting the first conductive stack structure and the third conductive stack structure on the well region. At the same time, a second conductive connection layer connected to the first conductive connection layer is formed on the non-well region. The second conductive connection layer has a preset pattern, which includes at least one of a grid shape, an S-shape, and a comb shape.

[0049] Secondly, embodiments of this application provide a semiconductor device, the semiconductor device comprising:

[0050] Substrate, the substrate comprising a well region and a non-well region;

[0051] A conductive stacked structure is located on the well region and the non-well region, respectively;

[0052] A conductive connection layer is located on top of the conductive stacked structure. The conductive connection layer is connected to the conductive stacked structure of the well region, but is not connected to the conductive stacked structure of the non-well region. The well region, the conductive stacked structure, and the conductive connection layer form a test structure.

[0053] In some embodiments, the conductive connection layer includes a first conductive connection layer located on the well region and a second conductive connection layer located on the non-well region, the second conductive connection layer having a preset pattern; the preset pattern includes at least one of a grid shape, an S-shape, and a comb shape.

[0054] In some embodiments, the conductive stacked structure includes at least a first conductive stacked structure and a second conductive stacked structure; the first conductive stacked structure is connected to the well region, and the second conductive stacked structure is connected to the non-well region.

[0055] In a direction perpendicular to the substrate, the projected area of ​​the second conductive stack is greater than the projected area of ​​the first conductive stack.

[0056] In some embodiments, the well region includes at least a first well region and a second well region; the first well region includes a transistor, and the second well region includes an active region.

[0057] In some embodiments, the conductive stacked structure further includes a third conductive stacked structure; the first conductive stacked structure is connected to the gate of the transistor, and the third conductive stacked structure is connected to the active region.

[0058] According to the semiconductor device formation method and semiconductor device provided in the embodiments of this application, by forming a conductive stacked structure and a conductive connection layer arranged at intervals on a substrate including a well region and a non-well region, the conductive connection layer connects to the conductive stacked structure in the well region but does not connect to the conductive stacked structure in the non-well region. In the structure of the semiconductor device provided in the embodiments of this application, the conductive stacked structure connecting the well region avoids a large amount of plasma accumulation, effectively alleviates the antenna effect in the well region, and the conductive stacked structure between the conductive connection layer and the substrate can improve the stability of the entire structure and improve the performance of the semiconductor device. Attached Figure Description

[0059] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0060] Figures 1A to 1C This is a partial structural schematic diagram of the semiconductor device provided in the embodiments of this application;

[0061] Figure 2 This is a schematic flowchart of a method for forming a semiconductor device provided in an embodiment of this application;

[0062] Figures 3A to 3Y This is a partial structural schematic diagram corresponding to the semiconductor device formation method provided in the embodiments of this application;

[0063] Figure label:

[0064] 10 - Semiconductor device; 101 - Substrate; 1011 - Well region; 1011-1 - First well region; 1011-2 - Second well region; 1012 - Non-well region; 102 - Conductive stacked structure; 1021 - First conductive stacked structure; 1022 - Second conductive stacked structure; 1023 - Third conductive stacked structure; 103 - Conductive interconnect layer; 1031 - First conductive interconnect layer; 1032 - Second conductive interconnect layer; 104 - Gate oxide layer; 105 - Gate; 301 - Well region; 3011 - First well region; 3012 - Second well region; 302 - Non-well region Region; 303-Transistor; 3031-Source; 3032-Drain; 3033-Gate oxide layer; 3034-Gate; 304-Active region; 305-Isolation structure; 306-First conductive layer stack; 307-Second conductive layer stack; 308-Third conductive layer stack; 309-First dielectric layer; 310-First via; 311-First initial conductive layer; 312-First gate conductive layer; 313-First active conductive layer; 314-First non-well conductive layer; 315-Second dielectric layer; 316-Second via; 317-Second initial conductive layer Electrical layer; 318-Second gate conductive layer; 319-Second active conductive layer; 320-Second non-well conductive layer; 321-Third dielectric layer; 322-Third via; 323-Third initial conductive layer; 324-Third gate conductive layer; 325-Third active conductive layer; 326-Third non-well conductive layer; 327-First dielectric layer; 328-First via; 329-First initial dielectric layer; 330-First groove; 331-First gate conductive layer; 332-First active conductive layer; 333-First non-well conductive layer; 334-Second dielectric layer; 33 5-Second via; 336-Second initial dielectric layer; 337-Second groove; 338-Second gate conductive layer; 339-Second active conductive layer; 340-Second non-well conductive layer; 341-Third dielectric layer; 342-Third via; 343-Third initial dielectric layer; 344-Third groove; 345-Third gate conductive layer; 346-Third active conductive layer; 347-Third non-well conductive layer; 348-Insulating dielectric layer; 349-Connection hole; 350-Conductive connection layer; 3051-First conductive connection layer; 3052-Second conductive connection layer. Detailed Implementation

[0065] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the specific technical solutions of this application will be further described in detail below with reference to the accompanying drawings of the embodiments of this application. The following embodiments are used to illustrate this application, but are not intended to limit the scope of this application.

[0066] As the size of semiconductor devices continues to shrink, the impact of plasma damage mechanisms caused by metal plasma etching processes on device reliability is becoming increasingly apparent. In particular, the damage caused by metal etching of large-area pad metals is becoming more and more obvious, and the plasma damage caused by plasma etching processes is positively correlated with the metal antenna ratio.

[0067] In some embodiments, the antenna ratio is equal to the ratio between the metal area and the gate oxide area. However, with the development of large-scale integrated circuits, the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) continues to shrink, and the thickness of the gate oxide layer also decreases accordingly. In this case, gate oxide layer damage caused by plasma processing is an important factor in the long-term reliability degradation and parameter drift of the device.

[0068] In order to reduce plasma damage to semiconductor devices, this application embodiment uses a metal via suspension method to eliminate plasma damage generated during the etching of the bottom pad metal (PAD). A metal PAD of a preset shape is used to reduce plasma damage caused during PAD etching. In addition, the metal via suspension method can eliminate plasma damage caused by the etching of the bottom PAD metal and reduce plasma damage caused by the top metal, thereby improving device reliability.

[0069] To reduce the damage caused by plasma to semiconductor devices, embodiments of this application provide a semiconductor device. Figures 1A to 1C This is a partial structural schematic diagram of the semiconductor device provided in an embodiment of this application. For example... Figure 1A As shown, the semiconductor device 10 provided in this application embodiment includes a substrate 101, a conductive stacked structure 102, and a conductive connection layer 103. The substrate 101 includes a well region 1011 and a non-well region 1012. The conductive stacked structure 102 is located above the well region 1011 and the non-well region 1012. The conductive connection layer 103 is located above the conductive stacked structure 102. The conductive connection layer 103 is connected to the conductive stacked structure 102 of the well region 1011, and the conductive connection layer 103 is not connected to the conductive stacked structure 102 of the non-well region 1012.

[0070] In some embodiments, the conductive connection layer 103 has a preset pattern, which includes any one of the following: a grid shape, an S-shape, or a comb shape.

[0071] In some embodiments, such as Figure 1B As shown, well region 1011 includes a first well region 1011-1 and a second well region 1011-2. The first well region 1011-1 includes a transistor, which includes a gate oxide layer 104 and a gate 105. The second well region 1011-2 includes an active region. The conductive stack structure 102 includes a first conductive stack structure 1021, a second conductive stack structure 1022, and a third conductive stack structure 1023. The gate 105 of the transistor and the conductive connection layer 103 are connected through the first conductive stack structure 1021, and the active region and the conductive connection layer 103 are connected through the third conductive stack structure 1023. On a plane perpendicular to the substrate, the projected area of ​​the first conductive stack structure 1021 and the third conductive stack structure 1023 is smaller than the projected area of ​​the third conductive stack structure 1023.

[0072] In some embodiments, the conductive connection layer 103 includes a first conductive connection layer 1031 located on the well region 1011 and a second conductive connection layer 1032 located on the non-well region 1012, such as Figure 1C As shown, the second conductive connection layer 1032 has a preset pattern. Here, the preset pattern refers to the projection pattern of the second conductive connection layer 1032 on a surface perpendicular to the substrate, and the preset pattern includes at least one of a grid shape, an S-shape, and a comb shape.

[0073] It should be noted that the areas not shown in the accompanying drawings are all dielectric layers. To make the structure of the embodiments of this application clearer, the dielectric layers are not shown.

[0074] In this embodiment, the conductive connection layer connects to the first conductive stacked structure in the well region but is not connected to the third conductive stacked structure in the non-well region. This allows the first conductive stacked structure connecting to the well region in the semiconductor device structure provided by this embodiment to avoid charge accumulation caused by the etching of the metal layer in the third conductive stacked structure. Furthermore, the conductive connection layer with a preset pattern reduces the area of ​​the metal layer connected to the transistor gate, and the reduction in the area of ​​the metal layer in both the first and third conductive stacked structures effectively alleviates the antenna effect in the well region. Moreover, the conductive stacked structure between the conductive connection layer and the substrate can improve the stability of the entire semiconductor device structure and enhance the performance of the semiconductor device.

[0075] Based on the semiconductor devices provided in the foregoing embodiments, this application further provides a method for forming a semiconductor device. Figure 2 This is a schematic flowchart of a method for forming a semiconductor device provided in an embodiment of this application, as shown below. Figure 2 As shown, a semiconductor device can be formed through the following steps:

[0076] Step S201: Provide a substrate, which includes a well region and a non-well region.

[0077] Step S202: Form a conductive stacked structure with spaced intervals on the well region and the non-well region.

[0078] Step S203: A conductive connection layer is formed on the conductive stacked structure. The conductive connection layer connects to the conductive stacked structure in the well region, but does not connect to the conductive stacked structure in the non-well region. The well region, the conductive stacked structure, and the conductive connection layer form a test structure.

[0079] In some embodiments, hundreds or thousands of chips are fabricated on a single wafer. The semiconductor device provided in this application embodiment is located within one of these chips. Drilling paths exist between adjacent chips, and each individual chip in the wafer can be obtained by dicing along these paths. The conductive stack-up structure and conductive interconnect layer provided in this application embodiment are located within the drill paths. The conductive layer and conductive interconnect layer in the conductive stack-up structure are used to connect detection devices to detect the performance of the semiconductor device provided in this application embodiment.

[0080] Please refer to the following. Figures 3A to 3V The method for forming a semiconductor device provided in the embodiments of this application will be further described in detail. Figures 3A to 3V This is a partial structural schematic diagram corresponding to the semiconductor device formation method provided in the embodiments of this application.

[0081] like Figure 3A As shown, step S201 is performed, providing a substrate, which includes a well region 301 and a non-well region 302.

[0082] In some embodiments, the substrate may be a silicon substrate, and the substrate may also include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or combinations thereof.

[0083] In some embodiments, a well region can refer to a region of the substrate formed by implanting P-type or N-type impurities, and a non-well region can also be a region formed by implanting P-type or N-type impurities into a region of the substrate. In the embodiments of this application, a well region can refer to a doped region or a region with a different conductivity type than the substrate, while a non-well region is different from a well region. A non-well region can be an undoped substrate region or a region with the same conductivity type as the substrate.

[0084] Please refer to the following. Figures 3B to 3S Step S202 is executed to form a conductive stacked structure arranged at intervals on the well region 301 and the non-well region 302.

[0085] In some embodiments, a transistor 303 and an active region 304 are formed in the well region 301, such as Figure 3B As shown, well region 301 includes a first well region 3011 and a second well region 3012 arranged at intervals. Transistor 303 is formed in the first well region 3011, and active region 304 is formed in the second well region 3012. An isolation structure 305 is provided between transistor 303 and active region 304. In the embodiments of this application, transistor 303 includes at least source 3031, drain 3032, gate oxide layer 3033, and gate 3034.

[0086] In some embodiments, the active region 304 may be inversely doped with the well region 301. For example, when the well region 301 is a P-type substrate, the active region 304 is doped with N-type atoms.

[0087] In some embodiments, forming spaced conductive stacked structures on the well region 301 and the non-well region 302 includes: simultaneously forming a first conductive stacked structure 306 on the transistor 303 and connected to the gate 3034 of the transistor 303; forming a second conductive stacked structure 307 on the non-well region 302 spaced from the first conductive stacked structure 306; and forming a third conductive stacked structure 308 on the active region 304 of the well region 301 spaced from the second conductive stacked structure 307. The conductive connection layer is connected to the transistor 303 through the first conductive stacked structure 306, and the conductive connection layer is connected to the active region 304 through the third conductive stacked structure 308.

[0088] Please refer to the following. Figures 3C to 3S A conductive multilayer structure can be formed through the following steps:

[0089] S2021. A first dielectric layer is formed on the substrate, the first dielectric layer covering the transistor, the active region and the non-well region.

[0090] In some embodiments, a first dielectric layer 309 covering the transistor 303, the active region 304, and the non-well region 302 can be formed on the substrate surface using deposition methods such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Figure 3C As shown.

[0091] In some embodiments, the material of the first dielectric layer 309 may be an oxide such as zirconium oxide, hafnium oxide, zirconium titanate, ruthenium oxide, antimony oxide, or aluminum oxide, and the first dielectric layer 309 is non-conductive.

[0092] S2022. Pattern the first dielectric layer and form at least two first vias in the first dielectric layer on the well region, the first vias exposing the gate, active region and non-well region of the transistor respectively.

[0093] In some embodiments, after forming the first dielectric layer 309, the first dielectric layer 309 can be patterned by etching methods such as wet etching, dry etching, or plasma etching. Alternatively, photoresist can be deposited on the first dielectric layer 309 and patterned to form at least two first vias 310 in the first dielectric layer 309, each first via 310 exposing the gate 3034 and the active region 304 of the transistor 303, respectively. In some embodiments, when patterning the first dielectric layer 309, first vias 310 exposing the non-well region 302 can also be formed, such as... Figure 3D As shown.

[0094] In some embodiments, after the first via 310 is formed, it can be filled by physical vapor deposition, chemical vapor deposition or atomic layer deposition. It should be noted that the filling material can be tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, silicide or any combination thereof.

[0095] S2023. A first initial conductive layer is formed on the first dielectric layer, and the first initial conductive layer is patterned to form a first gate conductive layer, a first active conductive layer and a first non-well conductive layer, wherein the first gate conductive layer is connected to the gate of the transistor through a first via, and the first active conductive layer is connected to the active region through a first via.

[0096] In some embodiments, as shown in 3E and 3F, a first initial conductive layer 311 can be formed on the first dielectric layer 309 by PCD, CVD or ALD, and the first initial conductive layer 311 can be patterned to form a first gate conductive layer 312, a first active conductive layer 313 and a first non-well conductive layer 314. The first gate conductive layer 312 is connected to the gate 3034 of the transistor 303 through a first via 310, and the first active conductive layer 313 is connected to the active region 304 through the first via 310.

[0097] In some embodiments, the patterning process can employ methods such as wet etching, dry etching, or plasma etching.

[0098] In some embodiments, the first initial conductive layer 311 may be made of materials such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, metal nitride, or metal silicide.

[0099] In some embodiments, when patterning the first initial conductive layer 311, the projected areas of the first gate conductive layer 312 and the first active conductive layer 313 formed in the direction perpendicular to the substrate are smaller than the projected area of ​​the first non-well conductive layer 314. This results in a smaller area of ​​the metal layers (i.e., the first gate conductive layer 312 and the first active conductive layer 313) connected to the gate 3034 and the active region 304, respectively. Therefore, the first gate conductive layer 312 and the first active conductive layer 313 accumulate less charge during the etching process, causing less damage to the gate oxide layer 3033 and the active region 304 of the transistor. In subsequent performance testing of the transistor and the active region, the measurement results of the transistor or the active region can be accurately obtained without the problem of measurement result distortion caused by the transistor being damaged by a large amount of charge.

[0100] In some embodiments, after forming the first gate conductive layer 312 and the first active conductive layer 313, a portion of the first gate conductive layer 312 and a portion of the first active conductive layer 313 with a first thickness of h1 are removed to obtain etched first gate conductive layer 312 and etched first active conductive layer 313. The etched first gate conductive layer 312 and etched first active conductive layer 313 have smaller volumes and accumulate less charge during the etching process, thus avoiding damage to the gate oxide layer of the transistor and improving the performance of the transistor.

[0101] S2024. A second dielectric layer is formed on the first gate conductive layer, the first active conductive layer and the first non-well conductive layer, and the second dielectric layer is patterned. A plurality of second vias are formed in the second dielectric layer, and the second vias expose the first gate conductive layer, the first active conductive layer and the first non-well conductive layer respectively.

[0102] Here, as Figure 3G As shown, forming a second dielectric layer 315 on the first gate conductive layer 312, the first active conductive layer 313, and the first non-well conductive layer 314 can mean that the second dielectric layer 315 is formed on the etched first gate conductive layer 312, the etched first active conductive layer 313, and the first non-well conductive layer 314 by means of PCD, CVD, or ALD. The material of the second dielectric layer 315 can be the same as or different from the material of the first dielectric layer 309.

[0103] In this embodiment, the second dielectric layer 315 can be patterned by etching, and a plurality of second vias 316 can be formed in the second dielectric layer 315. Each second via 316 exposes the first gate conductive layer 312, the first active conductive layer 313 and the first non-well conductive layer 314 respectively.

[0104] In this embodiment of the application, after the second through hole 316 is formed, a conductive material can be filled into the second through hole 316. The conductive material filled can be the same as or different from the material filled into the first through hole 310.

[0105] S2025. A second initial conductive layer is formed on the second dielectric layer. The second initial conductive layer is patterned to form a second gate conductive layer connected to the first gate conductive layer through a second via, a second active conductive layer connected to the first active conductive layer, and a second non-well conductive layer connected to the first non-well conductive layer.

[0106] In some embodiments, such as Figure 3H and Figure 3I As shown, a second initial conductive layer 317 can be formed on the second dielectric layer 315 by PCD, CVD or ALD, and the second initial conductive layer 317 can be patterned. A second gate conductive layer 318, a second active conductive layer 319 and a second non-well conductive layer 320 can be formed on each second via.

[0107] In some embodiments, when patterning the second initial conductive layer 317, the projected areas of the second gate conductive layer 318 and the second active conductive layer 319 formed in the direction perpendicular to the substrate are smaller than the projected area of ​​the second non-well conductive layer 320, making the areas of the second gate conductive layer 318 and the second active conductive layer 319 smaller. Therefore, the second gate conductive layer 318 and the second active conductive layer 319 accumulate less charge during the etching process, resulting in less damage to the gate oxide layer 3033 and the active region 304 of the transistor.

[0108] In some embodiments, after forming the second gate conductive layer 318 and the second active conductive layer 319, a portion of the second gate conductive layer 318 and a portion of the second active conductive layer 319 with a second thickness of h2 are removed to obtain an etched second gate conductive layer 318 and an etched second active conductive layer 319. The etched second gate conductive layer 318 and the etched second active conductive layer 319 have smaller volumes and accumulate less charge during the etching process, thus avoiding damage to the gate oxide layer 3033.

[0109] S2026. A third dielectric layer is formed on the second gate conductive layer, the second active conductive layer, and the second non-well conductive layer, and the third dielectric layer is patterned. A plurality of third vias are formed in the third dielectric layer, and each third via exposes the second gate conductive layer, the second active conductive layer, and the second non-well conductive layer, respectively.

[0110] In some embodiments, a third dielectric layer 321 is formed on the etched second gate conductive layer 318, the etched second active conductive layer 319, and the second non-well conductive layer 320, and a third via 322 is formed, such as... Figure 3J As shown.

[0111] In some embodiments, the third through hole 322 can also be filled with conductive material, which may be the same as or different from the conductive material filled in the first through hole 310 and the second through hole 316.

[0112] S2027. A third initial conductive layer is formed on the third dielectric layer, the third initial conductive layer is patterned, and a third gate conductive layer, a third active conductive layer, and a third non-well conductive layer are formed respectively connected to the second gate conductive layer through a third via, the third active conductive layer, and the second non-well conductive layer.

[0113] In some embodiments, such as Figure 3K and Figure 3L As shown, a third initial conductive layer 323 can be formed on the third dielectric layer 322 by PCD, CVD or ALD, and the third initial conductive layer 323 can be patterned. A third gate conductive layer 324, a third active conductive layer 325 and a third non-well conductive layer 326 are formed on each third via.

[0114] In some embodiments, after forming the first initial conductive layer 311, the first initial conductive layer 311 on the well region 301 is partially removed; after forming the second initial conductive layer 317, the second initial conductive layer 317 on the well region 301 is partially removed; and after forming the third initial conductive layer 323, the third initial conductive layer 323 on the well region 301 is partially removed, such that in the direction perpendicular to the substrate, the height of the second conductive stack 307 is greater than the height of the first conductive stack 306 and the third conductive stack 308. That is, in the direction perpendicular to the substrate, the height of the conductive layer in the second conductive stack 307 is greater than the height of the conductive layer in the first conductive stack 306 and the third conductive stack 308.

[0115] In some embodiments, the conductive layer in the second conductive stack 307 is a test metal pad. Therefore, the cross-sectional area of ​​the conductive layer in the second conductive stack 307 is larger than that of the conductive layers in the first conductive stack 306 and the third conductive stack 308, enabling accurate connection to the test device during testing.

[0116] In some embodiments, when patterning the third initial conductive layer 323, the projected areas of the third gate conductive layer 324 and the third active conductive layer 325 formed in the direction perpendicular to the substrate are smaller than the projected area of ​​the third non-well conductive layer 326, making the areas of the third gate conductive layer 324 and the third active conductive layer 325 smaller. Therefore, the third gate conductive layer 324 and the third active conductive layer 325 accumulate less charge during the etching process, resulting in less damage to the gate oxide layer 3033 and the active region 304 of the transistor.

[0117] In some embodiments, after forming the third gate conductive layer 324 and the third active conductive layer 325, a portion of the third gate conductive layer 324 and a portion of the third active conductive layer 325 with a third thickness of h3 are removed to obtain the etched third gate conductive layer 324 and the etched third active conductive layer 325. The etched third gate conductive layer 324 and the etched third active conductive layer 325 have smaller volumes and accumulate less charge during the etching process, thus avoiding damage to the gate oxide layer 3033.

[0118] In some embodiments, a first gate conductive layer 312, a second gate conductive layer 318, and a third gate conductive layer 324 connected to the gate 3033 of transistor 303 constitute a first conductive stack structure 306; a first active conductive layer 313, a second active conductive layer 319, and a third active conductive layer 325 connected to active region 304 constitute a third conductive stack structure 308; and a first non-well conductive layer 314, a second non-well conductive layer 320, and a third non-well conductive layer 326 constitute a second conductive stack structure 307.

[0119] In this embodiment, by forming a conductive stack structure with spaced distribution in the well region and non-well region, the area of ​​the metal wiring layer (i.e., conductive layer) connected to the well region is reduced, which reduces the charge accumulated during etching and avoids damage to the gate of the transistor leading to semiconductor failure. Furthermore, by forming the conductive stack structure through stepwise deposition, this embodiment prevents the occurrence of uneven stress in the conductive stack structure due to uneven filling of the dielectric layer, thereby improving the structural stability of the semiconductor device.

[0120] In this embodiment, in the first conductive stack connected to the transistor gate, a smaller first gate conductive layer is formed during etching, followed by the formation of a smaller second and third gate conductive layers. The smaller metal layer connected to the gate does not cause a large amount of charge accumulation during etching, effectively mitigating the antenna effect.

[0121] In the above embodiments, when forming different conductive layers, the present application first deposits an initial conductive layer, then patterns the initial conductive layer to obtain spaced conductive layers. In some embodiments, spaced grooves can also be formed in the dielectric layer, and then the grooves are filled to form spaced conductive layers. Therefore, please refer to the following... Figures 3M to 3S The conductive multilayer structure can also be achieved through the following steps:

[0122] Step S10: Form a first dielectric layer on the substrate, the first dielectric layer covering the transistor, the active region and the non-well region.

[0123] Step S11: Pattern the first dielectric layer and form at least two first vias in the first dielectric layer on the well region. The first vias expose the gate and active region of the transistor, respectively.

[0124] In some embodiments, a first dielectric layer 327 is formed covering the surfaces of transistor 303, active region 304, and non-well region 302, and the first dielectric layer 327 is patterned. A first via 328 is formed in the first dielectric layer 327 on the well region 301 to expose the gate 3034 of transistor 303 and the active region 304, as shown below. Figure 3M As shown.

[0125] Step S12: Form a first initial dielectric layer on the first dielectric layer, pattern the first initial dielectric layer, form a plurality of first grooves in the first initial dielectric layer, expose a first via in the first groove in the well region, and expose the first dielectric layer in the first groove in the non-well region.

[0126] In this embodiment, after forming a first initial dielectric layer 329 on the first dielectric layer 327, a plurality of first grooves 330 are formed in the first initial dielectric layer 329. The first grooves 330 on the well region 301 expose the first vias connecting the gate 3034 and the active region 304, and the first grooves 330 on the non-well region 302 expose the first dielectric layer 327, such as... Figure 3N As shown.

[0127] Step S13: Fill the first groove and the first through hole to form a first gate conductive layer connected to the gate of the transistor, a first active conductive layer connected to the active region, and a first non-well conductive layer, respectively.

[0128] In some embodiments, the first groove 330 and the first via 328 can be filled with conductive material to form a first gate conductive layer 331 connected to the gate 3034, a first active conductive layer 332 connected to the active region 304, and a first non-well conductive layer 333.

[0129] In some embodiments, after forming the first gate conductive layer 331 and the first active conductive layer 332, a portion of the first gate conductive layer 331 and the first active conductive layer 332 may be removed. In the direction perpendicular to the substrate, the height h4 of the first gate conductive layer 331 and the first active conductive layer 332 is less than the height of the first non-well conductive layer 333. Figure 3O As shown.

[0130] Step S14: A second dielectric layer is formed on the first gate conductive layer, the first active conductive layer, and the first non-well conductive layer, and the second dielectric layer is patterned. A plurality of second vias are formed in the second dielectric layer. The second vias on the well region expose the first gate conductive layer and the first active conductive layer, respectively, and the second vias on the non-well region expose the first non-well conductive layer.

[0131] Step S15: Form a second initial dielectric layer on the second dielectric layer, pattern the second initial dielectric layer, and form a plurality of second grooves that expose second through holes respectively.

[0132] Please refer to the following. Figure 3P A second dielectric layer 334 is formed on the first gate conductive layer 331, the first active conductive layer 332, and the first non-well conductive layer 333, and the second dielectric layer 334 is patterned to form second vias 335 that expose the first gate conductive layer 331, the first active conductive layer 332, and the first non-well conductive layer 333. A second initial dielectric layer 336 is formed on the second dielectric layer 334, and the second initial dielectric layer 336 is patterned to form a plurality of second grooves 337 that expose the second vias 335 respectively.

[0133] Step S16: Fill the second groove and the second via to form the second gate conductive layer, the second active conductive layer and the second non-well conductive layer, respectively.

[0134] Step S17: A third dielectric layer is formed on the second gate conductive layer, the second active conductive layer, and the second non-well conductive layer, and the third dielectric layer is patterned. A plurality of third vias are formed in the third dielectric layer, and the third vias expose the second gate conductive layer, the second active conductive layer, and the second non-well conductive layer, respectively.

[0135] In some embodiments, a second gate conductive layer 338, a second active conductive layer 339, and a second non-well conductive layer 340 are formed by filling the second groove 337 and the second via 335 with conductive materials. After forming the second gate conductive layer 338 and the second active conductive layer 339, a portion of the second gate conductive layer 338 and a portion of the second active conductive layer 339 can be removed. In the direction perpendicular to the substrate, the height of the second gate conductive layer 338 and the second active conductive layer 339 is less than the height of the second non-well conductive layer 340. Figure 3Q As shown.

[0136] In some embodiments, a third dielectric layer 341 is formed on the second gate conductive layer 338, the second active conductive layer 339, and the second non-well conductive layer 340, and the third dielectric layer 341 is patterned. A plurality of third vias 342 are formed in the third dielectric layer 341, and the third vias 342 expose the second gate conductive layer 338, the second active conductive layer 339, and the second non-well conductive layer 340, respectively.

[0137] Step S18: Form a third initial dielectric layer on the third dielectric layer, pattern the third initial dielectric layer, and form a plurality of third grooves, each of which exposes a third through hole.

[0138] In some embodiments, a third initial dielectric layer 343 is formed on the third dielectric layer 341, and the third initial dielectric layer 343 is patterned to form a plurality of third grooves 344, each of which exposes a third via 342. Figure 3R As shown.

[0139] Step S19: Fill the third groove and the third via to form the third gate conductive layer, the third active conductive layer and the third non-well conductive layer.

[0140] Please refer to the following. Figure 3S The third groove 344 and the third via 342 are filled with conductive material to form the third gate conductive layer 345, the third active conductive layer 346 and the third non-well conductive layer 347, respectively. After the third gate conductive layer 345 and the third active conductive layer 346 are formed, a portion of the third gate conductive layer 345 and the third active conductive layer 346 can be removed. In the direction perpendicular to the substrate, the height of the third gate conductive layer 345 and the third active conductive layer 346 is less than that of the third non-well conductive layer 347, so that in the direction perpendicular to the substrate, the height of the second conductive stack structure 307 is greater than that of the first conductive stack structure 306 and the third conductive stack structure 308.

[0141] Please refer to the following. Figures 3T to 3VIn step S203, a conductive connection layer is formed on the conductive stacked structure. The conductive connection layer connects to the conductive stacked structure of the well region 301, but does not connect to the conductive stacked structure of the non-well region 302.

[0142] In some embodiments, forming a conductive connection layer can be achieved through the following steps:

[0143] Step S2031: An insulating dielectric layer is formed on the first conductive stacked structure, the second conductive stacked structure, and the third conductive stacked structure.

[0144] like Figure 3T As shown, an insulating dielectric layer 348 is formed on the first conductive stacked structure 306, the second conductive stacked structure 307, and the third conductive stacked structure 308. The material of the insulating dielectric layer 348 may be the same as or different from the material of the first dielectric layer 309.

[0145] Step S2032: Form at least two connection holes in the insulating dielectric layer, wherein the at least two connection holes expose the first conductive stack structure and the third conductive stack structure, respectively.

[0146] At least two connection holes 349 are formed in the insulating dielectric layer 348 by etching. The connection holes 349 expose the surfaces of the third gate conductive layer 324 in the first conductive stack structure 306 and the third active conductive layer 325 in the third conductive stack structure 308, respectively. Figure 3U As shown.

[0147] In some embodiments, conductive material may be filled into the connection hole 349 to connect the first conductive stack structure 306 and the third conductive stack structure 308 with the conductive connection layer.

[0148] Step S2033: An initial conductive connection layer is formed on the insulating dielectric layer, and the initial conductive connection layer is patterned to form a first conductive connection layer connecting the first conductive stack structure and the third conductive stack structure on the well region, and a second conductive connection layer connected to the first conductive connection layer is formed on the non-well region. The second conductive connection layer has a preset pattern, which includes at least one of a grid shape, an S-shape, and a comb shape.

[0149] Please refer to the following. Figure 3VAfter forming the connection hole 349, an initial conductive connection layer is formed on the surface of the connection hole 349 and the insulating dielectric layer 348. The initial conductive connection layer is patterned to form a conductive connection layer 350 with a preset pattern. The conductive connection layer 350 includes a first conductive connection layer 3051 connecting the first conductive stack structure 306 and the third conductive stack structure 308. At the same time, a second conductive connection layer 3052 connected to the first conductive connection layer 3051 is formed on the non-well region 302. The second conductive connection layer 3052 has a preset pattern.

[0150] In some embodiments, the preset pattern of the second conductive connection layer 3052 includes any one of the following: a mesh shape, an S-shape, and a comb shape, based on the foregoing embodiments, such as Figure 3W to 3Y As shown, Figure 3W to 3Y This is a top view of the structure of the semiconductor device provided in the embodiments of this application, wherein, Figure 3W A top view of the second conductive interconnect layer 3052, which is a grid-shaped structure, is shown. Figure 3X A top view of the second conductive interconnect layer 3052, which is S-shaped, is shown. Figure 3Y A top view of the second conductive interconnect layer 3052, which is a comb-shaped structure, is shown.

[0151] Please continue to refer to Figure 3W The width a1 of the second conductive connection layer 3052 provided in this application embodiment can be less than 7 micrometers, so that the area of ​​the conductive connection layer is greatly reduced, the amount of plasma charge reaching the gate oxide layer is reduced, the antenna effect is avoided, and at the same time, it also has a good ohmic contact effect.

[0152] In some embodiments, the well region 301, the conductive stacked structure, and the conductive connection layer 350 form a test structure, which includes at least a first test structure and a second test structure; wherein, the transistor 303, the first conductive stacked structure 306, and the conductive connection layer 350 form the first test structure; and the active region 304, the third conductive stacked structure 308, and the conductive connection layer 350 form the second test structure.

[0153] In this embodiment, the first test structure is used to perform performance testing on transistor 303, and the second test structure is used to perform performance testing on active region 304. Here, during testing, the test device can be directly connected to the conductive connection layer 350 to detect transistor 303 and active region 304.

[0154] In this embodiment, the conductive connection layer 350 provided in this embodiment has a preset pattern, which can reduce the area of ​​the metal layer connected to the gate oxide layer in the semiconductor device, thereby reducing the amount of plasma charge reaching the gate oxide layer, and can also ensure the ohmic contact effect during device performance testing, without causing contact problems.

[0155] The conductive connection layer in this embodiment is suspended on the second conductive stack structure and is not connected to the second conductive stack structure. This isolates the connection between the metal layer in the second conductive stack structure and the conductive connection layer, so that the plasma charge generated by the etching process of the metal layer in the second conductive stack structure will not accumulate in the first and third conductive stack structures. Therefore, there is less charge in the first and third conductive stack structures, which will not damage the gate oxide layer of the transistor, thereby improving the performance and yield of the semiconductor device.

[0156] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected to achieve the purpose of this embodiment according to actual needs.

[0157] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0158] The above description is merely a specific embodiment of this application, but the scope of protection of this invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this invention should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for forming a semiconductor device, characterized in that, The method includes: A substrate is provided, the substrate comprising a well region and a non-well region; A conductive stacked structure arranged at intervals is formed on the well region and the non-well region; A conductive connection layer is formed on the conductive stacked structure, the conductive connection layer connecting the conductive stacked structure of the well region, and the conductive connection layer not connecting to the conductive stacked structure of the non-well region; wherein, the well region, the conductive stacked structure, and the conductive connection layer form a test structure; The method further includes: A transistor is formed in the well region; A conductive stacked structure arranged at intervals is formed on the well region and the non-well region, including: Simultaneously, a first conductive stacked structure connected to the gate of the transistor is formed on the transistor, and a second conductive stacked structure spaced apart from the first conductive stacked structure is formed on the non-well region. The conductive connection layer is connected to the transistor through the first conductive stacked structure. The method further includes: An active region with inverse doping to the well region is formed in the well region; The method of forming a conductive stacked structure arranged at intervals on the well region and the non-well region further includes: A third conductive stack structure, spaced apart from the second conductive stack structure, is formed on the active region, and the conductive connection layer is connected to the active region through the third conductive stack structure.

2. The method according to claim 1, characterized in that, The well region includes a first well region and a second well region arranged at intervals, the transistor is formed in the first well region, and the active region is formed in the second well region; there is an isolation structure between the transistor and the active region.

3. The method according to claim 1, characterized in that, A conductive stacked structure arranged at intervals is formed on the well region and the non-well region, including: A first dielectric layer is formed on the substrate, the first dielectric layer covering the transistor, the active region and the non-well region; The first dielectric layer is patterned, and at least two first vias are formed in the first dielectric layer on the well region, the first vias exposing the gate of the transistor and the active region, respectively; A first initial conductive layer is formed on the first dielectric layer, and the first initial conductive layer is patterned to form a first gate conductive layer, a first active conductive layer and a first non-well conductive layer, wherein the first gate conductive layer is connected to the gate of the transistor through a first via, and the first active conductive layer is connected to the active region through a first via. A second dielectric layer is formed on the first gate conductive layer, the first active conductive layer and the first non-well conductive layer, and the second dielectric layer is patterned. A plurality of second vias are formed in the second dielectric layer, and the second vias expose the first gate conductive layer, the first active conductive layer and the first non-well conductive layer respectively. A second initial conductive layer is formed on the second dielectric layer, and the second initial conductive layer is patterned to form a second gate conductive layer connected to the first gate conductive layer through the second via, a second active conductive layer connected to the first active conductive layer, and a second non-well conductive layer connected to the first non-well conductive layer. A third dielectric layer is formed on the second gate conductive layer, the second active conductive layer and the second non-well conductive layer, and the third dielectric layer is patterned. A plurality of third vias are formed in the third dielectric layer, and the third vias expose the second gate conductive layer, the second active conductive layer and the second non-well conductive layer respectively. A third initial conductive layer is formed on the third dielectric layer. The third initial conductive layer is patterned to form a third gate conductive layer that is connected to the second gate conductive layer through the third via, a third active conductive layer that is connected to the second active conductive layer, and a third non-well conductive layer that is connected to the second non-well conductive layer. The first gate conductive layer, the second gate conductive layer, and the third gate conductive layer connected to the gate of the transistor constitute the first conductive stack structure; the first active conductive layer, the second active conductive layer, and the third active conductive layer connected to the active region constitute the third conductive stack structure; and the first non-well conductive layer, the second non-well conductive layer, and the third non-well conductive layer constitute the second conductive stack structure.

4. The method according to claim 3, characterized in that, The method further includes: After forming the first initial conductive layer, the first initial conductive layer on the well region is partially removed. After forming the second initial conductive layer, the second initial conductive layer on the well region is partially removed. After forming the third initial conductive layer, the third initial conductive layer on the well region is partially removed, such that in the direction perpendicular to the substrate, the height of the second conductive stack is greater than the heights of the first conductive stack and the third conductive stack.

5. The method according to claim 1, characterized in that, A conductive stacked structure arranged at intervals is formed on the well region and the non-well region, including: A first dielectric layer is formed on the substrate, the first dielectric layer covering the transistor, the active region and the non-well region; The first dielectric layer is patterned, and at least two first vias are formed in the first dielectric layer on the well region, the first vias exposing the gate of the transistor and the active region, respectively; A first initial dielectric layer is formed on the first dielectric layer, the first initial dielectric layer is patterned, and a plurality of first grooves are formed in the first initial dielectric layer. The first grooves on the well region expose the first via, and the first grooves on the non-well region expose the first dielectric layer. The first groove and the first through hole are filled to form a first gate conductive layer connected to the gate of the transistor, a first active conductive layer connected to the active region, and a first non-well conductive layer, respectively. A second dielectric layer is formed on the first gate conductive layer, the first active conductive layer and the first non-well conductive layer, and the second dielectric layer is patterned. A plurality of second vias are formed in the second dielectric layer. The second vias on the well region expose the first gate conductive layer and the first active conductive layer, respectively. The second vias on the non-well region expose the first non-well conductive layer. A second initial dielectric layer is formed on the second dielectric layer, and the second initial dielectric layer is patterned to form a plurality of second grooves that expose the second through holes respectively; The second groove and the second through hole are filled to form a second gate conductive layer, a second active conductive layer and a second non-well conductive layer, respectively; A third dielectric layer is formed on the second gate conductive layer, the second active conductive layer and the second non-well conductive layer, and the third dielectric layer is patterned. A plurality of third vias are formed in the third dielectric layer, and the third vias expose the second gate conductive layer, the second active conductive layer and the second non-well conductive layer respectively. A third initial dielectric layer is formed on the third dielectric layer, the third initial dielectric layer is patterned, and a plurality of third grooves are formed, the third grooves exposing the third through holes respectively; The third groove and the third via are filled to form a third gate conductive layer, a third active conductive layer and a third non-well conductive layer; The first gate conductive layer, the second gate conductive layer, and the third gate conductive layer connected to the gate of the transistor constitute the first conductive stack structure; the first active conductive layer, the second active conductive layer, and the third active conductive layer connected to the active region constitute the third conductive stack structure; and the first non-well conductive layer, the second non-well conductive layer, and the third non-well conductive layer constitute the second conductive stack structure.

6. The method according to claim 5, characterized in that, The method further includes: After forming the first gate conductive layer and the first active conductive layer, the first gate conductive layer and the first active conductive layer are partially removed. After forming the second gate conductive layer and the second active conductive layer, the second gate conductive layer and the second active conductive layer are partially removed. After forming the third gate conductive layer and the third active conductive layer, the third gate conductive layer and the third active conductive layer are partially removed, such that in the direction perpendicular to the substrate, the height of the second conductive stack structure is greater than the height of the first conductive stack structure and the third conductive stack structure.

7. The method according to claim 1, characterized in that, The test structure includes at least a first test structure and a second test structure; The transistor, the first conductive stack-up structure, and the conductive interconnect layer form the first test structure; The active region, the third conductive stack structure, and the conductive connection layer form the second test structure.

8. The method according to claim 1, characterized in that, A conductive interconnect layer is formed on the conductive stacked structure, including: An insulating dielectric layer is formed on the first conductive stacked structure, the second conductive stacked structure and the third conductive stacked structure; At least two connection holes are formed in the insulating dielectric layer on the well region, and the connection holes are respectively connected to the first conductive stacked structure and the third conductive stacked structure. An initial conductive connection layer is formed on the insulating dielectric layer, and the initial conductive connection layer is patterned to form a first conductive connection layer connecting the first conductive stack structure and the third conductive stack structure on the well region. At the same time, a second conductive connection layer connected to the first conductive connection layer is formed on the non-well region. The second conductive connection layer has a preset pattern, which includes at least one of a grid shape, an S-shape, and a comb shape.

9. A semiconductor device, characterized in that, The semiconductor device includes: Substrate, the substrate comprising a well region and a non-well region; A conductive stacked structure is located on the well region and the non-well region, respectively; A conductive connection layer is located on top of the conductive stacked structure. The conductive connection layer is connected to the conductive stacked structure of the well region, and the conductive connection layer is not connected to the conductive stacked structure of the non-well region. The well region, the conductive stacked structure, and the conductive connection layer form a test structure. The conductive stacked structure includes at least a first conductive stacked structure and a second conductive stacked structure; the first conductive stacked structure is connected to the well region, and the second conductive stacked structure is connected to the non-well region; In a direction perpendicular to the substrate, the projected area of ​​the second conductive stack is larger than the projected area of ​​the first conductive stack. The well region includes at least a first well region and a second well region; the first well region includes a transistor, and the second well region includes an active region.

10. The semiconductor device according to claim 9, characterized in that, The conductive connection layer includes a first conductive connection layer located on the well region and a second conductive connection layer located on the non-well region, wherein the second conductive connection layer has a preset pattern. The preset pattern includes at least one of grid shape, S-shape and comb shape.

11. The semiconductor device according to claim 9, characterized in that, The conductive stacked structure further includes a third conductive stacked structure; the first conductive stacked structure is connected to the gate of the transistor, and the third conductive stacked structure is connected to the active region.

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