Semiconductor devices

Abstract

This invention discloses a semiconductor device, comprising: a bottom package; a top package stacked on the bottom package; an interposer layer disposed between the bottom package and the top package, wherein the top package is electrically connected to the interposer layer via a plurality of peripheral solder balls; and a plurality of dummy metal components disposed on the interposer layer and surrounded by the plurality of peripheral solder balls, wherein the plurality of dummy metal components are formed on corresponding dummy pads of the interposer layer, and wherein the height of each of the plurality of dummy metal components is smaller than the height of the peripheral solder balls. In this manner, when bottom filler is applied between the top package and the interposer layer, the dummy metal components can create a capillary effect on the bottom filler, thereby filling the gap between the top package and the interposer layer with the bottom filler. This allows the high thermal conductivity of the bottom filler to dissipate heat, further improving heat dissipation efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor device. Background Technology

[0002] The rapid development of electronic devices in recent years has spurred demand for greater functionality in consumer electronics, with a particular emphasis on multi-functionality, miniaturization, and weight reduction. These limitations, stemming from the relatively unchanged state of semiconductor technology, make the design of microelectronic structures more complex and challenging.

[0003] High-bandwidth package-on-package (HBPoP) has been introduced as a potential candidate for processors that can be integrated into smartphones, tablets, and other consumer electronics. The advantages of HBPoP lie in its high bandwidth and short path for signal transmission, making it suitable for high-performance computing.

[0004] However, compared to flip-chip chip-scale package (FCCSP), HBPoP exhibits worse thermal performance due to the additional thermal resistance of the DRAM top package. Furthermore, HBPoP suffers from lower reliability because the solder balls between the interposer and the DRAM top package are not protected. It is also difficult to fill the gap between the interposer and the DRAM top package with underfill. Summary of the Invention

[0005] In view of this, the present invention provides a semiconductor device relating to a thermally enhanced package-on-package (PoP) having dummy thermal features (dummy metal components) on an interposer to improve the heat dissipation efficiency of the semiconductor device.

[0006] According to a first aspect of the present invention, a semiconductor device is disclosed, comprising:

[0007] Bottom packaging;

[0008] The top package is stacked on top of the bottom package;

[0009] An interposer layer is disposed between the bottom package and the top package, wherein the top package is electrically connected to the interposer layer via peripheral solder balls; and

[0010] A dummy metal component is disposed on the interposer layer and surrounded by an outer solder ball, wherein the dummy metal component is formed on a corresponding dummy pad on the interposer layer, and the height of each of the dummy metal components is smaller than the height of the outer solder ball.

[0011] According to a second aspect of the present invention, a semiconductor device is disclosed, comprising:

[0012] Bottom packaging;

[0013] The top package is stacked on top of the bottom package;

[0014] An interposer layer is disposed between the bottom package and the top package, wherein the top package is electrically connected to the interposer layer via peripheral solder balls; and

[0015] Hot grains are disposed on the interlayer and surrounded by the outer solder balls.

[0016] The semiconductor device of the present invention includes: a bottom package; a top package stacked on the bottom package; an interposer disposed between the bottom package and the top package, wherein the top package is electrically connected to the interposer via peripheral solder balls; and dummy metal components disposed on the interposer and surrounded by peripheral solder balls, wherein the dummy metal components are formed on corresponding dummy pads of the interposer, and wherein the height of each of the dummy metal components is smaller than the height of the peripheral solder balls. In this manner, when bottom filler is applied between the top package and the interposer, the dummy metal components can create a capillary effect on the bottom filler, thereby filling the gap between the top package and the interposer with the bottom filler. This allows the high thermal conductivity of the bottom filler to dissipate heat, further improving heat dissipation efficiency. Attached Figure Description

[0017] Figure 1 This is a schematic cross-sectional view illustrating an exemplary PoP according to an embodiment of the present invention;

[0018] Figure 2 This is a perspective top view showing an exemplary layout of a dummy metal component on an intermediary layer;

[0019] Figure 3 It is along Figure 2 A sectional view taken by line I-I' in the middle;

[0020] Figures 4 to 10 Various layouts of dummy metal components on an intermediary layer according to some embodiments are shown, wherein Figure 7 It is along Figure 6 The cross-sectional view taken from line II-II' in the diagram. Figure 9 It is along Figure 8 A cross-sectional view taken from line III-III'; and

[0021] Figure 11 This is a schematic cross-sectional view illustrating an exemplary PoP according to another embodiment of the present invention. Detailed Implementation

[0022] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0023] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0024] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0025] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0026] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0027] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0028] This invention relates to thermally enhanced package-on-package (PoP) and can be applied to high-bandwidth PoP (HBPoP) or Info-PoP (integrated fan-out PoP). PoP is a scheme involving stacking one chip package on top of another, known as semiconductor packaging. For example, PoP can combine vertically discrete memory and ball grid array (BGA) packages. In a PoP package design, the top package can be interconnected to the bottom package via peripheral solder balls.

[0029] The thermal performance of HBPoP is unsatisfactory due to the additional thermal resistance of the DRAM top package. Furthermore, HBPoP has poor reliability because the solder balls between the interposer and the DRAM top package are not protected. This invention addresses these problems. According to some embodiments, HBPoP is provided with a dummy thermal feature or dummy metal component, such as a dummy metal feature or thermal die disposed on the interposer.

[0030] Figure 1 This is a schematic cross-sectional view illustrating an exemplary PoP according to an embodiment of the present invention. Figure 1 As shown, PoP 1 includes a bottom package 10 and a top package 20 stacked on the bottom package 10. According to one embodiment, the top package 20 may be a memory package, but is not limited thereto. According to one embodiment, the bottom package 10 may include a semiconductor chip 101 mounted on a package substrate (or bottom substrate) 100 in a flip-chip manner. According to one embodiment, for example, the package substrate 100 may be a three-layer (3L) or four-layer (4L) coreless embedded trace substrate (ETS), but is not limited thereto. According to one embodiment, the semiconductor chip 101, such as a logic die or system-on-a-chip (SoC), may be electrically connected to the package substrate 100 via a plurality of connection elements 112, such as copper bumps, pillars, or microbumps, but is not limited thereto.

[0031] According to one embodiment, a plurality of ball grid array (BGA) solder balls SB can be provided on the lower surface of the package substrate 100. For example, the spacing of the BGA solder balls SB on the lower surface of the package substrate 100 may be equal to or less than 0.35 mm, but is not limited thereto. The semiconductor chip 101 may be overlaid or encapsulated by an over-mold 140, such as an engineering molding compound or molding compound.

[0032] According to one embodiment, for example, the top package 20 may include at least one memory chip 201 mounted on a package substrate (or top substrate) 200. According to one embodiment, for example, the memory chip 201 may be a high-bandwidth memory (HBM) chip or a low-power DRAM (LPDRAM) chip, but is not limited thereto. According to one embodiment, for example, the memory chip 201 may be electrically connected to the package substrate 200 via a bond wire 203. The memory chip 201, the bond wire (bond lead) 203, and the top surface 200a of the package substrate 200 are covered or encapsulated by a plastic coating (or top plastic coating) 240.

[0033] According to one embodiment, the top package 20 is electrically connected to the bottom package 10 via an intermediate interposer 30. According to one embodiment, the interposer 30 may be, for example, two cored substrates, but is not limited thereto. The interposer 30 may include an interconnect structure 301 electrically connected to a through-mold via 150, such as copper pillars embedded in the plastic-coated component 140 and disposed around the periphery (outer periphery) of the semiconductor chip 101.

[0034] According to one embodiment, the top package 20 is mounted on the interposer 30 and electrically connected to the interposer 30 via a plurality of peripheral solder balls (PSBs). According to one embodiment, a small gap 40 is formed between the top package 20 and the interposer 30. According to one embodiment, the gap 40 is filled with capillary underfill 410. The capillary underfill 410 surrounds and protects the peripheral solder balls (PSBs), thereby improving the reliability of PoP 1.

[0035] According to one embodiment, to facilitate the formation of capillary bottom filler 410 within the gap 40, a plurality of dummy metal components 420 may be provided in the central region 40c of the gap 40. The dummy metal components 420 are, for example, copper pillars or bump patterns. The dummy metal components 420 are surrounded by peripheral solder balls (PSBs) and located above the semiconductor chip 101. In one embodiment, the dummy metal components 420 may be directly above the semiconductor chip 101 (i.e., overlapping in the top view). In another embodiment, at least some of the dummy metal components 420 may be located at other positions on the semiconductor chip 101, such as positions not overlapping with the semiconductor chip 101 in the top view. The dummy metal components 420 may be formed by any suitable method known in the art, such as electroplating or deposition. The number of dummy metal components 420 can be set as needed. In the top view, the plurality of dummy metal components 420 form an array, in which the dummy metal components 420 may be arranged regularly or randomly. When applying bottom filler between the top package and the interlayer, a capillary effect can be created on the bottom filler by using a dummy metal component, thereby filling the gap between the top package and the interlayer. In this way, the high thermal conductivity of the bottom filler can be used to dissipate heat, further improving heat dissipation efficiency.

[0036] By providing dummy metal components 420 on the interposer layer 30, the capillary bottom filler 410 can fill the gaps 40 using the capillary effect. According to one embodiment, the height of each dummy metal component 420 is less than the height of the peripheral solder ball PSB, so that the dummy metal components 420 do not directly contact the bottom surface 200b of the package substrate 200. This avoids interference with the mounting of the top package 20 onto the bottom package 10, ensuring that the structure of the top package 20 is not damaged after mounting. According to one embodiment, the dummy metal components 420 can be formed on each dummy pad 320 of the interposer layer 30. However, it should be understood that in some embodiments, the height of the dummy metal components 420 can be equal to the height of the peripheral solder ball PSB, allowing the dummy metal components 420 to directly contact the bottom surface 200b of the package substrate 200.

[0037] According to one embodiment, the dummy pad 320 can be an electrically floating pad, meaning that no vias are formed below the dummy pad 320 to electrically connect the dummy pad 320 to any other interconnect structure in the interposer layer 30, or that the dummy pad 320 is not powered. In another embodiment, at least some of the dummy pads 320 can be electrically connected to ground traces or ground structures in the interposer layer 30, thereby increasing the heat dissipation path and improving heat dissipation efficiency by connecting the dummy pads 320 to ground traces or ground structures. Using the dummy metal component 420 to dissipate the heat generated by the semiconductor chip 101 is also beneficial. The capillary bottom filler 410 and the dummy metal component 420 together enhance the thermal performance of the PoP 1. Specifically, when the gap 40 cannot be filled with bottom filler or other fillers, the gap 40 contains air (and of course, peripheral solder balls (PSBs)), and air has very low heat dissipation efficiency, resulting in slow and inefficient heat dissipation of the semiconductor chip 101. In this invention, multiple dummy metal components 420 are provided on the interposer layer 30. When bottom filler (e.g., molding compound) is added, the capillary effect formed by the multiple dummy metal components 420 can be used to fill the gaps, even filling (or almost filling) the entire gap 40. Since the thermal conductivity of the bottom filler is much greater than that of air, the above-mentioned solution of this invention can significantly improve heat dissipation efficiency, allowing more heat from the semiconductor chip 101 to be dissipated through the heat dissipation path above the semiconductor chip 101, making the operation of the semiconductor chip and its packaging more stable and reliable.

[0038] Figure 2 This is a perspective top view showing an exemplary layout of dummy metal components on an intermediary layer, where the same numerical designations represent the same elements, areas, or layers. Figure 3 It is along Figure 2 The cross-sectional view taken by line I-I' in the diagram. (See diagram below.) Figure 2 and Figure 3 As shown, a 7x7 copper pillar or bump array is demonstrated as an example of a dummy metal feature (dummy metal component) on an interposer layer. It should be understood that the layout and number of the dummy metal component 420 and the surrounding solder balls PSB are for illustrative purposes only. Figure 3 In this configuration, the dummy metal component 420 does not directly contact the bottom surface 200b of the package substrate 200. Heat dissipation efficiency can be further improved by connecting at least a portion of the dummy pad 320 to a ground trace or ground structure 303 in the interposer layer 30. Therefore, the capillary bottom filler 410, the dummy metal component 420, or the dummy pad 320 can serve as heat dissipation elements for the POP 1. In some embodiments, the dummy metal component 420 may directly contact the bottom surface 200b of the package substrate 200. Figure 2In the example shown, the dummy metal parts 420 can be arranged regularly to form a rectangular array of dummy metal parts 420, which facilitates manufacturing. The array of dummy metal parts 420 can also be other shapes, such as triangles, trapezoids, etc. Furthermore, Figure 2 In one embodiment, the dummy metal component 420 array is surrounded by peripheral solder balls (PSBs). In other embodiments, the peripheral solder balls (PSBs) may not be surrounded by the dummy metal component 420 array. For example, one side of the dummy metal component 420 array may not have peripheral solder balls (PSBs) but may be replaced by dummy metal components 420.

[0039] Figures 4 to 10 Various layouts of dummy metal components on an intermediary layer according to some embodiments are shown, wherein Figure 7 It is along Figure 6 The cross-sectional view taken from line II-II' in the diagram. Figure 9 It is along Figure 8 The cross-sectional view taken from line III-III' in the diagram. (See diagram below.) Figure 4 As shown, the dummy metal components 420 can be aligned with each other along the first direction D1 and arranged in an alternating manner along the second direction D2. Figure 5 As shown, the dummy metal component 420 can be arranged within the circular region 40c'. Figure 5 In the example, the arrangement of the dummy metal components 420 is not regular, for example, it is a randomly arranged array of dummy metal components 420. The above-described arrangement of the present invention can be freely selected according to needs or process requirements, which improves the design flexibility of the high heat dissipation efficiency semiconductor device of the present invention.

[0040] like Figure 6 and Figure 7 As shown, the dummy metal component 420 can be a solder ball. In Figure 7 In this embodiment, the dummy metal component 420 does not directly contact the bottom surface 200b of the packaging substrate 200. However, it is understood that in some embodiments, the dummy metal component 420 may directly contact the bottom surface 200b of the packaging substrate 200. For example... Figure 6-7 In the example shown, the dummy metal part 420 can be formed using a process similar to or the same as that of the surrounding solder balls PSB, which makes it easier to manufacture and saves process steps.

[0041] like Figure 8 and Figure 9 As shown, the dummy metal component 420 can have a cylindrical shape. In Figure 9 In this embodiment, the dummy metal component 420 does not directly contact the bottom surface 200b of the packaging substrate 200. However, it is understood that in some embodiments, the dummy metal component 420 may directly contact the bottom surface 200b of the packaging substrate 200. For example... Figure 6-7In the example shown, the cylindrical dummy metal parts 420 can better control the spacing between the dummy metal parts 420, so as to obtain a suitable spacing and more fully fill the gap 40 with the bottom filler.

[0042] like Figure 10 As shown, each dummy metal component 420 may have strips or bars extending along a first direction D1 and staggered along a second direction D2. Figure 10 In this invention, the capillary bottom packing 410 can be injected into the gap 40 along the first direction D1. Figure 6-10 The illustrated approach can be freely selected according to needs or process requirements, improving the design flexibility of the high heat dissipation efficiency semiconductor device of this invention. For example, a method that simplifies the manufacturing of dummy metal components and reduces manufacturing costs can be chosen.

[0043] Please refer to Figure 11 , Figure 11 This is a cross-sectional schematic diagram of another embodiment of the PoP of the present invention. Figure 11 As shown, PoP 2 similarly includes a bottom package 10 and a top package 20 stacked on the bottom package 10. According to one embodiment, the top package 20 may be a memory package, but is not limited thereto. According to one embodiment, the bottom package 10 may include a semiconductor chip 101 mounted on the package substrate 100 in a flip-chip manner. According to one embodiment, for example, the package substrate 100 may include a three-layer or four-layer embedded trace substrate (ETS), but is not limited thereto. According to one embodiment, the semiconductor chip 101, such as a logic chip or system-on-a-chip, may be electrically connected to the package substrate 100 via multiple connection elements 112, such as copper bumps, pillars, or microbumps, but the connection elements are not limited to these.

[0044] According to one embodiment, a plurality of BGA solder balls SB can be provided on the lower surface of the package substrate 100. For example, the spacing between the BGA solder balls SB on the lower surface of the package substrate 100 may be equal to or less than 0.35 mm, but is not limited thereto. The semiconductor chip 101 may be packaged by an encapsulation 140 (e.g., engineering molding compound).

[0045] According to one embodiment, for example, the top package 20 may include at least one memory chip 201 mounted on the package substrate 200. According to one embodiment, for example, the memory chip 201 may be an HBM or LPDRAM chip, but is not limited thereto. According to one embodiment, for example, the memory chip 201 may be electrically connected to the package substrate 200 via bonding wires 203. The memory chip 201, bonding wires 203, and the top surface 200a of the package substrate 200 are covered or encapsulated by an overlay 240.

[0046] According to one embodiment, the top package 20 is electrically connected to the bottom package 10 via an intermediary layer 30. According to one embodiment, the intermediary layer 30 may be, for example, two cored substrates, but is not limited thereto. The intermediary layer 30 may include interconnect structures 301 electrically connected to through-holes 150, such as copper pillars embedded in the plastic-coated component 140 and disposed around the periphery (outer periphery) of the semiconductor chip 101.

[0047] According to one embodiment, a top package 20 is mounted on an interposer 30 and electrically connected to the interposer 30 via a plurality of peripheral solder balls (PSBs). According to one embodiment, a small gap 40 is formed between the top package 20 and the interposer 30. According to one embodiment, a thermal die (e.g., a dummy silicon die) 50 is disposed on the interposer 30 and surrounded by peripheral solder balls (PSBs). The thermal die 50 can be adhered to the top surface of the interposer 30 using an adhesive layer 510. In one embodiment, the height of the hot die 50 is less than the height of the peripheral solder ball PSB, so that the hot die 50 does not directly contact the bottom surface 200b of the package substrate 200. The hot die 50 can be, for example, a silicon die or a silicon wafer. The thermal conductivity of the hot die 50 is greater than that of air. Therefore, the hot die 50 can conduct heat from the semiconductor chip 101 to the outside more quickly, helping to dissipate heat from the semiconductor chip 101. At the same time, since the hot die 50 does not directly contact the bottom surface 200b of the package substrate 200 (e.g., there is a gap between them), the heat conducted by the hot die 50 will not affect the operation of the memory chip 201 in the top package 20. In another embodiment, the height of the hot die 50 can be substantially equal to the height of the peripheral solder ball PSB, so that the hot die 50 directly contacts the bottom surface 200b of the package substrate 200. In other embodiments, the hot die 50 and the bottom surface 200b of the package substrate 200 can be in indirect contact through a thermal interface material or other thermally conductive material. When the hot die 50 is in direct or indirect contact with the bottom surface 200b of the packaging substrate 200, the hot die 50 can conduct heat from the semiconductor chip 101 to the top package 20, and then dissipate the heat to the outside through the top package 20. This method can be used when the semiconductor chip 101 is the main heat source and the memory chip 201 is not the main heat source, thereby helping to dissipate heat from the semiconductor chip 101, which is the main heat source. Therefore, the present invention allows for free selection of the contact state between the hot die 50 and the top package 20 for different application scenarios, increasing design flexibility.

[0048] According to one embodiment, the hot die 50 may be electrically floating, meaning that no connection is formed below the hot die 50 for electrically connecting the hot die 50 to any other interconnect structure in the interposer layer 30. The heat dissipation die 50 is used to dissipate heat generated by the semiconductor chip 101 because it is more cost-effective. Furthermore, in this embodiment, one or more hot dies 50 may be disposed in the gap 40; or, in other embodiments, multiple dummy metal components 420 may be used in combination with one or more hot dies 50. This not only allows for heat dissipation using the hot die but also utilizes capillary effect to fill the bottom filler within the gap 40, thereby further accelerating heat dissipation and improving heat dissipation efficiency. In one embodiment, multiple hot dies 50 and multiple dummy metal components 420 may be alternately arranged within the gap 40, forming an alternating arrangement of dummy metal component array 420 and hot die 50.

[0049] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Bottom packaging; Top package, stacked on the bottom package, including the top substrate; An interposer layer is disposed between the bottom package and the top package, wherein the top package is electrically connected to the interposer layer via peripheral solder balls; as well as A dummy metal component is disposed on the interposer layer and surrounded by an outer solder ball, wherein the dummy metal component is formed on a corresponding dummy pad on the interposer layer, and wherein the height of each of the dummy metal components is smaller than the height of the outer solder ball; Each of these dummy metal components does not directly contact the bottom surface of the top encapsulation; At least a portion of the dummy pad is electrically connected to the ground trace or grounding structure in the interposer layer.

2. The semiconductor device as claimed in claim 1, characterized in that, Also includes: The capillary bottom filler is disposed in the gap between the intermediate layer and the top encapsulation.

3. The semiconductor device as claimed in claim 2, characterized in that, The capillary bottom filler surrounds and protects the outer solder ball, and the capillary bottom filler is in direct contact with the dummy metal component.

4. The semiconductor device as claimed in claim 1, characterized in that, The dummy metal component includes copper bumps or copper pillars; or, the dummy metal component includes solder balls.

5. The semiconductor device as claimed in claim 1, characterized in that, The top package is a memory package, wherein the memory package includes at least one memory chip mounted on the top substrate.

6. The semiconductor device as claimed in claim 5, characterized in that, The memory chip includes a high-bandwidth memory chip or a low-power DRAM chip.

7. The semiconductor device as claimed in claim 5, characterized in that, The memory chip is electrically connected to the top substrate via bonding leads.

8. The semiconductor device as claimed in claim 1, characterized in that, The bottom package includes a semiconductor chip mounted on the bottom substrate of the bottom package in a flip-chip manner.

9. The semiconductor device as claimed in claim 8, characterized in that, The bottom substrate includes a three- or four-layer coreless embedded wiring substrate.

10. The semiconductor device as claimed in claim 8, characterized in that, The semiconductor chip includes a logic die or a system-on-a-chip, and the semiconductor chip is packaged by a cover.

11. The semiconductor device as claimed in claim 8, characterized in that, The interposer includes interconnect structures that are electrically connected to through-holes embedded in and surrounding the semiconductor chip within a casing.

12. The semiconductor device as claimed in claim 1, characterized in that, Also includes: Hot grains are disposed on the interlayer and surrounded by the outer solder balls.

13. The semiconductor device as claimed in claim 12, characterized in that, The thermal grain is bonded to the top surface of the intermediate layer using an adhesive layer.

14. The semiconductor device as claimed in claim 12, characterized in that, The thermal grains do not directly contact the bottom surface of the top substrate.

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