Semiconductor device

Abstract

Semiconductor devices are disclosed. The semiconductor devices can include an active pattern disposed on a substrate and a source / drain pattern on the active pattern. The source / drain pattern can include a bottom surface in contact with a top surface of the active pattern. The semiconductor devices can also include a channel pattern connected to the source / drain pattern, a gate electrode extending to over the channel pattern, and a fence insulating layer extending from a side surface of the active pattern to an underside surface of the source / drain pattern. A pair of intermediate insulating patterns can be in contact with an inside surface of the fence insulating layer at both sides of the bottom surface of the source / drain pattern and between the active pattern and the source / drain pattern.

Description

[0001] This patent application claims priority to Korean Patent Application No. 10-2020-0181225, filed on December 22, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to a semiconductor device, and more specifically, to a semiconductor device including a field-effect transistor. Background Technology

[0003] Semiconductor devices comprise integrated circuits composed of metal-oxide-semiconductor field-effect transistors (MOS-FETs). To meet the growing demand for semiconductor devices with smaller pattern sizes and reduced design rules, MOS-FETs are being actively scaled down. However, this scaling down of MOS-FETs leads to a degradation in the operational properties of the semiconductor device. Various studies are underway to overcome the technological limitations associated with the scaling down of semiconductor devices and to achieve high-performance semiconductor devices. Summary of the Invention

[0004] An exemplary embodiment of the inventive concept provides a semiconductor device with improved electrical characteristics.

[0005] According to an example embodiment of the inventive concept, a semiconductor device may include: an active pattern on a substrate; a source / drain pattern on the active pattern, the source / drain pattern including a bottom surface contacting the top surface of the active pattern; a channel pattern connected to the source / drain pattern; a gate electrode extending to intersect the channel pattern; a fence insulating layer extending from a side surface of the active pattern to a lower side surface of the source / drain pattern; and a pair of intermediate insulating patterns on both sides of the bottom surface of the source / drain pattern and contacting the inner surface of the fence insulating layer between the active pattern and the source / drain pattern.

[0006] According to an example embodiment of the inventive concept, a semiconductor device may include: a substrate including a PMOSFET region and an NMOSFET region adjacent to each other in a first direction; a first active pattern and a second active pattern, respectively, on the PMOSFET region and the NMOSFET region; a first source / drain pattern on the first active pattern and a second source / drain pattern on the second active pattern; a first gate electrode and a second gate electrode, respectively, intersecting the first active pattern and the second active pattern and extending in the first direction; a first channel pattern connected to the first source / drain pattern and a second channel pattern connected to the second source / drain pattern, each of the first channel pattern and the second channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern stacked sequentially and spaced apart from each other; and a pair of intermediate insulating patterns between the second source / drain pattern and the second active pattern, and on both sides of the bottom surface of the second source / drain pattern that contacts the top surface of the second active pattern. The pair of intermediate insulating patterns may be on the NMOSFET region.

[0007] According to an example embodiment of the inventive concept, a semiconductor device may include: a substrate including a PMOSFET region and an NMOSFET region adjacent to each other in a first direction; a first active pattern and a second active pattern, respectively, in the PMOSFET region and the NMOSFET region; a first source / drain pattern on the first active pattern and a second source / drain pattern on the second active pattern; a first channel pattern connected to the first source / drain pattern and a second channel pattern connected to the second source / drain pattern, each of the first channel pattern and the second channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and spaced apart from each other. The configuration includes: a first barrier insulating layer extending from the side surface of the first active pattern to the lower surface of the first source / drain pattern; a second barrier insulating layer extending from the side surface of the second active pattern to the lower surface of the second source / drain pattern; a pair of intermediate insulating patterns located on both sides of the bottom surface of the second source / drain pattern and between the second active pattern and the second source / drain pattern to contact the inner surface of the second barrier insulating layer; a first gate electrode and a second gate electrode intersecting the first active pattern and the second active pattern respectively, and extending in a first direction, each of the first gate electrode and the second gate electrode including a first portion between the substrate and the first semiconductor pattern, in the first semiconductor pattern. The second portion between the second semiconductor pattern, the third portion between the second semiconductor pattern and the third semiconductor pattern, and the fourth portion on the third semiconductor pattern; inner spacers, respectively between the first to third portions of the second gate electrode and the second source / drain pattern; a first gate insulating layer and a second gate insulating layer, respectively between the first channel pattern and the first gate electrode and between the second channel pattern and the second gate electrode; a first gate spacer and a second gate spacer, respectively on the side surface of the first gate electrode and the side surface of the second gate electrode; a first gate cover pattern and a second gate cover pattern, respectively on the top surface of the first gate electrode and the top surface of the second gate electrode; the first gate cover pattern and the second gate cover pattern; An interlayer insulating layer is provided on a first gate overlay pattern and a second gate overlay pattern; active contacts penetrate the first interlayer insulating layer and are respectively bonded to a first source / drain pattern and a second source / drain pattern; gate contacts penetrate the first interlayer insulating layer and are respectively bonded to a first gate electrode and a second gate electrode; a second interlayer insulating layer is provided on the first interlayer insulating layer; a first metal layer is provided in the second interlayer insulating layer, the first metal layer including first interconnects electrically connected to the active contacts and the gate contacts respectively; a third interlayer insulating layer is provided on the second interlayer insulating layer; and a second metal layer is provided in the third interlayer insulating layer, the second metal layer including second interconnects electrically connected to the first interconnects respectively. Attached Figure Description

[0008] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concept.

[0009] Figures 2A to 2D They are along Figure 1 A sectional view taken from lines A-A', B-B', C-C', and D-D'.

[0010] Figure 3A and Figure 3B It is shown Figure 2C An enlarged sectional view of part Q.

[0011] Figure 3C Is Figure 2B An enlarged planar view taken at the horizontal point of line N-N'.

[0012] Figures 4A to 14D This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept.

[0013] Figure 15A and Figure 15B It is along Figure 1 A cross-sectional view taken along lines A-A' and B-B' to illustrate a semiconductor device according to an exemplary embodiment of the inventive concept. Detailed Implementation

[0014] Example embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings, in which example embodiments are illustrated.

[0015] Figure 1 This is a plan view illustrating a semiconductor device according to an example embodiment of the inventive concept. Figures 2A to 2D They are along Figure 1 A sectional view taken from lines A-A', B-B', C-C', and D-D'. Figure 3A and Figure 3B It is shown Figure 2C An enlarged sectional view of part Q. Figure 3C Is Figure 2B An enlarged planar view taken at the horizontal point of line N-N'.

[0016] Reference Figure 1 and Figures 2A to 2D The logic unit LC can be disposed on the substrate 100. The logic transistors constituting the logic circuit can be disposed on the logic unit LC. The substrate 100 can be a semiconductor substrate formed of or including silicon, germanium, silicon-germanium, etc., and / or a compound semiconductor substrate. As an example, the substrate 100 can be a silicon wafer.

[0017] The logic cell LC may include a PMOSFET region PR and an NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be defined by a second trench TR2 formed in the upper part of the substrate 100. In other words, the second trench TR2 may be placed between the PMOSFET region PR and the NMOSFET region NR. The PMOSFET region PR and the NMOSFET region NR may be separated from each other in a first direction D1, and the second trench TR2 is placed between the PMOSFET region PR and the NMOSFET region NR.

[0018] The first active pattern AP1 and the second active pattern AP2 can be defined by a first trench TR1 formed in the upper part of the substrate 100. The first active pattern AP1 and the second active pattern AP2 can be disposed on each of the PMOSFET region PR and the NMOSFET region NR. The first trench TR1 can be shallower than the second trench TR2. The first active pattern AP1 and the second active pattern AP2 can extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 can be vertical protrusions of the substrate 100.

[0019] The device isolation layer ST can be configured to fill the first trench TR1 and the second trench TR2. The device isolation layer ST may include a silicon oxide layer. The upper portion of the first active pattern AP1 and the upper portion of the second active pattern AP2 may protrude vertically above the device isolation layer ST (e.g., see...). Figure 2D The device isolation layer ST may not cover the upper part of the first active pattern AP1 and the upper part of the second active pattern AP2. The device isolation layer ST may cover the lower surface of the first active pattern AP1 and the lower surface of the second active pattern AP2.

[0020] The insulating layer LIN can be disposed between the device isolation layer ST and the first active pattern AP1, and between the device isolation layer ST and the second active pattern AP2. The insulating layer LIN can be conformally disposed along the first trench TR1 and the second trench TR2. In an example embodiment, the insulating layer LIN can be formed of SiN or SiON, or may include SiN or SiON.

[0021] A first channel pattern CH1 may be disposed on a first active pattern AP1. A second channel pattern CH2 may be disposed on a second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first semiconductor patterns to the third semiconductor patterns SP1, SP2, and SP3 may be separated from each other in the vertical direction (i.e., the third direction D3).

[0022] Each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of silicon (Si), germanium (Ge), and / or silicon-germanium (SiGe), or may include silicon (Si), germanium (Ge), and / or silicon-germanium (SiGe). In an example embodiment, each of the first to third semiconductor patterns SP1, SP2, and SP3 may be formed of crystalline silicon or may include crystalline silicon.

[0023] Multiple first recesses RS1 can be formed in the upper part of the first active pattern AP1. First source / drain patterns SD1 can be respectively disposed in the first recesses RS1. The first source / drain patterns SD1 can be impurity regions of a first conductivity type (e.g., p-type). A first channel pattern CH1 can be placed between each pair of first source / drain patterns SD1. In other words, each pair of first source / drain patterns SD1 can be interconnected with each other through the stacked first semiconductor patterns to third semiconductor patterns SP1, SP2, and SP3 of the first channel patterns CH1.

[0024] Multiple second recesses RS2 can be formed in the upper part of the second active pattern AP2. Second source / drain patterns SD2 can be respectively disposed in the second recesses RS2. The second source / drain patterns SD2 can be impurity regions of a second conductivity type (e.g., n-type). A second channel pattern CH2 can be placed between each pair of second source / drain patterns SD2. In other words, each pair of second source / drain patterns SD2 can be interconnected through the stacked first to third semiconductor patterns SP1, SP2, and SP3 of the second channel patterns CH2.

[0025] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth (SEG) process. As an example, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a top surface located substantially at the same level as the top surface of the third semiconductor pattern SP3. However, in some example embodiments, the top surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the top surface of the third semiconductor pattern SP3.

[0026] The first source / drain pattern SD1 may comprise a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. In this case, a pair of first source / drain patterns SD1 may apply compressive stress to the first channel pattern CH1 between them. The second source / drain pattern SD2 may be formed of the same semiconductor material as the substrate 100 (e.g., Si) or may comprise the same semiconductor material as the substrate 100 (e.g., Si). In an example embodiment, the second source / drain pattern SD2 may be formed of single-crystal silicon or may comprise single-crystal silicon.

[0027] Each of the first source / drain patterns SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 stacked sequentially. (Refer to...) Figure 2A Describe the cross-sectional shape of the first source / drain pattern SD1, which is cut parallel to the second direction D2.

[0028] The first semiconductor layer SEL1 may cover the inner surface of the first recess RS1. The first semiconductor layer SEL1 may have a decreasing thickness in the upward direction. For example, the thickness of the first semiconductor layer SEL1 measured along a third direction D3 at the bottom level of the first recess RS1 may be greater than the thickness of the first semiconductor layer SEL1 measured along a second direction D2 at the top level of the first recess RS1. Due to the cross-sectional profile of the first recess RS1, the first semiconductor layer SEL1 may have a "U" shaped cross-section.

[0029] The second semiconductor layer SEL2 can fill the remaining space of the first recess RS1 except for the first semiconductor layer SEL1. The volume of the second semiconductor layer SEL2 can be larger than the volume of the first semiconductor layer SEL1. In other words, the ratio of the volume of the second semiconductor layer SEL2 to the total volume of the first source / drain pattern SD1 can be greater than the ratio of the volume of the first semiconductor layer SEL1 to the total volume of the first source / drain pattern SD1.

[0030] Each of the first semiconductor layer SEL1 and the second semiconductor layer SEL2 may be formed of silicon germanium (SiGe) or may include silicon germanium (SiGe). Specifically, the first semiconductor layer SEL1 may be configured to have a relatively low germanium concentration. In some example embodiments, the first semiconductor layer SEL1 may be configured to contain only silicon (Si) and no germanium (Ge). The germanium concentration of the first semiconductor layer SEL1 may range from about 0 at% to about 10 at% (“at%” is atomic percentage).

[0031] The second semiconductor layer SEL2 can be configured to have a relatively high germanium concentration. As an example, the germanium concentration of the second semiconductor layer SEL2 can range from about 30 at% to about 70 at%. The germanium concentration of the second semiconductor layer SEL2 can increase towards D3, for example, the germanium concentration can be gradient. For example, the germanium concentration of the second semiconductor layer SEL2 may be about 40 at% near the first semiconductor layer SEL1, but may be about 60 at% at its top level. The change in germanium concentration between the second semiconductor layer SEL2 and the first semiconductor layer SEL1 can be linear or can follow a logarithmic distribution; however, the example embodiment is not limited to this.

[0032] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 may include impurities (e.g., boron) that give the first source / drain pattern SD1 p-type conductivity. In some example embodiments, the concentration of impurities in the second semiconductor layer SEL2 (in at%) may be greater than the concentration of impurities in the first semiconductor layer SEL1. The change in impurity concentration between the second semiconductor layer SEL2 and the first semiconductor layer SEL1 may be linear or may follow a logarithmic distribution; however, the example embodiments are not limited thereto.

[0033] The gate electrode GE can be configured to intersect with the first active pattern AP1 and the second active pattern AP2 and extend in the first direction D1. The gate electrode GE can be arranged in the second direction D2 with a first spacing P1. When viewed in a plan view, each of the gate electrodes GE can be superimposed with the first channel pattern CH1 and the second channel pattern CH2.

[0034] The gate electrode GE may include a first portion P01 disposed between the substrate 100 and the first semiconductor pattern SP1, a second portion P02 disposed between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion P03 disposed between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion P04 on the third semiconductor pattern SP3.

[0035] Return to reference Figure 2A The first to third portions P01, P02, and P03 of the gate electrode GE on the PMOSFET region PR can have different widths. For example, the maximum width of the third portion P03 in the second direction D2 can be greater than the maximum width of the second portion P02 in the second direction D2. The maximum width of the first portion P01 in the second direction D2 can be greater than the maximum width of the third portion P03 in the second direction D2.

[0036] Return to reference Figure 2D The gate electrode GE can be disposed on the top surface TS, bottom surface BS, and opposite side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. In other words, the logic transistor according to this example embodiment can be a three-dimensional field-effect transistor (e.g., a multi-bridge channel field-effect transistor (MBCFET)) in which the gate electrode GE is configured to three-dimensionally surround the channel pattern.

[0037] Return to reference Figure 1 and Figures 2A to 2DA pair of gate spacers GS may be disposed on opposite side surfaces of the fourth portion P04 of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE and in a first direction D1. The top surface of the gate spacers GS may be higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be coplanar with the top surface of the first interlayer insulating layer 110, which will be described below. The gate spacers GS may be formed of at least one of SiCN, SiCON, and SiN, or may include at least one of SiCN, SiCON, and SiN. In some example embodiments, the gate spacers GS may have a multilayer structure comprising at least two layers, each of which is made of SiCN, SiCON, or SiN.

[0038] A gate overlay pattern GP may be disposed on the gate electrode GE. The gate overlay pattern GP may extend along the gate electrode GE and in a first direction D1. The gate overlay pattern GP may be formed of a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below, or may include a material having etch selectivity relative to the first interlayer insulating layer 110 and the second interlayer insulating layer 120, which will be described below. For example, the gate overlay pattern GP may be formed of at least one of SiON, SiCN, SiCON, and SiN, or may include at least one of SiON, SiCN, SiCON, and SiN.

[0039] The gate insulating layer GI can be disposed between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate insulating layer GI can cover the top surface TS, bottom surface BS, and opposite side surface SW of each of the first to third semiconductor patterns SP1, SP2, and SP3. The gate insulating layer GI can cover the top surface of the device isolation layer ST below the gate electrode GE (e.g., see...). Figure 2D ).

[0040] In some example embodiments, the gate insulating layer GI may include a silicon oxide layer, a silicon oxynitride layer, and / or a high-k dielectric layer. The high-k dielectric layer may be formed of at least one high-k dielectric material whose dielectric constant is higher than that of silicon oxide, or may include at least one high-k dielectric material whose dielectric constant is higher than that of silicon oxide. As an example, the high-k dielectric material may be formed from at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate, or may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and / or lead zinc niobate. In some example embodiments, the semiconductor device may include a negative capacitance (NC) FET using a negative capacitor. For example, the gate insulating layer GI may include a ferroelectric layer exhibiting ferroelectric material properties and a paraelectric layer exhibiting paraelectric material properties.

[0041] Ferroelectric layers can have negative capacitance, and paraelectric layers can have positive capacitance. When two or more capacitors are connected in series, and each capacitor has positive capacitance, the total capacitance can be smaller than the capacitance of each individual capacitor. Conversely, when at least one of the capacitors connected in series has negative capacitance, the total capacitance of the series-connected capacitors can be positive and can be larger than the absolute value of each individual capacitor.

[0042] When a ferroelectric layer with negative capacitance and a paraelectric layer with positive capacitance are connected in series, the total capacitance of the series-connected ferroelectric and paraelectric layers can be increased. Due to this increase in total capacitance, transistors including ferroelectric layers can have a subthreshold swing (SS) of less than 60 mV / dec at room temperature.

[0043] The ferroelectric layer can possess ferroelectric material properties. The ferroelectric layer can be formed from at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide, or can include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and / or lead zirconium titanium oxide. Here, hafnium zirconium oxide can be hafnium oxide doped with zirconium (Zr). Optionally, hafnium zirconium oxide can be a compound composed of hafnium (Hf), zirconium (Zr), and / or oxygen (O).

[0044] The ferroelectric layer may also include dopants. For example, dopants may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of dopant in the ferroelectric layer may vary depending on the ferroelectric material included in the ferroelectric layer.

[0045] When the ferroelectric layer includes hafnium oxide, the dopant in the ferroelectric layer may include at least one of, for example, gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al) and yttrium (Y).

[0046] When the dopant includes aluminum (Al), the aluminum content in the ferroelectric layer can range from about 3 at% to about 8 at% ("at%" is atomic percentage). Here, the aluminum content in the dopant can be the ratio of the number of aluminum atoms to the number of hafnium atoms and aluminum atoms.

[0047] When the dopant includes silicon (Si), the silicon content in the ferroelectric layer can range from about 2 at% to about 10 at%. When the dopant includes yttrium (Y), the yttrium content in the ferroelectric layer can range from about 2 at% to about 10 at%. When the dopant includes gadolinium (Gd), the gadolinium content in the ferroelectric layer can range from about 1 at% to about 7 at%. When the dopant includes zirconium (Zr), the zirconium content in the ferroelectric layer can range from about 50 at% to about 80 at%.

[0048] The paraelectric layer may possess paraelectric material properties. The paraelectric layer may be formed from, for example, at least one of silicon oxide and / or a high-k metal oxide, or may include, for example, at least one of silicon oxide and / or a high-k metal oxide. The metal oxide that can be used as the paraelectric layer may include, for example, at least one of hafnium oxide, zirconium oxide, and / or aluminum oxide, but the inventive concept is not limited to these examples.

[0049] The ferroelectric layer and the paraelectric layer can be formed of the same material or may include the same material. The ferroelectric layer may have ferroelectric material properties, but the paraelectric layer may not have ferroelectric material properties. For example, in the case where both the ferroelectric and paraelectric layers contain hafnium oxide, the crystal structure of the hafnium oxide in the ferroelectric layer may be different from the crystal structure of the hafnium oxide in the paraelectric layer.

[0050] The ferroelectric layer can exhibit ferroelectric material properties, for example, these properties may only be present when the ferroelectric layer is within a specific thickness range. In some example embodiments, the ferroelectric layer may have a thickness range of 0.5 to 10 nm, but the inventive concept is not limited to this example. Since the thickness of the ferroelectric layer associated with the ferroelectric material properties varies depending on the type of ferroelectric material, the thickness of the ferroelectric layer can be varied depending on the type of ferroelectric material.

[0051] As an example, the gate insulating layer may include a single ferroelectric layer. As another example, the gate insulating layer may include multiple ferroelectric layers spaced apart from each other. The gate insulating layer may have a multilayer structure in which multiple ferroelectric layers and multiple paraelectric layers are stacked alternately.

[0052] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may be disposed on the gate insulating layer GI and may be adjacent to the first to third semiconductor patterns SP1, SP2, and SP3. The first metal pattern may include a work function metal that can be used to adjust the threshold voltage of the transistor. By adjusting the thickness and composition of the first metal pattern, a transistor with a desired threshold voltage can be realized. For example, the first to third portions P01, P02, and P03 of the gate electrode GE may be composed of the first metal pattern or the work function metal.

[0053] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include at least one metal selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo), and nitrogen (N). In some example embodiments, the first metal pattern may also include carbon (C). The first metal pattern may include a plurality of stacked active power metal layers.

[0054] The second metal pattern may include a metal material whose resistance is lower than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). For example, the fourth portion P04 of the gate electrode GE may include the first metal pattern and the second metal pattern on the first metal pattern.

[0055] Return to reference Figure 2B The inner spacer IP can be disposed on the NMOSFET region NR. Each of the inner spacer IPs can be positioned between the second source / drain pattern SD2 and the corresponding portions of the first to third portions P01, P02, and P03 of the gate electrode GE. The inner spacer IP can be in direct contact with the second source / drain pattern SD2. Each of the first to third portions P01, P02, and P03 of the gate electrode GE can be separated from the second source / drain pattern SD2 by the inner spacer IP. (Refer to...) Figures 3A to 3C A more detailed description of the inner spacer IP.

[0056] A first interlayer insulating layer 110 may be disposed on a substrate 100. The first interlayer insulating layer 110 may cover a gate spacer GS and a first source / drain pattern SD1 and a second source / drain pattern SD2. The first interlayer insulating layer 110 may have a top surface substantially coplanar with the top surface of the gate overlay pattern GP and the top surface of the gate spacer GS. A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110 to cover the gate overlay pattern GP. In some example embodiments, at least one of the first interlayer insulating layer 110 and the second interlayer insulating layer 120 may include a silicon oxide layer.

[0057] A pair of separator structures DB, facing each other in the second direction D2, can be disposed on both sides of the logic cell LC. The separator structures DB can extend in the first direction D1 and parallel to the gate electrode GE. The spacing between adjacent separator structures DB and the gate electrode GE can be equal to the first spacing P1.

[0058] The separator structure DB can be configured to penetrate the first interlayer insulating layer 110 and the second interlayer insulating layer 120, and can extend into the first active pattern AP1 and the second active pattern AP2. The separator structure DB can penetrate the upper part of each of the first active pattern AP1 and the second active pattern AP2. The separator structure DB can actively distinguish the PMOSFET region PR and NMOSFET region NR of the logic cell LC from the active regions of the adjacent logic cell.

[0059] The sacrificial layer SAL adjacent to the separator structure DB can be disposed on each of the first active pattern AP1 and the second active pattern AP2. The sacrificial layers SAL can be stacked and separated from each other. Each of the sacrificial layers SAL can be located at the same level as the corresponding portion of the first to third portions P01, P02, and P03 of the gate electrode GE. The separator structure DB can be configured to penetrate the sacrificial layer SAL.

[0060] The sacrificial layer SAL can be formed of silicon germanium (SiGe) or may include silicon germanium (SiGe). The germanium concentration of each in the sacrificial layer SAL can be in the range of about 10 at% to about 30 at%. The germanium concentration of the sacrificial layer SAL can be higher than the germanium concentration of the first semiconductor layer SEL1 described above.

[0061] The active contact AC can be configured to penetrate the first interlayer insulation layer 110 and the second interlayer insulation layer 120, and can be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2, respectively. A pair of active contacts AC can be respectively disposed on both sides of the gate electrode GE. When viewed in a plan view, the active contact AC can have a strip shape that extends in the first direction D1.

[0062] The active contact AC can be a self-aligned contact. For example, the active contact AC can be formed using a gate overlay pattern GP and a gate spacer GS via a self-aligned process. In some example embodiments, the active contact AC can cover at least a portion of the side surface of the gate spacer GS. Although not shown, the active contact AC can be configured to cover a portion of the top surface of the gate overlay pattern GP.

[0063] The silicide pattern SC can be placed between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2, respectively. The active contact AC can be electrically connected to the source / drain pattern SD1 or SD2 through the silicide pattern SC. The silicide pattern SC can be formed from at least one of the metal silicide materials (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide), or can include at least one of the metal silicide materials (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide).

[0064] The gate contact GC, electrically connected to the gate electrode GE, can be configured to penetrate the second interlayer insulating layer 120 and the gate cover pattern GP. (See reference...) Figure 2B Each of the active contacts AC has an upper region adjacent to the gate contact GC that can be filled with an upper insulating pattern UIP. Therefore, process defects (e.g., short circuits) that can occur when the gate contact GC comes into contact with its adjacent active contact AC can be prevented or reduced.

[0065] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may be formed of at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt, or may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may be configured to cover the side and bottom surfaces of the conductive pattern FM. In some example embodiments, the barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may be formed of at least one selected from titanium, tantalum, tungsten, nickel, cobalt, and platinum, or may include at least one of titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one selected from titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), nickel nitride (NiN), cobalt nitride (CoN), and platinum nitride (PtN).

[0066] The first metal layer M1 can be disposed in the third interlayer insulating layer 130. The first metal layer M1 may include a first lower interconnect M1_R, a second lower interconnect M1_I, and a lower via VI1. The lower via VI1 can be disposed below the first lower interconnect M1_R and the second lower interconnect M1_I.

[0067] Each of the first lower interconnects M1_R can extend in the second direction D2 to pass through the logic cell LC. Each of the first lower interconnects M1_R can be a power line. For example, a drain voltage VDD or a source voltage VSS can be applied to the first lower interconnect M1_R.

[0068] Reference Figure 1 A first cell boundary CB1 extending in the second direction D2 can be defined within the region of the logic cell LC. A second cell boundary CB2 extending in the second direction D2 can be defined within the region of the logic cell LC opposite to the first cell boundary CB1. A first lower interconnect M1_R with an applied drain voltage VDD (e.g., power supply voltage) can be disposed on the first cell boundary CB1. The first lower interconnect M1_R with an applied drain voltage VDD can extend along the first cell boundary CB1 and in the second direction D2. A first lower interconnect M1_R with an applied active voltage VSS (e.g., ground voltage) can be disposed on the second cell boundary CB2. The first lower interconnect M1_R with an applied active voltage VSS can extend along the second cell boundary CB2 and in the second direction D2.

[0069] The second lower interconnect M1_I can be disposed on the first direction D1 between the first lower interconnect M1_R, to which the drain voltage VDD and source voltage VSS are respectively applied. Each of the second lower interconnects M1_I can be a linear pattern or a strip pattern extending on the second direction D2. The second lower interconnects M1_I can be arranged to be separated from each other by a second spacing P2 on the first direction D1. The second spacing P2 can be smaller than the first spacing P1.

[0070] The lower via VI1 can be disposed below the first lower interconnect M1_R and the second lower interconnect M1_I of the first metal layer M1. The lower via VI1 can be placed between the active contact AC and the first lower interconnect M1_R, and between the active contact AC and the second lower interconnect M1_I, respectively. The lower via VI1 can also be placed between the gate contact GC and the second lower interconnect M1_I, respectively.

[0071] The lower interconnect M1_R or M1_I of the first metal layer M1 and the lower via VI1 thereunder can be formed by separate processes. In other words, each of the lower interconnect M1_R or M1_I and the lower via VI1 can be a single damascene process. The semiconductor device according to some example embodiments can be fabricated using a sub-20nm process.

[0072] The second metal layer M2 can be disposed in the fourth interlayer insulating layer 140. The second metal layer M2 may include upper interconnects M2_I. Each of the upper interconnects M2_I can be a linear pattern or a strip pattern extending in the first direction D1. In other words, the upper interconnects M2_I can extend parallel to each other in the first direction D1. When viewed in a plan view, the upper interconnects M2_I can be parallel to the gate electrode GE. The upper interconnects M2_I can be arranged with a third spacing in the second direction D2. The third spacing can be smaller than the first spacing P1. The third spacing can be larger than the second spacing P2.

[0073] The second metal layer M2 may also include an upper via VI2. The upper via VI2 may be located below the upper interconnect M2_I. The upper via VI2 may be located between the lower interconnect M1_R and M1_I and the upper interconnect M2_I, respectively.

[0074] The upper interconnect M2_I of the second metal layer M2 and the upper via VI2 below it can be formed by the same process and can be formed as a single object. In other words, the upper interconnect M2_I and the upper via VI2 of the second metal layer M2 can be formed by a dual damascene process.

[0075] The lower interconnects M1_R and M1_I of the first metal layer M1 and the upper interconnect M2_I of the second metal layer M2 can be formed of the same material or different conductive materials, or may include the same material or different conductive materials. For example, the lower interconnects M1_R and M1_I and the upper interconnect M2_I can be formed of at least one of the following metallic materials (e.g., aluminum, copper, tungsten, molybdenum, or cobalt), or may include at least one of the following metallic materials (e.g., aluminum, copper, tungsten, molybdenum, or cobalt).

[0076] In some example embodiments, although not shown, additional metal layers (e.g., a third metal layer, a fourth metal layer, a fifth metal layer, etc.) may be stacked on the fourth interlayer insulating layer 140. Each of the stacked metal layers may include wiring.

[0077] Reference Figure 2CThe first barrier insulating layer SF1 and the second barrier insulating layer SF2 can be configured to cover the substrate insulating layer LIN exposed by the device isolation layer ST. The first barrier insulating layer SF1 can cover the side surface of the first active pattern AP1, and the second barrier insulating layer SF2 can cover the side surface of the second active pattern AP2. The barrier insulating layers SF1 and SF2 can have a bottom surface placed in the second trench TR2 and in contact with the device isolation layer ST. Each of the first barrier insulating layer SF1 and the second barrier insulating layer SF2 can be formed of at least one of SiOCN, SiON, and SiCN, or can include at least one of SiOCN, SiON, and SiCN. As an example, each of the first barrier insulating layer SF1 and the second barrier insulating layer SF2 can be an amorphous insulating layer.

[0078] Reference Figure 2C , Figure 3A , Figure 3B and Figure 3C The regions adjacent to the first source / drain pattern SD1 and the second source / drain pattern SD2 are described in more detail.

[0079] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be respectively disposed in the first recess RS1 and the second recess RS2. Referring to the second source / drain pattern SD2, the lower part PB of the second source / drain pattern SD2 can be disposed in the second recess RS2.

[0080] The bottom surface of each of the first recess RS1 and the second recess RS2 may be lower than the top of the corresponding active pattern in the first active pattern AP1 and the second active pattern AP2. In other words, the first active pattern AP1 and the second active pattern AP2 may include an edge portion EP protruding above the bottom surface of the first recess RS1 and the second recess RS2. The edge portion EP may protrude along the insulating liner LIN or in the third direction D3. The insulating liner LIN may cover the side surface of the edge portion EP. As an example, the top of the insulating liner LIN may be at substantially the same level as the top of the edge portion EP. Compared to the insulating liner LIN, the first fence insulating layer SF1 and the second fence insulating layer SF2 may protrude in the third direction D3.

[0081] The second source / drain pattern SD2 may include a bottom surface BF in contact with the second active pattern AP2. A pair of intermediate insulating patterns RQ may be disposed on both sides of the bottom surface BF of the second source / drain pattern SD2. In other words, the pair of intermediate insulating patterns RQ may be separated from each other, and the bottom surface BF of the second source / drain pattern SD2 is disposed between them. At least a portion of the intermediate insulating pattern RQ may be disposed in the second recess RS2.

[0082] Each of a pair of intermediate insulating patterns RQ can be disposed between the second active pattern AP2 and the second source / drain pattern SD2, and can contact the inner surface of the second fence insulating layer SF2. In other words, each of the pair of intermediate insulating patterns RQ can occupy the space defined by the top surface of the second active pattern AP2, the side surface of the lower portion PB of the second source / drain pattern SD2, and the inner surface of the second fence insulating layer SF2. In some example embodiments, each of the pair of intermediate insulating patterns RQ can contact the adjacent inner surface of the edge portion EP. When a liner insulating layer LIN is provided therein, each of the intermediate insulating patterns RQ can be connected to the upper portion of the liner insulating layer LIN.

[0083] The upper portion PT of the second source / drain pattern SD2 can extend onto each of the pair of intermediate insulating patterns RQ to cover the pair of intermediate insulating patterns RQ. Not only can the pair of intermediate insulating patterns RQ be provided, but the bottom surface BF of the second source / drain pattern SD2 can also be provided to cover the second active pattern AP2. The pair of intermediate insulating patterns RQ can be provided below one of the second source / drain patterns SD2. In some example embodiments, in a cross-sectional view taken in a first direction D1 as the extension direction of the gate electrode GE, the pair of intermediate insulating patterns RQ can cover approximately 10% to approximately 30% of the top surface of the second active pattern AP2. The contact area between the second source / drain pattern SD2 and the second active pattern AP2 can be reduced by the pair of intermediate insulating patterns RQ, thus reducing the leakage current between adjacent second source / drain patterns SD2.

[0084] Compared to PMOSFET transistors, NMOSFET transistors disposed in the NMOSFET region can have a high doping concentration or may contain impurities with long diffusion lengths. Therefore, the bottom leakage current leaking through the second active pattern AP2 above the second source / drain pattern SD2 increases. According to an example embodiment of the inventive concept, this bottom leakage current can be reduced by the intermediate insulating pattern RQ, thus improving the operating characteristics of the semiconductor device. Furthermore, since the intermediate insulating pattern RQ does not cover the entire top surface of the second active pattern AP2, the second source / drain pattern SD2 can be directly connected to the second active pattern AP2; therefore, the second source / drain pattern SD2 can be epitaxially grown from the second active pattern AP2 without substantial difficulty.

[0085] The intermediate insulating pattern RQ can be locally disposed within a limited region (e.g., on the NMOSFET region NR) and may not be disposed on the PMOSFET region PR. That is, the intermediate insulating pattern RQ may not be disposed between the first active pattern AP1 and the first source / drain pattern SD1. In other words, the lower side surface of the first source / drain pattern SD1 may contact the first active pattern AP1 and the first barrier insulating layer SF1. Therefore, the first contact area between the first active pattern AP1 and the first source / drain pattern SD1 may be larger than the second contact area between the second active pattern AP2 and the second source / drain pattern SD2.

[0086] The intermediate insulating pattern RQ and the inner spacer IP can be formed using the same process and can comprise substantially the same materials. In some example embodiments, the intermediate insulating pattern RQ and the inner spacer IP can comprise one of SiN, SiCN, and SiOCN. The intermediate insulating pattern RQ and the inner spacer IP can be crystalline insulating layers. The intermediate insulating pattern RQ and the inner spacer IP can be formed of a different material than the second fence insulating layer SF2, or can comprise a different material than the second fence insulating layer SF2. In other words, the intermediate insulating pattern RQ and the inner spacer IP can be formed of one of SiN, SiCN, and SiOCN, or can comprise one of SiN, SiCN, and SiOCN, and the second fence insulating layer SF2 can be formed of another of SiN, SiCN, and SiOCN, or can comprise another of SiN, SiCN, and SiOCN. As an example, the intermediate insulating pattern RQ and the inner spacer IP can be formed of SiN, or can comprise SiN, and the second fence insulating layer SF2 can be formed of SiOCN, or can comprise SiOCN.

[0087] As an example, the inner spacers IP can be separated from each other on the third-direction D3, and the first semiconductor pattern SP1 and the second semiconductor pattern SP2 are placed between the inner spacers IP. The intermediate insulating pattern RQ can be positioned at the same level as the lowermost inner spacer IP_b of the inner spacers IP. Figures 3A to 3C As shown, a pair of intermediate insulation patterns RQ may include a first intermediate insulation pattern RQ_R and a second intermediate insulation pattern RQ_L. For example... Figure 3A As shown, the first intermediate insulation pattern RQ_R and the second intermediate insulation pattern RQ_L can have symmetrical or identical shapes, but in some example embodiments, such as Figure 3B As shown, one of the first intermediate insulation pattern RQ_R and the second intermediate insulation pattern RQ_L can be larger than the other or different from the other.

[0088] like Figure 3CAs shown, each of the pair of intermediate insulating patterns RQ can connect a pair of bottommost inner spacers IP_b to each other, the pair of bottommost inner spacers IP_b being spaced apart from each other, and a second source / drain pattern SD2 is positioned between the pair of bottommost inner spacers IP_b. Therefore, when viewed in a plan view, the second source / drain pattern SD2 can be surrounded by the pair of bottommost inner spacers IP_b and the pair of intermediate insulating patterns RQ. Optionally, at least a portion of the intermediate insulating pattern RQ may not be connected to the bottommost inner spacers IP_b.

[0089] Figures 4A to 14D This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an exemplary embodiment of the inventive concept. Specifically, Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 12A , Figure 13A and Figure 14A Is with Figure 1 The sectional view corresponding to line A-A'. Figure 9A , Figure 10A , Figure 11A , Figure 12B , Figure 13B and Figure 14B Is with Figure 1 The sectional view corresponding to line B-B'. Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 12C and Figure 14C Is with Figure 1 The sectional view corresponding to line C-C'. Figure 4B , Figure 5B , Figure 6B , Figure 7C , Figure 12D , Figure 13C and Figure 14D Is with Figure 1 The sectional view corresponding to line D-D'.

[0090] Reference Figure 4A and Figure 4BA substrate 100 can be configured to include a PMOSFET region PR and an NMOSFET region NR. A sacrificial layer SAL and an active layer ACL can be alternately stacked on the substrate 100. The sacrificial layer SAL can be formed of at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), or may include at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the active layer ACL can be formed of at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), or may include at least one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0091] For example, the sacrificial layer SAL can be formed of silicon germanium (SiGe) or may include silicon germanium (SiGe), and the active layer ACL can be formed of silicon (Si) or may include silicon (Si). The germanium concentration in each of the sacrificial layers SAL can be in the range of about 10 at% to about 30 at%.

[0092] Mask patterns MAP can be formed on the PMOSFET region PR and NMOSFET region NR of the substrate 100, respectively. The mask pattern MAP can be a linear pattern or a strip pattern extending in the second direction D2.

[0093] A first patterning process, in which a mask pattern MAP is used as an etching mask, can be performed to form a first trench TR1 defining a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 can be formed on a PMOSFET region PR and an NMOSFET region NR, respectively. Each of the first active pattern AP1 and the second active pattern AP2 may include a sacrificial layer SAL and an active layer ACL alternately stacked on its upper portion.

[0094] A second patterning process can be performed on substrate 100 to form a second trench TR2 defining a PMOSFET region PR and an NMOSFET region NR. The second trench TR2 can be formed to be deeper than the first trench TR1. Subsequently, an insulating liner LIN can be formed on substrate 100 to conformally cover the first trench TR1 and the second trench TR2. In some example embodiments, the insulating liner LIN can be formed of SiN or SiON, or may include SiN or SiON.

[0095] Reference Figure 5A and Figure 5B A device isolation layer ST can be formed on the substrate 100 to fill the first trench TR1 and the second trench TR2. For example, an insulating layer can be formed on the substrate 100 to cover the first active pattern AP1 and the second active pattern AP2. The device isolation layer ST can be formed by recessing the insulating layer until the sacrificial layer SAL is exposed.

[0096] The device isolation layer ST may be formed of an insulating material (e.g., silicon oxide) or may include an insulating material (e.g., silicon oxide). Each of the first active pattern AP1 and the second active pattern AP2 may include an upper portion protruding above the device isolation layer ST. For example, the upper portion of each of the first active pattern AP1 and the second active pattern AP2 may protrude vertically above the device isolation layer ST.

[0097] Reference Figure 6A and Figure 6B A sacrificial pattern PP can be formed on the substrate 100 to intersect with the first active pattern AP1 and the second active pattern AP2. Each of the sacrificial patterns PP can be a linear pattern or a strip pattern extending in the first direction D1. The sacrificial patterns PP can be arranged at specific intervals in the second direction D2.

[0098] In detail, the steps of forming the sacrificial pattern PP may include: forming a sacrificial layer on a substrate 100; forming a hard mask pattern MP on the sacrificial layer; and using the hard mask pattern MP as an etch mask to pattern the sacrificial layer. The sacrificial layer may be formed of polysilicon or may include polysilicon.

[0099] A pair of gate spacers GS can be formed on opposite side surfaces of the sacrificial pattern PP. The step of forming the gate spacers GS may include: conformally forming a gate spacer layer on the substrate 100; and anisotropically etching the gate spacer layer. The gate spacer layer may be formed of at least one of SiCN, SiCON, and SiN, or may include at least one of SiCN, SiCON, and SiN. In some example embodiments, the gate spacer layer may be a multilayer structure including at least two of SiCN, SiCON, and SiN.

[0100] Reference Figures 7A to 7C A first mask pattern HM1 can be formed to cover the NMOSFET region NR, and then a first recess RS1 can be formed in the upper part of the first active pattern AP1. During the formation of the first recess RS1, the device isolation layer ST located on both sides of each of the first active patterns AP1 can be partially recessed. Specifically, the first recess RS1 can be formed by etching the upper part of the first active pattern AP1 using a hard mask pattern MP and a gate spacer GS as an etching mask. A first fence insulating layer SF1 can be formed to cover the PMOSFET region PR. The first fence insulating layer SF1 can be formed by forming an insulating layer to cover the PMOSFET region PR and then performing an etching process to expose the first recess RS1. The first fence insulating layer SF1 can be formed of at least one of SiOCN, SiON, and SiCN, or can include at least one of SiOCN, SiON, and SiCN.

[0101] Reference Figure 8A and Figure 8B A first source / drain pattern SD1 can be formed in the first recess RS1. Specifically, a first selective epitaxial growth (SEG) process can be performed in which the inner surface of the first recess RS1 is used as a seed layer to form a first semiconductor layer SEL1. The first semiconductor layer SEL1 can be grown using the first semiconductor pattern to the third semiconductor pattern SP1, SP2 and SP3 exposed through the first recess RS1 and the substrate 100 as seed crystals. As an example, the first SEG process may include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0102] The first semiconductor layer SEL1 may be formed of a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100, or may include a semiconductor material (e.g., SiGe) having a lattice constant greater than that of the substrate 100. The first semiconductor layer SEL1 may be formed with a relatively low germanium concentration. In some example embodiments, the first semiconductor layer SEL1 may be configured to contain only silicon (Si) and no germanium (Ge). The germanium concentration of the first semiconductor layer SEL1 may be in the range of about 0 at% to about 10 at%.

[0103] A second semiconductor layer SEL2 can be formed by performing a second SEG process on the first semiconductor layer SEL1. The second semiconductor layer SEL2 can be formed to completely fill the first recess RS1. The second semiconductor layer SEL2 can be configured to have a relatively high germanium concentration. As an example, the germanium concentration of the second semiconductor layer SEL2 can be in the range of about 30 at% to about 70 at%.

[0104] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can form a first source / drain pattern SD1. The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can be doped with impurities in situ during the first SEG process and the second SEG process. Optionally, after forming the first source / drain pattern SD1, the first source / drain pattern SD1 can be doped with impurities. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type).

[0105] Reference Figure 9A and Figure 9BThe first mask pattern HM1 can be removed, and a second mask pattern HM2 can be formed to cover the PMOSFET region PR. A second recess RS2 can be formed in the upper part of the second active pattern AP2. During the formation of the second recess RS2, the device isolation layer ST located on both sides of each of the second active patterns AP2 can be partially recessed. A second fence insulating layer SF2 can be formed to cover the NMOSFET region NR. The second fence insulating layer SF2 can be formed by forming an insulating layer to cover the NMOSFET region NR and then performing an etching process to expose the second recess RS2. The second fence insulating layer SF2 can be formed of at least one of SiOCN, SiON, and SiCN, or can include at least one of SiOCN, SiON, and SiCN. In some example embodiments, with reference to Figure 7A and Figure 7B In the described process for forming the first fence insulating layer SF1, the second fence insulating layer SF2 may be formed together with the first fence insulating layer SF1. In some example embodiments, in the process for forming the gate spacer GS, at least a portion of the first fence insulating layer SF1 and the second fence insulating layer SF2 may be formed together with the gate spacer GS.

[0106] Reference Figure 10A and Figure 10B The sacrificial layer SAL on the NMOSFET region NR can be selectively etched to form a horizontal recess LR extending from the second recess RS2. The formation of the horizontal recess LR can be performed using an etchant selected for selectively etching the sacrificial layer SAL.

[0107] Reference Figure 11A and Figure 11B An inner spacer IP can be formed to fill the horizontal recess LR. The inner spacer IP can be formed by forming an insulating layer to cover the second recess RS2 and performing an etching process on the insulating layer. During the formation of the inner spacer IP, a pair of intermediate insulating patterns RQ can be formed on the top surface of the second active pattern AP2. The intermediate insulating patterns RQ can be formed as shown in the reference... Figure 3A and Figure 3B The described edge portion EP is adjacent. For example, due to the inner surface of the edge portion EP and the second fence insulating layer SF2, a portion of the insulating layer deposited to form the inner spacer IP can remain on the top surface of the second active pattern AP2, and such a remaining portion of the insulating layer can form the intermediate insulating pattern RQ. The inner spacer IP and the intermediate insulating pattern RQ can be formed from a material having a different etch selectivity or etch rate than the second fence insulating layer SF2. For example, the intermediate insulating pattern RQ and the inner spacer IP can comprise SiN, and the second fence insulating layer SF2 can comprise SiOCN.

[0108] Reference Figure 12A , Figure 12B , Figure 12C and Figure 12D A second source / drain pattern SD2 can be formed in the second recess RS2. Specifically, the second source / drain pattern SD2 can be formed using a SEG process in which the inner surface of the second recess RS2 serves as a seed layer. In some example embodiments, the second source / drain pattern SD2 can be formed of the same semiconductor material as the substrate 100 (e.g., Si), or can include the same semiconductor material as the substrate 100 (e.g., Si). The second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type). Due to its lateral growth, the second source / drain pattern SD2 can be formed to cover the intermediate insulating pattern RQ. The second mask pattern HM2 can then be removed.

[0109] A first interlayer insulating layer 110 can be formed to cover a first source / drain pattern SD1 and a second source / drain pattern SD2, a hard mask pattern MP, and a gate spacer GS. In some example embodiments, the first interlayer insulating layer 110 may be formed of silicon oxide or may include silicon oxide. The first interlayer insulating layer 110 can be planarized to expose the top surface of the sacrificial pattern PP. The planarization of the first interlayer insulating layer 110 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. All hard mask patterns MP can be removed during the planarization process. Therefore, the top surface of the first interlayer insulating layer 110 may be coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0110] Exposed sacrificial patterns PP can be selectively removed. As a result of removing the sacrificial patterns PP, upper trenches ET1 can be formed to expose the side surfaces of the sacrificial layer SAL. Simultaneously, some of the sacrificial patterns PP may not be removed. For example, sacrificial patterns PP located at cell boundaries may not be removed. Specifically, by forming a mask layer on the sacrificial patterns PP that should not be removed, accidental removal of the sacrificial patterns PP can be prevented or reduced.

[0111] Reference Figure 13A , Figure 13B and Figure 13CThe sacrificial layer SAL, exposed through the upper trench ET1, located on the PMOSFET region PR and the NMOSFET region NR, can be selectively removed. Specifically, an etching process that selectively etches only the sacrificial layer SAL can be performed to remove only the sacrificial layer SAL, leaving only the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3. Due to the selective removal of the sacrificial layer SAL, only the first semiconductor pattern to the third semiconductor pattern SP1, SP2, and SP3 can be left on each of the first active pattern AP1 and the second active pattern AP2. Hereinafter, the empty region formed by removing the sacrificial layer SAL will be referred to as the third recess ET2. The third recess ET2 can be defined between the first semiconductor pattern and the third semiconductor pattern SP1, SP2, and SP3.

[0112] Reference Figure 14A , Figure 14B , Figure 14C and Figure 14D A gate insulating layer GI can be conventionally formed in the upper trench ET1 and the third recess ET2. A gate electrode GE can be formed on the gate insulating layer GI. The gate electrode GE can be formed to fill the upper trench ET1 and the third recess ET2. Specifically, the gate electrode GE may include filling the first to third portions P01, P02, and P03 of the third recess ET2. The gate electrode GE may also include filling the fourth portion P04 of the upper trench ET1. A gate overlay pattern GP can be formed on the gate electrode GE.

[0113] Return to reference Figure 1 and Figures 2A to 2D A second interlayer insulating layer 120 may be formed on the first interlayer insulating layer 110. The second interlayer insulating layer 120 may include a silicon oxide layer. An active contact AC may be formed to penetrate the second interlayer insulating layer 120 and the first interlayer insulating layer 110 and be electrically connected to a first source / drain pattern SD1 and a second source / drain pattern SD2. A gate contact GC may be formed to penetrate the second interlayer insulating layer 120 and the gate overlay pattern GP and be electrically connected to the gate electrode GE.

[0114] A pair of separator structures DB can be formed on both sides of the logic cell LC. In some example embodiments, the separator structure DB can be formed to penetrate the second interlayer insulating layer 120, the remainder of the sacrificial pattern PP, and the upper portion of the active pattern AP1 or AP2 below the sacrificial pattern PP. The separator structure DB can be formed of at least one of an insulating material (e.g., silicon oxide or silicon nitride), or can include at least one of an insulating material (e.g., silicon oxide or silicon nitride). The upper portion of each of the active contacts AC adjacent to the gate contact GC can be removed, and then the upper portion of each of the active contacts AC adjacent to the gate contact GC can be filled with the upper insulating pattern UIP.

[0115] A third interlayer insulating layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer insulating layer 130. A fourth interlayer insulating layer 140 may be formed on the third interlayer insulating layer 130. A second metal layer M2 may be formed in the fourth interlayer insulating layer 140.

[0116] Figure 15A and Figure 15B It is along Figure 1 The cross-sectional views taken along lines A-A' and B-B' illustrate a semiconductor device according to some exemplary embodiments of the inventive concept.

[0117] According to some embodiments, a first active pattern AP1 may include a first channel pattern CH1 with a fin-like pattern protruding from a substrate 100. A second active pattern AP2 may include a second channel pattern CH2 with a fin-like pattern protruding from a substrate 100. The first channel pattern CH1 and the second channel pattern CH2 may be semiconductor patterns formed from the upper portion of the substrate 100 and may be connected to the substrate 100. Each of the gate electrodes GE may extend along the protruding top surface of the first channel pattern CH1 and the second channel pattern CH2.

[0118] A first source / drain pattern SD1 can be disposed in a first recess between the first channel patterns CH1. A second source / drain pattern SD2 can be disposed in a second recess between the second channel patterns CH2. Other components can be configured to have the same characteristics as the reference. Figures 2A to 2D The described features are essentially the same.

[0119] In some exemplary embodiments of the semiconductor device according to the inventive concept, an intermediate insulating pattern can be disposed on the NMOSFET region between the active pattern and the source / drain pattern, in which case the bottom leakage current can be reduced. Therefore, the electrical characteristics of the semiconductor device can be improved. Furthermore, the intermediate insulating pattern may not cover the entire top surface of the active pattern; thus, the intermediate insulating pattern may not hinder or reduce obstacles to the epitaxial growth of the source / drain pattern.

[0120] While exemplary embodiments of the inventive concept have been specifically shown and described, those skilled in the art will understand that variations in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: Active pattern, on the substrate; Source / drain pattern, on an active pattern, the source / drain pattern includes a bottom surface that contacts the top surface of the active pattern; Channel pattern, connected to source / drain pattern; The gate electrode extends to intersect with the channel pattern; The fence insulation layer extends from the side surface of the active pattern to the underside surface of the source / drain pattern; as well as A pair of intermediate insulating patterns are located on both sides of the bottom surface of the source / drain pattern, and the pair of intermediate insulating patterns are in contact with the inner surface of the fence insulation layer between the active pattern and the source / drain pattern.

2. The semiconductor device according to claim 1, wherein, The pair of intermediate insulation patterns comprises a material different from that of the fence insulation layer.

3. The semiconductor device according to claim 1, wherein, The intermediate insulation pattern includes one of SiN, SiON, SiCN, and SiOCN.

4. The semiconductor device according to claim 1, wherein, The pair of intermediate insulating patterns are separated from each other and the bottom surface of the source / drain pattern is placed between the pair of intermediate insulating patterns.

5. The semiconductor device according to claim 4, wherein, Each of the pair of intermediate insulating patterns is in contact with the source / drain pattern, the active pattern, and the fence insulation layer.

6. The semiconductor device according to claim 4, wherein, The active pattern includes a recess in its upper part, and The lower portions of the pair of intermediate insulating patterns and the source / drain patterns are in the recess.

7. The semiconductor device according to claim 1, wherein, The bottom surface of the pair of intermediate insulating patterns and the source / drain patterns is covered by the top surface of the source pattern. In a cross-sectional view taken along the extension direction of the gate electrode, the pair of intermediate insulating patterns cover 10% to 30% of the top surface of the active pattern.

8. The semiconductor device of claim 1, wherein the semiconductor device comprises: An insulating layer is placed between the fence insulation layer and the active pattern. The pair of intermediate insulating patterns are connected to the liner insulating layer.

9. The semiconductor device according to claim 1, wherein, Channel patterns comprise semiconductor patterns stacked and spaced apart from each other. The semiconductor device also includes an inner spacer disposed between the gate electrode and the source / drain pattern, and The pair of intermediate insulating patterns comprise the same material as the inner spacer.

10. The semiconductor device according to claim 9, wherein, The inner spacers are spaced apart from each other in a direction perpendicular to the substrate, and a semiconductor pattern is placed between the inner spacers. The lowest inner spacer in the inner spacers is at the same level as the pair of intermediate insulating patterns.

11. The semiconductor device according to claim 9, wherein, The lowest inner spacer in the inner spacers is connected to the pair of intermediate insulating patterns.

12. A semiconductor device, the semiconductor device comprising: The substrate includes a PMOSFET region and an NMOSFET region that are adjacent to each other in a first direction; The first active pattern and the second active pattern are respectively located in the PMOSFET region and the NMOSFET region; The first source / drain pattern on the first active pattern and the second source / drain pattern on the second active pattern; The first gate electrode and the second gate electrode intersect with the first active pattern and the second active pattern, respectively, and extend in the first direction; A first channel pattern connected to a first source / drain pattern and a second channel pattern connected to a second source / drain pattern, each of the first channel pattern and the second channel pattern comprising a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern stacked sequentially and separated from each other; as well as A pair of intermediate insulating patterns are located between the second source / drain pattern and the second active pattern, on both sides of the bottom surface of the second source / drain pattern that contacts the top surface of the second active pattern, and on the NMOSFET region.

13. The semiconductor device according to claim 12, wherein, The second contact area between the second source / drain pattern and the second active pattern is smaller than the first contact area between the first source / drain pattern and the first active pattern.

14. The semiconductor device of claim 12, wherein the semiconductor device comprises: The fence insulation layer extends from the side surface of the second active pattern to the underside surface of the second source / drain pattern. The pair of intermediate insulating patterns are in contact with the inner surface of the fence insulation layer.

15. The semiconductor device of claim 12, wherein the semiconductor device comprises: The inner spacer is located between the second gate electrode and the second source / drain pattern. The pair of intermediate insulating patterns comprises the same material as the inner spacer.

16. The semiconductor device according to claim 15, wherein, The inner spacers are separated from each other in a direction perpendicular to the substrate, and the first semiconductor pattern and the second semiconductor pattern are located between the inner spacers. The lowest inner spacer is at the same level as the pair of intermediate insulating patterns.

17. The semiconductor device according to claim 16, wherein, The lowest inner spacer in the inner spacers is connected to the pair of intermediate insulating patterns.

18. A semiconductor device, the semiconductor device comprising: The substrate includes a PMOSFET region and an NMOSFET region that are adjacent to each other in a first direction; The first active pattern and the second active pattern are respectively located in the PMOSFET region and the NMOSFET region; The first source / drain pattern on the first active pattern and the second source / drain pattern on the second active pattern; A first channel pattern connected to a first source / drain pattern and a second channel pattern connected to a second source / drain pattern, each of the first channel pattern and the second channel pattern comprising a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern stacked sequentially and separated from each other; A first fence insulation layer extends from the side surface of the first active pattern to the underside surface of the first source / drain pattern; The second fence insulation layer extends from the side surface of the second active pattern to the lower surface of the second source / drain pattern; A pair of intermediate insulating patterns are in contact with the inner surface of the second fence insulating layer on both sides of the bottom surface of the second source / drain pattern and between the second active pattern and the second source / drain pattern. The first gate electrode and the second gate electrode intersect with the first active pattern and the second active pattern respectively, and extend in a first direction. Each of the first gate electrode and the second gate electrode includes a first portion between the substrate and the first semiconductor pattern, a second portion between the first semiconductor pattern and the second semiconductor pattern, a third portion between the second semiconductor pattern and the third semiconductor pattern, and a fourth portion on the third semiconductor pattern. Inner spacers are respectively located between the first and third portions of the second gate electrode and the second source / drain pattern; The first gate insulating layer and the second gate insulating layer are respectively located between the first channel pattern and the first gate electrode and between the second channel pattern and the second gate electrode; The first gate spacer and the second gate spacer are respectively located on the side surface of the first gate electrode and the side surface of the second gate electrode. The first gate cover pattern and the second gate cover pattern are respectively on the top surface of the first gate electrode and the top surface of the second gate electrode. A first interlayer insulating layer is applied over the first gate cover pattern and the second gate cover pattern. An active contact penetrates the first interlayer insulation layer and is respectively bonded to the first source / drain pattern and the second source / drain pattern; The gate contact penetrates the first interlayer insulating layer and is respectively bonded to the first gate electrode and the second gate electrode; The second interlayer insulation layer is on top of the first interlayer insulation layer; A first metal layer, in a second interlayer insulating layer, includes first interconnects electrically connected to an active contact and a gate contact, respectively; The third interlayer insulation layer is on top of the second interlayer insulation layer; as well as The second metal layer, within the third interlayer insulating layer, includes second interconnects that are electrically connected to the first interconnects.

19. The semiconductor device according to claim 18, wherein, The lowest inner spacer is at the same level as the pair of intermediate insulating patterns.

20. The semiconductor device of claim 19, wherein, The lowest inner spacer in the inner spacers is connected to the pair of intermediate insulating patterns.

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