Transient voltage suppression device and manufacturing method thereof

Abstract

Disclosed is a transient voltage suppression device and a manufacturing method thereof, comprising: a semiconductor substrate; an isolation layer and an epitaxial layer located on the semiconductor substrate; a plurality of isolation structures, penetrating the epitaxial layer and extending into the isolation layer, dividing the device into a first region, a second region and a third region in the lateral direction; a plurality of first groove structures, located in the first region and the third region, penetrating the epitaxial layer, the isolation layer and extending into the semiconductor substrate; a well region, located in the epitaxial layer of the first region; a first injection region and a second injection region, located in the first region and the second region; a third injection region, located in the epitaxial layer on both sides of the well region, and the first injection region is located on both sides of the second injection region in the well region. The present application leads the negative electrode of the silicon-controlled rectifier unit and the anode of the diode from the back side of the device through the first groove structure, and the first interconnection line above the epitaxial layer is not limited, so that the electrode width of the positive electrode of the silicon-controlled rectifier unit can be increased, and the current density per unit area can be reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a transient voltage suppression device and a manufacturing method thereof. Background Art

[0002] As integrated circuit technology continues to develop, device size is becoming smaller and smaller and the operating voltage is becoming lower and lower. At the same time, device operation is becoming faster and faster and the operating frequency is becoming higher and higher. Therefore, it is more difficult to implement transient voltage suppression devices (TVS) or electrostatic discharge (ESD) protection devices to meet the needs of today's integrated circuits. The smaller the capacitance of TVS or ESD devices, the better, and the breakdown voltage of TVS or EDS devices is determined by the operating voltage of the integrated circuit, which is generally slightly higher than the operating voltage of the integrated circuit. Therefore, for integrated circuits with low operating voltages, TVS or ESD devices must provide low breakdown voltage and low capacitance to meet the requirements of low voltage and high speed, while also meeting the requirements of the smallest possible chip size, a larger peak-to-peak current Ipp in the breakdown direction, and a smaller clamping voltage.

[0003] In existing TVS devices, at least one lateral silicon-controlled rectifier (SCR) and one lateral PN diode are integrated. The power supply terminal Vcc or input / output terminal (I / O) and ground terminal GND of the TVS device are all led out from the front of the semiconductor device. Since both the SCR and the diode are lateral structures, in order to improve the current capacity, a multi-finger comb design is usually adopted. Each finger is very thin, which has high requirements for metal wiring. It is easy for the metal electrode to be too thin and the current density per unit area is too high, causing the device to burn out. In addition, the electrodes of the TVS device are also led out from the front, which is not suitable for the back bonding packaging process and has a high cost. Summary of the invention

[0004] In view of the above problems, the object of the present invention is to provide a transient voltage suppression device and a manufacturing method thereof, wherein the negative electrode of the silicon-controlled rectifier unit and the anode of the diode are led out from the back side of the device through a first groove structure, and there is no restriction on the metal lead of the positive electrode of the silicon-controlled rectifier unit, which can increase the electrode width, reduce the current density per unit area, and improve the chip area utilization.

[0005] According to a first aspect of the present invention, there is provided a transient voltage suppression device, comprising: a semiconductor substrate having a first conductivity type; an isolation layer located on the semiconductor substrate; an epitaxial layer located on the isolation layer; a plurality of isolation structures penetrating the epitaxial layer and extending into the isolation layer, wherein the plurality of isolation structures divide the transient voltage suppression device into a plurality of regions in a lateral direction, wherein the plurality of regions include a first region, a second region and a third region, wherein the second region and the third region are provided on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is away from the first region, and the The third region is located at the outermost side of the transient voltage suppression device; a plurality of first trench structures are located in the first region and the third region, penetrate the epitaxial layer, the isolation layer and extend into the semiconductor substrate; a well region is located in the first region and extends from the surface of the epitaxial layer toward the semiconductor substrate; a first injection region is located in the well region of the first region and in the second region and has a second conductivity type; a second injection region is located in the well region of the first region and in the second region and has a first conductivity type; a third injection region is located in the epitaxial layer on both sides of the well region of the first region; wherein, in the well region, the first injection region is located on both sides of the second injection region.

[0006] Preferably, the first region includes at least one silicon-controlled rectifier unit, the silicon-controlled rectifier unit includes a first triode, a second triode, a series resistor and a clamping diode, and the second region includes a diode.

[0007] Preferably, when the first region includes a plurality of silicon-controlled rectifier units, the plurality of silicon-controlled rectifier units are connected in parallel.

[0008] Preferably, when the second region and the third region are disposed on both sides of the first region, the diodes in the second regions on both sides are connected in parallel.

[0009] Preferably, the epitaxial layer has the second conductivity type, the well region has the first conductivity type, and the third implantation region has the second conductivity type.

[0010] Preferably, the well region extends from a surface of the epitaxial layer into the epitaxial layer, and the first trench structure is located on both sides of the well region.

[0011] Preferably, the first implantation region and the second implantation region are located in a well region of the first region and in an epitaxial layer of the second region.

[0012] Preferably, the first transistor includes a first injection region in the well region close to the side of the silicon-controlled rectifier unit, a well region and a third injection region close to the side of the silicon-controlled rectifier unit; the second transistor includes a well region, an epitaxial layer and an outer diffusion region of a first trench structure close to the side of the silicon-controlled rectifier unit; the clamping diode includes a well region and a third injection region away from the side of the silicon-controlled rectifier unit; the diode includes a first injection region, an epitaxial layer and a second injection region in the second region.

[0013] Preferably, the epitaxial layer has a first conductivity type, the well region has a second conductivity type, and the third implantation region has a first conductivity type.

[0014] Preferably, the well region extends from the surface of the epitaxial layer into the isolation layer, and the first trench structure penetrates the well region and the isolation layer and extends into the semiconductor substrate.

[0015] Preferably, the first implantation region and the second implantation region are located in the epitaxial layer of the first region and in the epitaxial layer of the second region.

[0016] Preferably, the first transistor includes a first injection region close to one side of the silicon-controlled rectifier unit, an epitaxial layer and a well region close to one side of the silicon-controlled rectifier unit; the second transistor includes an epitaxial layer, a well region close to one side of the silicon-controlled rectifier unit and an outer diffusion region of a first trench structure close to one side of the silicon-controlled rectifier unit; the clamping diode includes a well region and an epitaxial layer away from one side of the silicon-controlled rectifier unit; the diode includes a first injection region, an epitaxial layer and a second injection region in the second region.

[0017] Preferably, the first trench structure in the first region is the emitter of the second triode and is electrically connected to the semiconductor substrate via the first trench structure; the anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.

[0018] Preferably, the first trench structure extends into the semiconductor substrate to a depth of 1 μm to 10 μm.

[0019] Preferably, the first trench structure includes a first trench and a filling material located in the first trench, the filling material is polysilicon or amorphous silicon, and the filling material has a dopant of a first conductivity type.

[0020] Preferably, the dopant of the filling material diffuses outward through the sidewall and the bottom of the first trench to form an out-diffusion region around the first trench.

[0021] Preferably, the second injection region in the second region is arranged to overlap or not overlap with the adjacent isolation structure.

[0022] Preferably, the first conductivity type is P type, the second conductivity type is N type, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor; or the first conductivity type is N type, the second conductivity type is P type, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is a NIP transistor.

[0023] Preferably, the transient voltage suppression device also includes: a first electrode, located on a surface of the semiconductor substrate away from the epitaxial layer; a first interconnection line, the first interconnection line connecting the first injection region, the second injection region in the first region, and the second injection region in the second region; at least one second interconnection line, at least one second interconnection line respectively connecting the first injection region in the second region and the first trench structure in the third region.

[0024] Preferably, the first interconnection line is connected to one of a power source and a ground, and at least one of the second interconnection lines is connected to the other of the power source and the ground via the first trench structure, the semiconductor substrate, and the first electrode.

[0025] Preferably, the semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the filling material located in the first trench is a heavily doped structure, the first injection region is a heavily doped structure, the second injection region is a heavily doped structure, and the third injection region is a heavily doped structure.

[0026] Preferably, the resistivity of the semiconductor substrate is 0.0015 Ω·cm to 0.01 Ω·cm.

[0027] Preferably, the resistivity of the epitaxial layer is 10 Ω·cm to 200 Ω·cm, and the thickness is 1 μm to 10 μm.

[0028] Preferably, the isolation structure comprises a second trench and an insulating material filled in the second trench, and the second trench penetrates the epitaxial layer and extends into the isolation layer.

[0029] According to another aspect of the present invention, a method for manufacturing a transient voltage suppression device is provided, comprising: providing a semiconductor substrate, the semiconductor substrate having a first conductivity type; sequentially forming an isolation layer and an epitaxial layer on the semiconductor substrate; forming a plurality of isolation structures, the isolation structures penetrating the epitaxial layer and extending into the isolation layer, the plurality of isolation structures dividing the transient voltage suppression device into a plurality of regions in a lateral direction, the plurality of regions comprising a first region, a second region and a third region, wherein the second region and the third region are provided on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is away from the first region, and the The third region is located at the outermost side of the transient voltage suppression device; a plurality of first trench structures are formed in the first region and the third region, and the plurality of first trench structures penetrate the epitaxial layer, the isolation layer and extend into the semiconductor substrate; a well region is formed in the first region, and the well region extends from the surface of the epitaxial layer toward the semiconductor substrate; a first injection region is formed in the first region and the second region, and the first injection region has a second conductivity type; a second injection region is formed in the first region and the second region, and the second injection region has a first conductivity type; a third injection region is formed in the epitaxial layer on both sides of the well region in the first region; wherein, in the well region, the first injection region is located on both sides of the second injection region.

[0030] Preferably, at least one silicon-controlled rectifier unit is formed in the first region, the silicon-controlled rectifier unit comprising a first triode, a second triode, a series resistor and a clamping diode, and a diode is formed in the second region.

[0031] Preferably, when a plurality of silicon-controlled rectifier units are formed in the first region, the plurality of silicon-controlled rectifier units are connected in parallel.

[0032] Preferably, when the second region and the third region are disposed on both sides of the first region, the diodes in the second regions on both sides are connected in parallel.

[0033] Preferably, the epitaxial layer has the second conductivity type, the well region has the first conductivity type, and the third implantation region has the second conductivity type.

[0034] Preferably, the well region extends from a surface of the epitaxial layer into the epitaxial layer, and the first trench structure is located on both sides of the well region.

[0035] Preferably, the first implantation region and the second implantation region are located in a well region of the first region and in an epitaxial layer of the second region.

[0036] Preferably, the first transistor includes a first injection region in the well region close to the side of the silicon-controlled rectifier unit, a well region, and a third injection region in the well region close to the side of the silicon-controlled rectifier unit; the second transistor includes a well region, an epitaxial layer, and an outer diffusion region of a first trench structure close to the side of the silicon-controlled rectifier unit; the clamping diode includes a well region and a third injection region away from the side of the silicon-controlled rectifier unit; the diode includes a first injection region, an epitaxial layer, and a second injection region in the second region.

[0037] Preferably, the epitaxial layer has a first conductivity type, the well region has a second conductivity type, and the third implantation region has a first conductivity type.

[0038] Preferably, the well region extends from the surface of the epitaxial layer into the isolation layer, and the first trench structure penetrates the well region, the epitaxial layer and the isolation layer, and extends into the semiconductor substrate.

[0039] Preferably, the first implantation region and the second implantation region are located in the epitaxial layer of the first region and in the epitaxial layer of the second region.

[0040] Preferably, the first transistor includes a first injection region close to one side of the silicon-controlled rectifier unit, an epitaxial layer and a well region close to one side of the silicon-controlled rectifier unit; the second transistor includes an epitaxial layer, a well region close to one side of the silicon-controlled rectifier unit and an outer diffusion region of a first trench structure close to one side of the silicon-controlled rectifier unit; the clamping diode includes a well region and an epitaxial layer away from one side of the silicon-controlled rectifier unit; the diode includes a first injection region, an epitaxial layer and a second injection region in the second region.

[0041] Preferably, the first trench structure in the first region is the emitter of the second triode and is electrically connected to the semiconductor substrate via the first trench structure; the anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.

[0042] Preferably, the first trench structure extends into the semiconductor substrate to a depth of 1 μm to 10 μm.

[0043] Preferably, forming the first trench structure comprises: forming a first trench; and disposing a filling material in the first trench, wherein the filling material is polysilicon or amorphous silicon, wherein the filling material has a dopant of the second conductivity type.

[0044] Preferably, the dopant of the filling material diffuses outward through the sidewall and the bottom of the first trench to form an out-diffusion region around the first trench.

[0045] Preferably, the second injection region in the second area is arranged to overlap or not overlap with the adjacent isolation structure.

[0046] Preferably, the first conductivity type is P type, the second conductivity type is N type, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor; or the first conductivity type is N type, the second conductivity type is P type, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is a NIP transistor.

[0047] Preferably, the manufacturing method also includes: forming a first electrode on a surface of the semiconductor substrate away from the epitaxial layer; forming a first interconnect line and at least one second interconnect line, the first interconnect line connecting the first injection region, the second injection region and the second injection region in the first region; at least one second interconnect line respectively connects the first injection region in the second region and the first trench structure in the third region.

[0048] Preferably, the manufacturing method further comprises: connecting the first interconnection line to one of a power source and a ground, and connecting at least one of the second interconnection lines to the other of the power source and the ground via the first trench structure, the semiconductor substrate, and the first electrode.

[0049] Preferably, the semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the filling material located in the first trench is a heavily doped structure, the first injection region is a heavily doped structure, the second injection region is a heavily doped structure, and the third injection region is a heavily doped structure.

[0050] Preferably, the resistivity of the semiconductor substrate is 0.0015Ω.cm to 0.01Ω.cm.

[0051] Preferably, the resistivity of the epitaxial layer is 10 Ω.cm to 200 Ω.cm, and the thickness is 3 μm to 10 μm.

[0052] Preferably, forming the isolation structure comprises: forming a plurality of second trenches, wherein the second trenches penetrate the epitaxial layer and extend into the isolation layer; and filling the second trenches with an insulating material.

[0053] The transient voltage suppression device and the manufacturing method thereof provided in the embodiment of the present invention lead out the negative electrode of the silicon-controlled rectifier unit and the anode of the diode from the back side of the device through the first trench structure. The first trench structure includes a polycrystalline with a first conductive type dopant. The first interconnection line above the epitaxial layer has no restrictions, which can increase the electrode width of the positive electrode of the silicon-controlled rectifier unit, reduce the current density per unit area, and improve the chip area utilization.

[0054] Furthermore, the first trench structure extends into the semiconductor substrate, and the cathode of the silicon-controlled rectifier unit and the anode of the diode can be led out from the back side of the device, and a back side bonding process can be used for packaging, thereby reducing wire bonding and packaging costs.

[0055] Furthermore, the positive electrode pad of the silicon-controlled rectifier unit can be directly formed above the silicon-controlled rectifier unit, thereby improving chip area utilization.

[0056] Furthermore, a third injection region is formed outside the well region to reduce the trigger voltage of the silicon-controlled rectifier unit.

[0057] Furthermore, the second injection region in the second area overlaps with the isolation structure, which can reduce the PN junction area and lower the capacitance of the lateral diode. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0059] Figure 1 A cross-sectional schematic diagram showing a transient voltage suppression device according to a first embodiment of the present invention;

[0060] Figure 2 A cross-sectional schematic diagram showing a transient voltage suppression device according to a second embodiment of the present invention;

[0061] Figure 3 Schematic diagrams showing circuits of transient voltage suppression devices according to first and second embodiments of the present invention. DETAILED DESCRIPTION

[0062] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0063] The specific implementation of the present invention is further described in detail below in conjunction with the drawings and examples.

[0064] Figure 1 FIG. 2 is a cross-sectional schematic diagram of a transient voltage suppression device provided by a first embodiment of the present invention. Figure 1 As shown, the transient voltage suppression device 100 includes a semiconductor substrate 101, an isolation layer 110 located on the semiconductor substrate 101, an epitaxial layer 120 located on the isolation layer 110, a plurality of isolation structures 130, a plurality of first trench structures 140, a well region 150, and a first implantation region 151, a second implantation region 152, and a third implantation region 153.

[0065] In this embodiment, the semiconductor substrate 101 has a first conductivity type, and the epitaxial layer 120 has a second conductivity type. The first conductivity type is N-type, and the second conductivity type is P-type. Of course, in different embodiments, the conductivity types may be opposite, for example, the first conductivity type is P-type, and the second conductivity type is N-type.

[0066] In some embodiments, the semiconductor substrate 101 is a heavily doped structure, and the epitaxial layer 120 is a lightly doped structure. For example, the semiconductor substrate 101 is a heavily doped N+ type substrate, and the epitaxial layer 120 is a lightly doped P- type epitaxial layer.

[0067] In a preferred embodiment, the resistivity of the semiconductor substrate 101 is 0.0015 Ω·cm to 0.01 Ω·cm. The resistivity of the epitaxial layer 120 is 10 Ω·cm to 200 Ω·cm, and the thickness is 1 μm to 10 μm.

[0068] See also Figure 1 , a plurality of isolation structures 130 penetrate the epitaxial layer 120 and extend into the isolation layer 110, the plurality of isolation structures 130 divide the epitaxial layer 120 into a plurality of regions in a lateral direction, the plurality of regions include a first region, a second region and a third region, wherein the second region and the third region are arranged on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is away from the first region, and the third region is located at the outermost side of the transient voltage suppression device.

[0069] Figure 1 Only the second area and the third area are shown to be located on the left side of the first area for illustration. The second area and the third area may also be located on the right side of the first area. Furthermore, the second area and the third area may be arranged on both the left and right sides of the first area. The third areas on both sides are located on the outermost sides of the transient voltage suppression device.

[0070] In this embodiment, the isolation structure 130 includes a second trench 131 and an insulating material 132 filled in the second trench, wherein the second trench 131 penetrates the epitaxial layer 120 and extends into the isolation layer 110. The insulating material 132 includes silicon dioxide. The material of the isolation layer 110 includes silicon dioxide (SiO2). The thickness of the isolation layer 110 is generally 1 to 5 μm.

[0071] A plurality of first trench structures 140 penetrate the epitaxial layer 120 and the isolation layer 110 and extend into the semiconductor substrate 101. Each first trench structure 140 includes a first trench 141 and a filling material 142 located in the first trench 141, wherein the filling material 142 has a dopant of a first conductivity type. The filling material 142 is polycrystalline silicon or amorphous silicon. The dopant of the filling material 142 diffuses outward through the sidewall and bottom of the first trench 141, forming an outdiffusion region 143 around the first trench 141. The first trench structure extends into the semiconductor substrate 101 to a depth of 1 μm to 10 μm.

[0072] Each trench unit includes a plurality of first trench structures 140, the widths of the plurality of first trench structures 140 are the same, and the spacings between the plurality of first trench structures 140 in the same trench unit are the same. Figure 1 In the embodiment, each trench unit has 5 first trench structures. In fact, the number of first trench structures 140 in each trench unit is not limited, for example, it can be 4 to 20. The width of the first trench structure 140 is generally 0.5 to 2 um.

[0073] A plurality of first trench structures 140 are located in the first region and the third region.

[0074] The well region 150 is located in the epitaxial layer 120 of the first region and between the plurality of trench units in the first region. The well region 150 has a first conductivity type. For example, the well region 150 is an N-type well region. The ion implantation dose of the well region 150 is, for example, 1E11 to 5E13 cm -2 .

[0075] The first injection region 151 is formed in the well region 150 of the first region and the epitaxial layer 120 of the second region, and has the second conductivity type; the second injection region 152 is formed in the well region 150 of the first region and the epitaxial layer 120 of the second region, and has the first conductivity type; the third injection region 153 is formed in the epitaxial layer 120 on both sides of the well region 150 of the first region, and has the second conductivity type, and the third injection region 153 has a certain distance from the first trench structure 140. Among them, in the well region 150, the first injection region 151 is located on both sides of the second injection region 152. The first injection region 151, the second injection region 152 and the third injection region 153 are all heavily doped structures. For example, the first injection region 151 is heavily doped P+ type, the second injection region 152 is heavily doped N+ type, and the third injection region 153 is heavily doped P+ type.

[0076] In a preferred embodiment, the ion implantation dose of the first implantation region 151 is 4E14-2E16 cm -2 The ion implantation dose of the second implantation region 152 is 2E15-5E16 cm -2 The ion implantation dose of the third implantation region 153 is 4E14-2E16cm -2 .

[0077] The first region includes at least one silicon-controlled rectifier unit (SCR unit). When the first region includes a plurality of silicon-controlled rectifier units, the plurality of silicon-controlled rectifier units are connected in parallel.

[0078] In this embodiment, two SCR units are used as an example for explanation, but it is not limited to this. The two SCR units are connected in parallel. The three trench units in the first area divide the first area into a first block and a second block. Among them, an SCR unit is formed in the first block and the second block respectively, and each SCR unit includes a first triode (PNP), a second triode (NPN), a series resistor R and a clamping diode ZD.

[0079] In each block, the first injection region 151, the well region 150 and the third injection region 153 near the side of the silicon-controlled rectifier unit formed in each block in the well region 150 constitute a first triode (PNP), and the well region 150, the epitaxial layer 120 and the outer diffusion region 143 of the first trench structure 140 near the side of the silicon-controlled rectifier unit constitute a second triode (NPN). The well region 150 between the first injection region 151 and the second injection region 152 constitutes a series resistor R, and the well region 150 and the third injection region 153 away from the side of the silicon-controlled rectifier unit constitute a clamping diode ZD. The breakdown voltage of the transient voltage suppression device is mainly determined by the doping concentration of the well region 150. In this embodiment, the side of the silicon-controlled rectifier unit is the left side of the SCR unit formed in the block as an example for explanation, but it is not limited to this. Different blocks can also form different sides of the SCR unit in the block.

[0080] In the second region, the first implant region 151 , the epitaxial layer 120 , and the second implant region 152 form a lateral diode (PIN).

[0081] In a preferred embodiment, the second implantation region 152 in the second region overlaps with the isolation structure 130 , which can reduce the PN junction area and lower the parasitic capacitance of the lateral diode (PIN).

[0082] In this embodiment, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor. Of course, in different embodiments, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is a NIP transistor.

[0083] When the second region and the third region are disposed on both sides of the first region, the lateral diodes (PIN) in the second regions on both sides are connected in parallel.

[0084] See also Figure 1The transient voltage suppression device further includes a first interconnection line 161 and at least one second interconnection line 162, a dielectric layer 170 located on the epitaxial layer 120, a contact hole 171 in the dielectric layer 170, and a first electrode 180 located on the back of the semiconductor substrate 101, wherein the contact hole 171 in the dielectric layer 170 exposes the first injection region 151 and the second injection region 152, wherein the first interconnection line 161 is connected to the first injection region 151 and the second injection region 152 in the first region and the second injection region 152 in the second region through the contact hole 171 in the dielectric layer 170. Each of the second interconnections 162 is connected to the first injection region 151 in the second region and the first trench structure 140 in the third region through the contact hole 171 in the dielectric layer 170. In this embodiment, the first interconnection line 161 is connected to the power supply Vcc, and the second interconnection line 162 is connected to the ground GND via the first trench structure 140, the semiconductor substrate 101, and the first electrode 180 on the back of the semiconductor substrate 101.

[0085] In other preferred embodiments, the first interconnection line 161 is connected to the ground GND, and the second interconnection line 162 is connected to the power source Vcc via the first trench structure 140 , the semiconductor substrate 101 , and the first electrode 180 on the back side of the semiconductor substrate 101 .

[0086] Figure 3 The circuit diagram of the transient voltage suppression device of the embodiment of the present invention is shown. The diode (PIN) is connected between the power supply Vcc and the ground GND, the cathode of the diode (PIN) is connected to the power supply Vcc, and the anode of the diode (PIN) is connected to the ground GND; the emitter of the first transistor (PNP) is connected to the power supply Vcc, the base is connected to the power supply Vcc via the series resistor R, and the collector is connected to the base of the second transistor (NPN); the collector of the second transistor (NPN) is connected to the power supply Vcc via the series resistor R, and the emitter is connected to the ground GND. The clamping diode ZD is connected between the base of the first transistor (PNP) and the base of the second transistor (NPN). The first transistor (PNP) and the second transistor (NPN) constitute a lateral silicon-controlled rectifier unit. The startup voltage of the silicon-controlled rectifier unit is determined by the withstand voltage of the clamping diode ZD and the sum of the forward voltage between the base B and the emitter E of the second transistor (NPN). The series resistor R is composed of the body resistance of the well region 150.

[0087] Since the silicon-controlled rectifier unit removes the width limitation of the positive electrode metal lead, increases the width of the positive electrode, reduces the current density per unit area, improves the chip area utilization, increases the number of SCR units per unit area, and can improve the peak-to-peak current Ipp capability per unit area.

[0088] The transient voltage suppression device provided in the embodiment of the present invention leads the negative electrode of the silicon-controlled rectifier unit and the anode of the diode out from the back side of the device through the first groove structure. There is no restriction on the metal lead of the positive electrode of the silicon-controlled rectifier unit, which can increase the electrode width of the positive electrode of the silicon-controlled rectifier unit, reduce the current density per unit area, and improve the chip area utilization.

[0089] Furthermore, the first trench structure extends into the semiconductor substrate, and the cathode of the silicon-controlled rectifier unit and the anode of the diode can be led out from the back side of the device, and a back side bonding process can be used for packaging, thereby reducing wire bonding and packaging costs.

[0090] Furthermore, the positive electrode pad of the silicon-controlled rectifier unit can be directly formed above the silicon-controlled rectifier unit, thereby improving chip area utilization.

[0091] Furthermore, a third injection region is formed outside the well region to reduce the trigger voltage of the silicon-controlled rectifier unit.

[0092] Furthermore, the second injection region in the second area overlaps with the isolation structure, which can reduce the PN junction area and lower the capacitance of the lateral diode.

[0093] Figure 2 FIG. 2 is a cross-sectional schematic diagram of a transient voltage suppression device provided by a second embodiment of the present invention. Figure 1 Compared with the first embodiment shown, the epitaxial layer 120 of the transient voltage suppression device has a first conductivity type.

[0094] In this embodiment, the semiconductor substrate 101 has a first conductivity type, and the epitaxial layer 120 has a first conductivity type, wherein the first conductivity type is N type, and of course in different embodiments, the first conductivity type is P type.

[0095] In some embodiments, the semiconductor substrate 101 is a heavily doped structure, and the epitaxial layer 120 is a lightly doped structure. For example, the semiconductor substrate 101 is a heavily doped N+ type substrate, and the epitaxial layer 120 is a lightly doped N- type epitaxial layer.

[0096] The well region 150 is located in the first region, extends from the surface of the epitaxial layer 120 to the isolation layer 120, and has the second conductivity type. For example, the well region 150 is a P-type well region.

[0097] The first implantation region 151 is formed in the epitaxial layer of the first region and the second region, and has the second conductivity type; the second implantation region 152 is formed in the epitaxial layer 120 of the first region and the second region, and has the first conductivity type; the third implantation region 153 is formed in the epitaxial layer 120 on both sides of the well region 150 of the first region, and has the first conductivity type. The first implantation region 151, the second implantation region 152, and the third implantation region 153 are all heavily doped structures. For example, the first implantation region 151 is heavily doped P+ type, the second implantation region is heavily doped N+ type, and the third implantation region is heavily doped N+ type.

[0098] The plurality of first trench structures 140 in the first region penetrate the well region 150 , the epitaxial layer 120 , the isolation layer 110 and extend into the semiconductor substrate 101 .

[0099] The first region includes at least one silicon-controlled rectifier unit (SCR unit). When the first region includes a plurality of silicon-controlled rectifier units, the plurality of silicon-controlled rectifier units are connected in parallel.

[0100] In this embodiment, two SCR units are used as an example for explanation, but it is not limited to this. The two SCR units are connected in parallel. The three trench units in the first area divide the first area into a first block and a second block. Among them, an SCR unit is formed in the first block and the second block respectively, and each SCR unit includes a first triode (PNP), a second triode (NPN), a series resistor R and a clamping diode ZD.

[0101] In each block, the first injection region 151, the epitaxial layer 120 and the well region 150 near one side of the silicon-controlled rectifier unit formed in each block constitute a first triode (PNP), and the epitaxial layer 120, the well region 150 near one side of the silicon-controlled rectifier unit and the outer diffusion region 143 of the first trench structure 140 near one side of the silicon-controlled rectifier unit constitute a second triode (NPN). The epitaxial layer 120 between the first injection region 151 and the second injection region 152 constitutes a series resistor R, and the well region 150 and the third injection region 153 away from one side of the silicon-controlled rectifier unit constitute a clamping diode ZD. In this embodiment, the side of the silicon-controlled rectifier unit is the left side of the SCR unit formed in the block as an example for explanation, but it is not limited to this. Different blocks can also form different sides of the SCR unit in the block.

[0102] In the second region, the first implantation region 151, the epitaxial layer 120 and the second implantation region 152 form a lateral diode (PIN). When the second region and the third region are disposed on both sides of the first region, the lateral diodes (PIN) in the second regions on both sides are connected in parallel.

[0103] Compared with the first embodiment, the second embodiment of the present invention has a relatively larger series resistor R and a relatively smaller trigger current. The rest of the second embodiment of the present invention is the same as the first embodiment and will not be described again.

[0104] The transient voltage suppression device provided in the embodiment of the present invention leads the negative electrode of the silicon-controlled rectifier unit and the anode of the diode out from the back side of the device through the first groove structure. There is no restriction on the metal lead of the positive electrode of the silicon-controlled rectifier unit, which can increase the electrode width of the positive electrode of the silicon-controlled rectifier unit, reduce the current density per unit area, and improve the chip area utilization.

[0105] Furthermore, the first trench structure extends into the semiconductor substrate, and the cathode of the silicon-controlled rectifier unit and the anode of the diode can be led out from the back side of the device, and a back side bonding process can be used for packaging, thereby reducing wire bonding and packaging costs.

[0106] Furthermore, the positive electrode pad of the silicon-controlled rectifier unit can be directly formed above the silicon-controlled rectifier unit, thereby improving chip area utilization.

[0107] Furthermore, a third injection region is formed outside the well region to reduce the trigger voltage of the silicon-controlled rectifier unit.

[0108] Furthermore, the second injection region in the second area overlaps with the isolation structure, which can reduce the PN junction area and lower the capacitance of the lateral diode.

[0109] The embodiment of the present invention also provides a method for manufacturing a transient voltage suppression device. The method can be briefly described as follows:

[0110] In step S01, a semiconductor substrate 101 is provided, wherein the semiconductor substrate 101 has a first conductivity type and a resistivity of 0.0015 Ω·cm to 0.01 Ω·cm.

[0111] In step S02 , an isolation layer 110 and an epitaxial layer 120 are sequentially formed on a semiconductor substrate 101 . The isolation layer 110 is located on the semiconductor substrate 101 , and the epitaxial layer 120 is located on the isolation layer 110 . The epitaxial layer 120 has a first conductivity type or a second conductivity type.

[0112] In step S03, a plurality of isolation structures 130 are formed, wherein the isolation structures 130 penetrate the epitaxial layer 120 and extend into the isolation layer 110, and the plurality of isolation structures 130 divide the transient voltage suppression device into a plurality of regions in a lateral direction, wherein the plurality of regions include a first region, a second region, and a third region, wherein the second region and the third region are disposed on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is away from the first region, and the third region is located at the outermost side of the transient voltage suppression device.

[0113] In step S04 , a well region 150 is formed in the epitaxial layer 120 in the first region.

[0114] In this embodiment, the epitaxial layer 120 has the second conductivity type, and the well region 150 has the first conductivity type. For example, the epitaxial layer 120 is lightly doped P-type, and the well region is N-type; or the epitaxial layer 120 has the first conductivity type, and the well region 150 has the second conductivity type. For example, the epitaxial layer 120 is lightly doped N-type, and the well region 150 is P-type. The ion implantation dose of the well region 150 is, for example, 1E11 to 5E13 cm -2 After the implantation is completed, the well region 150 is annealed.

[0115] In step S05 , a plurality of first trenches 141 are formed in the first region and the third region. The first trenches 141 penetrate the epitaxial layer 120 and the isolation layer 110 and extend into the semiconductor substrate 101 .

[0116] In this embodiment, when the epitaxial layer 120 has the second conductivity type and the well region 150 has the first conductivity type, the first trenches 141 are formed on both sides of the well region 150 , that is, the well region 150 is located between the first trenches 141 .

[0117] Alternatively, when the epitaxial layer 120 has the first conductivity type and the well region 150 has the second conductivity type, the first trench 141 penetrates the well region 150, the epitaxial layer 120, the isolation layer 110 and extends into the semiconductor substrate 101. The first trench 141 extends into the semiconductor substrate 101 to a depth of 1 μm to 10 μm.

[0118] In step S06 , a filling material 142 having a first conductivity type dopant is formed in the plurality of first trenches 141 . The dopant of the filling material 142 diffuses outward through the sidewalls and bottom of the first trenches 141 to form an outdiffusion region 143 around the first trenches 141 .

[0119] In step S07, a first implantation region 151, a second implantation region 152 and a third implantation region 153 are formed. The first implantation region 151 has the second conductivity type, the second implantation region 152 has the first conductivity type and the third implantation region 153 is formed in the epitaxial layer 120 on both sides of the well region 150 in the first region.

[0120] The ion implantation dose of the first implantation region 151 is 4E14-2E16 cm -2 The ion implantation dose of the second implantation region 152 is 2E15-5E16 cm -2 The ion implantation dose of the third implantation region 153 is 4E14-2E16cm -2 .

[0121] When the epitaxial layer 120 has the second conductivity type and the well region 150 has the first conductivity type, the first implantation region 151 is formed in the well region 150 of the first region and the epitaxial layer 120 of the second region; the second implantation region 152 is formed in the well region 150 of the first region and the epitaxial layer 120 of the second region. The third implantation region 153 has the second conductivity type.

[0122] Alternatively, when the epitaxial layer 120 has the first conductivity type and the well region 150 has the second conductivity type, the first implantation region 151 is formed in the epitaxial layer of the first region and the second region; the second implantation region 152 is formed in the epitaxial layer 120 of the first region and the second region. The third implantation region 153 has the first conductivity type.

[0123] In step S08 , the first implantation region 151 , the second implantation region 152 , and the third implantation region 153 are annealed.

[0124] In step S09, a dielectric layer 170 is formed on the epitaxial layer 120, a contact hole 171 is formed in the dielectric layer 170, and a first interconnection line 161 and at least one second interconnection line 162 are formed on the dielectric layer 170. The first interconnection line 161 is connected to the first injection region 151 and the second injection region 152 in the first region and the second injection region 152 in the second region through the contact hole 171 in the dielectric layer 170. Each second interconnection line 162 is connected to the first injection region 151 in the second region and the first trench structure 140 outside the second region through the contact hole 171 in the dielectric layer 170.

[0125] In step S10 , the semiconductor substrate 101 is thinned and backside metallized to form a first electrode 108 .

[0126] The order of step S04 and step S05 in the above steps can be adjusted. For example, step S04 can be placed after step S08, and step S05 can be placed after step S03, but it is not limited thereto.

[0127] According to the embodiments of the present invention as described above, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and the modified use based on the present invention. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A transient voltage suppression device, characterized in that: include: A semiconductor substrate having a first conductivity type; An isolation layer, located on the semiconductor substrate; an epitaxial layer, located on the isolation layer; a plurality of isolation structures, penetrating the epitaxial layer and extending into the isolation layer, the plurality of isolation structures dividing the transient voltage suppression device into a plurality of regions in a lateral direction, the plurality of regions comprising a first region, a second region and a third region, wherein the second region and the third region are disposed on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is away from the first region, and the third region is located at the outermost side of the transient voltage suppression device; A plurality of first trench structures, located in the first region and the third region, penetrating the epitaxial layer and the isolation layer and extending into the semiconductor substrate; A well region, located in the first region, extending from the surface of the epitaxial layer toward the semiconductor substrate; A first implantation region, located in the well region of the first region and in the epitaxial layer of the second region, having a second conductivity type; A second implantation region, located in the well region of the first region and in the epitaxial layer of the second region, having a first conductivity type; A third implantation region is located in the epitaxial layer on both sides of the well region of the first region; Wherein, in the well region, the first injection region is located on both sides of the second injection region.

2. The transient voltage suppression device according to claim 1, characterized in that: The first region includes at least one silicon-controlled rectifier unit, wherein the silicon-controlled rectifier unit includes a first triode, a second triode, a series resistor, and a clamping diode, and the second region includes a diode.

3. The transient voltage suppression device according to claim 2, characterized in that: When the first region includes a plurality of silicon-controlled rectifier units, the plurality of silicon-controlled rectifier units are connected in parallel.

4. The transient voltage suppression device according to claim 2, characterized in that: When the second region and the third region are disposed on both sides of the first region, the diodes in the second regions on both sides are connected in parallel.

5. The transient voltage suppression device according to claim 2, characterized in that: The epitaxial layer has the second conductivity type, the well region has the first conductivity type, and the third implantation region has the second conductivity type.

6. The transient voltage suppression device according to claim 5, characterized in that: The well region extends from the surface of the epitaxial layer into the epitaxial layer, and the first trench structure is located at two sides of the well region.

7. The transient voltage suppression device according to claim 6, characterized in that: The first transistor includes a first injection region in the well region close to the side of the silicon-controlled rectifier unit, a well region, and a third injection region close to the side of the silicon-controlled rectifier unit; the second transistor includes a well region, an epitaxial layer, and an outer diffusion region of a first trench structure close to the side of the silicon-controlled rectifier unit; the clamping diode includes a well region and a third injection region away from the side of the silicon-controlled rectifier unit; the diode includes a first injection region, an epitaxial layer, and a second injection region in the second region.

8. The transient voltage suppression device according to claim 7, characterized in that: The first trench structure in the first region is the emitter of the second triode and is electrically connected to the semiconductor substrate via the first trench structure; the anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.

9. The transient voltage suppression device according to claim 1, characterized in that: The first trench structure extends into the semiconductor substrate to a depth of 1 μm to 10 μm.

10. The transient voltage suppression device according to claim 1, characterized in that: The first trench structure includes a first trench and a filling material located in the first trench, wherein the filling material is polysilicon or amorphous silicon, wherein the filling material has a dopant of a first conductivity type.

11. The transient voltage suppression device according to claim 10, characterized in that: Dopants of the filling material diffuse outward through the sidewalls and the bottom of the first trench to form an outdiffusion region around the first trench.

12. The transient voltage suppression device according to claim 1, characterized in that: The second implantation region in the second region is arranged to overlap or not overlap with the adjacent isolation structure.

13. The transient voltage suppression device according to claim 1, characterized in that: The first conductivity type is P type, the second conductivity type is N type, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor; or the first conductivity type is N type, the second conductivity type is P type, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is a NIP transistor.

14. The transient voltage suppression device according to claim 1, characterized in that: Also includes: A first electrode is located on a surface of the semiconductor substrate away from the epitaxial layer; a first interconnection line connecting the first injection region and the second injection region in the first region and the second injection region in the second region; At least one second interconnection line, wherein the at least one second interconnection line is respectively connected to the first injection region in the second region and the first trench structure in the third region.

15. The transient voltage suppression device according to claim 14, characterized in that: The first interconnection line is connected to one of a power source and a ground, and at least one of the second interconnection lines is connected to the other of the power source and the ground via the first trench structure, the semiconductor substrate, and the first electrode.

16. The transient voltage suppression device according to claim 10, characterized in that: The semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the filling material in the first trench is a heavily doped structure, the first injection region is a heavily doped structure, the second injection region is a heavily doped structure, and the third injection region is a heavily doped structure.

17. The transient voltage suppression device according to claim 1, characterized in that: The resistivity of the semiconductor substrate is 0.0015Ω·cm~0.01Ω·cm.

18. The transient voltage suppression device according to claim 1, characterized in that: The resistivity of the epitaxial layer is 10Ω·cm~200Ω·cm, and the thickness is 1μm~10μm.

19. The transient voltage suppression device according to claim 1, characterized in that: The isolation structure includes a second trench and an insulating material filled in the second trench, wherein the second trench penetrates the epitaxial layer and extends into the isolation layer.

20. A transient voltage suppression device, characterized in that: include: A semiconductor substrate having a first conductivity type; An isolation layer, located on the semiconductor substrate; an epitaxial layer, located on the isolation layer; a plurality of isolation structures, penetrating the epitaxial layer and extending into the isolation layer, the plurality of isolation structures dividing the transient voltage suppression device into a plurality of regions in a lateral direction, the plurality of regions comprising a first region, a second region and a third region, wherein the second region and the third region are disposed on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is away from the first region, and the third region is located at the outermost side of the transient voltage suppression device; A plurality of first trench structures, located in the first region and the third region, penetrating the epitaxial layer and the isolation layer and extending into the semiconductor substrate; A well region, located in the first region, extending from the surface of the epitaxial layer toward the semiconductor substrate; A first implantation region, located in the epitaxial layer of the first region and in the epitaxial layer of the second region, having a second conductivity type; A second implantation region, located in the epitaxial layer of the first region and in the epitaxial layer of the second region, having a first conductivity type; A third implantation region is located in the epitaxial layer on both sides of the well region of the first region; Wherein, in the epitaxial layer, the first injection region is located on both sides of the second injection region.

21. The transient voltage suppression device according to claim 20, characterized in that: The first region includes at least one silicon-controlled rectifier unit, wherein the silicon-controlled rectifier unit includes a first triode, a second triode, a series resistor, and a clamping diode, and the second region includes a diode.

22. The transient voltage suppression device according to claim 21, characterized in that: When the first region includes a plurality of silicon-controlled rectifier units, the plurality of silicon-controlled rectifier units are connected in parallel.

23. The transient voltage suppression device according to claim 21, characterized in that: When the second region and the third region are disposed on both sides of the first region, the diodes in the second regions on both sides are connected in parallel.

24. The transient voltage suppression device according to claim 21, characterized in that: The epitaxial layer has a first conductivity type, the well region has a second conductivity type, and the third implant region has a first conductivity type.

25. The transient voltage suppression device according to claim 24, characterized in that: The well region extends from the surface of the epitaxial layer into the isolation layer, and the first trench structure penetrates the well region and the isolation layer and extends into the semiconductor substrate.

26. The transient voltage suppression device according to claim 25, characterized in that: The first transistor includes a first injection region close to one side of the silicon-controlled rectifier unit, an epitaxial layer, and a well region close to one side of the silicon-controlled rectifier unit; the second transistor includes an epitaxial layer, a well region close to one side of the silicon-controlled rectifier unit, and an outer diffusion region of a first trench structure close to one side of the silicon-controlled rectifier unit; the clamping diode includes a well region and an epitaxial layer away from one side of the silicon-controlled rectifier unit; the diode includes a first injection region, an epitaxial layer, and a second injection region in the second region.

27. The transient voltage suppression device according to claim 26, characterized in that: The first trench structure in the first region is the emitter of the second triode and is electrically connected to the semiconductor substrate via the first trench structure; the anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.

28. The transient voltage suppression device according to claim 20, characterized in that: The first trench structure extends into the semiconductor substrate to a depth of 1 μm to 10 μm.

29. The transient voltage suppression device according to claim 20, characterized in that: The first trench structure includes a first trench and a filling material located in the first trench, wherein the filling material is polysilicon or amorphous silicon, wherein the filling material has a dopant of a first conductivity type.

30. The transient voltage suppression device according to claim 29, characterized in that: Dopants of the filling material diffuse outward through the sidewalls and the bottom of the first trench to form an outdiffusion region around the first trench.

31. The transient voltage suppression device according to claim 20, characterized in that: The second implantation region in the second region is arranged to overlap or not overlap with the adjacent isolation structure.

32. The transient voltage suppression device according to claim 20, characterized in that: The first conductivity type is P type, the second conductivity type is N type, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor; or the first conductivity type is N type, the second conductivity type is P type, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is a NIP transistor.

33. The transient voltage suppression device according to claim 20, characterized in that: Also includes: A first electrode is located on a surface of the semiconductor substrate away from the epitaxial layer; a first interconnection line connecting the first injection region and the second injection region in the first region and the second injection region in the second region; At least one second interconnection line, wherein the at least one second interconnection line is respectively connected to the first injection region in the second region and the first trench structure in the third region.

34. The transient voltage suppression device according to claim 33, characterized in that: The first interconnection line is connected to one of a power source and a ground, and at least one of the second interconnection lines is connected to the other of the power source and the ground via the first trench structure, the semiconductor substrate, and the first electrode.

35. The transient voltage suppression device according to claim 29, characterized in that: The semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the filling material in the first trench is a heavily doped structure, the first injection region is a heavily doped structure, the second injection region is a heavily doped structure, and the third injection region is a heavily doped structure.

36. The transient voltage suppression device according to claim 20, characterized in that: The resistivity of the semiconductor substrate is 0.0015Ω·cm~0.01Ω·cm.

37. The transient voltage suppression device according to claim 20, characterized in that: The resistivity of the epitaxial layer is 10Ω·cm~200Ω·cm, and the thickness is 1μm~10μm.

38. The transient voltage suppression device according to claim 20, characterized in that: The isolation structure includes a second trench and an insulating material filled in the second trench, wherein the second trench penetrates the epitaxial layer and extends into the isolation layer.

39. A method for manufacturing a transient voltage suppression device, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate having a first conductivity type; forming an isolation layer and an epitaxial layer in sequence on the semiconductor substrate; forming a plurality of isolation structures, wherein the isolation structures penetrate the epitaxial layer and extend into the isolation layer, wherein the plurality of isolation structures divide the transient voltage suppression device into a plurality of regions in a lateral direction, wherein the plurality of regions include a first region, a second region, and a third region, wherein the second region and the third region are disposed on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is away from the first region, and the third region is located at the outermost side of the transient voltage suppression device; forming a plurality of first trench structures in the first region and the third region, wherein the plurality of first trench structures penetrate the epitaxial layer and the isolation layer and extend into the semiconductor substrate; forming a well region in the first region, wherein the well region extends from a surface of the epitaxial layer toward a semiconductor substrate; forming a first implantation region in the well region of the first region and in the epitaxial layer of the second region, wherein the first implantation region has a second conductivity type, forming a second implantation region in the well region of the first region and in the epitaxial layer of the second region, the second implantation region having a first conductivity type; forming a third implantation region in the epitaxial layer on both sides of the well region in the first region; Wherein, in the well region, the first injection region is located on both sides of the second injection region.

40. The manufacturing method according to claim 39, characterized in that: At least one silicon-controlled rectifier unit is formed in the first region, the silicon-controlled rectifier unit comprising a first triode, a second triode, a series resistor and a clamping diode, and a diode is formed in the second region.

41. The manufacturing method according to claim 40, characterized in that: When a plurality of silicon-controlled rectifier units are formed in the first region, the plurality of silicon-controlled rectifier units are connected in parallel.

42. The manufacturing method according to claim 40, characterized in that When the second region and the third region are disposed on both sides of the first region, the diodes in the second regions on both sides are connected in parallel.

43. The manufacturing method according to claim 40, characterized in that: The epitaxial layer has the second conductivity type, the well region has the first conductivity type, and the third implantation region has the second conductivity type.

44. The manufacturing method according to claim 43, characterized in that The well region extends from the surface of the epitaxial layer into the epitaxial layer, and the first trench structure is located at two sides of the well region.

45. The manufacturing method according to claim 44, characterized in that: The first transistor includes a first injection region in the well region close to the side of the silicon-controlled rectifier unit, a well region, and a third injection region in the well region close to the side of the silicon-controlled rectifier unit; the second transistor includes a well region, an epitaxial layer, and an outer diffusion region of a first trench structure close to the side of the silicon-controlled rectifier unit; the clamping diode includes a well region and a third injection region away from the side of the silicon-controlled rectifier unit; the diode includes a first injection region, an epitaxial layer, and a second injection region in the second region.

46. ​​The manufacturing method according to claim 45, characterized in that The first trench structure in the first region is the emitter of the second triode and is electrically connected to the semiconductor substrate via the first trench structure; the anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.

47. The manufacturing method according to claim 39, characterized in that: The first trench structure extends into the semiconductor substrate to a depth of 1 μm to 10 μm.

48. The manufacturing method according to claim 39, characterized in that Forming a first trench structure includes: forming a first trench; and A filling material is disposed in the first trench, wherein the filling material is polysilicon or amorphous silicon, wherein the filling material has a dopant of the second conductivity type.

49. The manufacturing method according to claim 48, characterized in that Dopants of the filling material diffuse outward through the sidewalls and the bottom of the first trench to form an outdiffusion region around the first trench.

50. The manufacturing method according to claim 39, characterized in that: The second implantation region in the second region is arranged to overlap or not overlap with the adjacent isolation structure.

51. The manufacturing method according to claim 39, characterized in that The first conductivity type is P type, the second conductivity type is N type, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor; or the first conductivity type is N type, the second conductivity type is P type, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is a NIP transistor.

52. The manufacturing method according to claim 39, characterized in that: Also includes: forming a first electrode on a surface of the semiconductor substrate away from the epitaxial layer; forming a first interconnection line and at least one second interconnection line, wherein the first interconnection line connects the first injection region and the second injection region in the first region and the second injection region in the second region; At least one of the second interconnection lines is respectively connected to the first implantation region in the second region and the first trench structure in the third region.

53. The manufacturing method according to claim 52, characterized in that: Also includes: The first interconnection line is connected to one of a power source and a ground, and at least one of the second interconnection lines is connected to the other of the power source and the ground via the first trench structure, the semiconductor substrate, and the first electrode.

54. The manufacturing method according to claim 48, characterized in that The semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the filling material in the first trench is a heavily doped structure, the first injection region is a heavily doped structure, the second injection region is a heavily doped structure, and the third injection region is a heavily doped structure.

55. The manufacturing method according to claim 39, characterized in that The resistivity of the semiconductor substrate is 0.0015Ω.cm~0.01Ω.cm.

56. The manufacturing method according to claim 39, characterized in that The resistivity of the epitaxial layer is 10Ω.cm-200Ω.cm, and the thickness is 3μm-10μm.

57. The manufacturing method according to claim 39, characterized in that The formation of the isolation structure includes: forming a plurality of second trenches, wherein the second trenches penetrate the epitaxial layer and extend into the isolation layer; The second trench is filled with an insulating material.

58. A method for manufacturing a transient voltage suppression device, characterized in that: include: Providing a semiconductor substrate, the semiconductor substrate having a first conductivity type; forming an isolation layer and an epitaxial layer in sequence on the semiconductor substrate; forming a plurality of isolation structures, wherein the isolation structures penetrate the epitaxial layer and extend into the isolation layer, wherein the plurality of isolation structures divide the transient voltage suppression device into a plurality of regions in a lateral direction, wherein the plurality of regions include a first region, a second region, and a third region, wherein the second region and the third region are disposed on at least one side of the first region, the second region is adjacent to the first region, the third region is adjacent to the second region and is away from the first region, and the third region is located at the outermost side of the transient voltage suppression device; forming a plurality of first trench structures in the first region and the third region, wherein the plurality of first trench structures penetrate the epitaxial layer and the isolation layer and extend into the semiconductor substrate; forming a well region in the first region, wherein the well region extends from a surface of the epitaxial layer toward a semiconductor substrate; forming a first implantation region in the epitaxial layer of the first region and in the epitaxial layer of the second region, wherein the first implantation region has a second conductivity type, forming a second implantation region in the epitaxial layer of the first region and in the epitaxial layer of the second region, the second implantation region having a first conductivity type; forming a third implantation region in the epitaxial layer on both sides of the well region in the first region; Wherein, in the epitaxial layer, the first injection region is located on both sides of the second injection region.

59. The manufacturing method according to claim 58, characterized in that At least one silicon-controlled rectifier unit is formed in the first region, the silicon-controlled rectifier unit comprising a first triode, a second triode, a series resistor and a clamping diode, and a diode is formed in the second region.

60. The manufacturing method according to claim 58, characterized in that When a plurality of silicon-controlled rectifier units are formed in the first region, the plurality of silicon-controlled rectifier units are connected in parallel.

61. The manufacturing method according to claim 58, characterized in that When the second region and the third region are disposed on both sides of the first region, the diodes in the second regions on both sides are connected in parallel.

62. The manufacturing method according to claim 59, characterized in that The epitaxial layer has a first conductivity type, the well region has a second conductivity type, and the third implant region has a first conductivity type.

63. The manufacturing method according to claim 62, characterized in that: The well region extends from the surface of the epitaxial layer into the isolation layer, and the first trench structure penetrates the well region, the epitaxial layer and the isolation layer and extends into the semiconductor substrate.

64. The manufacturing method according to claim 63, characterized in that The first transistor includes a first injection region close to one side of the silicon-controlled rectifier unit, an epitaxial layer, and a well region close to one side of the silicon-controlled rectifier unit; the second transistor includes an epitaxial layer, a well region close to one side of the silicon-controlled rectifier unit, and an outer diffusion region of a first trench structure close to one side of the silicon-controlled rectifier unit; the clamping diode includes a well region and an epitaxial layer away from one side of the silicon-controlled rectifier unit; the diode includes a first injection region, an epitaxial layer, and a second injection region in the second region.

65. The manufacturing method according to claim 64, characterized in that The first trench structure in the first region is the emitter of the second triode and is electrically connected to the semiconductor substrate via the first trench structure; the anode of the diode is electrically connected to the semiconductor substrate via the first trench structure in the third region.

66. The manufacturing method according to claim 58, characterized in that The first trench structure extends into the semiconductor substrate to a depth of 1 μm to 10 μm.

67. The manufacturing method according to claim 58, characterized in that Forming a first trench structure includes: forming a first trench; and A filling material is disposed in the first trench, wherein the filling material is polysilicon or amorphous silicon, wherein the filling material has a dopant of the second conductivity type.

68. The manufacturing method according to claim 67, characterized in that Dopants of the filling material diffuse outward through the sidewalls and the bottom of the first trench to form an outdiffusion region around the first trench.

69. The manufacturing method according to claim 58, characterized in that The second implantation region in the second region is arranged to overlap or not overlap with the adjacent isolation structure.

70. The manufacturing method according to claim 58, characterized in that The first conductivity type is P type, the second conductivity type is N type, the first transistor is a PNP transistor, the second transistor is an NPN transistor, and the diode is a PIN transistor; or the first conductivity type is N type, the second conductivity type is P type, the first transistor is an NPN transistor, the second transistor is a PNP transistor, and the diode is a NIP transistor.

71. The manufacturing method according to claim 58, characterized in that Also includes: forming a first electrode on a surface of the semiconductor substrate away from the epitaxial layer; forming a first interconnection line and at least one second interconnection line, wherein the first interconnection line connects the first injection region and the second injection region in the first region and the second injection region in the second region; At least one of the second interconnection lines is respectively connected to the first implantation region in the second region and the first trench structure in the third region.

72. The manufacturing method according to claim 71, characterized in that Also includes: The first interconnection line is connected to one of a power source and a ground, and at least one of the second interconnection lines is connected to the other of the power source and the ground via the first trench structure, the semiconductor substrate, and the first electrode.

73. The manufacturing method according to claim 67, characterized in that The semiconductor substrate is a heavily doped structure, the epitaxial layer is a lightly doped structure, the filling material in the first trench is a heavily doped structure, the first injection region is a heavily doped structure, the second injection region is a heavily doped structure, and the third injection region is a heavily doped structure.

74. The manufacturing method according to claim 58, characterized in that The resistivity of the semiconductor substrate is 0.0015Ω.cm~0.01Ω.cm.

75. The manufacturing method according to claim 58, characterized in that The resistivity of the epitaxial layer is 10Ω.cm-200Ω.cm, and the thickness is 3μm-10μm.

76. The manufacturing method according to claim 58, characterized in that The formation of the isolation structure includes: forming a plurality of second trenches, wherein the second trenches penetrate the epitaxial layer and extend into the isolation layer; The second trench is filled with an insulating material.

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