Semiconductor structure and its formation method

Abstract

A semiconductor structure and a method for forming the same are disclosed. The method includes: providing a substrate, forming a gate structure on the substrate, forming source / drain doped layers in the substrate on both sides of the gate structure, forming a first interlayer dielectric layer on the exposed portion of the substrate, the first interlayer dielectric layer covering the top of the gate structure; forming an opening through the first interlayer dielectric layer between the gate structures, the opening exposing the source / drain doped layers; forming a bottom source / drain plug within the opening, the top of the bottom source / drain plug being lower than the top of the opening and higher than the top of the gate structure; forming an etch stop layer on the sidewall of the exposed opening of the bottom source / drain plug; forming a gate contact hole located between adjacent etch stop layers and penetrating the first interlayer dielectric layer, the bottom of the gate contact hole exposing the gate structure; and forming a source / drain contact hole located between adjacent etch stop layers and penetrating a second interlayer dielectric layer. The etch stop layer improves the alignment accuracy between the top and bottom source / drain plugs.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, people have increasingly higher requirements for the integration level and performance of integrated circuits. In order to improve integration level and reduce costs, the critical dimensions of components are constantly shrinking, and the circuit density inside integrated circuits is increasing. This development makes it impossible for the wafer surface to provide enough area to fabricate the required interconnects.

[0003] To meet the interconnect requirements of reduced critical dimensions, current interconnect structures are used to connect different metal layers or between metal layers and the substrate. Interconnect structures include interconnect lines and contact holes formed within contact openings. The contact holes connect to semiconductor devices, and the interconnect lines connect the contact holes to form a circuit. Contact holes within a transistor structure include gate contact holes located on the surface of the gate structure for connecting the gate structure to external circuitry, and source / drain contact holes located on the surfaces of the source / drain doped layers for connecting the source / drain doped layers to external circuitry.

[0004] Currently, to further reduce transistor area, the ContactOver Active Gate (COAG) process has been introduced. Compared to traditional gate contact plugs located above the gate structure in the isolation region, the COAG process can place the gate contact plug above the gate structure in the active area (AA), thereby further saving chip area. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a substrate on which a gate structure is formed, source / drain doped layers formed within the substrate on both sides of the gate structure, a first interlayer dielectric layer formed on the exposed portion of the substrate of the gate structure, the first interlayer dielectric layer covering the top of the gate structure; a bottom source / drain plug located in the first interlayer dielectric layer between the gate structures and connected to the source / drain doped layers, the top of the bottom source / drain plug being lower than the top of the first interlayer dielectric layer and higher than the top of the gate structure; a second interlayer dielectric layer penetrating the first interlayer dielectric layer above the top of the bottom source / drain plug; an etch stop layer located between the sidewall of the second interlayer dielectric layer and the first interlayer dielectric layer; a gate plug penetrating the first interlayer dielectric layer between adjacent etch stop layers, the bottom of the gate plug being connected to the gate structure; and a top source / drain plug penetrating the second interlayer dielectric layer between adjacent etch stop layers, the bottom of the top source / drain plug being connected to the bottom source / drain plug.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, wherein a gate structure is formed on the substrate, source and drain doped layers are formed in the substrate on both sides of the gate structure, a first interlayer dielectric layer is formed on the exposed portion of the substrate of the gate structure, the first interlayer dielectric layer covering the top of the gate structure; forming an opening through the first interlayer dielectric layer between the gate structures, the opening exposing the source and drain doped layers; forming a bottom source and drain plug in the opening, the top of the bottom source and drain plug being lower than the top of the opening and higher than the source and drain doped layers. The top of the gate structure; an etch barrier layer is formed on the sidewall of the opening exposed by the bottom source / drain plug; after forming the etch barrier layer, a second interlayer dielectric layer is formed in the remaining opening; a gate contact hole is formed between adjacent etch barrier layers and through the first interlayer dielectric layer, the bottom of the gate contact hole exposing the gate structure; a source / drain contact hole is formed between adjacent etch barrier layers and through the second interlayer dielectric layer, the bottom of the source / drain contact hole exposing the bottom source / drain plug; a gate plug is formed in the gate contact hole, and a top source / drain plug is formed in the source / drain contact hole.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a semiconductor structure in which a bottom source / drain plug is located in a first interlayer dielectric layer between gate structures and is connected to the source / drain doped layer. A second interlayer dielectric layer penetrates the first interlayer dielectric layer at the top of the bottom source / drain plug. An etch stop layer is located between the sidewall of the second interlayer dielectric layer and the first interlayer dielectric layer. A gate plug penetrates the first interlayer dielectric layer between adjacent etch stop layers, and the bottom of the gate plug is connected to the gate structure. A top source / drain plug penetrates the second interlayer dielectric layer between adjacent etch stop layers, and the bottom of the top source / drain plug is connected to the bottom source / drain plug. A gate plug is formed in a gate contact hole, and a top source / drain plug is formed in a source / drain contact hole. This invention forms an etch barrier layer between the sidewall of the second interlayer dielectric layer and the first interlayer dielectric layer. This etch barrier layer can achieve self-alignment during the formation of both the gate contact hole and the source / drain contact hole. This improves the positional accuracy of the gate contact hole and the source / drain contact hole, thereby improving the alignment accuracy of the top source / drain plug with the corresponding bottom source / drain plug, and the alignment accuracy of the gate plug with the corresponding gate structure. This, in turn, improves the performance of the semiconductor structure. Furthermore, during the formation of the source / drain contact hole, only the etch selectivity ratio between the second interlayer dielectric layer and the etch barrier layer needs to be considered; during the formation of the gate contact hole, only the etch selectivity ratio between the first interlayer dielectric layer and the etch barrier layer needs to be considered. Therefore, it is easy to achieve self-alignment during the formation of both the gate contact hole and the source / drain contact hole.

[0010] This invention provides a method for forming a semiconductor structure, comprising: forming an opening in a first interlayer dielectric layer penetrating between gate structures, the opening exposing source / drain doped layers; forming a bottom source / drain plug within the opening, the top of the bottom source / drain plug being lower than the top of the opening; forming an etch stop layer on the sidewall of the opening exposed by the bottom source / drain plug; then forming a second interlayer dielectric layer in the remaining opening; forming a gate contact hole located between adjacent etch stop layers and penetrating the first interlayer dielectric layer, the bottom of the gate contact hole exposing the gate structure; forming a source / drain contact hole located between adjacent etch stop layers and penetrating the second interlayer dielectric layer, the bottom of the source / drain contact hole exposing the bottom source / drain plug; forming a gate plug within the gate contact hole; and forming a top source / drain plug within the source / drain contact hole. This invention achieves self-alignment during the formation of both the source / drain contact holes and the gate contact holes by forming an etch barrier layer on the exposed sidewall of the bottom source / drain plug. This improves the positional accuracy of the gate contact holes and the source / drain contact holes, thereby improving the alignment accuracy between the top source / drain plug and the corresponding bottom source / drain plug, as well as the alignment accuracy between the gate plug and the corresponding gate structure, and ultimately improving the performance of the semiconductor structure. Moreover, during the formation of the source / drain contact holes, only the etch selectivity ratio between the second interlayer dielectric layer and the etch barrier layer needs to be considered, and during the formation of the gate contact holes, only the etch selectivity ratio between the first interlayer dielectric layer and the etch barrier layer needs to be considered. Therefore, it is easy to achieve self-alignment during the formation of both the gate contact holes and the source / drain contact holes. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of a semiconductor structure.

[0012] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 3 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the method for forming a semiconductor structure of the present invention;

[0014] Figure 16 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention. Detailed Implementation

[0015] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using a semiconductor structure formation method as an example.

[0016] Figure 1 This is a schematic diagram of a semiconductor structure.

[0017] The semiconductor structure includes: a substrate including a substrate 10 and fins 11 located on the substrate 10; a gate structure 22 spanning the fins 11 and covering a portion of the top and a portion of the sidewalls of the fins 11; source / drain doped layers 20 located within the fins 11 on both sides of the gate structure 22; a bottom source / drain plug 18 located on top of the source / drain doped layers 20; an etch stop layer 21 located on top of the bottom source / drain plug 18; sidewalls 14 located on the sidewalls of the gate structure 22; a first interlayer dielectric layer 12 located on the exposed substrate of the gate structure 22, the first interlayer dielectric layer 12 covering the top of the gate structure 22 and the etch stop layer 21; a second interlayer dielectric layer 15 located on top of the first interlayer dielectric layer 12; a gate plug 19 penetrating the top of the first interlayer dielectric layer 12 and the second interlayer dielectric layer 15 of the gate structure 22; and a top source / drain plug 16 penetrating the top of the second interlayer dielectric layer 15 and the etch stop layer 21 of the bottom source / drain plug 18.

[0018] During the formation of the semiconductor structure, a gate plug 19 is formed in the gate contact hole, and a top source / drain plug 16 is formed in the source / drain contact hole.

[0019] Research has revealed that as device feature sizes decrease, the spacing between adjacent fins 11 also decreases. Consequently, the spacing between adjacent gate structures 22 also decreases. Consequently, during the formation of source / drain contact holes, overlay shift significantly affects the positional accuracy of these contact holes, potentially leading to misalignment between the top source / drain plug 16 and the corresponding bottom source / drain plug 18 (e.g., ...). Figure 1 (As shown by the dashed coil in the middle), which can easily lead to a degradation in the performance of the semiconductor structure.

[0020] To address the aforementioned technical problem, embodiments of the present invention provide a method for forming a semiconductor structure, comprising: providing a substrate, forming a gate structure on the substrate, forming source / drain doped layers in the substrate on both sides of the gate structure, forming a first interlayer dielectric layer on the exposed portion of the substrate of the gate structure, the first interlayer dielectric layer covering the top of the gate structure; forming an opening penetrating the first interlayer dielectric layer between the gate structures, the opening exposing the source / drain doped layers; forming a bottom source / drain plug within the opening, the top of the bottom source / drain plug being lower than the top of the opening, and the top of the bottom source / drain plug being higher than... At the top of the gate structure; an etch barrier layer is formed on the sidewall of the opening exposed by the bottom source / drain plug; after forming the etch barrier layer, a second interlayer dielectric layer is formed in the remaining opening; a gate contact hole is formed between adjacent etch barrier layers and through the first interlayer dielectric layer, the bottom of the gate contact hole exposing the gate structure; a source / drain contact hole is formed between adjacent etch barrier layers and through the second interlayer dielectric layer, the bottom of the source / drain contact hole exposing the bottom source / drain plug; a gate plug is formed in the gate contact hole, and a top source / drain plug is formed in the source / drain contact hole.

[0021] In the embodiment of the present invention, an opening is formed in a first interlayer dielectric layer penetrating between gate structures, the opening exposing source / drain doped layers; a bottom source / drain plug is formed within the opening, the top of the bottom source / drain plug being lower than the top of the opening; an etch barrier layer is formed on the sidewall of the opening exposed by the bottom source / drain plug; a second interlayer dielectric layer is then formed in the remaining opening; a gate contact hole is formed between adjacent etch barrier layers and penetrating the first interlayer dielectric layer, the bottom of the gate contact hole exposing the gate structure; a source / drain contact hole is formed between adjacent etch barrier layers and penetrating the second interlayer dielectric layer, the bottom of the source / drain contact hole exposing the bottom source / drain plug; a gate plug is formed within the gate contact hole; and a top source / drain plug is formed within the source / drain contact hole. This invention achieves self-alignment during the formation of both the source / drain contact holes and the gate contact holes by forming an etch barrier layer on the exposed sidewall of the bottom source / drain plug. This improves the positional accuracy of the gate contact holes and the source / drain contact holes, thereby improving the alignment accuracy between the top source / drain plug and the corresponding bottom source / drain plug, as well as the alignment accuracy between the gate plug and the corresponding gate structure, and ultimately improving the performance of the semiconductor structure. Moreover, during the formation of the source / drain contact holes, only the etch selectivity ratio between the second interlayer dielectric layer and the etch barrier layer needs to be considered, and during the formation of the gate contact holes, only the etch selectivity ratio between the first interlayer dielectric layer and the etch barrier layer needs to be considered. Therefore, it is easy to achieve self-alignment during the formation of both the gate contact holes and the source / drain contact holes.

[0022] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figure 2 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0024] The semiconductor structure includes: a substrate on which a gate structure 307 is formed, and source / drain doped layers 308 are formed in the substrate on both sides of the gate structure 307. A first interlayer dielectric layer 302 is formed on the exposed substrate of the gate structure 307, and the first interlayer dielectric layer 302 covers the top of the gate structure 307; a bottom source / drain plug 312 located in the first interlayer dielectric layer 302 between the gate structures 307 and connected to the source / drain doped layers 308, wherein the top of the bottom source / drain plug 312 is lower than the top of the first interlayer dielectric layer 302 and higher than the top of the gate structure 307; and a second... Interlayer dielectric layer 314 extends through the first interlayer dielectric layer 302 above the bottom source / drain plug 312; etch stop layer 313 is located between the sidewall of the second interlayer dielectric layer 314 and the first interlayer dielectric layer 302; gate plug 316 extends through the first interlayer dielectric layer 302 between adjacent etch stop layers 313, and the bottom of the gate plug 316 is connected to the gate structure 307; top source / drain plug 317 extends through the second interlayer dielectric layer 314 between adjacent etch stop layers 313, and the bottom of the top source / drain plug 317 is connected to the bottom source / drain plug 312.

[0025] A gate plug 316 is formed in a gate contact hole, and a top source / drain plug 317 is formed in a source / drain contact hole. By forming an etch stop layer 313 between the sidewall of the second interlayer dielectric layer 314 and the first interlayer dielectric layer 302, the etch stop layer 313 can achieve self-alignment during the formation of both the gate contact hole and the source / drain contact hole. This is beneficial to improving the positional accuracy of the gate contact hole and the source / drain contact hole, thereby improving the alignment accuracy of the top source / drain plug 317 with the corresponding bottom source / drain plug 312, and the alignment accuracy of the gate plug 316 with the corresponding gate structure 307, thus improving the performance of the semiconductor structure. Moreover, during the formation of the source / drain contact hole, only the etch selectivity ratio between the second interlayer dielectric layer 314 and the etch stop layer 313 needs to be considered, and during the formation of the gate contact hole, only the etch selectivity ratio between the first interlayer dielectric layer 302 and the etch stop layer 313 needs to be considered. Therefore, it is easy to achieve self-alignment during the formation of both the gate contact hole and the source / drain contact hole.

[0026] In this embodiment, the semiconductor structure is a FinFET (Fin Field-Effect Transistor). The substrate includes a substrate 300 and fins 301 located on the substrate 300. In this embodiment, the substrate 300 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, and the substrate may also be other types of substrates such as silicon-on-insulator (SiI) substrate or germanium-on-insulator (CHI) substrate.

[0027] In this embodiment, the fin 301 is disposed on the substrate 300, and the material of the fin 301 is the same as that of the substrate, which is silicon.

[0028] In other embodiments, when the semiconductor structure is a planar transistor, the substrate may also be a planar substrate.

[0029] In this embodiment, the semiconductor structure further includes an isolation layer 350 located on the substrate 300 exposed by the fin 301, and the isolation layer 350 covers part of the sidewall of the fin 301.

[0030] The isolation layer 350 is used to isolate adjacent devices. The material of the isolation layer 350 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 350 is silicon oxide.

[0031] In this embodiment, the gate structure 307 is a metal gate structure, used to control the opening and closing of the transistor channel.

[0032] The gate structure 307 includes a high-k gate dielectric layer, a work function layer located on the high-k gate dielectric layer, and a gate electrode layer located on the work function layer.

[0033] In this embodiment, the source / drain doped layer 308 is located in the fins 301 on both sides of the gate structure 307.

[0034] When the semiconductor device is a PMOS transistor, the material of the source / drain doped layer 308 is silicon germanide doped with P-type ions, wherein the P-type ions include B, Ga, or In. When the semiconductor device is an NMOS transistor, the material of the source / drain doped layer 308 is silicon carbide or silicon doped with N-type ions, wherein the N-type ions include P, As, or Sb.

[0035] In this embodiment, the semiconductor structure further includes a sidewall 304 located on the substrate exposed by the gate structure 307, and the sidewall 304 covers the sidewall of the gate structure 307.

[0036] The sidewall 304 is used to protect the sidewalls of the gate structure 307, and also to define the formation locations of the source / drain doped layers 308. The sidewall 304 can be a single-layer structure or a multilayer structure, and the material of the sidewall 304 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 304 is a single-layer structure, and the material of the sidewall 304 is silicon nitride.

[0037] In this embodiment, the semiconductor structure further includes a gate cap layer 306, located on top of the gate structure 307.

[0038] The gate cap layer 306 protects the gate structure 307.

[0039] In this embodiment, the gate cap layer 306 is made of silicon nitride.

[0040] In this embodiment, the first interlayer dielectric layer 302 is located on the substrate exposed by the gate structure 307, and the first interlayer dielectric layer 302 also covers the top of the gate structure 307.

[0041] The first interlayer dielectric layer 302 is used to isolate adjacent transistors. The material of the first interlayer dielectric layer 302 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first interlayer dielectric layer 302 is silicon oxide.

[0042] It should be noted that, in this embodiment, in the first interlayer dielectric layer 302 located on top of the gate structure 307, the surface opposite to the sidewall of the etch barrier layer 313 is the first side surface, and the surface opposite to the sidewall of the bottom source / drain plug 312 is the second side surface, and the first side surface protrudes relative to the second side surface.

[0043] Specifically, the first side protrudes relative to the second side, thus reducing the probability that the etch barrier layer 313 covers the top surface of the bottom source / drain plug 312. In other words, the etch barrier layer 313 exposes more of the top surface of the bottom source / drain plug 312. Correspondingly, after the top source / drain plug 317 is formed on the top surface of the bottom source / drain plug 312, the contact area between the bottom source / drain plug 312 and the top source / drain plug 317 is larger, thereby improving the electrical connection effect between the bottom source / drain plug 312 and the top source / drain plug 317, which is beneficial to improving the performance of the semiconductor structure.

[0044] It should be noted that the protrusion of the first side relative to the second side should not be too large or too small. If the protrusion of the first side relative to the second side is too large, it may occupy too much of the top space of the gate structure 307, thereby affecting the formation of the gate plug and thus the structural performance of the semiconductor. If the protrusion of the first side relative to the second side is too small, since the etch barrier layer 313 has a certain lateral dimension, it may cover the top surface of the top source / drain plug 317, thereby affecting the electrical connection between the top source / drain plug 317 and the corresponding bottom source / drain plug 312. Therefore, in this embodiment, the protrusion of the first side relative to the second side is 50 angstroms to 200 angstroms. For example, the protrusion of the first side relative to the second side is 70 angstroms, 100 angstroms, or 150 angstroms.

[0045] In this embodiment, the bottom source / drain plug 312 is located in the first interlayer dielectric layer 302 between the gate structures 307 and is connected to the source / drain doped layer 308. The top of the bottom source / drain plug 312 is lower than the top of the first interlayer dielectric layer 302 and higher than the top of the gate structure 307.

[0046] The bottom source / drain plug 312 is in contact with the source / drain doped layer 308 to enable electrical connection between the source / drain doped layer 308 and external circuits or other interconnect structures.

[0047] In this embodiment, the top of the bottom source / drain plug 312 is lower than the top of the first interlayer dielectric layer 302.

[0048] The bottom source / drain plug 312 is positioned below the top of the first interlayer dielectric layer 302, providing space for the etching barrier layer 313 and the second interlayer dielectric layer 314.

[0049] In this embodiment, the bottom source / drain plug 312 is made of tungsten. Tungsten has low resistivity, which helps improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps reduce the resistance of the bottom source / drain plug 312, thereby reducing power consumption. In other embodiments, the bottom source / drain plug can also be made of conductive materials such as cobalt or ruthenium.

[0050] In this embodiment, the distance from the top of the bottom source / drain plug 312 to the top of the first interlayer dielectric layer 302 is 50 angstroms to 500 angstroms.

[0051] It should be noted that the distance from the top of the bottom source / drain plug 312 to the top of the first interlayer dielectric layer 302 should not be too large or too small. If the distance from the top of the bottom source / drain plug 312 to the top of the first interlayer dielectric layer 302 is too large, it will easily occupy too much space of the bottom source / drain plug 312, thereby reducing the electrical connection effect between the top source / drain plug 317 and the bottom source / drain plug 312, thus affecting the electrical performance of the semiconductor. The distance from the top of the bottom source / drain plug 312 to the top of the first interlayer dielectric layer 302 will affect the height of the etch stop layer 313. If the distance from the top of the bottom source / drain plug 312 to the top of the first interlayer dielectric layer 302 is too small, it will easily occupy too much space of the etch stop layer 313, resulting in the etch stop layer 313 being too small. During the formation of the top source / drain plug 317, the etch stop layer 313 may not be able to perform its corresponding function, reducing the alignment accuracy between the top source / drain plug 317 and the corresponding bottom source / drain plug 312, thereby affecting the structural performance of the semiconductor. Therefore, in this embodiment, the distance from the top of the bottom source / drain plug 312 to the top of the first interlayer dielectric layer 302 is 50 angstroms to 500 angstroms. For example, the distance from the top of the bottom source / drain plug 312 to the top of the first interlayer dielectric layer 302 is 100 angstroms, 150 angstroms, 200 angstroms, 300 angstroms, 350 angstroms, or 400 angstroms.

[0052] In this embodiment, the second interlayer dielectric layer 314 penetrates the first interlayer dielectric layer 302 at the top of the bottom source / drain plug 312.

[0053] The material of the second interlayer dielectric layer 314 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride. In this embodiment, the material of the second interlayer dielectric layer 314 is silicon oxide.

[0054] In this embodiment, the etching barrier layer 313 is located between the sidewall of the second interlayer dielectric layer 314 and the first interlayer dielectric layer 302.

[0055] The etch barrier layer 313 can better define the overlay alignment accuracy, that is, self-alignment is achieved during the formation of the gate contact hole and the source / drain contact hole. This is beneficial to improve the positional accuracy of the gate contact hole and the source / drain contact hole, thereby improving the alignment accuracy of the top source / drain plug and the corresponding bottom source / drain plug 312, as well as the alignment accuracy of the gate plug and the corresponding gate structure 307, and thus improving the performance of the semiconductor structure. Moreover, during the formation of the source / drain contact hole, only the etching selectivity ratio between the second interlayer dielectric layer 314 and the etch barrier layer 313 needs to be considered, and during the formation of the gate contact hole, only the etching selectivity ratio between the first interlayer dielectric layer 302 and the etch barrier layer 313 needs to be considered. Therefore, it is easy to achieve self-alignment during the formation of the gate contact hole and the source / drain contact hole.

[0056] It should be noted that the lateral dimension of the etch barrier layer 313 should not be too large or too small. If the lateral dimension of the etch barrier layer 313 is too large, it will easily occupy too much space on the top of the gate structure 307, causing the formed gate plug 316 to fail to meet the process requirements, thereby affecting the structural performance of the semiconductor. If the lateral dimension of the etch barrier layer 313 is too small, it will easily fail to perform its corresponding function in the etching process for forming gate contact holes or source / drain contact holes, thus making it difficult to achieve self-alignment during the formation of gate contact holes or source / drain contact holes. Therefore, in this embodiment, the lateral dimension of the etch barrier layer 313 is 50 Å to 200 Å, defined as the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure 307. For example, the lateral dimension of the etch barrier layer 313 is 70 Å, 100 Å, or 150 Å.

[0057] In this embodiment, the material of the etching barrier layer 313 includes one or more of silicon nitride, silicon carbide, and silicon carbide.

[0058] The silicon nitride, silicon carbide, or silicon carbide generally have the characteristics of high hardness, wear resistance, and etching resistance, which enables the etching barrier layer 313 to maintain a good morphology.

[0059] In this embodiment, the semiconductor structure further includes a protective layer 311 located on the sidewall of the bottom source / drain plug 312, and the top of the protective layer 311 is flush with the top of the bottom source / drain plug 312.

[0060] Specifically, the protective layer 311 protects the sidewalls of the bottom source / drain plug 312.

[0061] The material of the protective layer 311 includes one or more of silicon nitride or silicon carbonitride.

[0062] In this embodiment, the lateral dimension of the protective layer 311 is 50 angstroms to 200 angstroms, with the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure 307 as the lateral direction.

[0063] It should be noted that the lateral dimension of the protective layer 311 should not be too large or too small. If the lateral dimension of the protective layer 311 is too large, it will occupy too much space of the bottom source / drain plug 312, thus preventing the bottom source / drain plug 312 from meeting process requirements. If the lateral dimension of the protective layer 311 is too small, it will easily lead to the bottom source / drain plug 312 being too large, increasing the probability of short circuit between the bottom source / drain plug 312 and the adjacent gate structure 307, thereby affecting the structural performance of the semiconductor. Therefore, in this embodiment, the lateral dimension of the protective layer 311 is 50 angstroms to 200 angstroms, with the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure defined as the lateral direction. For example, the lateral dimension of the protective layer 311 is 70 angstroms, 100 angstroms, or 150 angstroms.

[0064] It should be noted that, in this embodiment, the semiconductor structure further includes: a bottom residual layer 346, located between the top of the bottom source / drain plug 312 and the second interlayer dielectric layer 314, and the bottom of the barrier layer 313 and the etch barrier layer 313 are connected, and the barrier layer 313 and the etch barrier layer 313 are an integral structure.

[0065] During the process of forming the top source / drain plug 317 on the top of the bottom source / drain plug 312, the second interlayer dielectric layer 314 needs to be etched. During the etching of the second interlayer dielectric layer 314, the bottom residual layer 346 can act as an etching stop layer, and the bottom residual layer 346 protects the bottom source / drain plug 312.

[0066] In this embodiment, the semiconductor structure further includes a third interlayer dielectric layer 315, located on top of the first interlayer dielectric layer 302, the second interlayer dielectric layer 314, and the etch barrier layer 313.

[0067] The third interlayer dielectric layer 315 is used to achieve electrical isolation between the gate plug 316 and the top source / drain plug 317.

[0068] Therefore, the material of the third interlayer dielectric layer 315 is an insulating material. The material of the third interlayer dielectric layer 315 includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the third interlayer dielectric layer 315 is silicon oxide.

[0069] In this embodiment, the gate plug 316 penetrates the first interlayer dielectric layer 302 between adjacent etch barrier layers 313, and the bottom of the gate plug 316 is connected to the gate structure 307.

[0070] The gate plug 316 is used to realize the electrical connection between the gate structure 307 and external circuitry or other interconnection structures.

[0071] In this embodiment, the top source / drain plug 317 penetrates the second interlayer dielectric layer 314 between adjacent etch barrier layers 313, and the bottom of the top source / drain plug 317 is connected to the bottom source / drain plug 312.

[0072] The top source / drain plug 317 and the bottom source / drain plug 312 constitute a source / drain plug, thereby enabling the electrical connection of the source / drain doped layer 308 with other interconnect structures or external circuits.

[0073] It should be noted that, in this embodiment, the gate plug 316 and the top source / drain plug 317 also penetrate the third interlayer dielectric layer 315.

[0074] Specifically, the gate plug 316 and the top source / drain plug 317 penetrate the third interlayer dielectric layer 315, increasing their volume and achieving better electrical connection performance during electrical connections with other interconnect structures or external circuits.

[0075] In this embodiment, under the action of the etch barrier layer 313, self-alignment is easily achieved during the formation of both the gate contact hole and the source / drain contact hole. Therefore, the gate plug 316 can be formed above the gate structure 307 in the active region. The gate plug 316 is an active gate contact hole plug (COAG). Compared with the scheme where the gate plug is located in contact with the gate structure in the isolation region, this embodiment eliminates the portion of the gate structure 307 located in the isolation region, which helps to save chip area and achieve further reduction in chip size.

[0076] Figures 3 to 15 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure fabrication method of the present invention.

[0077] refer to Figure 3 A substrate is provided, on which a gate structure 107 is formed. Active and drain doped layers 108 are formed in the substrate on both sides of the gate structure 107. A first interlayer dielectric layer 102 is formed on the exposed substrate of the gate structure 107, and the first interlayer dielectric layer 102 covers the top of the gate structure 107.

[0078] The substrate includes a substrate 100 and fins 101 located on the substrate 100. In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate may also be made of other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0079] In this embodiment, the fin 101 is disposed on the substrate 100, and the material of the fin 101 is the same as that of the substrate, which is silicon.

[0080] In other embodiments, when the formation method is used to form a planar transistor, the substrate may also be a planar substrate.

[0081] Continue to refer to Figure 3 In this embodiment, the method for fabricating the semiconductor structure further includes: after forming the fin 101, forming an isolation layer 150 on the substrate 100 exposed by the fin 101, the isolation layer 150 covering part of the sidewall of the fin 101.

[0082] The isolation layer 150 is used to isolate adjacent devices. The material of the isolation layer 150 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 150 is silicon oxide.

[0083] In this embodiment, the gate structure 107 is a metal gate structure, used to control the opening and closing of the transistor channel.

[0084] The gate structure 107 includes a high-k gate dielectric layer, a work function layer conformally covering the high-k gate dielectric layer, and a gate electrode layer covering the work function layer.

[0085] In this embodiment, the gate structure 107 is formed by forming a high k last metal gate last after forming a high k last gate dielectric layer. Therefore, before the gate structure 107 is formed, the position of the gate structure 107 is occupied by a dummy gate.

[0086] In this embodiment, after forming the pseudo-gate structure, source / drain doped layers 108 are formed in the fins 101 on both sides of the pseudo-gate structure.

[0087] When the formed semiconductor device is a PMOS transistor, the material of the source / drain doped layer 108 is silicon germanide doped with P-type ions, wherein the P-type ions include B, Ga, or In. When the formed semiconductor device is an NMOS transistor, the material of the source / drain doped layer 108 is silicon carbide or silicon doped with N-type ions, wherein the N-type ions include P, As, or Sb.

[0088] It should be noted that, in the step of providing the substrate, the sidewalls of the gate structure 107 are formed with sidewalls 104. Specifically, the sidewalls 104 are formed before the source / drain doped layer 108 is formed.

[0089] The sidewall 104 is used to protect the sidewall of the gate structure 107, and the sidewall 104 is also used to define the formation location of the source / drain doped layer 108.

[0090] The sidewall 104 can be a single-layer structure or a multi-layer structure, and the material of the sidewall 104 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 104 is a single-layer structure, and the material of the sidewall 104 is silicon nitride.

[0091] In this embodiment, a first interlayer dielectric layer 102 is formed on the exposed substrate of the gate structure 107, and the first interlayer dielectric layer 102 also covers the top of the gate structure 107.

[0092] The first interlayer dielectric layer 102 is used to isolate adjacent transistors. The first interlayer dielectric layer 102 also serves to provide a process basis for the subsequent formation of openings exposing the source / drain doped layers 108.

[0093] The first interlayer dielectric layer 102 is made of an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride. In this embodiment, the first interlayer dielectric layer 102 is made of silicon oxide.

[0094] It should be noted that, in the step of providing the substrate, a gate cap layer 106 is formed on the top of the gate structure 107.

[0095] The gate capping layer 106 protects the gate structure 107 during subsequent manufacturing processes. In this embodiment, the gate capping layer 106 is made of silicon nitride.

[0096] In this embodiment, after etching back a portion of the thickness of the gate structure 107 to form a groove surrounded by the sidewall 104 and the gate structure 107, the gate cap layer 106 is formed in the groove.

[0097] refer to Figure 4 An opening 109 is formed through the first interlayer dielectric layer 102 between the gate structures 107, and the opening 109 exposes the source and drain doped layers 108.

[0098] Subsequently, a bottom source / drain plug is formed in the opening 109, and an etching barrier layer is formed on the sidewall of the opening exposed by the bottom source / drain plug. The remaining space of the opening 109 exposed by the bottom source / drain plug and the etching barrier layer is used to form a second interlayer dielectric layer.

[0099] The step of forming the opening includes: forming a mask material layer (not shown) on top of the first interlayer dielectric layer 102; patterning the mask material layer, with the remaining mask material layer serving as a mask layer 103; and etching the first interlayer dielectric layer 102 using the mask layer 103 as a mask to form an opening 109 exposing the source / drain doped layer 108.

[0100] In this embodiment, the first interlayer dielectric layer 102 is etched using a dry etching process.

[0101] It should be noted that after forming the opening 109, the process also includes removing the mask layer 103.

[0102] Combination and reference Figures 5 to 6 After forming the opening 109, the method further includes: performing lateral etching on the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 at a preset height H near the top of the opening 109.

[0103] The direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure 107 is called the transverse direction.

[0104] Subsequently, a bottom source / drain plug is formed within the opening 109. The distance from the top of the bottom source / drain plug to the top of the first interlayer dielectric layer 102 is equal to the preset height. By first performing lateral etching on the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 at the preset height H, after the bottom source / drain plug is formed, the sidewall of the opening 109 exposed by the bottom source / drain plug protrudes relative to the sidewall of the bottom source / drain plug. Therefore, after forming an etch barrier layer on the sidewall of the opening exposed by the bottom source / drain plug, the probability of the etch barrier layer covering the top surface of the bottom source / drain plug is reduced. In other words, more of the top surface of the bottom source / drain plug is exposed by the etch barrier layer. Correspondingly, after forming the top source / drain plug on the top surface of the bottom source / drain plug, the contact area between the bottom source / drain plug and the top source / drain plug is larger, thereby improving the electrical connection effect between the bottom source / drain plug and the top source / drain plug, which is beneficial to improving the performance of the semiconductor structure.

[0105] Moreover, compared with the scheme of first forming the bottom source / drain plug and then laterally etching the exposed opening sidewall of the bottom source / drain plug, this embodiment first laterally etches the opening 109 sidewall of the preset height H, thereby avoiding damage to the bottom source / drain plug caused by the lateral etching.

[0106] Continue to refer to Figures 5 to 6 Before performing lateral etching on the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 at a preset height H, the method further includes: forming a protective layer 111 on a portion of the sidewall of the opening 109, the protective layer 111 being exposed on the sidewall of the opening at a preset height H.

[0107] The protective layer 111 is used to define the height of the opening 109 to be etched laterally.

[0108] Furthermore, in the subsequent process of forming the bottom source / drain plug, the process of forming the bottom source / drain plug includes a back etching step, and the protective layer 111 can also serve as an etching stop.

[0109] In this embodiment, since the protective layer 111 needs to be retained, the material of the protective layer 111 is selected as a dielectric material.

[0110] Furthermore, when the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 at the preset height H is laterally etched, there is a high etching selectivity between the material of the first interlayer dielectric layer 102 and the material of the protective layer 111; during the subsequent formation of the bottom source / drain plug, there is also a high etching selectivity between the material of the bottom source / drain plug and the material of the protective layer 111.

[0111] Correspondingly, the protective layer 111 has high etching resistance.

[0112] Specifically, the material of the protective layer 111 includes one or more of silicon nitride and silicon carbonitride.

[0113] As an example, the material of the protective layer 111 is silicon nitride.

[0114] Specifically, the steps for forming the protective layer 111 include: as follows Figure 5 As shown, a protective material layer 110 is formed on the sidewalls and bottom of the opening 109, and on the top of the first interlayer dielectric layer 102; a filling layer 142 is formed inside the opening 109, and the distance from the top of the filling layer 142 to the top of the first interlayer dielectric layer 102 is the preset height H; Figure 6 As shown, the protective material layer 110 exposed by removing the filling layer 142 is used as the remaining protective material layer 111.

[0115] The filling layer 142 serves as an etching mask for the protective material layer 110 exposed by etching. The filling layer 142 protects the covered protective material layer 110, thereby allowing a portion of the protective material layer 110 to be retained.

[0116] In this embodiment, the filling layer 142 is a material that can act as a mask and is easy to remove.

[0117] In this embodiment, the filling layer 142 is made of organic materials, such as BARC (bottom anti-reflective coating), ODL (organic dielectric layer), photoresist, DARC (dielectric anti-reflective coating), spin-on carbon (SOC), DUO (Deep UV Light Absorbing Oxide), or APF (Advanced Patterning Film).

[0118] In this embodiment, a dry etching process is used to remove the protective material layer 110 exposed by the filling layer 142.

[0119] Specifically, the dry etching process is an anisotropic dry etching process.

[0120] The anisotropic dry etching process has a longitudinal etching rate that is much higher than the transverse etching rate, which can achieve a fairly accurate pattern transformation, causes less damage to the sidewall of the first interlayer dielectric layer 102, and is conducive to precise control of the height of the protective layer 111 located on the sidewall of the opening 109.

[0121] In this embodiment, the protective material layer 110 is formed using an atomic layer deposition (ALD) process.

[0122] Specifically, the atomic layer deposition (ALD) process involves multiple ALD cycles, which helps improve the thickness uniformity of the protective material layer 110, enabling it to cover the bottom and sidewalls of the opening 109, as well as the top of the first interlayer dielectric layer 102. Furthermore, the ALD process offers good gap-filling performance and step coverage, thereby improving the conformal coverage capability of the protective material layer 110. In other embodiments, the protective material layer can also be formed using chemical vapor deposition (CVD).

[0123] It should be noted that after removing the protective material layer 110 exposed by the filling layer 142, the process also includes removing the filling layer 142.

[0124] Specifically, removing the filler layer 142 provides space for forming the bottom source drain plug.

[0125] In this embodiment, the filling layer 142 is removed using an ashing process.

[0126] In this embodiment, after removing the filling layer 142, the method further includes removing the protective layer 111 at the bottom of the opening 109 to expose the surface of the source / drain doped layer 108.

[0127] Accordingly, refer to Figure 6 In the step of lateral etching of the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 at a preset height H, the lateral etching is performed using the protective layer 111 as a mask.

[0128] In this embodiment, a dry etching process is used to laterally etch the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 at a preset height H.

[0129] Specifically, the dry etching process is an anisotropic dry etching process.

[0130] The anisotropic dry etching process has a longitudinal etching rate that is much greater than the lateral etching rate, which is beneficial for precise control of the lateral etching amount.

[0131] Prior to lateral etching, a mask layer (not shown) is formed on top of the first interlayer dielectric layer 102. This mask layer defines the area of ​​the first interlayer dielectric layer 102 to be laterally etched. For example, the material of the mask layer can be photoresist.

[0132] In this embodiment, in the step of lateral etching the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 at a preset height H, the lateral etching amount is 50 angstroms to 200 angstroms.

[0133] It should be noted that the lateral etching depth should not be too large or too small. If the lateral etching depth is too large, it will easily occupy too much of the top space of the gate structure 107, making the gate plug formed on the top of the gate structure 107 fail to meet the process requirements, thus affecting the structural performance of the semiconductor. If the lateral etching depth is too small, after forming an etch barrier layer on the exposed sidewall of the bottom source / drain plug, the etch barrier layer, due to its certain lateral dimension, will easily cover the top surface of the top source / drain plug, thus affecting the electrical connection between the top source / drain plug and the corresponding bottom source / drain plug. Therefore, in this embodiment, in the step of lateral etching the first interlayer dielectric layer 102 exposed on the sidewall of the opening 109 at a preset height H, the lateral etching depth is 50 angstroms to 200 angstroms.

[0134] Reference Figures 7 to 8 A bottom source / drain plug 112 is formed within the opening 109, the top of the bottom source / drain plug 112 being lower than the top of the opening 109 and higher than the top of the gate structure 107.

[0135] The bottom source / drain plug 112 is in contact with the source / drain doped layer 108 to enable electrical connection between the source / drain doped layer 108 and external circuits or other interconnect structures.

[0136] Subsequently, a top source / drain plug is formed on the bottom source / drain plug 112, which is in contact with the bottom source / drain plug 112. The top source / drain plug and the source / drain doped layer 108 are electrically connected through the bottom source / drain plug 112.

[0137] In this embodiment, the top of the bottom source drain plug 112 is lower than the top of the opening 109.

[0138] The top of the bottom source drain plug 112 is lower than the top of the opening 109, which provides space for the subsequent formation of an etching barrier layer on the exposed sidewall of the opening of the bottom source drain plug 112.

[0139] In this embodiment, the bottom source / drain plug 112 is made of tungsten. Tungsten has low resistivity, which helps to improve the signal delay of the subsequent RC circuit and increase the processing speed of the chip. It also helps to reduce the resistance of the bottom source / drain plug 112, thereby reducing power consumption. In other embodiments, the bottom source / drain plug can also be made of conductive materials such as cobalt or ruthenium.

[0140] In this embodiment, the step of forming the bottom source / drain plug 112 includes: as follows Figure 7 As shown, in the opening 109 (e.g.) Figure 6 As shown, a conductive material layer 140 is filled in; as Figure 8 As shown, the conductive material layer 140 is planarized with the top of the first interlayer dielectric layer 102 as the stop position; after the planarization, the conductive material layer 140 with a certain thickness is etched back with the top of the protective layer 111 as the stop position, and the remaining conductive material layer 140 after the etch back serves as the bottom source / drain plug 112.

[0141] By first planarizing the conductive material layer 140, the conductive material layer 140 located in the opening 109 is retained, and the top surface flatness of the remaining conductive material layer 140 is made higher. This improves the etching uniformity when the conductive material layer 140 in the opening 109 is subsequently etched back, and correspondingly improves the top surface flatness and height uniformity of the bottom source / drain plug 112.

[0142] In this embodiment, a dry etching process (e.g., anisotropic dry etching process) is used to etch back a portion of the thickness of the conductive material layer 140.

[0143] Accordingly, in this embodiment, the distance from the top of the bottom source / drain plug 112 to the top of the first interlayer dielectric layer 102 is equal to the preset height H.

[0144] refer to Figure 9 An etch barrier layer 113 is formed on the sidewall of the opening 109 exposed by the bottom source drain plug 112.

[0145] Subsequently, a second interlayer dielectric layer is formed in the remaining openings, forming a gate contact hole located between adjacent etch stop layers and penetrating the first interlayer dielectric layer. The bottom of the gate contact hole exposes the gate structure, forming a source / drain contact hole located between adjacent etch stop layers and penetrating the second interlayer dielectric layer. The bottom of the source / drain contact hole exposes the bottom source / drain plug, and a gate plug is formed in the gate contact hole. A top source / drain plug is formed in the source / drain contact hole. In this embodiment, by forming an etch barrier layer 113 on the sidewall of the exposed opening 109 of the bottom source / drain plug 112, the etch barrier layer 113 can better define the overlay alignment accuracy during the subsequent formation of the source / drain contact holes and the gate contact holes. That is, self-alignment is achieved during the formation of the gate contact holes and the source / drain contact holes. This is beneficial to improve the positional accuracy of the gate contact holes and the source / drain contact holes, thereby improving the alignment accuracy between the top source / drain plug and the corresponding bottom source / drain plug 112, and the alignment accuracy between the gate plug and the corresponding gate structure 107, thus improving the performance of the semiconductor structure. Moreover, during the formation of the source / drain contact holes, only the etching selectivity ratio between the second interlayer dielectric layer and the etch barrier layer 113 needs to be considered, and during the formation of the gate contact holes, only the etching selectivity ratio between the first interlayer dielectric layer 102 and the etch barrier layer 113 needs to be considered. Therefore, it is easy to achieve self-alignment during the formation of the gate contact holes and the source / drain contact holes.

[0146] In this embodiment, the step of forming an etching barrier layer 113 on the sidewall of the exposed opening 109 of the bottom source / drain plug 112 includes: forming an etching barrier material layer 143 on the sidewall of the exposed opening 109 of the bottom source / drain plug 112, the top of the bottom source / drain plug 112, and the top of the first interlayer dielectric layer 102, wherein the etching barrier material layer 143 located on the sidewall of the opening 109 serves as the etching barrier layer 113.

[0147] The etching barrier material layer 143 provides the technological basis for forming the etching barrier layer 113.

[0148] In this embodiment, the etch barrier material layer 143 is formed using atomic layer deposition (ALD). In other embodiments, the etch barrier material layer may also be formed using chemical vapor deposition (CVD).

[0149] In this embodiment, during the formation of the etching barrier layer 113, the etching barrier material layer 143 on the top of the bottom source / drain plug 112 and the top of the first interlayer dielectric layer 102 is retained so that the etching barrier material layer 143 on the top of the first interlayer dielectric layer 102 can be removed during the subsequent formation of the second interlayer dielectric layer, thereby simplifying the process steps.

[0150] In this embodiment, there is a high etching selectivity between each interlayer dielectric layer and the etching barrier layer 113, thereby enabling self-alignment to be achieved during the subsequent formation of source / drain contact holes and gate contact holes.

[0151] As an example, the material of the etch barrier layer 113 must satisfy the following condition: the etch selectivity ratio between each interlayer dielectric layer and the etch barrier layer 113 is greater than 3.

[0152] For example, the etching selectivity ratio between each interlayer dielectric layer and the etching barrier layer 113 is greater than 3 and less than 10.

[0153] Specifically, the etching barrier layer 113 has a higher etching resistance than each interlayer dielectric layer.

[0154] In this embodiment, the material of the etching barrier layer 113 includes one or two of silicon nitride, silicon carbide, and silicon carbide.

[0155] As an example, the etch barrier layer 113 is made of silicon nitride. In other embodiments, the etch barrier layer is made of silicon carbide.

[0156] refer to Figures 10 to 11 After the etching barrier layer 113 is formed, a second interlayer dielectric layer 114 is formed in the remaining opening 109.

[0157] The second interlayer dielectric layer 114 provides space for the subsequent formation of the top source / drain plug.

[0158] In this embodiment, the step of forming the second interlayer dielectric layer 114 in the remaining opening 109 includes: as follows Figure 10 As shown, a dielectric material layer 190 is formed in the remaining opening 109, the dielectric material layer 190 covering the etching barrier material layer 143; as Figure 11As shown, the dielectric material layer 190 is planarized with the top of the first interlayer dielectric layer 102 as the stop position, and the remaining dielectric material layer 190 serves as the second interlayer dielectric layer 114. During the planarization process, the etching barrier material layer 143 above the top of the first interlayer dielectric layer 102 is removed.

[0159] The dielectric material layer 190 provides a process basis for forming the second interlayer dielectric layer 114.

[0160] It should be noted that the planarization process of the dielectric material layer 190 also includes planarizing the etching barrier material layer 143, which is higher than the top of the first interlayer dielectric layer 102. Accordingly, the process steps are simplified and the process cost is reduced.

[0161] In this embodiment, after removing the etching barrier material layer 143 above the top of the first interlayer dielectric layer 102, the remaining etching barrier material layer 143 on the top of the bottom source / drain plug 112 is retained as the bottom residual layer 146.

[0162] refer to Figure 12 After forming the second interlayer dielectric layer 114, the method further includes forming a third interlayer dielectric layer 115 on top of the first interlayer dielectric layer 102 and the second interlayer dielectric layer 114.

[0163] The third interlayer dielectric layer 115 provides space for forming gate contact holes and source / drain contact holes, and also serves to achieve electrical isolation between the subsequent gate plug and the top source / drain plug.

[0164] In this embodiment, the third interlayer dielectric layer 115 ensures that the heights of the gate plug and the top source / drain plug meet the process requirements, while also preventing the height of the first interlayer dielectric layer 102 from being too high. Consequently, the aspect ratio of the opening 109 is not too large, which facilitates the formation of the bottom source / drain plug 112, the formation of the etching barrier layer 113, and the lateral etching of the first interlayer dielectric layer 102 exposed on the wall of the opening 109 at a preset height H. This reduces the process difficulty and lowers the process cost.

[0165] The material of the third interlayer dielectric layer 115 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the third interlayer dielectric layer 115 is silicon oxide.

[0166] refer to Figure 13A gate contact hole 130 is formed between adjacent etch barrier layers 113 and through the first interlayer dielectric layer 102, with the bottom of the gate contact hole 130 exposing the gate structure 107.

[0167] The gate contact hole 130 provides space for the subsequent formation of the gate plug.

[0168] In this embodiment, during the step of forming the gate contact hole 130, the gate contact hole 130 penetrates the third interlayer dielectric layer 115 and the first interlayer dielectric layer 102.

[0169] In this embodiment, a dry etching process is used to remove the third interlayer dielectric layer 115 and the first interlayer dielectric layer 102 on the top of the gate structure 107, forming a gate contact hole 130 that exposes the gate structure 107.

[0170] It should be noted that, in this embodiment, the process of forming the gate contact hole 130 also includes: removing the gate cap layer 106 on the top of the gate structure 107.

[0171] refer to Figure 14 A source / drain contact hole 131 is formed between adjacent etch barrier layers 113 and through the second interlayer dielectric layer 114, with the bottom of the source / drain contact hole 131 exposing the bottom source / drain plug 112.

[0172] The source / drain contact hole 131 provides space for the subsequent formation of the top source / drain plug.

[0173] In this embodiment, during the step of forming the source / drain contact hole 131, the source / drain contact hole 131 penetrates the third interlayer dielectric layer 115 and the second interlayer dielectric layer 114.

[0174] In this embodiment, a dry etching process is used to remove the third interlayer dielectric layer 115 and the second interlayer dielectric layer 114 on the top of the bottom source / drain plug 112, forming a source / drain contact hole 131 that exposes the bottom source / drain plug 112.

[0175] It should be noted that the process of forming the source / drain contact hole 131 also includes removing the bottom residual layer 146 on top of the bottom source / drain plug 112. During the etching of the third interlayer dielectric layer 115 and the first interlayer dielectric layer 102, the bottom residual layer 146 can also act as an etching stop, thereby reducing the probability of the bottom source / drain plug 112 being over-etched.

[0176] refer to Figure 15 A gate plug 116 is formed in the gate contact hole 130, and a top source / drain plug 117 is formed in the source / drain contact hole 131.

[0177] The gate plug 116 is used to realize the electrical connection between the gate structure 107 and external circuitry or other interconnection structures.

[0178] The top source / drain plug 117 and the bottom source / drain plug 112 constitute a source / drain plug, thereby enabling the electrical connection of the source / drain doped layer 108 with other interconnect structures or external circuits.

[0179] Specifically, after filling the gate contact hole 130 and the source / drain contact hole 131 with conductive material, the conductive material is planarized, and the conductive material in the gate contact hole 130 is retained as the gate plug 116, and the conductive material in the source / drain contact hole 131 is retained as the top source / drain plug 117.

[0180] The specific description of the gate plug 116 and the top source / drain plug 117 will not be repeated here in this embodiment.

[0181] In this embodiment, under the action of the etch barrier layer 113, self-alignment is easily achieved during the formation of the gate contact hole 130 and the source / drain contact hole 131. Therefore, the gate plug 116 can be formed above the gate structure 107 in the active region. The gate plug 116 is an active gate contact hole plug (COAG). Compared with the scheme where the gate plug contacts the gate structure located in the isolation region, this embodiment eliminates the portion of the gate structure 107 located in the isolation region, which is beneficial for saving chip area and achieving further reduction in chip size.

[0182] Figure 16 This is a schematic diagram of the structure corresponding to each step in another embodiment of the method for forming the semiconductor structure of the present invention.

[0183] The similarities between the embodiments of the present invention and the first embodiment will not be repeated here. The differences between the embodiments of the present invention and the first embodiment are as follows:

[0184] refer to Figure 16 In the same step, the gate contact hole 230 and the source / drain contact hole 231 are formed.

[0185] By forming the gate contact hole 230 and the source / drain contact hole 231 in the same step, the process steps are simplified, the process cost is reduced, and the manufacturing efficiency is improved.

[0186] Furthermore, in this embodiment, a gate cap layer 206 is formed on the top of the gate structure 207, and a bottom residual layer 246 is formed on the top of the bottom source / drain plug 212. Therefore, during the etching of the third interlayer dielectric layer 215, the second interlayer dielectric layer 214, and the first interlayer dielectric layer 202, the gate cap layer 206 and the bottom residual layer 246 can be used as etching stop positions, making it easy to form the gate contact hole 230 and the source / drain contact hole 231 in the same etching step, and minimizing damage to the gate contact hole 230 and the source / drain contact hole 231.

[0187] For a detailed description of the formation method described in this embodiment, please refer to the corresponding description in the first embodiment; this embodiment will not repeat the description here.

[0188] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A substrate on which a gate structure is formed, and source and drain doped layers are formed in the substrate on both sides of the gate structure. A first interlayer dielectric layer is formed on the exposed substrate of the gate structure, and the first interlayer dielectric layer covers the top of the gate structure. A bottom source / drain plug is located in the first interlayer dielectric layer between the gate structures and is connected to the source / drain doped layer. The top of the bottom source / drain plug is lower than the top of the first interlayer dielectric layer and higher than the top of the gate structure. The second interlayer dielectric layer penetrates the first interlayer dielectric layer at the top of the bottom source / drain plug; An etching barrier layer is located between the sidewall of the second interlayer dielectric layer and the first interlayer dielectric layer; A gate plug extends through the first interlayer dielectric layer between adjacent etch barrier layers, and the bottom of the gate plug is connected to the gate structure; A top source / drain plug extends through the second interlayer dielectric layer between adjacent etch barrier layers, and the bottom of the top source / drain plug is connected to the bottom source / drain plug.

2. The semiconductor structure as described in claim 1, characterized in that, In the first interlayer dielectric layer located on top of the gate structure, the surface opposite to the sidewall of the etch barrier layer is the first side surface, and the surface opposite to the sidewall of the bottom source / drain plug is the second side surface, with the first side surface protruding relative to the second side surface.

3. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a protective layer located on the sidewall of the bottom source / drain plug, with the top of the protective layer flush with the top of the bottom source / drain plug.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes: a third interlayer dielectric layer, located on top of the first interlayer dielectric layer, the second interlayer dielectric layer and the etch barrier layer; The gate plug and the top source / drain plug also extend through the third interlayer dielectric layer.

5. The semiconductor structure as described in claim 1, characterized in that, With the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure as the lateral direction, the lateral dimension of the etch barrier layer is 50 angstroms to 200 angstroms.

6. The semiconductor structure as described in claim 1, characterized in that, The distance from the top of the bottom source / drain plug to the top of the first interlayer dielectric layer is 50 angstroms to 500 angstroms.

7. The semiconductor structure as described in claim 2, characterized in that, The first side protrudes from the second side by an amount of 50 angstroms to 200 angstroms.

8. The semiconductor structure as described in claim 3, characterized in that, With the direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure as the lateral direction, the lateral dimension of the protective layer is 50 angstroms to 200 angstroms.

9. The semiconductor structure as described in claim 1, characterized in that, The etching barrier layer is made of one or more of silicon nitride, silicon carbide, and silicon carbide.

10. The semiconductor structure as described in claim 3, characterized in that, The protective layer is made of one or more of silicon nitride and silicon carbonitride.

11. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, on which a gate structure is formed, and source and drain doped layers are formed in the substrate on both sides of the gate structure. A first interlayer dielectric layer is formed on the exposed substrate of the gate structure, and the first interlayer dielectric layer covers the top of the gate structure. An opening is formed in the first interlayer dielectric layer that penetrates between the gate structures, and the opening exposes the source and drain doped layers; A bottom source / drain plug is formed within the opening, the top of the bottom source / drain plug being lower than the top of the opening and higher than the top of the gate structure; An etch barrier layer is formed on the exposed sidewall of the bottom source drain plug; After the etching barrier layer is formed, a second interlayer dielectric layer is formed in the remaining opening; A gate contact hole is formed between adjacent etch barrier layers and through the first interlayer dielectric layer, with the bottom of the gate contact hole exposing the gate structure. A source / drain contact hole is formed between adjacent etch barrier layers and through the second interlayer dielectric layer, with the bottom of the source / drain contact hole exposing the bottom source / drain plug; A gate plug is formed in the gate contact hole, and a top source / drain plug is formed in the source / drain contact hole.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, The direction parallel to the substrate surface and perpendicular to the sidewall of the gate structure is defined as the lateral direction; After forming an opening in the first interlayer dielectric layer that penetrates between the gate structures, and before forming a bottom source / drain plug in the opening, the method further includes: laterally etching the first interlayer dielectric layer exposed on the sidewall of the opening at a predetermined height near the top of the opening. In the step of forming a bottom source / drain plug within the opening, the distance from the top of the bottom source / drain plug to the top of the first interlayer dielectric layer is equal to the preset height.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, After forming an opening in the first interlayer dielectric layer that penetrates between the gate structures, before performing lateral etching on the first interlayer dielectric layer exposed at a predetermined height on the sidewall of the opening, the method further includes: forming a protective layer on a portion of the sidewall of the opening, the protective layer being exposed at a predetermined height on the sidewall of the opening; In the step of lateral etching the first interlayer dielectric layer exposed on the sidewall of the opening at a preset height, the protective layer is used as a mask for the lateral etching.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, The steps of forming the protective layer include: forming a protective material layer on the sidewalls and bottom of the opening, and on the top of the first interlayer dielectric layer; forming a filling layer inside the opening, wherein the distance from the top of the filling layer to the top of the first interlayer dielectric layer is the preset height; removing the protective material layer exposed by the filling layer, and the remaining protective material layer serves as the protective layer. After removing the protective material layer exposed by the filler layer, the process further includes: removing the filler layer.

15. The method for forming a semiconductor structure as described in claim 12, characterized in that, A dry etching process is used to etch the first interlayer dielectric layer exposed at a predetermined height on the sidewall of the opening.

16. The method for forming a semiconductor structure as described in claim 14, characterized in that, The filling layer is made of organic materials.

17. The method for forming a semiconductor structure as described in claim 14, characterized in that, The protective material layer exposed by the filling layer is removed using a dry etching process.

18. The method for forming a semiconductor structure as described in claim 11, characterized in that, The step of forming an etching barrier layer on the exposed opening sidewall of the bottom source / drain plug includes: forming an etching barrier material layer on the exposed opening sidewall of the bottom source / drain plug, the top of the bottom source / drain plug, and the top of the first interlayer dielectric layer, wherein the etching barrier material layer located on the opening sidewall serves as an etching barrier layer. The step of forming the second interlayer dielectric layer in the remaining opening includes: forming a dielectric material layer in the remaining opening, the dielectric material layer covering the etch barrier material layer; planarizing the dielectric material layer with the top of the first interlayer dielectric layer as the stop position, the remaining dielectric material layer serving as the second interlayer dielectric layer, wherein, during the planarization process, the etch barrier material layer above the top of the first interlayer dielectric layer is removed.

19. The method for forming a semiconductor structure as described in claim 13, characterized in that, The steps of forming the bottom source / drain plug include: filling the opening with a conductive material layer; planarizing the conductive material layer with the top of the first interlayer dielectric layer as the stop position; after the planarization, etching back a portion of the conductive material layer with the top of the protective layer as the stop position, and using the remaining conductive material layer after etching back as the bottom source / drain plug.

20. The method for forming a semiconductor structure as described in claim 11, characterized in that, After forming the second interlayer dielectric layer and before forming the gate contact hole and the source / drain contact hole, the method further includes: forming a third interlayer dielectric layer on top of the first interlayer dielectric layer and the second interlayer dielectric layer; In the step of forming the gate contact hole, the gate contact hole penetrates the third interlayer dielectric layer and the first interlayer dielectric layer; In the step of forming the source / drain contact hole, the source / drain contact hole penetrates the third interlayer dielectric layer and the second interlayer dielectric layer.

21. The method for forming a semiconductor structure as described in claim 14, characterized in that, The protective material layer is formed using atomic layer deposition (ALD).

22. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the same step, the gate contact hole and the source / drain contact hole are formed.

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