Semiconductor device

Abstract

A semiconductor device includes a first active pattern disposed on a substrate; a device isolation layer filling a trench defining the first active pattern; a first channel pattern and a first source / drain pattern disposed on the first active pattern, wherein the first channel pattern includes semiconductor patterns stacked and spaced apart from each other; a gate electrode extending and spanning the first channel pattern; a gate dielectric layer disposed between the first channel pattern and the gate electrode; and a first passivation pattern disposed between the device isolation layer and a first sidewall of the first active pattern. The first passivation pattern includes an upper portion protruding upward from the device isolation layer and a lower portion buried in the device isolation layer. The gate dielectric layer covers the upper portion of the first passivation pattern.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods of manufacturing them, and more specifically, to semiconductor devices including field-effect transistors and methods of manufacturing them. Background Technology

[0002] Semiconductor devices can include integrated circuits, which include metal-oxide-semiconductor field-effect transistors (MOSFETs). As the size and design rules of semiconductor devices continue to shrink, the size of MOSFETs is also shrinking proportionally. This scaling down of MOSFETs can degrade the operating characteristics of semiconductor devices. Summary of the Invention

[0003] Some embodiments of the present invention provide semiconductor devices with improved reliability and enhanced electrical characteristics.

[0004] Some embodiments of the present invention provide methods for manufacturing semiconductor devices with improved reliability and enhanced electrical properties.

[0005] According to some embodiments of the present invention, a semiconductor device includes: a first active pattern disposed on a substrate; a device isolation layer filling a trench defining the first active pattern; a first channel pattern and a first source / drain pattern disposed on the first active pattern, the first channel pattern including a plurality of semiconductor patterns stacked and spaced apart from each other; a gate electrode extending across the first channel pattern; a gate dielectric layer disposed between the first channel pattern and the gate electrode; and a first passivation pattern disposed between the device isolation layer and a first sidewall of the first active pattern. The first passivation pattern includes an upper portion protruding upward from the device isolation layer and a lower portion buried in the device isolation layer. The gate dielectric layer covers the upper portion of the first passivation pattern.

[0006] According to some embodiments of the present invention, a semiconductor device includes: a first active pattern disposed on a substrate; a device isolation layer filling a trench defining the first active pattern; a first channel pattern and a first source / drain pattern disposed on the first active pattern, the first channel pattern including a plurality of semiconductor patterns stacked and spaced apart from each other; a gate electrode extending across the first channel pattern; a gate dielectric layer disposed between the first channel pattern and the gate electrode; a first passivation pattern disposed between the device isolation layer and a first sidewall of the first active pattern; and a second passivation pattern disposed between the device isolation layer and a second sidewall of the first active pattern, the second sidewall being opposite to the first sidewall. The size of the first passivation pattern is different from the size of the second passivation pattern.

[0007] According to some embodiments of the present invention, a semiconductor device includes a first active pattern disposed on a substrate, a device isolation layer filling a trench defining the first active pattern, and a first passivation pattern disposed between the device isolation layer and a first sidewall of the first active pattern. The semiconductor device also includes a first source / drain pattern disposed on the first active pattern and a first channel pattern connected to the first source / drain pattern, the first channel pattern including a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern sequentially stacked and spaced apart from each other. The semiconductor device further includes a gate electrode extending across the first channel pattern in a first direction, the gate electrode including a first portion disposed between the first active pattern and the first semiconductor pattern, a second portion disposed between the first semiconductor pattern and the second semiconductor pattern, a third portion disposed between the second semiconductor pattern and the third semiconductor pattern, and a fourth portion disposed on the third semiconductor pattern. The semiconductor device further includes a gate dielectric layer disposed between a first channel pattern and a gate electrode, a plurality of gate spacers disposed on opposing sidewalls of a fourth portion of the gate electrode, a gate cap pattern disposed on the top surface of the gate electrode, a first interlayer dielectric layer disposed on the gate cap pattern, an active contact penetrating the first interlayer dielectric layer and electrically connected to a first source / drain pattern, and a gate contact penetrating the first interlayer dielectric layer and electrically connected to the gate electrode. The semiconductor device also includes: a second interlayer dielectric layer disposed on the first interlayer dielectric layer; a first metal layer disposed in the second interlayer dielectric layer, the first metal layer including a plurality of first lines electrically connected to the active contact and the gate contact; a third interlayer dielectric layer disposed on the second interlayer dielectric layer; and a second metal layer disposed in the third interlayer dielectric layer. The second metal layer includes a plurality of second lines electrically connected to corresponding first lines among the plurality of first lines. A first passivation pattern includes an upper portion protruding upward from the device isolation layer and a lower portion buried in the device isolation layer. The gate dielectric layer covers the upper portion of the first passivation pattern.

[0008] According to some embodiments of the present invention, a method of manufacturing a semiconductor device includes alternately stacking a plurality of sacrificial layers and a plurality of active layers on a substrate, and forming trenches defining active patterns and stacked patterns on the active patterns by performing a patterning process on the substrate. The stacked patterns include sacrificial layers and active layers. The method further includes: selectively forming a passivation layer on the stacked patterns; forming a device isolation layer that fills the trenches and covers the stacked patterns; exposing the stacked patterns by recessing the device isolation layer and removing the passivation layer, wherein at least a portion of the passivation layer is retained and forms a passivation pattern; forming source / drain patterns on the active patterns; and replacing the sacrificial layers of the stacked patterns with gate electrodes. Attached Figure Description

[0009] The above and other features of the present invention will become more apparent from the detailed description of embodiments of the invention with reference to the accompanying drawings, in which:

[0010] Figure 1 A plan view of a semiconductor device illustrating some embodiments of the concept according to the present invention is shown.

[0011] Figure 2A , Figure 2B , Figure 2C and Figure 2D It shows the respective along Figure 1 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'.

[0012] Figure 3 It shows Figure 2D Enlarged cross-sectional view of part M.

[0013] Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A Some embodiments of the invention are shown. Figure 1 The cross-sectional view corresponding to line A-A'.

[0014] Figure 7B , Figure 8B , Figure 9B and Figure 10B Some embodiments of the invention are shown. Figure 1 The cross-sectional view corresponding to line B-B'.

[0015] Figure 7C , Figure 8C , Figure 9C and Figure 10C Some embodiments of the invention are shown. Figure 1 The cross-sectional view corresponding to line C-C'.

[0016] Figure 4B , Figure 5B , Figure 6B , Figure 7D , Figure 8D , Figure 9D and Figure 10D Some embodiments of the invention are shown. Figure 1 The cross-sectional view corresponding to line D-D'.

[0017] Figures 11 to 13 The illustration shows methods for forming passivation layers and device isolation layers according to some embodiments of the present invention. Figure 1 The cross-sectional view corresponding to line D-D'.

[0018] Figure 14 and Figure 15 The diagram illustrates a method for forming a passivation layer and a device isolation layer according to a comparative example. Figure 1 The cross-sectional view corresponding to line D-D'.

[0019] Figure 16 The diagram illustrates a method for forming a passivation layer and a device isolation layer according to another comparative example. Figure 1 The cross-sectional view corresponding to line D-D'.

[0020] Figure 17 and Figure 18 The illustration shows a method for forming a passivation layer according to some embodiments of the present invention. Figure 1 The cross-sectional view corresponding to line D-D'.

[0021] Figure 19 and Figure 20 The illustration shows a semiconductor device demonstrating some embodiments of the concept according to the present invention. Figure 2D An enlarged cross-sectional view of a modified example of part M drawn in the figure.

[0022] Figure 21 and Figure 22 A cross-sectional view of a semiconductor device illustrating some embodiments of the concept according to the present invention is shown. Detailed Implementation

[0023] Figure 1 A plan view of a semiconductor device illustrating some embodiments of the concept according to the present invention is shown. Figure 2A , Figure 2B , Figure 2C and Figure 2D It shows the respective along Figure 1 The cross-sectional views taken from lines A-A', B-B', C-C' and D-D'. Figure 3 The display shows Figure 2D Enlarged cross-sectional view of part M.

[0024] Reference Figure 1 and Figures 2A to 2D The logic unit LC can be provided on the substrate 100. The logic unit LC may include logic transistors constituting a logic circuit. The substrate 100 may be a compound semiconductor substrate or a semiconductor substrate comprising, for example, silicon, germanium, or silicon-germanium. For example, the substrate 100 may be a silicon substrate. The logic unit LC may include a p-type metal-oxide-semiconductor field-effect transistor (PMOSFET) region PR and an n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) region NR. The PMOSFET region PR and the NMOSFET region NR may be spaced apart from each other in a first direction D1.

[0025] The first active pattern AP1 and the second active pattern AP2 may be defined by a trench TR formed on the upper part of the substrate 100. The first active pattern AP1 and the second active pattern AP2 may be provided on the PMOSFET region PR and the NMOSFET region NR, respectively. The first active pattern AP1 and the second active pattern AP2 may extend in a second direction D2. The first active pattern AP1 and the second active pattern AP2 may be vertical protrusions of the substrate 100.

[0026] The trench TR may be filled with a device isolation layer ST. The device isolation layer ST may include a silicon oxide layer. The device isolation layer ST may not cover either the first channel pattern CH1 or the second channel pattern CH2, which will be described below.

[0027] The liner OLI can be interposed between the device isolation layer ST and the first and second active patterns AP1 and AP2. The liner OLI can directly contact and cover the sidewalls of each of the first active pattern AP1 and the second active pattern AP2. For example, the liner OLI can directly contact and cover the sidewalls of the trench TR. The liner OLI can directly contact and cover the bottom surface of the trench TR. For example, the liner OLI can comprise a silicon oxide layer. In one embodiment of the inventive concept, the liner OLI can comprise the same material as the device isolation layer ST, in which case there may be no boundary between the liner OLI and the device isolation layer ST.

[0028] The passivation pattern NLP can be interposed between the device isolation layer ST and the upper sidewall of each of the first and second active patterns AP1 and AP2. The passivation pattern NLP can also be interposed between the substrate OLI and the device isolation layer ST. The passivation pattern NLP can be adjacent to the upper sidewall of each of the first active pattern AP1 and the second active pattern AP2, but not adjacent to the lower sidewall of each of the first active pattern AP1 and the second active pattern AP2. The passivation pattern NLP can include, for example, SiOC, SiN, SiC, AlO, TiO2, or combinations thereof. For example, the passivation pattern NLP can include SiN. A further detailed description of the passivation pattern NLP will be provided below. Figure 3 Described.

[0029] A first channel pattern CH1 may be provided on a first active pattern AP1. A second channel pattern CH2 may be provided on a second active pattern AP2. Each of the first channel pattern CH1 and the second channel pattern CH2 may include a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 stacked sequentially. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may be spaced apart from each other in a vertical direction (e.g., third direction D3).

[0030] Each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include, for example, silicon (Si), germanium (Ge), or silicon-germanium (SiGe). For example, each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 may include crystalline silicon.

[0031] Multiple first source / drain patterns SD1 can be provided on a first active pattern AP1. Multiple first recesses RS1 can be formed on the upper part of the first active pattern AP1. Multiple first source / drain patterns SD1 can be provided in corresponding first recesses RS1. The first source / drain patterns SD1 can be impurity regions having a first conductivity type (e.g., p-type). A first channel pattern CH1 can be interposed between a pair of first source / drain patterns SD1. For example, the pair of first source / drain patterns SD1 can be interconnected by a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 that are stacked and spaced apart from each other.

[0032] Multiple second source / drain patterns SD2 can be provided on the second active pattern AP2. Multiple second recesses RS2 can be formed on the upper part of the second active pattern AP2. Multiple second source / drain patterns SD2 can be provided in corresponding second recesses RS2. The second source / drain patterns SD2 can be impurity regions having a second conductivity type (e.g., n-type). A second channel pattern CH2 can be interposed between a pair of second source / drain patterns SD2. For example, the pair of second source / drain patterns SD2 can be interconnected by stacked first, second, and third semiconductor patterns SP1 to SP3.

[0033] The first source / drain pattern SD1 and the second source / drain pattern SD2 can be epitaxial patterns formed by a selective epitaxial growth process. In one embodiment, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a top surface at a level substantially the same as the top surface of the third semiconductor pattern SP3. In another embodiment, each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a top surface at a level higher than the top surface of the third semiconductor pattern SP3.

[0034] Reference Figure 2C The passivation pattern NLP can be provided on the lower sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2. For example, the passivation pattern NLP can be interposed between the device isolation layer ST and the first and second source / drain patterns SD1 and SD2.

[0035] The first source / drain pattern SD1 may include a semiconductor element (e.g., SiGe) whose lattice constant is greater than that of the semiconductor element of the substrate 100. Therefore, a pair of first source / drain patterns SD1 can provide compressive stress to the first channel pattern CH1. The second source / drain pattern SD2 may include the same semiconductor element as the semiconductor element of the substrate 100 (e.g., Si).

[0036] Each of the first source / drain patterns SD1 may include a first semiconductor layer SEL1 and a second semiconductor layer SEL2 disposed on the first semiconductor layer SEL1.

[0037] Reference Figure 2A The following description will describe the cross-sectional shape of the first source / drain pattern SD1 in the second direction D2.

[0038] The first semiconductor layer SEL1 may cover the inner wall of the first recess RS1. The first semiconductor layer SEL1 may have a thickness that decreases from its bottom to its top. For example, the thickness of the first semiconductor layer SEL1 on the bottom of the first recess RS1 in the third direction D3 may be greater than the thickness of the first semiconductor layer SEL1 on the top of the first recess RS1 in the second direction D2. The first semiconductor layer SEL1 may be shaped into a U-shape along the contour of the first recess RS1.

[0039] The second semiconductor layer SEL2 can fill the remaining portion of the first recess RS1 that is filled with the first semiconductor layer SEL1. The second semiconductor layer SEL2 can have a larger volume than the first semiconductor layer SEL1. For example, the ratio of the volume of the second semiconductor layer SEL2 to the total volume of the first source / drain pattern SD1 can be greater than the ratio of the volume of the first semiconductor layer SEL1 to the total volume of the first source / drain pattern SD1.

[0040] Each of the first semiconductor layer SEL1 and the second semiconductor layer SEL2 may include silicon germanium (SiGe). For example, in one embodiment, the first semiconductor layer SEL1 may contain germanium (Ge) at a relatively low concentration. In another embodiment, the first semiconductor layer SEL1 may include only silicon (Si) and not germanium (Ge). The first semiconductor layer SEL1 may have a germanium concentration of about 0 at% to about 10 at%.

[0041] The second semiconductor layer SEL2 may contain germanium (Ge) at a relatively high concentration. For example, the second semiconductor layer SEL2 may have a germanium concentration of about 30 at% to about 70 at%. The germanium concentration of the second semiconductor layer SEL2 may increase in the third direction D3. For example, the second semiconductor layer SEL2 adjacent to the first semiconductor layer SEL1 may have a germanium concentration of about 40 at%, but the upper part of the second semiconductor layer SEL2 may have a germanium concentration of about 60 at%.

[0042] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 may include impurities (e.g., boron) that give the first source / drain pattern SD1 a p-type conductivity. The impurity concentration (e.g., atomic percentage) of the second semiconductor layer SEL2 may be greater than that of the first semiconductor layer SEL1.

[0043] The first semiconductor layer SEL1 can prevent stacking faults between the substrate 100 and the second semiconductor layer SEL2, and between the second semiconductor layer SEL2 and the first, second, and third semiconductor patterns SP1, SP2, and SP3. Stacking faults can increase channel resistance. Stacking faults can occur at the bottom of the first recess RS1. Therefore, in one embodiment, the first semiconductor layer SEL1 adjacent to the bottom of the first recess RS1 can have a relatively large thickness to prevent stacking faults.

[0044] When the sacrificial layer SAL is replaced by the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE, as described below, the first semiconductor layer SEL1 can protect the second semiconductor layer SEL2. For example, the first semiconductor layer SEL1 can prevent the second semiconductor layer SEL2 from being etched by the etching material used to etch the sacrificial layer SAL.

[0045] The gate electrode GE can be provided to extend along a first direction D1 while spanning a first channel pattern CH1 and a second channel pattern CH2. The gate electrodes GE can be arranged in a second direction D2 at a first pitch P1. Each of the gate electrodes GE can overlap perpendicularly with the first channel pattern CH1 and the second channel pattern CH2.

[0046] The gate electrode GE may include a first portion PO1 inserted between the first semiconductor pattern SP1 and the active pattern AP1 or AP2, a second portion PO2 inserted between the first semiconductor pattern SP1 and the second semiconductor pattern SP2, a third portion PO3 inserted between the second semiconductor pattern SP2 and the third semiconductor pattern SP3, and a fourth portion PO4 on the third semiconductor pattern SP3.

[0047] Reference Figure 2AIn the PMOSFET region PR, the gate electrode GE can have different widths at its first portion PO1, second portion PO2, and third portion PO3. For example, the maximum width of the third portion PO3 in the second direction D2 can be greater than the maximum width of the second portion PO2 in the second direction D2. The maximum width of the first portion PO1 in the second direction D2 can be greater than the maximum width of the third portion PO3 in the second direction D2.

[0048] Reference Figure 2D The gate electrode GE can be provided on the top surface TS, bottom surface BS, and opposite sidewall SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. Therefore, the transistor according to one embodiment can be a three-dimensional field-effect transistor (e.g., MBCFET or GAAFET) in which the gate electrode GE three-dimensionally surrounds the first channel pattern CH1 and the second channel pattern CH2.

[0049] Reference Figure 1 and Figures 2A to 2D A pair of gate spacers GS may be disposed on opposing sidewalls of the fourth portion PO4 of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE in a first direction D1. The gate spacers GS may have a top surface higher than the top surface of the gate electrode GE. The top surface of the gate spacers GS may be substantially coplanar with the top surface of the first interlayer dielectric layer 110, which will be described below. The gate spacers GS may comprise at least one of, for example, SiCN, SiCON, and SiN. Alternatively, each of the gate spacers GS may comprise a multilayer formed of at least two of, for example, SiCN, SiCON, and SiN.

[0050] A gate cap pattern GP can be provided on the gate electrode GE. The gate cap pattern GP can extend along the gate electrode GE in a first direction D1. The gate cap pattern GP can include a material that has etch selectivity relative to the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, which will be described below. For example, the gate cap pattern GP can include at least one of SiON, SiCN, SiCON, and SiN.

[0051] The gate dielectric layer GI can be interposed between the gate electrode GE and the first channel pattern CH1, and between the gate electrode GE and the second channel pattern CH2. The gate dielectric layer GI can cover the top surface TS, bottom surface BS, and opposite sidewall SW of each of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The gate dielectric layer GI can cover the top surface of the device isolation layer ST located beneath the gate electrode GE (see...). Figure 2D ).

[0052] In one embodiment of the present invention, the gate dielectric layer GI may include one or more of a silicon oxide layer, a silicon oxide nitride layer, and a high-k dielectric layer. The high-k dielectric layer may include a material whose dielectric constant is greater than that of the silicon oxide layer. For example, the high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0053] In one embodiment, the semiconductor device may include a negative capacitance field-effect transistor using a negative capacitor. For example, the gate dielectric layer GI may include a ferroelectric material layer having ferroelectric properties and a paraelectric material layer having paraelectric properties.

[0054] Ferroelectric material layers can have negative capacitance, and paraelectric material layers can have positive capacitance. For example, when two or more capacitors are connected in series, and when each capacitor has positive capacitance, the total capacitance can be reduced to less than the capacitance of each individual capacitor. In contrast, when at least one of the two or more capacitors connected in series has negative capacitance, the total capacitance can be increased to a positive value greater than the absolute value of the capacitance of each individual capacitor.

[0055] When a ferroelectric material layer with negative capacitance is connected in series with a paraelectric material layer with positive capacitance, the total capacitance of the series-connected ferroelectric and paraelectric material layers can be increased. This increase in total capacitance can be used to allow transistors including ferroelectric material layers to have a subthreshold swing of less than about 60 mV / decade at room temperature.

[0056] The ferroelectric material layer can possess ferroelectric properties. The ferroelectric material layer can include at least one of, for example, hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, and lead zirconium titanium oxide. In one embodiment, the hafnium zirconium oxide can be a material in which the hafnium oxide is doped with zirconium (Zr). In one embodiment, the hafnium zirconium oxide can be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0057] The ferroelectric material layer may also include impurities incorporated therein. For example, impurities may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), and tin (Sn). The type of impurities included in the ferroelectric material layer may vary depending on the ferroelectric material incorporated into the layer.

[0058] When the ferroelectric material layer includes hafnium oxide, the ferroelectric material layer may include at least one of the following impurities: gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0059] When the impurity is aluminum (Al), the ferroelectric material layer may comprise about 3 to about 8 atomic percent aluminum. In this description, the impurity ratio may be the ratio of aluminum to the sum of hafnium and aluminum.

[0060] When the impurity is silicon (Si), the ferroelectric material layer may comprise about 2 to about 10 atomic percent silicon. When the impurity is yttrium (Y), the ferroelectric material layer may comprise about 2 to about 10 atomic percent yttrium. When the impurity is gadolinium (Gd), the ferroelectric material layer may comprise about 1 to about 7 atomic percent gadolinium. When the impurity is zirconium (Zr), the ferroelectric material layer may comprise about 50 to about 80 atomic percent zirconium.

[0061] The paraelectric material layer may possess paraelectric properties. The paraelectric material layer may include at least one of, for example, silicon oxide and a high-k dielectric metal oxide. The metal oxide included in the paraelectric material layer may include at least one of, for example, hafnium oxide, zirconium oxide, and aluminum oxide. However, embodiments of the present invention are not limited thereto.

[0062] The ferroelectric material layer and the paraelectric material layer may contain the same material. The ferroelectric material layer may have ferroelectric properties, but the paraelectric material layer may not. For example, when both the ferroelectric and paraelectric material layers contain hafnium oxide, the hafnium oxide in the ferroelectric material layer may have a different crystal structure than the hafnium oxide in the paraelectric material layer.

[0063] The ferroelectric material layer can have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material layer can range, for example, from about 0.5 nm to about 10 nm. Because ferroelectric materials have their own critical thickness for exhibiting ferroelectric properties, the thickness of the ferroelectric material layer can depend on the ferroelectric material itself.

[0064] In one embodiment, the gate dielectric layer GI may include a single ferroelectric material layer. In another embodiment, the gate dielectric layer GI may include multiple ferroelectric layers spaced apart from each other. The gate dielectric layer GI may have a stacked structure in which multiple ferroelectric material layers and multiple paraelectric material layers are stacked alternately.

[0065] The gate electrode GE may include a first metal pattern and a second metal pattern disposed on the first metal pattern. The first metal pattern may be provided on the gate dielectric layer GI and may be adjacent to the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. The first metal pattern may include a work function metal that controls the threshold voltage of the transistor. The thickness and composition of the first metal pattern may be adjusted to achieve the desired threshold voltage of the transistor. For example, the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE may be formed from the first metal pattern or the work function metal.

[0066] The first metal pattern may include a metal nitride layer. For example, the first metal pattern may include nitrogen (N) and at least one metal selected from titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). Furthermore, the first metal pattern may also include carbon (C). The first metal pattern may include multiple stacked work function metal layers.

[0067] The second metal pattern may include a metal whose resistance is less than that of the first metal pattern. For example, the second metal pattern may include at least one metal selected from tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta). The fourth portion PO4 of the gate electrode GE may include, for example, the first metal pattern and the second metal pattern on the first metal pattern.

[0068] Reference Figure 2B An internal spacer IP can be provided on the NMOSFET region NR. The internal spacer IP can be correspondingly interposed between the second source / drain pattern SD2 and the first, second, and third portions PO1, PO2, and PO3 of the gate electrode GE. The internal spacer IP can be in direct contact with the second source / drain pattern SD2. The internal spacer IP can separate each of the first portion PO1, the second portion PO2, and the third portion PO3 of the gate electrode GE from the second source / drain pattern SD2.

[0069] A first interlayer dielectric layer 110 may be provided on the substrate 100. The first interlayer dielectric layer 110 may cover the gate spacer GS and the first source / drain pattern SD1 and the second source / drain pattern SD2. The first interlayer dielectric layer 110 may have a top surface that is substantially coplanar with the top surface of the gate cap pattern GP and the top surface of the gate spacer GS. A second interlayer dielectric layer 120 covering the gate cap pattern GP may be disposed on the first interlayer dielectric layer 110. For example, the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 may comprise silicon oxide layers.

[0070] A pair of discrete structures DB, facing each other in the second direction D2, can be provided on opposite sides of the logic cell LC. The discrete structures DB can extend substantially parallel to the gate electrode GE in the first direction D1. The discrete structures DB and their adjacent gate electrode GE can be arranged with a first pitch P1.

[0071] The separation structure DB can penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120, and can extend into the first active pattern AP1 and the second active pattern AP2. The separation structure DB can penetrate the first channel pattern CH1 and the second channel pattern CH2. The separation structure DB can separate the PMOSFET region PR and NMOSFET region NR of the logic cell LC from the PMOSFET region or NMOSFET region of the adjacent logic cell.

[0072] Active contacts AC can penetrate the first interlayer dielectric layer 110 and the second interlayer dielectric layer 120 and are correspondingly electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A pair of active contacts AC can be provided on opposite sides of the gate electrode GE. In a plan view, the active contacts AC can have a strip extending in a first direction D1.

[0073] The active contact AC can be a self-aligned contact. For example, a gate cap pattern GP and a gate spacer GS can be used to form the active contact AC in a self-aligned manner. For example, the active contact AC can cover at least a portion of the sidewall of the gate spacer GS. In one embodiment, the active contact AC can partially cover a portion of the top surface of the gate cap pattern GP.

[0074] A silicide pattern SC can be correspondingly inserted between the active contact AC and the first source / drain pattern SD1, and between the active contact AC and the second source / drain pattern SD2. The active contact AC can be electrically connected to one of the first source / drain pattern SD1 and the second source / drain pattern SD2 via the silicide pattern SC. The silicide pattern SC may include a metal silicide, such as at least one of, for example, titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and cobalt silicide.

[0075] The gate contact GC can penetrate the second interlayer dielectric layer 120 and the gate cap pattern GP and be electrically connected to the gate electrode GE. For example, refer to Figure 2B The upper dielectric pattern UIP can fill the upper portion of each active contact AC adjacent to the gate contact CG. Therefore, according to embodiments conceived in this invention, process defects such as electrical short circuits caused by the contact between the gate contact GC and its adjacent active contact AC can be prevented.

[0076] Each of the active contact AC and the gate contact GC may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. For example, the conductive pattern FM may include at least one metal selected from aluminum, copper, tungsten, molybdenum, and cobalt. The barrier pattern BM may cover the sidewalls and bottom surface of the conductive pattern FM. The barrier pattern BM may include a metal layer and a metal nitride layer. The metal layer may include at least one of, for example, titanium, tantalum, tungsten, nickel, cobalt, and platinum. The metal nitride layer may include at least one of, for example, a titanium nitride (TiN) layer, a tantalum nitride (TaN) layer, a tungsten nitride (WN) layer, a nickel nitride (NiN) layer, a cobalt nitride (CoN) layer, and a platinum nitride (PtN) layer.

[0077] A first metal layer M1 may be provided within the third interlayer dielectric layer 130. The first metal layer M1 may include a first lower line M1_R, a second lower line M1_I, and a lower pass VI1. The lower pass VI1 may be provided below the first lower line M1_R and the second lower line M1_I.

[0078] Each of the first lower lines M1_R can extend along the second direction D2 while spanning the logic cell LC. Each of the first lower lines M1_R can be a power supply line. For example, a drain voltage Vdd or a source voltage Vss can be supplied to the first lower line M1_R.

[0079] Reference Figure 1 A logic cell LC may include a first cell boundary CB1 extending in a second direction D2. A second cell boundary CB2 may be defined on the logic cell LC at a position opposite to the position defining the first cell boundary CB1. A first lower line M1_R to which a drain voltage Vdd or a power supply voltage is applied may be provided on the first cell boundary CB1. The first lower line M1_R to which the drain voltage Vdd is applied may extend along the first cell boundary CB1 in the second direction D2. A first lower line M1_R to which a source voltage Vss or a ground voltage is applied may be provided on the second cell boundary CB2. The first lower line M1_R to which the source voltage Vss is applied may extend along the second cell boundary CB2 in the second direction D2.

[0080] The second lower lines M1_I can be arranged along a first direction D1 between the first lower line M1_R to which the drain voltage Vdd is applied and the first lower line M1_R to which the source voltage Vss is applied. Each second lower line M1_I can have a linear or strip shape extending in a second direction D2. The second lower lines M1_I can be arranged in the first direction D1 with a second pitch P2. The second pitch P2 can be smaller than the first pitch P1.

[0081] The lower pass VI1 can be provided below the first lower line M1_R and the second lower line M1_I of the first metal layer M1. The lower pass VI1 can be correspondingly interposed between the active contact AC and the first and second lower lines M1_R and M1_I. The lower pass VI1 can also be correspondingly interposed between the gate contact GC and the second lower line M1_I.

[0082] The lower line M1_R or M1_I of the first metal layer M1 and the lower pass VI1 therebelow can be formed by separate processes. For example, the lower line M1_R or M1_I and the lower pass VI1 can each be formed by a single damascene process. The semiconductor device according to one embodiment can be manufactured using a sub-20nm process.

[0083] A second metal layer M2 may be provided in the fourth interlayer dielectric layer 140. The second metal layer M2 may include upper lines M2_I. Each upper line M2_I may have a linear or strip shape extending in a first direction D1. For example, the upper lines M2_I may extend substantially parallel to each other in the first direction D1. In a plan view, the upper lines M2_I may be substantially parallel to the gate electrode GE. Some of the upper lines M2_I may be arranged along the second direction D2 with a third pitch P3. Others of the upper lines M2_I may be arranged along the second direction D2 with a pitch greater than the third pitch P3. The third pitch P3 may be smaller than the first pitch P1. The third pitch P3 may be greater than the second pitch P2.

[0084] The second metal layer M2 may also include an upper passage VI2. The upper passage VI2 may be provided below the upper line M2_I. The upper passage VI2 may be correspondingly interposed between the upper line M2_I and the lower lines M1_R and M1_I.

[0085] The upper line M2_I of the second metal layer M2 and the upper passage VI2 below it can be formed as a single piece in the same process. For example, a dual damascene process can be used to form the upper passage VI2 and the upper line M2_I of the second metal layer M2 substantially simultaneously.

[0086] The lower lines M1_R and M1_I of the first metal layer M1 may include conductive materials that are the same as or different from the conductive material of the upper line M2_I of the second metal layer M2. For example, the lower lines M1_R and M1_I and the upper line M2_I may include at least one metallic material selected from aluminum, copper, tungsten, molybdenum and cobalt.

[0087] In one embodiment of the present invention, additional metal layers may be stacked on the fourth interlayer dielectric layer 140. Each of the stacked metal layers may include a routing line.

[0088] Reference Figure 3The following description will describe in detail the passivation pattern NLP disposed on the first active pattern AP1. The first active pattern AP1 may have a first sidewall SW1 and a second sidewall SW2 that are opposite to each other in a first direction D1. The passivation pattern NLP may include a first passivation pattern NLP1 disposed on the first sidewall SW1 and a second passivation pattern NLP2 disposed on the second sidewall SW2.

[0089] For example, the first passivation pattern NLP1 may include an upper UPP protruding upward from the device isolation layer ST and a lower LWP buried in the device isolation layer ST. The upper UPP may have a first top surface TOS1 that is higher than the second top surface TOS2 of the first active pattern AP1. The first top surface TOS1 of the upper UPP may be lower than the bottom surface BS of the first semiconductor pattern SP1 (e.g., the lowest of semiconductor patterns SP1, SP2, and SP3). For example, the first top surface TOS1 of the upper UPP may be located at the level between the second top surface TOS2 of the first active pattern AP1 and the bottom surface BS of the first semiconductor pattern SP1. The lower LWP may face the first sidewall SW1 of the first active pattern AP1 through the substrate OLI.

[0090] The gate dielectric layer GI can extend from the top surface of the device isolation layer ST toward the second top surface TOS2 of the first active pattern AP1 while spanning the upper UPP of the first passivation pattern NLP1. The gate dielectric layer GI can directly cover the first top surface TOS1 and the opposite sidewalls of the upper UPP. For example, the gate dielectric layer GI can directly contact and cover the first top surface TOS1 and the opposite sidewalls of the upper UPP. The gate dielectric layer GI can have a structure that protrudes along the contour of the upper UPP.

[0091] The first passivation pattern NLP1 may have a first height HE1, and the second passivation pattern NLP2 may have a second height HE2. For example, the first height HE1 may be the length from the bottom surface (or lowermost part) of the first passivation pattern NLP1 to the first top surface TOS1 (or uppermost part) in a third direction D3. The first height HE1 may be used to define the size of the first passivation pattern NLP1, and the second height HE2 may be used to define the size of the second passivation pattern NLP2.

[0092] According to one embodiment, the first passivation pattern NLP1 and the second passivation pattern NLP2 may have substantially the same dimensions as each other. For example, the first height HE1 and the second height HE2 may be substantially the same as each other.

[0093] According to one embodiment of the present invention, the first passivation pattern NLP1 and the second passivation pattern NLP2 may have different dimensions from each other. For example, the first height HE1 and the second height HE2 may be different from each other.

[0094] According to some embodiments of the present invention, passivation pattern NLP can prevent excessive recessing of the top surface of the device isolation layer ST, which could degrade the electrical characteristics of the semiconductor device. Passivation pattern NLP can stably form the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, as well as the gate electrode GE, in the first portion PO1, the second portion PO2, and the third portion PO3 between the active pattern AP1 or AP2, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3, thereby improving reliability and electrical characteristics.

[0095] Figures 4A to 10D A cross-sectional view is shown illustrating a method for manufacturing a semiconductor device according to some embodiments of the concept according to the present invention. In detail, Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A and Figure 10A Some embodiments of the invention are shown. Figure 1 The cross-sectional view corresponding to line A-A'. Figure 7B , Figure 8B , Figure 9B and Figure 10B It shows the relationship with Figure 1 The cross-sectional view corresponding to line B-B'. Figure 7C , Figure 8C , Figure 9C and Figure 10C It shows the relationship with Figure 1 The cross-sectional view corresponding to line C-C'. Figure 4B , Figure 5B , Figure 6B , Figure 7D , Figure 8D , Figure 9D and Figure 10D It shows the relationship with Figure 1 The cross-sectional view corresponding to line D-D'.

[0096] Reference Figure 4A and Figure 4B The substrate 100 may include a PMOSFET region PR and an NMOSFET region NR. A sacrificial layer SAL and an active layer ACL may be alternately formed and stacked on the substrate 100. The sacrificial layer SAL may include, for example, one of silicon (Si), germanium (Ge), and silicon-germanium (SiGe), and the active layer ACL may include, for example, another of silicon (Si), germanium (Ge), and silicon-germanium (SiGe).

[0097] For example, the sacrificial layer SAL may include silicon germanium (SiGe), and the active layer ACL may include silicon (Si). Each sacrificial layer SAL may have a germanium concentration of about 10 at% to about 30 at%.

[0098] Mask patterns can be formed correspondingly on the PMOSFET region PR and NMOSFET region NR of the substrate 100. The mask patterns can be linear or strip-shaped extending in the second direction D2.

[0099] A patterning process can be performed in which a mask pattern is used as an etching mask to form a trench TR defining a first active pattern AP1 and a second active pattern AP2. The first active pattern AP1 and the second active pattern AP2 can be formed on the PMOSFET region PR and the NMOSFET region NR, respectively. A stacked pattern STP can be formed on each of the first active pattern AP1 and the second active pattern AP2. The stacked pattern STP may include alternately stacked sacrificial layer SAL and active layer ACL. During the patterning process, the stacked pattern STP can be formed together with the first active pattern AP1 and the second active pattern AP2.

[0100] A substrate OLI can be formed on the first active pattern AP1 and the second active pattern AP2. An atomic layer deposition (ALD) process can be performed to conformally form the substrate OLI. The substrate OLI can cover the stacked pattern STP and the first active pattern AP1 and the second active pattern AP2. The substrate OLI may include a silicon oxide layer.

[0101] A passivation layer NLI can be formed on the substrate OLI. The passivation layer NLI can be selectively formed on the stacked pattern STP. For example, the passivation layer NLI may not be formed on the sidewalls of each of the first active pattern AP1 and the second active pattern AP2, and may not be formed in the trench TR. Or, as... Figure 4B As shown, the passivation layer NLI can be formed on the upper sidewall of each of the first active pattern AP1 and the second active pattern AP2, but not on the lower sidewall of each of the first active pattern AP1 and the second active pattern AP2, and can be partially formed in the trench TR. The passivation layer NLI can include, for example, SiOC, SiN, SiC, AlO, TiO2, or combinations thereof. For example, the passivation layer NLI can include SiN. A detailed description of the formation of the passivation layer NLI will be provided below with reference to... Figures 11 to 17 To describe.

[0102] Reference Figure 5A and Figure 5BA device isolation layer ST can be formed to fill the trench TR. For example, a dielectric layer can be formed on the entire surface of the substrate 100 to cover the stacked pattern STP and the first active pattern AP1 and the second active pattern AP2. The dielectric layer can be recessed until the stacked pattern STP is exposed, which can form the device isolation layer ST.

[0103] The device isolation layer ST may include a dielectric material, such as a silicon oxide layer. A stacked pattern STP may protrude upwards from the device isolation layer ST. For example, the stacked pattern STP may protrude vertically upwards from the device isolation layer ST.

[0104] An etching process can be performed to etch and remove the substrate OLI and passivation layer NLI on the stacked pattern STP. Removal of the substrate OLI and passivation layer NLI exposes the active layer ACL and sacrificial layer SAL of the stacked pattern STP. During the etching process, at least a portion of the passivation layer NLI may not be removed but may be retained to form the passivation pattern NLP.

[0105] The passivation pattern NLP can be interposed between the device isolation layer ST and the first and second active patterns AP1 and AP2. The upper part of the passivation pattern NLP can protrude upwards (see...). Figure 3 ).

[0106] Reference Figure 6A and Figure 6B The sacrificial pattern PP can be formed on the substrate 100 to span the stacked pattern STP. Each sacrificial pattern PP can be formed as a line or strip extending in a first direction D1. The sacrificial patterns PP can be arranged along a second direction D2 at a certain pitch.

[0107] For example, forming a sacrificial pattern PP may include forming a sacrificial layer on the entire surface of the substrate 100, forming a hard mask pattern MP on the sacrificial layer, and using the hard mask pattern MP as an etch mask to pattern the sacrificial layer. The sacrificial layer may include polysilicon.

[0108] A pair of gate spacers GS can be formed on opposite sidewalls of each sacrificial pattern PP. The formation of the gate spacers GS may include conformally forming a gate spacer layer over the entire surface of the substrate 100 and anisotropically etching the gate spacer layer. The gate spacer layer may include at least one of, for example, SiCN, SiCON, and SiN. Alternatively, the gate spacer layer may be a multilayer comprising, for example, at least two of, SiCN, SiCON, and SiN.

[0109] Reference Figures 7A to 7DA first recess RS1 can be formed in a stacked pattern STP on a first active pattern AP1. A second recess RS2 can be formed in a stacked pattern STP on a second active pattern AP2. During the formation of the first recess RS1 and the second recess RS2, the device isolation layer ST can be further recessed on opposite sides of each of the first active pattern AP1 and the second active pattern AP2 (see...). Figure 7C ).

[0110] For example, a hard mask pattern MP and a gate spacer GS can be used as an etching mask so that a stacked pattern STP on a first active pattern AP1 can be etched to form a first recess RS1. The first recess RS1 can be formed between a pair of sacrificial patterns PP. A second recess RS2 in a stacked pattern STP on a second active pattern AP2 can be formed using the same method used to form the first recess RS1.

[0111] The active layer ACL can be formed by sequentially stacking a first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3 between the first recesses RS1. The active layer ACL can also be formed by sequentially stacking the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 between the second recesses RS2. The first channel pattern CH1 can be composed of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 between the first recesses RS1, and the second channel pattern CH2 can be composed of the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 between the second recesses RS2.

[0112] Reference Figures 8A to 8D A first source / drain pattern SD1 can be formed in the corresponding first recess RS1. For example, a first selective epitaxial growth (SEG) process can be performed, in which the inner wall of the first recess RS1 serves as a seed layer to form the first semiconductor layer SEL1. The first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 exposed to the first recess RS1, as well as the substrate 100, can be used as a seed for growing the first semiconductor layer SEL1 therefrom. For example, the first SEG process can include chemical vapor deposition (CVD) or molecular beam epitaxy (MBE).

[0113] The first semiconductor layer SEL1 may include a semiconductor element (e.g., SiGe) whose lattice constant is greater than that of the semiconductor elements included in the substrate 100. The first semiconductor layer SEL1 may contain germanium (Ge) at a relatively low concentration. In one embodiment of the present invention, the first semiconductor layer SEL1 may include only silicon (Si) and not germanium (Ge). The first semiconductor layer SEL1 may have a germanium concentration of about 0 at% to about 10 at%.

[0114] A second selective epitaxial growth (SEG) process can be performed on the first semiconductor layer SEL1 to form a second semiconductor layer SEL2. The second semiconductor layer SEL2 can be formed to completely fill the first recess RS1. The second semiconductor layer SEL2 can contain germanium (Ge) at a relatively high concentration. For example, the second semiconductor layer SEL2 can have a germanium concentration of about 30 at% to about 70 at%.

[0115] The first semiconductor layer SEL1 and the second semiconductor layer SEL2 can form a first source / drain pattern SD1. In one embodiment, impurities can be implanted in situ during the first and second SEG processes. In one embodiment, after the formation of the first source / drain pattern SD1, impurities can be implanted into the first source / drain pattern SD1. The first source / drain pattern SD1 can be doped to have a first conductivity type (e.g., p-type).

[0116] A second source / drain pattern SD2 can be formed in the corresponding second recess RS2. For example, a selective epitaxial growth (SEG) process can be performed, in which the inner wall of the second recess RS2 is used as a seed to form the second source / drain pattern SD2. For example, the second source / drain pattern SD2 may include the same semiconductor element as the semiconductor element of the substrate 100 (e.g., Si). The second source / drain pattern SD2 can be doped to have a second conductivity type (e.g., n-type). An internal spacer IP can be formed correspondingly between the second source / drain pattern SD2 and the sacrificial layer SAL.

[0117] Reference Figures 9A to 9D A first interlayer dielectric layer 110 may be formed to cover a first source / drain pattern SD1 and a second source / drain pattern SD2, a hard mask pattern MP, and a gate spacer GS. For example, the first interlayer dielectric layer 110 may include a silicon oxide layer.

[0118] The first interlayer dielectric layer 110 can be planarized until the top surface of the sacrificial pattern PP is exposed. The first interlayer dielectric layer 110 can be planarized using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, the hard mask pattern MP can be completely removed. As a result, the first interlayer dielectric layer 110 can have a top surface that is substantially coplanar with the top surface of the sacrificial pattern PP and the top surface of the gate spacer GS.

[0119] Exposed sacrificial patterns PP can be selectively removed. Removal of the sacrificial patterns PP can create a first empty space ET1 (see [reference needed]) exposing the first channel pattern CH1 and the second channel pattern CH2. Figure 9D ).

[0120] The sacrificial layer SAL exposed to the first void ET1 can be selectively removed to form the second void ET2 (see...). Figure 9D For example, an etching process that selectively etches the sacrificial layer SAL can be performed, such that the sacrificial layer SAL can be removed, while the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3 can be retained.

[0121] For silicon-germanium with a relatively high germanium concentration, the etching process can have a high etching rate. For example, for silicon-germanium with a germanium concentration greater than about 10 at%, the etching process can have a high etching rate.

[0122] During the etching process, the sacrificial layer SAL can be removed from the PMOSFET region PR and the NMOSFET region NR. The etching process may include a wet etching process. The etching material used in the etching process can rapidly etch the sacrificial layer SAL, which has a relatively high germanium concentration. During the etching process, the first source / drain pattern SD1 on the PMOSFET region PR can be protected by the first semiconductor layer SEL1, which has a relatively low germanium concentration.

[0123] Reference Figure 9D When the sacrificial layer SAL is selectively removed, the stacked first semiconductor pattern SP1, second semiconductor pattern SP2, and third semiconductor pattern SP3 can remain on each of the first active pattern AP1 and the second active pattern AP2. A second empty space ET2 can be formed in the corresponding region from which the sacrificial layer SAL has been removed. The second empty space ET2 can be defined between the active pattern AP1 or AP2, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3.

[0124] Reference Figures 10A to 10D A gate dielectric layer GI can be conventionally formed in the first empty space ET1 and the second empty space ET2. A gate electrode GE can be formed on the gate dielectric layer GI. The gate electrode GE can be formed to fill the first empty space ET1 and the second empty space ET2. For example, the gate electrode GE may include a first portion PO1, a second portion PO2, and a third portion PO3 filling the second empty space ET2. The gate electrode GE may also include a fourth portion PO4 filling the first empty space ET1. A gate cap pattern GP can be formed on the gate electrode GE.

[0125] Return to reference Figure 1 and Figures 2A to 2DA second interlayer dielectric layer 120 may be formed on the first interlayer dielectric layer 110. The second interlayer dielectric layer 120 may include a silicon oxide layer. An active contact AC may be formed to penetrate the second interlayer dielectric layer 120 and the first interlayer dielectric layer 110 and be electrically connected to the first source / drain pattern SD1 and the second source / drain pattern SD2. A gate contact GC may be formed to penetrate the second interlayer dielectric layer 120 and the gate cap pattern GP and be electrically connected to the gate electrode GE.

[0126] A pair of discrete structures DB can be formed on opposite sides of the logic cell LC. The discrete structures DB can extend from the second interlayer dielectric layer 120 through the gate electrode GE into the active pattern AP1 or AP2. The discrete structures DB may include a dielectric material, such as, for example, a silicon oxide layer or a silicon nitride layer.

[0127] A third interlayer dielectric layer 130 may be formed on the active contact AC and the gate contact GC. A first metal layer M1 may be formed in the third interlayer dielectric layer 130. A fourth interlayer dielectric layer 140 may be formed on the third interlayer dielectric layer 130. A second metal layer M2 may be formed in the fourth interlayer dielectric layer 140.

[0128] Figures 11 to 13 The illustration shows methods for forming passivation layers and device isolation layers according to some embodiments of the present invention. Figure 1 The cross-sectional view corresponding to line D-D'.

[0129] Reference Figure 11 After forming the substrate OLI on the first active pattern AP1 and the second active pattern AP2, a passivation layer NLI can be conformally formed on the entire surface of the substrate 100. The passivation layer NLI can cover the entire first active pattern AP1, the second active pattern AP2, and the stacked pattern STP.

[0130] Plasma treatment process (PLT) can be performed only on the upper portion of the passivation layer NLI or on the passivation layer NLI on the stacked pattern STP. The upper portion of the passivation layer NLI where the plasma treatment process PLT has been performed may have greater etch resistance than the lower portion where the plasma treatment process PLT has not been performed. For example, the plasma treatment process PLT can make the upper portion of the passivation layer NLI (e.g., the passivation layer NLI on the stacked pattern STP) etch-selective relative to the lower portion of the passivation layer NLI (e.g., the passivation layer NLI in the trench TR).

[0131] Reference Figure 12 Due to the etch selectivity between the upper and lower portions of the passivation layer NLI, the lower portion of the passivation layer NLI can be selectively etched and removed. Therefore, the passivation layer NLI can be formed as... Figure 4B The shape shown. In one embodiment, the passivation layer NLI may be selectively retained only on the stacked pattern STP.

[0132] Reference Figure 13 A dielectric layer can be formed on the entire surface of the substrate 100, and then the dielectric layer can be planarized to form a device isolation layer ST. A thermal processing step ANL can be performed on the device isolation layer ST.

[0133] During the thermal processing step ANL, the first active pattern AP1 and the second active pattern AP2, which are not covered by the passivation layer NLI, can apply stress STR to the device isolation layer ST in the trench TR. Therefore, the device isolation layer ST in the trench TR can become denser and more rigid. During the thermal processing step ANL, the stacked pattern STP can be protected by the passivation layer NLI, thus preventing deformation.

[0134] Figure 14 and Figure 15 The diagram illustrates a method for forming a passivation layer and a device isolation layer according to a comparative example. Figure 1 The cross-sectional view corresponding to line D-D'.

[0135] In some embodiments of the present invention, as referred to above... Figure 11 and Figure 12 The lower portion of the passivation layer NLI can be selectively removed. In contrast, refer to... Figure 14 In a comparative example, the passivation layer NLI may not be removed, and a device isolation layer ST may be formed on the passivation layer NLI. In this case, during the heat treatment process ANL, the passivation layer NLI cannot adequately apply stress STR to the device isolation layer ST in the trench TR. As a result, the device isolation layer ST in the trench TR may be relatively less dense and rigid.

[0136] Reference Figure 15 It can make Figure 14 The device isolation layer ST is recessed to expose the stacked pattern STP, and the upper part of the passivation layer NLI can be removed. In this comparative example, because the device isolation layer ST in the trench TR is relatively non-rigid, the top surface of the device isolation layer ST may be over-etched and recessed. This may increase the volume of the gate electrode GE formed on the device isolation layer ST, and as a result, the electrical characteristics may deteriorate.

[0137] Figure 16 The diagram illustrates a method for forming a passivation layer and a device isolation layer according to another comparative example. Figure 1 The cross-sectional view corresponding to line D-D'.

[0138] Reference Figure 16In this comparative example, the passivation layer NLI according to an embodiment of the present invention is omitted, and the device isolation layer ST can be formed on the substrate OLI. In this case, stress STR can be sufficiently applied to the device isolation layer ST in the trench TR during the thermal processing ANL. However, there is no passivation layer NLI to protect the stacked pattern STP, therefore, the sacrificial layer SAL and the active layer ACL may deform during the thermal processing ANL. For example, the thermal processing ANL may cause the sacrificial layer SAL to shrink. Furthermore, the thermal processing ANL may change the shape of the active layer ACL.

[0139] The stacked pattern STP can be used in subsequent processes to form the channel pattern CH1 or CH2 and the gate electrode GE. Therefore, deformation may occur, which may negatively affect the electrical characteristics and reliability of the final semiconductor device.

[0140] Return to reference Figure 13 According to one embodiment of the present invention, the passivation layer NLI can be selectively formed on the upper sidewalls of the stacked pattern STP and the active patterns AP1 and AP2, or only on the stacked pattern STP. Therefore, deformation of the stacked pattern STP during the thermal processing ANL can be prevented. Furthermore, according to one embodiment of the present invention, the passivation layer NLI can be at least partially removed in the trench TR, thus allowing sufficient stress STR to be applied to the device isolation layer ST in the trench TR. As a result, one embodiment of the present invention can prevent the problems described above with reference to the comparative examples and can improve the reliability and electrical characteristics of the semiconductor device.

[0141] Figure 17 and Figure 18 The illustration shows a method for forming a passivation layer according to some embodiments of the present invention. Figure 1 The cross-sectional view corresponding to line D-D'.

[0142] Reference Figure 17 After forming the substrate OLI on the first active pattern AP1 and the second active pattern AP2, a passivation layer NLI can be conformally formed on the entire surface of the substrate 100. The passivation layer NLI can cover the entire first active pattern AP1, the second active pattern AP2, and the stacked pattern STP. It can be formed according to... Figure 17 The above references are omitted in the implementation method. Figure 11 The plasma processing technology PLT is described.

[0143] Reference Figure 18The passivation layer NLI can undergo an anisotropic etching process (AIE), in which the passivation layer NLI is selectively etched. The trench TR can have a gentler sidewall slope than the sidewall slope of the stacked pattern STP. Therefore, during the anisotropic etching process, the passivation layer NLI disposed on the sidewalls of the stacked pattern STP can be left unetched. Selective removal of the passivation layer NLI on the top surface of the stacked pattern STP and in the trench TR can be performed. As a result, the passivation layer NLI can remain on the sidewalls of the stacked pattern STP, which thus protects the stacked pattern STP during the aforementioned heat treatment process (ANL).

[0144] Figure 19 and Figure 20 The illustration shows a semiconductor device demonstrating some embodiments of the concept according to the present invention. Figure 2D An enlarged cross-sectional view of a modified example of part M, as shown in the drawing. For ease of explanation, the previous references are used in the following description. Figure 1 , Figures 2A to 2D and Figure 3 Detailed descriptions of the technical features and components will be omitted, and the description will focus on their differences.

[0145] Reference Figure 19 The first passivation pattern NLP1 disposed on the first sidewall SW1 of the first active pattern AP1 may have a different size than the second passivation pattern NLP2 disposed on the second sidewall SW2 of the first active pattern AP1. For example, the upper part of the first passivation pattern NLP1 may be omitted. Therefore, the first height HE1 of the first passivation pattern NLP1 may be smaller than the second height HE2 of the second passivation pattern NLP2.

[0146] Reference Figure 20 The passivation pattern NLP can be optionally provided only on the second sidewall SW2 of the first active pattern AP1. For example, the passivation pattern NLP can be omitted on the first sidewall SW1 of the first active pattern AP1. In one embodiment, the passivation pattern NLP can be omitted on both the first sidewall SW1 and the second sidewall SW2 of the first active pattern AP1.

[0147] Figure 21 and Figure 22 A cross-sectional view illustrating some embodiments of a semiconductor device according to the present invention is shown. For ease of explanation, reference is previously made to the following description. Figure 1 , Figures 2A to 2D and Figure 3 Detailed descriptions of the technical features and components will be omitted, and the description will focus on their differences.

[0148] Reference Figure 21The SRAM cell SRC can be provided on the substrate 100. Storage transistors can be provided on the SRAM cell SRC. For example, the SRAM cell SRC can be a 6T-SRAM. The SRAM cell SRC can include a PMOSFET region PR and an NMOSFET region NR.

[0149] A pair of first active patterns AP1 can be provided on the PMOSFET region PR. A second active pattern AP2 can be provided on each of the NMOSFET regions NR. A first trench TR1 can be defined between the first active patterns AP1. A second trench TR2 can be defined between the first active pattern AP1 and the second active pattern AP2 adjacent to the first active pattern AP1. The first trench TR1 can have a width smaller than the width of the second trench TR2.

[0150] A pair of first active patterns AP1 may have a first pitch PI1 between them, and the first active pattern AP1 and its adjacent second active pattern AP2 may have a second pitch PI2 between them. The first pitch PI1 and the second pitch PI2 may be different from each other. For example, the second pitch PI2 may be greater than the first pitch PI1.

[0151] A first passivation pattern NLP1 can be provided on the upper sidewall of the first trench TR1, and a second passivation pattern NLP2 can be provided on the upper sidewall of the second trench TR2. For example, a first active pattern AP1 can include a first sidewall SW1 and a second sidewall SW2 opposite to each other. The first sidewall SW1 can be adjacent to another first active pattern AP1 (facing another first active pattern AP1), and the second sidewall SW2 can be adjacent to a second active pattern AP2 (facing the second active pattern AP2). The first passivation pattern NLP1 can be interposed between the first sidewall SW1 and the device isolation layer ST, and the second passivation pattern NLP2 can be interposed between the second sidewall SW2 and the device isolation layer ST.

[0152] The first passivation pattern NLP1 may have a different size than the second passivation pattern NLP2. For example, according to one embodiment of the present invention, the size of the first passivation pattern NLP1 may be larger than the size of the second passivation pattern NLP2. However, the embodiments of the present invention are not limited thereto. For example, according to one embodiment of the present invention, the size of the first passivation pattern NLP1 may be smaller than the size of the second passivation pattern NLP2.

[0153] The dimensions of the first passivation pattern NLP1 and the second passivation pattern NLP2 can vary depending on the width of the first trench TR1 in which the first passivation pattern NLP1 is disposed and the width of the second trench TR2 in which the second passivation pattern NLP2 is disposed. For example, the dimensions of the first passivation pattern NLP1 and the second passivation pattern NLP2 can vary depending on the pitch between adjacent active patterns AP1 and / or AP2.

[0154] In one embodiment, as referred to above Figure 20 The first passivation pattern NLP1 and the second passivation pattern NLP2, or both, may be omitted. For example, the presence of the first passivation pattern NLP1 and the second passivation pattern NLP2 may depend on the pitch between adjacent active patterns AP1 and / or AP2.

[0155] The first metal layer M1 disposed on the SRAM cell SRC may include a first bit line BL1, a second bit line BL2, and a power supply line VDD. The second metal layer M2 disposed on the SRAM cell SRC may include a ground line VSS.

[0156] Reference Figure 22 A semiconductor device according to one embodiment of the present invention may include a substrate 100 comprising a peripheral region PER. The peripheral region PER may be a region in which transistors constituting a processing core or input / output terminals are disposed. The transistors disposed in the peripheral region PER can operate at a higher power than that required to operate the transistors disposed on the logic cell LC described above.

[0157] A pair of peripheral active pattern PAPs ( Figure 22 (Only one of them is shown) can be provided in the peripheral region PER. A peripheral channel pattern PCH can be provided on the peripheral active pattern PAP. The peripheral channel pattern PCH can include a stacked first semiconductor pattern SP1, a second semiconductor pattern SP2, and a third semiconductor pattern SP3. The peripheral channel pattern PCH can also include a sacrificial layer SAL interposed between the peripheral active pattern PAP, the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the third semiconductor pattern SP3. For example, unlike transistors disposed on logic cells LC, transistors disposed in the peripheral region PER can be configured such that the sacrificial layer SAL is not removed but retained.

[0158] The passivation pattern NLP can be interposed between the device isolation layer ST and the upper sidewall of the peripheral active pattern PAP. The passivation pattern NLP disposed in the peripheral region PER can have the same or different dimensions as the passivation pattern NLP disposed on the logic cell LC described above. The description of the passivation pattern NLP disposed in the peripheral region PER can be the same as the description of the passivation pattern NLP disposed on the logic cell LC described above.

[0159] A peripheral gate electrode PGE can be provided on a peripheral channel pattern PCH. A peripheral gate dielectric layer PGI can be interposed between the peripheral channel pattern PCH and the peripheral gate electrode PGE. The peripheral gate dielectric layer PGI may include a dielectric layer EG that directly contacts and covers the top surface and opposite sidewalls of the peripheral channel pattern PCH. The peripheral gate dielectric layer PGI may also include a high-k dielectric layer HK disposed on the dielectric layer EG. The dielectric layer EG may be thicker than the high-k dielectric layer HK. The dielectric layer EG may include a silicon oxide layer or a silicon oxide nitride layer. The high-k dielectric layer HK may include a high-k dielectric material.

[0160] The dielectric layer EG can cover the upper portion of the passivation pattern NLP, which protrudes upward from the device isolation layer ST. For example, the dielectric layer EG can directly contact and cover the top surface and opposite sidewalls of the upper portion of the passivation pattern NLP.

[0161] The semiconductor device according to embodiments of the present invention can prevent excessive recessing of the top surface of the device isolation layer, which would degrade the electrical characteristics of the semiconductor device. Furthermore, according to embodiments of the present invention, channels and gate electrodes can be formed stably, resulting in improved reliability and electrical characteristics of the semiconductor device.

[0162] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as defined by the appended claims.

[0163] This application claims priority to Korean Patent Application No. 10-2020-0182042, filed on December 23, 2020, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: The first active pattern is disposed on the substrate; A device isolation layer is filled with trenches that define the first active pattern; A first channel pattern and a first source / drain pattern are disposed on the first active pattern, wherein the first channel pattern comprises a plurality of semiconductor patterns that are stacked and spaced apart from each other. The gate electrode extends and spans the first channel pattern; A gate dielectric layer is disposed between the first channel pattern and the gate electrode; as well as A first passivation pattern is disposed between the device isolation layer and the first sidewall of the first active pattern. The first passivation pattern includes: The upper part protruding upward from the device's isolation layer; as well as The lower part buried in the device's isolation layer The gate dielectric layer covers the top surface and the opposite sidewall of the upper portion of the first passivation pattern.

2. The semiconductor device of claim 1, wherein the top surface of the upper portion of the first passivation pattern is higher than the top surface of the first active pattern. The top surface of the upper part of the first passivation pattern is lower than the bottom surface of the lowermost semiconductor pattern in the semiconductor pattern.

3. The semiconductor device according to claim 1, further comprising: A second passivation pattern is disposed between the device isolation layer and the second sidewall of the first active pattern, the second sidewall being opposite to the first sidewall. The size of the first passivation pattern is different from the size of the second passivation pattern.

4. The semiconductor device according to claim 1, wherein neither the first passivation pattern nor an additional passivation pattern is provided between the device isolation layer and the second sidewall of the first active pattern, and the second sidewall is opposite to the first sidewall.

5. The semiconductor device according to claim 1, further comprising: The second and third active patterns are disposed on the substrate. The first active pattern to the third active pattern are arranged sequentially along a first direction, and the first pitch between the first active pattern and the second active pattern is different from the second pitch between the second active pattern and the third active pattern. as well as A second passivation pattern is disposed between the device isolation layer and the sidewall of the second active pattern. The first sidewall of the first active pattern faces the second active pattern. The sidewall of the second active pattern faces the third active pattern, and The size of the first passivation pattern is different from the size of the second passivation pattern.

6. The semiconductor device of claim 1, further comprising a liner disposed between the first passivation pattern and the first sidewall of the first active pattern. The first passivation pattern includes SiOC, SiN, SiC, AlO, TiO2, or a combination thereof, and The liner comprises a silicon oxide layer.

7. The semiconductor device of claim 1, wherein the gate dielectric layer directly contacts and covers the top surface and the opposite sidewall of the upper portion of the first passivation pattern.

8. The semiconductor device of claim 1, wherein the first passivation pattern is further disposed between the first source / drain pattern and the device isolation layer.

9. The semiconductor device of claim 1, wherein the semiconductor pattern comprises a first semiconductor pattern, a second semiconductor pattern, and a third semiconductor pattern stacked sequentially. The gate electrode includes: The first part is disposed between the first active pattern and the first semiconductor pattern; The second part is disposed between the first semiconductor pattern and the second semiconductor pattern; The third part is disposed between the second semiconductor pattern and the third semiconductor pattern; as well as The fourth part is disposed on the third semiconductor pattern.

10. The semiconductor device of claim 1, wherein the gate electrode surrounds the top surface, bottom surface and opposite sidewalls of each of the semiconductor patterns.

11. A semiconductor device, comprising: The first active pattern is disposed on the substrate; A device isolation layer is filled with trenches that define the first active pattern; A first channel pattern and a first source / drain pattern are disposed on the first active pattern, wherein the first channel pattern comprises a plurality of semiconductor patterns that are stacked and spaced apart from each other. The gate electrode extends and spans the first channel pattern; A gate dielectric layer is disposed between the first channel pattern and the gate electrode; A first passivation pattern is disposed between the device isolation layer and the first sidewall of the first active pattern; as well as A second passivation pattern is disposed between the device isolation layer and the second sidewall of the first active pattern, the second sidewall being opposite to the first sidewall. The size of the first passivation pattern is different from the size of the second passivation pattern. The first passivation pattern includes: The upper part protruding upward from the device's isolation layer; as well as The lower part buried in the device's isolation layer The gate dielectric layer covers the top surface and the opposite sidewall of the upper portion of the first passivation pattern.

12. The semiconductor device according to claim 11, The top surface of the upper part of the first passivation pattern is higher than the top surface of the first active pattern. The top surface of the upper part of the first passivation pattern is lower than the bottom surface of the lowermost semiconductor pattern in the semiconductor pattern.

13. The semiconductor device of claim 12, wherein the gate dielectric layer covers the upper portion of the first passivation pattern.

14. The semiconductor device of claim 11, further comprising: The second and third active patterns are disposed on the substrate. The first active pattern is disposed between the second active pattern and the third active pattern, and The first pitch between the first active pattern and the second active pattern is different from the second pitch between the first active pattern and the third active pattern.

15. The semiconductor device according to claim 11, further comprising: Multiple layers are disposed between the first sidewall of the first active pattern and the first passivation pattern, and between the second sidewall of the first active pattern and the second passivation pattern. The first passivation pattern and the second passivation pattern include SiOC, SiN, SiC, AlO, TiO2, or combinations thereof, and The liner comprises a silicon oxide layer.

16. A semiconductor device, comprising: The first active pattern is disposed on the substrate; A device isolation layer is filled with trenches that define the first active pattern; A first passivation pattern is disposed between the device isolation layer and the first sidewall of the first active pattern; A first source / drain pattern disposed on the first active pattern and a first channel pattern connected to the first source / drain pattern, the first channel pattern comprising a first semiconductor pattern, a second semiconductor pattern and a third semiconductor pattern that are stacked sequentially and spaced apart from each other; A gate electrode, spanning the first channel pattern and extending in a first direction, includes a first portion disposed between the first active pattern and the first semiconductor pattern, a second portion disposed between the first semiconductor pattern and the second semiconductor pattern, a third portion disposed between the second semiconductor pattern and the third semiconductor pattern, and a fourth portion disposed on the third semiconductor pattern; A gate dielectric layer is disposed between the first channel pattern and the gate electrode; Multiple gate spacers are disposed on opposite sidewalls of the fourth portion of the gate electrode; A gate cap pattern is disposed on the top surface of the gate electrode; A first interlayer dielectric layer is disposed on the gate cap pattern; An active contact penetrates the first interlayer dielectric layer and is electrically connected to the first source / drain pattern; The gate contact penetrates the first interlayer dielectric layer and is electrically connected to the gate electrode; The second interlayer dielectric layer is disposed on the first interlayer dielectric layer; A first metal layer is disposed in the second interlayer dielectric layer, and the first metal layer includes a plurality of first lines electrically connected to the active contact and the gate contact; The third interlayer dielectric layer is disposed on the second interlayer dielectric layer; as well as The second metal layer is disposed within the third interlayer dielectric layer. The second metal layer includes a plurality of second lines, which are electrically connected to a corresponding first line among the plurality of first lines. The first passivation pattern includes: The upper part protruding upward from the device's isolation layer; as well as The lower part buried in the device's isolation layer The gate dielectric layer covers the top surface and the opposite sidewall of the upper portion of the first passivation pattern.

17. The semiconductor device of claim 16, wherein the top surface of the upper portion of the first passivation pattern is higher than the top surface of the first active pattern. The top surface of the upper part of the first passivation pattern is lower than the bottom surface of the first semiconductor pattern.

18. The semiconductor device of claim 16, further comprising: A second passivation pattern is disposed between the device isolation layer and the second sidewall of the first active pattern, the second sidewall being opposite to the first sidewall. The size of the first passivation pattern is different from the size of the second passivation pattern.

19. The semiconductor device of claim 16, further comprising: The second and third active patterns are disposed on the substrate. The first active pattern to the third active pattern are arranged sequentially along the first direction, and the first pitch between the first active pattern and the second active pattern is different from the second pitch between the second active pattern and the third active pattern. as well as A second passivation pattern is disposed between the device isolation layer and the sidewall of the second active pattern. The first sidewall of the first active pattern faces the second active pattern. The sidewall of the second active pattern faces the third active pattern, and The size of the first passivation pattern is different from the size of the second passivation pattern.

20. The semiconductor device of claim 16, further comprising: A liner is disposed between the first sidewall of the first passivation pattern and the first active pattern. The first passivation pattern includes SiOC, SiN, SiC, AlO, TiO2, or a combination thereof, and The liner comprises a silicon oxide layer.

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