Semiconductor structure and method of fabrication, three-dimensional memory and storage system

Abstract

The disclosure provides a semiconductor structure and a preparation method, a three-dimensional memory and a storage system, and relates to the technical field of semiconductor chips, so as to reduce the risk of high resistance or open circuit caused by etching of the gate line layer. The preparation method of the semiconductor structure comprises the following steps: sequentially forming a first dielectric layer, a first barrier layer, a first polysilicon layer, a second barrier layer and an initial stack structure on a substrate, and the initial stack structure comprises a plurality of second dielectric layers and a plurality of sacrificial layers which are alternately stacked. The semiconductor structure is applied to the three-dimensional memory to realize the read and write operations of data.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and preparation method, a three-dimensional memory and a storage system. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of process technology, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging memory cells three-dimensionally on a substrate. However, the product yield in the manufacturing process of 3D NAND is low. Summary of the Invention

[0003] Embodiments of this disclosure provide a semiconductor structure and fabrication method, a three-dimensional memory and a storage system to improve product yield.

[0004] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions:

[0005] On one hand, a method for fabricating a semiconductor structure is provided. The method includes: forming a first dielectric layer on a substrate; forming a first barrier layer on a side of the first dielectric layer away from the substrate; forming a first polysilicon layer on a side of the first barrier layer away from the substrate; forming a second barrier layer on a side of the first polysilicon layer away from the substrate; and forming an initial stacked structure on a side of the second barrier layer away from the substrate; the initial stacked structure includes a plurality of alternately stacked second dielectric layers and a plurality of sacrificial layers.

[0006] Based on this, some embodiments of the present disclosure provide a method for fabricating a semiconductor structure in which a first barrier layer is formed on the side of the first polysilicon layer close to the substrate, and a second barrier layer is formed on the side of the first polysilicon layer away from the substrate. Both the first and second barrier layers are configured to block oxide ions included in the oxidant used in subsequent oxidation processes from passing through.

[0007] In this case, in subsequent processes, such as during the oxidation of the polysilicon at the bottom of the sacrificial gap and gate line gap, since the first barrier layer and the second barrier layer are respectively provided on the sides of the first polysilicon layer near and away from the substrate, the oxide ions included in the oxidant used in the oxidation process cannot pass through the first barrier layer and the second barrier layer. As a result, the first polysilicon layer is oxidized over a large area on the surface near and away from the substrate, reducing the expansion of the first polysilicon layer in the direction perpendicular to the substrate, reducing the risk of the sacrificial gap being compressed, thereby reducing the risk of high resistance due to compression deformation of the gate layer near the substrate in the stacked structure, such as the bottom select gate, and improving product yield.

[0008] In some embodiments, the thickness of the first barrier layer is 1 nm to 5 nm along a direction perpendicular to the substrate; and / or, the thickness of the second barrier layer is 1 nm to 5 nm.

[0009] In some embodiments, forming the first barrier layer includes: forming a first polycrystalline silicon thin film on the side of the first dielectric layer away from the substrate; and treating the first polycrystalline silicon thin film with a nitrogen-containing gas to form the first barrier layer.

[0010] In some embodiments, forming the second barrier layer includes: treating the surface of the first polysilicon layer away from the substrate with a nitrogen-containing gas to form the second barrier layer. Alternatively, forming a second polysilicon film on the side of the first polysilicon layer away from the substrate; treating the second polysilicon film with a nitrogen-containing gas to form the second barrier layer.

[0011] In some embodiments, between forming the second barrier layer and forming the initial stacked structure, the method further includes: forming a third dielectric layer on the side of the second barrier layer away from the substrate; forming a third barrier layer on the side of the third dielectric layer away from the substrate; forming a second polysilicon layer on the side of the third barrier layer away from the substrate; and forming a fourth barrier layer on the side of the second polysilicon layer away from the substrate.

[0012] In some embodiments, the thickness of the third barrier layer is 1 nm to 5 nm; and / or, the thickness of the fourth barrier layer is 1 nm to 5 nm.

[0013] In some embodiments, forming the third barrier layer includes: forming a third polycrystalline silicon thin film on the side of the third dielectric layer away from the substrate; and treating the third polycrystalline silicon thin film with a nitrogen-containing gas to form the third barrier layer.

[0014] In some embodiments, forming the fourth barrier layer includes: treating the surface of the second polysilicon layer away from the substrate with a nitrogen-containing gas to form the fourth barrier layer. Alternatively, forming a fourth polysilicon film on the side of the second polysilicon layer away from the substrate; treating the fourth polysilicon film with a nitrogen-containing gas to form the fourth barrier layer.

[0015] In some embodiments, after forming an initial stacked structure on the side of the second barrier layer away from the substrate, the method further includes: forming a channel structure through the initial stacked structure; forming a gate line gap through the initial stacked structure; removing the sacrificial layer through the gate line gap to form a sacrificial gap; oxidizing the polysilicon at the bottom of the sacrificial gap and the gate line gap; forming a gate layer within the sacrificial gap; and forming a gate line isolation structure within the gate line gap.

[0016] In some embodiments, forming a channel structure through the initial stacked structure includes: forming a channel hole through the initial stacked structure; oxidizing the polysilicon at the bottom of the channel hole; and forming a channel structure within the channel hole.

[0017] In some embodiments, after forming the gate isolation structure, the method further includes: sequentially removing the substrate, the first dielectric layer, the first barrier layer, the first polysilicon layer, and the second barrier layer to expose the portion of the channel structure extending into the first polysilicon layer.

[0018] In some embodiments, a third dielectric layer is formed before the initial stacked structure is formed; the third dielectric layer is also removed during the removal of the second barrier layer.

[0019] In some embodiments, the channel structure includes a memory functional layer and a semiconductor channel layer formed sequentially; during the removal of the third dielectric layer, the exposed portion of the memory functional layer of the channel structure is also removed to expose the semiconductor channel layer. After exposing the semiconductor channel layer, the fabrication method further includes forming a source layer on the side of the second polysilicon layer away from the initial stacked structure, the source layer being electrically connected to the semiconductor channel layer.

[0020] On the other hand, a semiconductor structure is provided. The semiconductor structure includes a source layer, a second polysilicon layer, a fourth barrier layer, and a stacked structure. The second polysilicon layer is disposed on one side of the source layer. The fourth barrier layer is disposed on the side of the second polysilicon layer away from the source layer. The stacked structure is disposed on the side of the fourth barrier layer away from the second polysilicon layer; the stacked structure includes a plurality of alternately stacked second dielectric layers and a plurality of gate layers.

[0021] In some embodiments, the material of the fourth barrier layer includes silicon nitride or aluminum oxide.

[0022] In another aspect, a semiconductor structure is provided. The semiconductor structure includes a substrate, a first dielectric layer, a first barrier layer, a first polysilicon layer, a second barrier layer, and a stacked structure. The first dielectric layer is disposed on one side of the substrate. The first barrier layer is disposed on the side of the first dielectric layer away from the substrate. The first polysilicon layer is disposed on the side of the first barrier layer away from the first dielectric layer. The second barrier layer is disposed on the side of the first polysilicon layer away from the first barrier layer. The stacked structure is disposed on the side of the second barrier layer away from the first polysilicon layer; the stacked structure includes a plurality of alternately stacked second dielectric layers and a plurality of gate layers.

[0023] In some embodiments, the semiconductor structure further includes a third dielectric layer, a third barrier layer, a second polysilicon layer, and a fourth barrier layer. The third dielectric layer is disposed between the second barrier layer and the stacked structure. The second polysilicon layer is disposed between the third barrier layer and the stacked structure. The fourth barrier layer is disposed between the second polysilicon layer and the stacked structure.

[0024] In some embodiments, the material of the first barrier layer includes silicon nitride or aluminum oxide; and / or, the material of the second barrier layer includes silicon nitride or aluminum oxide; and / or, the material of the third barrier layer includes silicon nitride or aluminum oxide; and / or, the material of the fourth barrier layer includes silicon nitride or aluminum oxide.

[0025] Furthermore, a three-dimensional memory is provided. It includes a semiconductor structure and peripheral devices, wherein the semiconductor structure is the semiconductor structure described in any of the above embodiments or is prepared by the method described in any of the above embodiments, and the semiconductor structure is electrically connected to the peripheral devices.

[0026] In another aspect, a storage system is provided. The storage system includes a controller and a three-dimensional memory, the three-dimensional memory being the three-dimensional memory described in any of the above embodiments, and the controller is coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

[0027] It is understood that the beneficial effects of the semiconductor structure, three-dimensional memory and storage system provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure preparation method described above, and will not be repeated here. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0029] Figures 1-7 This is a flowchart of a method for fabricating a semiconductor structure according to some embodiments;

[0030] Figures 8-14 This is a diagram illustrating the fabrication steps of a semiconductor structure fabrication method according to some embodiments;

[0031] Figure 15 This is a three-dimensional structural diagram of a semiconductor structure provided according to some embodiments;

[0032] Figure 16 A cross-sectional view of a semiconductor structure provided according to some embodiments;

[0033] Figure 17 This is a structural diagram of a three-dimensional memory according to some embodiments;

[0034] Figure 18 This is a structural diagram of another three-dimensional memory according to some embodiments;

[0035] Figure 19 This is a block diagram of a storage system according to some embodiments;

[0036] Figure 20 This is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0037] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0038] In the description of this disclosure, it should be understood that the terms “center,” “upper,” “lower,” “front,” “rear,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer,” etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0039] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0040] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0041] In describing some embodiments, the term "connection" and its derivative expressions may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0042] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0043] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0044] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0045] This document describes exemplary embodiments with reference to sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0046] The term "three-dimensional memory" refers to a semiconductor structure formed by strings of memory cell transistors (referred to herein as "memory cell strings," such as NAND memory cell strings) arranged in an array on the main surface of a substrate and extending in a direction perpendicular to the substrate. As used herein, the term "perpendicularly" means nominally perpendicular to the main surface of the substrate (i.e., the lateral surface).

[0047] As used in this disclosure, whether a component (e.g., a layer, structure, or device) is "on," "above," or "below" another component (e.g., a layer, structure, or device) of a semiconductor structure (e.g., a three-dimensional memory) is determined when the substrate is in a third-party Z-direction (refer to...). Figure 14 When the device is located in the lowest plane of the semiconductor structure in the thickness direction (i.e., the direction of the device thickness), it is determined relative to the substrate of the semiconductor structure in the third direction Z. The same concept is used throughout this disclosure to describe spatial relationships.

[0048] In the fabrication process of 3D NAND, after removing the sacrificial layer through the gate line gaps to form the sacrificial gap, the sacrificial gap usually needs to be oxidized to improve the leakage current prevention performance of the fabricated 3D NAND. However, during the oxidation process of the sacrificial gap, a large area of ​​the sacrificial polysilicon layer in the substrate is often oxidized, causing the sacrificial polysilicon layer to expand in the direction perpendicular to the substrate. This compresses the sacrificial gap, resulting in compression deformation of the gate layer near the substrate in the 3D NAND. This causes high impedance in the select transistor corresponding to the bottom select gate, leading to a decrease in product yield.

[0049] Based on this, see Figure 1 and Figure 14 Some embodiments of this disclosure provide a method for fabricating a semiconductor structure 100, the method comprising steps S11 to S15.

[0050] S11: As Figure 8 As shown, a first dielectric layer 11 is formed on the substrate 10.

[0051] In the above steps, any one of the thin film deposition processes, namely chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD), can be used to form the first dielectric layer 11 on the substrate 10.

[0052] The substrate 10 can be used to support the device structure thereon. In the etching process that removes the substrate 10, the first dielectric layer 11 can be configured as an etching stop layer. Specifically, the etching rate of the material of the first dielectric layer 11 is different from the etching rate of the material of the substrate 10. For example, the material of the first dielectric layer 11 is silicon oxide, and the material of the substrate 10 is monocrystalline silicon.

[0053] It should be noted that the substrate 10 may include amorphous silicon, polycrystalline silicon, single-crystal silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials; the substrate 10 may also be made of non-conductive materials such as glass, plastic, or sapphire wafers. The material of the first dielectric layer 11 may include at least one of silicon oxide, silicon oxynitride, doped silicon oxide, organosilicon glass, and organic insulating materials.

[0054] S12: As Figure 8 As shown, a first barrier layer 12 is formed on the side of the first dielectric layer 11 away from the substrate 10.

[0055] In the above steps, any one of the thin film deposition processes, such as CVD, PVD, or ALD, can be used to form the first barrier layer 12 on the side of the first dielectric layer 11 away from the substrate 10. Of course, the first barrier layer 12 can also be formed by combining the thin film deposition process with other processes, as detailed in S121~S122.

[0056] The first barrier layer 12 is configured to block oxide ions from passing through the oxidant used in subsequent oxidation processes (e.g., S19); for example, the material of the first barrier layer 12 may include silicon nitride. In this case, materials including... The gas containing oxide ions acts as an oxidizing agent, and the first barrier layer 12 can block it. Oxide ions pass through. Of course, the material of the first barrier layer 12 may also include other materials, such as aluminum oxide, but this disclosure is not limited thereto. The thickness of the first barrier layer 12 is 1 nm to 5 nm along the direction perpendicular to the substrate 10.

[0057] S13: As Figure 8 As shown, a first polysilicon layer 13 is formed on the side of the first barrier layer 12 away from the substrate 10.

[0058] In the above steps, any one of the thin film deposition processes, CVD, PVD, or ALD, can be used to form a first polysilicon layer 13 on the side of the first barrier layer 12 away from the substrate 10. The material of the first polysilicon layer 13 includes a polysilicon layer or doped polysilicon. In the etching process for removing the first barrier layer 12, the first polysilicon layer 13 can be configured as an etching stop layer. Specifically, the etching rate of the material of the first barrier layer 12 is different from the etching rate of the material of the first polysilicon layer 13.

[0059] S14: As Figure 8 As shown, a second barrier layer 14 is formed on the side of the first polysilicon layer 13 away from the substrate 10.

[0060] In the above steps, any one of the thin film deposition processes, such as CVD, PVD, or ALD, can be used to form the second barrier layer 14 on the side of the first polysilicon layer 13 away from the substrate 10. Of course, the second barrier layer 14 can also be formed by combining a thin film deposition process with other processes, as detailed in S141.

[0061] The second barrier layer 14 is configured to block oxide ions from passing through the oxidant used in subsequent oxidation processes (e.g., S19); for example, the material of the second barrier layer 14 may include silicon nitride. In this case, materials including... The gas containing oxide ions acts as an oxidizing agent, and the second barrier layer 14 can block it. Oxide ions pass through. Of course, the material of the second barrier layer 14 can also include other materials, such as aluminum oxide, but this disclosure is not limited thereto. The thickness of the second barrier layer 14 is 1 nm to 5 nm along the direction perpendicular to the substrate 10.

[0062] S15: As Figure 8 As shown, an initial stacked structure 200 is formed on the side of the second barrier layer 14 away from the substrate 10.

[0063] In the above steps, the initial stacked structure 200 can be formed using any thin film deposition process such as CVD, PVD, or ALD. The initial stacked structure 200 includes multiple alternately stacked second dielectric layers 31 and multiple sacrificial layers 33. The thicknesses of the multiple second dielectric layers 31 and the multiple sacrificial layers 33 can be the same or different, and can be set according to specific process requirements. Furthermore, this disclosure does not limit the number of layers in the initial stacked structure 200; for example, the number of layers in the initial stacked structure 200 can be 8, 64, 128, etc.

[0064] In some embodiments, among the second dielectric layer 31 and sacrificial layer 33 of the initial stacked structure 200, the layer closest to the substrate 10 is the second dielectric layer 31. In other embodiments, among the second dielectric layer 31 and sacrificial layer 33 of the initial stacked structure 200, the layer closest to the substrate 10 is the sacrificial layer 33.

[0065] The material of the second dielectric layer 31 may include at least one of silicon oxide, silicon oxynitride, doped silicon oxide, organosilicon glass, and organic insulating materials. The material of the sacrificial layer 33 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0066] It should be noted that the materials of the sacrificial layer 33 and the second dielectric layer 31 can be used in combination, so that the etching rate of the material of the sacrificial layer 33 is different from that of the material of the second dielectric layer 31 during the etching process. Therefore, in subsequent processes, the sacrificial layer 33 can be removed while the second dielectric layer 31 is retained.

[0067] As described above, in some embodiments of this disclosure, a method for fabricating a semiconductor structure 100 includes forming a first barrier layer 12 on the side of the first polysilicon layer 13 close to the substrate 10, and forming a second barrier layer 14 on the side of the first polysilicon layer 13 away from the substrate 10. Both the first barrier layer 12 and the second barrier layer 14 are configured to block oxide ions from passing through the oxidant used in subsequent oxidation processes.

[0068] In this case, during subsequent processes, such as the oxidation of the polysilicon at the bottom of the sacrificial gap CV and the gate line gap GLS, since the first barrier layer 13 is provided with a first barrier layer 12 and a second barrier layer 14 on its sides near and away from the substrate 10, the oxide ions included in the oxidant used in the oxidation process cannot pass through the first barrier layer 12 and the second barrier layer 14. This results in a large-area oxidation of the first polysilicon layer 13 on its surfaces near and away from the substrate 10, reducing the expansion of the first polysilicon layer 13 in the direction perpendicular to the substrate 10, reducing the risk of the sacrificial gap CV being compressed, and thus reducing the portion of the gate layer 32 near the substrate 10 in the stacked structure 30, such as the bottom select gate (BSG) (see...). Figure 15 This reduces the risk of high resistance due to compression deformation and improves product yield.

[0069] In some embodiments, see Figure 2 The above S12 includes S121~S122.

[0070] S121: A first polycrystalline silicon thin film is formed on the side of the first dielectric layer 11 away from the substrate 10.

[0071] In the above steps, any one of the thin film deposition processes, CVD, PVD, or ALD, can be used to form a first polycrystalline silicon thin film on the side of the first dielectric layer 11 away from the substrate 10. The thickness of the first polycrystalline silicon thin film can be 1 nm to 5 nm along the direction perpendicular to the substrate 10.

[0072] S122: The first polycrystalline silicon thin film is treated with nitrogen-containing gas to form the first barrier layer 12.

[0073] In the above steps, the first polycrystalline silicon thin film can react with a nitrogen-containing gas to form a silicon nitride thin film, namely the first barrier layer 12. The nitrogen-containing gas may include ammonia and / or nitrogen, but this disclosure is not limited thereto.

[0074] In some embodiments, S14 may include S141 or S142-S143.

[0075] S141: The surface of the first polysilicon layer 13 away from the substrate 10 is treated with nitrogen-containing gas to form the second barrier layer 14.

[0076] In the above steps, the surface of the first polysilicon layer 13 away from the substrate 10 can react with a nitrogen-containing gas, such that the portion of the first polysilicon layer 13 farther from the substrate 10 reacts with the nitrogen-containing gas to form a silicon nitride thin film, namely the second barrier layer 14. The nitrogen-containing gas may include ammonia and / or nitrogen, but this disclosure is not limited thereto.

[0077] S142: A second polysilicon thin film is formed on the side of the first polysilicon layer 13 away from the substrate 10.

[0078] In the above steps, any one of the thin film deposition processes, CVD, PVD, or ALD, can be used to form a second polycrystalline silicon thin film on the side of the first dielectric layer 11 away from the substrate 10. The thickness of the second polycrystalline silicon thin film can be 1 nm to 5 nm along the direction perpendicular to the substrate 10.

[0079] S143: The second polycrystalline silicon thin film is treated with nitrogen-containing gas to form the second barrier layer 14.

[0080] In the above steps, the second polycrystalline silicon film can react with a nitrogen-containing gas to form a silicon nitride film, namely the second barrier layer 14. The nitrogen-containing gas may include ammonia and / or nitrogen, but this disclosure is not limited thereto.

[0081] In some embodiments, see Figure 3 Between S14 and S15, the preparation method also includes S21 to S24.

[0082] S21: As Figure 8 As shown, a third dielectric layer 22 is formed on the side of the second barrier layer 14 away from the substrate 10.

[0083] In the above steps, any one of the thin film deposition processes of CVD, PVD, and ALD can be used to form the third dielectric layer 22 on the side of the second barrier layer 14 away from the substrate 10. The material of the third dielectric layer 22 may include at least one of silicon oxide, silicon oxynitride, doped silicon oxide, organosilicon glass, and organic insulating materials.

[0084] S22: As Figure 8 As shown, a third barrier layer 23 is formed on the side of the third dielectric layer 22 away from the substrate 10.

[0085] In the above steps, any one of the thin film deposition processes, such as CVD, PVD, or ALD, can be used to form the third barrier layer 23 on the side of the third dielectric layer 22 away from the substrate 10. Of course, a combination of thin film deposition and other processes can also be used to form the third barrier layer 23, as detailed in S221~S222.

[0086] The third barrier layer 23 is configured to block oxide ions from passing through the oxidant used in subsequent oxidation processes (e.g., S19); for example, the material of the third barrier layer 23 may include silicon nitride; in this case, materials including... The gas containing oxide ions acts as an oxidizing agent, and the third barrier layer 23 can block it. Oxide ions pass through. Of course, the material of the third barrier layer 23 can also include other materials, such as aluminum oxide, but this disclosure is not limited thereto. The thickness of the third barrier layer 23 is 1 nm to 5 nm along the direction perpendicular to the substrate 10.

[0087] S23: As Figure 8 As shown, a second polysilicon layer 20 is formed on the side of the third barrier layer 23 away from the substrate 10.

[0088] In the above steps, any one of the thin film deposition processes, CVD, PVD, or ALD, can be used to form a second polysilicon layer 20 on the side of the third barrier layer 23 away from the substrate 10. The material of the second polysilicon layer 20 includes a polysilicon layer or a doped polysilicon layer.

[0089] In the etching process for removing the third dielectric layer 22, the second polysilicon layer 20 can be configured as an etching stop layer. Specifically, the etching rate of the material of the third barrier layer 23 is different from the etching rate of the material of the second polysilicon layer 20.

[0090] S24: As Figure 8 As shown, a fourth barrier layer 21 is formed on the side of the second polysilicon layer 20 away from the substrate 10.

[0091] In the above steps, any one of the thin film deposition processes, such as CVD, PVD, or ALD, can be used to form the fourth barrier layer 21 on the side of the second polysilicon layer 20 away from the substrate 10. Of course, the fourth barrier layer 21 can also be formed by combining a thin film deposition process with other processes, as detailed in S241.

[0092] The fourth barrier layer 21 is configured to block oxide ions from passing through the oxidant used in subsequent oxidation processes (e.g., S19); for example, the material of the fourth barrier layer 21 may include silicon nitride; in this case, materials including... The gas containing oxide ions acts as an oxidizing agent, and the fourth barrier layer 21 can block it. Oxide ions pass through. Of course, the material of the fourth barrier layer 21 can also include other materials, such as aluminum oxide, but this disclosure is not limited thereto. The thickness of the fourth barrier layer 21 is 1 nm to 5 nm along the direction perpendicular to the substrate 10.

[0093] In some embodiments, see Figure 6 The above S22 includes S221 to S222.

[0094] S221: A third polycrystalline silicon thin film is formed on the side of the third dielectric layer 22 away from the substrate 10.

[0095] In the above steps, any one of CVD, PVD, or ALD thin film deposition processes can be used to form a third polycrystalline silicon thin film on the side of the third dielectric layer 22 away from the substrate 10. The thickness of the third polycrystalline silicon thin film along the direction perpendicular to the substrate 10 can be 1 nm to 5 nm.

[0096] S222: The third polycrystalline silicon thin film is treated with nitrogen-containing gas to form the third barrier layer 23.

[0097] In the above steps, the third polycrystalline silicon thin film can react with a nitrogen-containing gas to form a silicon nitride thin film, namely the third barrier layer 23. The nitrogen-containing gas may include ammonia and / or nitrogen, but this disclosure is not limited thereto.

[0098] In some embodiments, S24 may include S241 or S242-S243.

[0099] S241: The surface of the second polysilicon layer 20 away from the substrate 10 is treated with nitrogen-containing gas to form a fourth barrier layer 21.

[0100] In the above steps, the surface of the second polysilicon layer 20 away from the substrate 10 can react with nitrogen-containing gas, so that the portion of the second polysilicon layer 20 that is farther away from the substrate 10 reacts with the nitrogen-containing gas, thereby forming a silicon nitride thin film, namely the fourth barrier layer 21.

[0101] S242: A fourth polysilicon thin film is formed on the side of the second polysilicon layer 20 away from the substrate.

[0102] In the above steps, any one of the thin film deposition processes, CVD, PVD, or ALD, can be used to form a fourth polycrystalline silicon thin film on the side of the first dielectric layer 11 away from the substrate 10. The thickness of the fourth polycrystalline silicon thin film can be 1 nm to 5 nm along the direction perpendicular to the substrate 10.

[0103] S243: The fourth polycrystalline silicon thin film is treated with nitrogen-containing gas to form the fourth barrier layer 21.

[0104] In the above steps, the fourth polycrystalline silicon thin film can react with a nitrogen-containing gas to form a silicon nitride thin film, namely the fourth barrier layer 21. The nitrogen-containing gas may include ammonia and / or nitrogen, but this disclosure is not limited thereto.

[0105] In some embodiments, see Figure 7 After S15, the above preparation method also includes S151 to S156.

[0106] S151: As Figure 10 As shown, a channel structure 40 is formed that penetrates the initial stacked structure 200.

[0107] For example, the channel structure 40 may extend into the first polysilicon layer 13, that is, through the first polysilicon layer 13 near the surface of the initial stacked structure 200. Specifically, the formation of the channel structure 40 through the initial stacked structure 200 can be referred to S161 to S163.

[0108] The specific details of forming the channel structure 40 can be found in S1521~S1523, which will not be elaborated here.

[0109] S152: As Figure 9 and Figure 10 As shown, a gate line gap (GLS) is formed that runs through the initial stacked structure 200.

[0110] In the above steps, gate line gaps (GLS) can be formed in the initial stacked structure 200 using a dry / wet etching process. Exemplarily, the gate line gaps (GLS) can extend into the first polysilicon layer 13. For example, the gate line gaps (GLS) can be formed using anisotropic etching (any one of dry etching methods such as ion milling, plasma etching, reactive ion etching, and laser ablation).

[0111] The first polysilicon layer 13 can be configured as an etch stop layer for etching to form the gate line gap (GLS), that is, the etching of the gate line gap (GLS) is stopped by the first polysilicon layer 13, so that the gate line gap (GLS) will not extend further to the first barrier layer 12, the first dielectric layer 11 and the substrate 10.

[0112] S153: As Figure 10 and Figure 11 As shown, the sacrificial layer 33 is removed via the gate gap GLS to form the sacrificial gap CV.

[0113] In the above steps, the gate gap (GLS) is used as an etchant channel, and isotropic etching is employed to remove the sacrificial layer 33 to form the sacrificial gap CV. Isotropic etching can be performed using selective wet etching or vapor phase etching. In wet etching, an etchant solution is used as the etchant; in vapor phase etching, an etchant gas is used as the etchant. Since the first barrier layer 12, the second barrier layer 14, and the third barrier layer 23 and the fourth barrier layer 21 (mentioned below) are relatively thin (for example, less than the thickness of the sacrificial layer 33), their corresponding contact area with the etchant is small, resulting in a slower etching rate. Therefore, during the process of removing the sacrificial layer 33 to form the sacrificial gap CV, by controlling the etching time and the thicknesses of the first barrier layer 12, the second barrier layer 14, and the third barrier layer 23 and the fourth barrier layer 21 relative to the sacrificial layer 33, it is possible to remove the sacrificial layer 33 to form the sacrificial gap CV while preserving a large area of ​​the first barrier layer 12, the second barrier layer 14, and the third barrier layer 23 and the fourth barrier layer 21.

[0114] It should be noted that when the material of the first dielectric layer 11 is silicon oxide and the material of the sacrificial layer 33 is silicon nitride, phosphoric acid solution can be used as an etchant in wet etching; and at least one of C4F8, C4F6 and CH2F2 can be used as an etching gas in vapor phase etching.

[0115] S154: See also Figure 11 The polysilicon at the bottom of the sacrificial gap (CV) and the gate line gap (GLS) is oxidized.

[0116] The above steps may employ methods including... The gas of oxide ions is used as an oxidant to process the polysilicon at the bottom of the sacrificial gap CV and the gate gap GLS under a high temperature environment, thereby changing the properties of the inner surface of the sacrificial gap CV, improving the leakage protection performance, and forming an oxide layer on the surface of the first polysilicon layer 13 exposed through the gate gap GLS, so as to protect the gate isolation structure 50 formed in the gate gap GLS in subsequent processes.

[0117] S155: As Figure 11 and Figure 12 As shown, a gate layer 32 is formed within the sacrificial gap CV.

[0118] In the above steps, the gate gap (GLS) can be used as a deposition channel, and any thin film deposition process of CVD, PVD, or ALD can be used to form the gate layer 32 within the sacrificial gap (CV).

[0119] In some embodiments, such as Figure 12 As shown, the gate layer 32 may include a conductor layer 321, and the material of the conductor layer 321 may include a conductive material, such as at least one selected from tungsten, cobalt, copper, aluminum, doped silicon, and silicide. In this case, the conductor layer 321 can be formed within the sacrificial gap CV using any of the thin film deposition processes of CVD, PVD, and ALD.

[0120] In some embodiments, such as Figure 12 As shown, the gate layer 32 may further include an adhesive layer 322. The conductor layer 321 is separated from both the second dielectric layer 31 and the channel structure 40 by the adhesive layer 322. The adhesive layer 322 is configured to improve the adhesion of the conductor layer 321. The material of the adhesive layer 322 includes at least one of titanium nitride, tantalum nitride, and tungsten carbide. In this case, the adhesive layer 322 and the conductor layer 321 can be sequentially formed within the sacrificial gap CV using any of the thin film deposition processes of CVD, PVD, and ALD.

[0121] In some embodiments, such as Figure 12As shown, the gate layer 32 may further include a high dielectric constant layer 323. The adhesive layer 322 is separated from both the second dielectric layer 31 and the channel structure 40 by the high dielectric constant layer 323, i.e., the adhesive layer 322 is located between the high dielectric constant layer 323 and the conductor layer 321. The adhesive layer 322 is configured to improve the adhesion between the conductor layer 321 and the high dielectric constant layer 323. The dielectric constant of the high dielectric constant layer 323 is greater than 9. Exemplarily, the material of the high dielectric constant layer 323 includes at least one of alumina, hafnium oxide, and tantalum oxide. In this case, any thin film deposition process selected from CVD, PVD, and ALD can be used to sequentially form the high dielectric constant layer 323, the adhesive layer 322, and the conductor layer 321 within the sacrificial gap CV.

[0122] Based on the above, such as Figure 12 As shown, a stacked structure 30 can be formed, which includes an alternately stacked second dielectric layer 31 and a gate layer 32.

[0123] S156: As Figure 11 and Figure 12 As shown, a gate line isolation structure 50 is formed within the gate line gap (GLS).

[0124] In the above steps, the gate isolation structure 50 can be formed within the gate gap (GLS) using any of the following thin-film deposition processes: CVD, PVD, and ALD. For example, the gate isolation structure 50 can extend into the first polysilicon layer 13.

[0125] In some embodiments, see Figure 12 The gate line isolation structure 50 includes a first insulating layer 51, which is formed within the gate line gap GLS and covers the exposed sides of the gate line layer 32 by the gate line gap GLS to prevent short circuits between different gate line layers 32 within the gate line gap GLS and to prevent oxidation of the gate line layer 32.

[0126] It should be noted that the material of the first insulating layer 51 is an insulating material; for example, the material of the first insulating layer 51 includes at least one of silicon nitride, silicon oxide, and silicon oxynitride, but this disclosure is not limited thereto.

[0127] In some embodiments, such as Figure 12 As shown, the gate line isolation structure 50 also includes a gate line filling layer 52. After the first insulating layer 51 is formed in the gate line gap GLS, the gate line filling layer 52 can also be formed in the gate line gap GLS to provide mechanical support.

[0128] It should be noted that the material of the gate line filling layer 52 can be a conductive material or an insulating material. When the source signal is led out through the gate line isolation structure 50, the material of the gate line filling layer 52 can be a conductive material, for example, the material of the gate line filling layer 52 includes polysilicon, but this disclosure is not limited thereto.

[0129] In some embodiments, see Figure 4 The above S151 includes S1511 to S1513.

[0130] S1511: See also Figure 9 This forms a channel hole CH that penetrates the initial stacked structure 200.

[0131] In the above steps, the channel holes CH in the initial stacked structure 200 can be formed by a dry / wet etching process. Exemplarily, the channel holes CH can extend into the first polysilicon layer 13. For example, the channel holes CH can be formed using anisotropic etching (any one of dry etching processes such as ion milling, plasma etching, reactive ion etching, laser ablation, etc.).

[0132] In some embodiments, such as Figure 9 As shown, the channel hole CH formed in S161 that penetrates the initial stacked structure 200 and the gate line gap GLS formed in S17 that penetrates the initial stacked structure 200 can be performed in the same process, for example, by forming the channel hole CH and the gate line gap GLS in a single etching process.

[0133] In other embodiments, the formation of the channel hole CH penetrating the initial stacked structure 200 in S161 and the formation of the gate line gap GLS penetrating the initial stacked structure 200 in S17 can also be performed in different processes. For example, the channel hole CH can be formed by one etching process and the gate line gap GLS can be formed by another etching process. The order of the above two steps is not limited in this disclosure.

[0134] S1512: See also Figure 9 The polycrystalline silicon at the bottom of the channel hole CH is subjected to oxidation treatment.

[0135] The above steps may employ methods including... The gas of oxide ions is used as an oxidant to process the polysilicon at the bottom of the channel hole CH under high temperature. An oxide layer is formed on the surface of the first polysilicon layer 13 exposed through the channel hole CH, so as to protect the channel structure 40 formed in the channel hole CH in subsequent processes.

[0136] In some embodiments, the oxidation treatment of the polysilicon at the bottom of the channel hole CH in S162 and the oxidation treatment of the polysilicon at the bottom of the gate gap GLS in S19 can be performed in the same process. For example, an oxide layer can be formed at the bottom of both the channel hole CH and the bottom of the gate gap GLS through a single oxidation process.

[0137] In other embodiments, the oxidation treatment of the polysilicon at the bottom of the channel hole CH in S162 and the oxidation treatment of the polysilicon at the bottom of the gate gap GLS in S19 can also be performed in different processes. For example, an oxide layer can be formed at the bottom of the channel hole CH by a first oxidation process and an oxide layer can be formed at the bottom of the gate gap GLS by a second oxidation process. It should be noted that when the second oxidation process is performed after the formation of the sacrificial gap CV, the inner surface of the sacrificial gap CV can also be oxidized simultaneously during the formation of the oxide layer at the bottom of the gate gap GLS.

[0138] S1513: As Figure 9 and Figure 10 As shown, a channel structure 40 is formed within the channel hole CH.

[0139] In the above steps, any of the thin film deposition processes of CVD, PVD, and ALD can be used to sequentially deposit a barrier layer 41, a charge trapping layer 42, a tunneling layer 43, and a semiconductor channel layer 44 along the inner wall of the channel hole CH to form a channel structure 40. Among them, the barrier layer 41, the charge trapping layer 42, and the tunneling layer 43 can be referred to as the storage functional layer.

[0140] It should be noted that the materials of the barrier layer 41, charge trapping layer 42, tunneling layer 43 and semiconductor channel layer 44 can be silicon oxide, silicon nitride, silicon oxide and polysilicon, respectively, to form a "SONP" structure.

[0141] In some embodiments, after the storage functional layer and the semiconductor channel layer 44 are sequentially formed on the inner wall of the channel hole CH, a channel filling layer 45 may also be formed within the channel hole CH. For example, any thin film deposition process selected from CVD, PVD, and ALD can be used to fill the channel hole CG, where the storage functional layer and the semiconductor channel layer 44 are formed, with an insulating material, such as silicon oxide, to form a channel structure 40 having a storage functional layer, a semiconductor channel layer 44, and a channel filling layer 45.

[0142] Based on this, see S156, see below. Figure 5 The preparation method also includes S26.

[0143] S26: As Figure 12 and Figure 13As shown, the substrate 10, the first dielectric layer 11, the first barrier layer 12, the first polysilicon layer 13 and the second barrier layer 14 are removed in sequence to expose the portion of the channel structure 40 extending into the first polysilicon layer 13.

[0144] In the above steps, chemical mechanical planarization (CMP) and dry / wet etching processes can be used to remove the substrate 10.

[0145] In some embodiments, the etching rates of the materials of the first dielectric layer 11 and the first barrier layer 12 are similar. Thus, removing the first dielectric layer 11 and removing the first barrier layer 12 in S26 can be performed in the same process, for example, by removing the first dielectric layer 11 and the first barrier layer 12 in a single wet etching process. The first polysilicon layer 13 can serve as an etching stop layer for the wet etching process removing the first dielectric layer 11 and the first barrier layer 12. It should be noted that removing the first dielectric layer 11 and removing the first barrier layer 12 in S26 can also be performed in different processes, i.e., etching the first dielectric layer 11 first, and then etching the first barrier layer 12.

[0146] In the above steps, a wet etching process can be used to remove the first polysilicon layer 13, and the etching can be stopped at the second barrier layer 14 by selecting a predetermined etchant.

[0147] In the above steps, a wet etching process can be used to remove the second barrier layer 14, thereby exposing the portion of the channel structure 40 that extends into the first polysilicon layer 13.

[0148] In some embodiments, the etching rates of the materials of the second barrier layer 14 and the third dielectric layer 22 are similar. Thus, during the wet etching process to remove the second barrier layer 14, the third dielectric layer 22 is also removed. That is, the removal of the second barrier layer 14 and the removal of the third dielectric layer 22 can be performed in the same step, for example, by removing both the second barrier layer 14 and the third dielectric layer 22 in a single wet etching process. It should be noted that the removal of the second barrier layer 14 and the third dielectric layer 22 can also be performed in different steps, i.e., the second barrier layer 14 is etched first, followed by the third dielectric layer 22.

[0149] In some embodiments, the etching rates of the materials of the second barrier layer 14, the third dielectric layer 22, and the storage functional layer of the channel structure 40 are similar. Thus, during the wet etching process to remove the second barrier layer 14, the third dielectric layer 22 and the exposed portion of the storage functional layer of the channel structure 40 are also removed. That is, the removal of the second barrier layer 14, the removal of the third dielectric layer 22, and the removal of the exposed portion of the storage functional layer of the channel structure 40 can be performed in the same process, for example, by removing the second barrier layer 14, the third dielectric layer 22, and the exposed portion of the storage functional layer of the channel structure 40 in a single wet etching process to expose the semiconductor channel layer 44 of the channel structure 40. The exposed portion of the channel structure 40 is the portion of the channel structure 40 that extends beyond the second polysilicon layer 20 near the end of the substrate 10. It should be noted that the removal of the second barrier layer 14, the third dielectric layer 22 and the exposed portion of the channel structure 40 storage functional layer can also be carried out in different processes, i.e., first etch the second barrier layer 14, then etch the third dielectric layer 22, and finally etch the storage functional layer.

[0150] After exposing the semiconductor channel layer 44, as Figure 5 As shown, the preparation method also includes S27.

[0151] S27: As Figure 13 and Figure 14 As shown, the second polysilicon layer 20 is located away from the initial stacked structure 200 (see...). Figure 9 The source layer SL is formed on one side of the ).

[0152] In the above steps, the source layer SL is electrically connected to the semiconductor channel layer 44. During the formation of the source layer SL, a laser annealing process can be performed. After laser annealing, the second polysilicon layer 20 can serve as an interface layer, which can strengthen the bonding between the source layer SL and the stacked structure 30, and improve the delamination problem between them.

[0153] It should be noted that the source layer SL is made of semiconductor materials, such as single-crystal silicon, single-crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL can be partially or completely doped.

[0154] Please see Figure 14 and Figure 15 Some embodiments of this disclosure also provide a semiconductor structure 100, including a source layer SL, a second polysilicon layer 20, a fourth barrier layer 21, and a stacked structure 30.

[0155] The second polysilicon layer 20 is disposed on one side of the source layer SL. The stacked structure 30 is disposed on the side of the fourth barrier layer 21 away from the second polysilicon layer 20. The stacked structure 30 includes a plurality of alternately stacked second dielectric layers 31 and a plurality of gate layers 32.

[0156] In some embodiments, please refer to Figure 14 and Figure 15 The aforementioned semiconductor structure 100 further includes a channel structure 40 and a gate isolation structure 50. The channel structure 40 penetrates the stacked structure 30, the fourth barrier layer 21, and the second polysilicon layer 20, and extends into the source layer SL. The gate isolation structure 50 penetrates the stacked structure 30, the fourth barrier layer 21, and the second polysilicon layer 20, and extends into the source layer SL.

[0157] It should be noted that, as Figure 14 and Figure 15 As shown, the stacked structure 30 includes an array region CA and a step region SS. The step region SS can be located between the array regions CA or on the outer periphery of the array regions CA. The array region CA is used to form multiple memory cell strings 70. One end of each memory cell string 70 is connected to the source layer SL, and the other end is connected to the bit line BL. Each memory cell string 70 includes multiple memory cells. The step region SS is used to provide contacts to connect the word line connection line WL-CL and the string select line connection line SSL-CL.

[0158] In addition, the semiconductor structure 100 may further include a capping layer 60. The capping layer 60 may cover the portion of the semiconductor structure 100 located in the step region, thereby protecting the semiconductor structure 100. The material of the capping layer 60 may include an insulating material, such as one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0159] It should be noted that the materials of the source layer SL, the second polysilicon layer 20, the fourth barrier layer 21, the stacked structure 30, the channel structure 40, and the gate isolation structure 50 can all be referred to the above, and will not be repeated here.

[0160] Please see Figure 15 and Figure 16 Some embodiments of this disclosure also provide a semiconductor structure 100, including a substrate 10, a first dielectric layer 11, a first barrier layer 12, a first polysilicon layer 13, a second barrier layer 14, and a stacked structure 30.

[0161] The first dielectric layer 11 is disposed on one side of the substrate 10. A first barrier layer 12 is disposed on the side of the first dielectric layer 11 away from the substrate 10, and is configured to block oxide ions from passing through. A first polysilicon layer 13 is disposed on the side of the first barrier layer 12 away from the first dielectric layer 11. A second barrier layer 14 is disposed on the side of the first polysilicon layer 13 away from the first barrier layer 12, and is configured to block oxide ions from passing through. A stacked structure 30 is disposed on the side of the second barrier layer 14 away from the first polysilicon layer 13, and the stacked structure 30 includes a plurality of alternately stacked second dielectric layers 31 and a plurality of gate layers 32.

[0162] In some embodiments, please refer to Figure 15 and Figure 16 The semiconductor structure 100 further includes a channel structure 40 and a gate isolation structure 50, wherein the channel structure 40 penetrates the stacked structure 30 and the gate isolation structure 50 penetrates the stacked structure 30.

[0163] It should be noted that, as Figure 15 and Figure 16 As shown, the stacked structure 30 includes an array region CA and a step region SS. The step region SS can be located between the array regions CA or on the outer periphery of the array regions CA. The array region CA is used to form multiple memory cell strings 70. One end of each memory cell string 70 is connected to the source layer SL, and the other end is connected to the bit line BL. Each memory cell string 70 includes multiple memory cells. The step region SS is used to provide contacts to connect the word line connection line WL-CL and the string select line connection line SSL-CL.

[0164] In addition, the semiconductor structure 100 may further include a capping layer 60. The capping layer 60 may cover the portion of the semiconductor structure 100 located in the step region SS, thereby protecting the semiconductor structure 100. The material of the capping layer 60 may include an insulating material, such as one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, or other suitable materials.

[0165] It should be noted that the materials of the substrate 10, the first dielectric layer 11, the first barrier layer 12, the first polysilicon layer 13, the second barrier layer 14, the stacked structure 30, the channel structure 40, and the gate isolation structure 50 can all be referred to the above, and will not be repeated here.

[0166] In some embodiments, the semiconductor structure 100 further includes a third dielectric layer 22, a third barrier layer 23, a second polysilicon layer 20, and a fourth barrier layer 21.

[0167] The third dielectric layer 22 is disposed between the second barrier layer 14 and the stacked structure 30. The third barrier layer 23 is disposed between the third dielectric layer 22 and the stacked structure 30, and is configured to block oxide ions from passing through. The second polysilicon layer 20 is disposed between the third barrier layer 23 and the stacked structure 30. The fourth barrier layer 21 is disposed between the second polysilicon layer 20 and the stacked structure 30, and is configured to block oxide ions from passing through.

[0168] It should be noted that the materials of the third dielectric layer 22, the third barrier layer 23, the second polysilicon layer 20, and the fourth barrier layer 21 can all be referred to above, and will not be repeated here.

[0169] Please see Figure 17 and Figure 18 Some embodiments of this disclosure also provide a three-dimensional memory 300, which includes a semiconductor structure 100 and peripheral devices 400 as described in some embodiments above.

[0170] The semiconductor structure 100 may be, for example, a storage array device 500 used for storage in a three-dimensional memory 300. The storage array device 500 is electrically connected to the peripheral device 400 to enable the peripheral device 400 to support the functions of the storage array device 500, such as reading, writing and erasing data in the storage cells.

[0171] See Figure 15 In some embodiments, the storage array device 500 includes a storage cell string array 510 and an array interconnect layer 520 disposed on the side of the storage cell string array 510 near the peripheral device 400, and the storage cell string array 510 is electrically connected to the array interconnect layer 520.

[0172] In some embodiments, the peripheral device 400 includes a series of circuits 410 such as a page buffer, and a peripheral interconnect layer 420 disposed on the side of the series of circuits 410 close to the memory array device 500, the series of circuits 410 being electrically connected to the peripheral interconnect layer 420.

[0173] As can be seen from the above, the storage array device 500 and the peripheral device 400 can be electrically connected through the array interconnect layer 520 and the peripheral interconnect layer 420, thereby enabling the storage cell string array 510 to be electrically connected to a series of circuits 410.

[0174] Figure 19 This is a block diagram of a storage system 1000 according to some embodiments. Figure 20 This is a block diagram of a storage system 1000 according to some other embodiments. See also... Figure 19 and Figure 20Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller 500 and a three-dimensional memory 300 as described in some of the embodiments above, the controller 500 being coupled to the three-dimensional memory 300 to control the three-dimensional memory 300 to store data.

[0175] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones, desktop computers, laptop computers, tablet computers, vehicle computers, game consoles, printers, positioning devices, wearable electronic devices, smart sensors, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0176] In some embodiments, see Figure 19 The storage system 1000 includes a controller 500 and a three-dimensional memory 300, and the storage system 1000 can be integrated into a memory card.

[0177] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0178] In other embodiments, see Figure 20 The storage system 1000 includes a controller 500 and multiple three-dimensional storage devices 300, and the storage system 1000 is integrated into a solid state drive (SSD).

[0179] It is understood that the beneficial effects of the semiconductor structure 100, the three-dimensional memory 300 and the memory system 1000 provided in the above embodiments of this disclosure can be referred to the beneficial effects of the semiconductor structure preparation method described above, and will not be repeated here.

[0180] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A first dielectric layer is formed on the substrate; A first barrier layer is formed on the side of the first dielectric layer away from the substrate; A first polycrystalline silicon layer is formed on the side of the first barrier layer away from the substrate; A second barrier layer is formed on the side of the first polysilicon layer away from the substrate; An initial stacked structure is formed on the side of the second barrier layer away from the substrate; The initial stacked structure includes multiple alternating second dielectric layers and multiple sacrificial layers; Between forming the second barrier layer and forming the initial stacked structure, the following is also included: A third dielectric layer is formed on the side of the second barrier layer away from the substrate; A third barrier layer is formed on the side of the third dielectric layer away from the substrate; A second polysilicon layer is formed on the side of the third barrier layer away from the substrate; A fourth barrier layer is formed on the side of the second polysilicon layer away from the substrate.

2. The preparation method according to claim 1, characterized in that, Along a direction perpendicular to the substrate, the thickness of the first barrier layer is 1 nm to 5 nm; and / or, the thickness of the second barrier layer is 1 nm to 5 nm.

3. The preparation method according to claim 1, characterized in that, The formation of the first barrier layer includes: A first polycrystalline silicon thin film is formed on the side of the first dielectric layer away from the substrate; The first polycrystalline silicon thin film is treated with nitrogen-containing gas to form the first barrier layer.

4. The preparation method according to claim 1, characterized in that, The formation of the second barrier layer includes: The surface of the first polycrystalline silicon layer away from the substrate is treated with a nitrogen-containing gas to form the second barrier layer; Alternatively, a second polycrystalline silicon thin film may be formed on the side of the first polycrystalline silicon layer away from the substrate; The second polycrystalline silicon thin film is treated with a nitrogen-containing gas to form the second barrier layer.

5. The preparation method according to claim 1, characterized in that, The thickness of the third barrier layer is 1 nm to 5 nm; and / or, the thickness of the fourth barrier layer is 1 nm to 5 nm.

6. The preparation method according to claim 1, characterized in that, The formation of the third barrier layer includes: A third polycrystalline silicon thin film is formed on the side of the third dielectric layer away from the substrate; The third polycrystalline silicon thin film is treated with nitrogen-containing gas to form the third barrier layer.

7. The preparation method according to claim 1, characterized in that, The formation of the fourth barrier layer includes: The surface of the second polycrystalline silicon layer away from the substrate is treated with a nitrogen-containing gas to form the fourth barrier layer; Alternatively, a fourth polycrystalline silicon thin film may be formed on the side of the second polycrystalline silicon layer away from the substrate; The fourth polycrystalline silicon thin film is treated with nitrogen-containing gas to form the fourth barrier layer.

8. The preparation method according to any one of claims 1 to 7, characterized in that, After forming the initial stacked structure on the side of the second barrier layer away from the substrate, the method further includes: A channel structure is formed that penetrates the initial stacked structure and extends into the first polysilicon layer; Forming grid line gaps that penetrate the initial stacked structure; The sacrificial layer is removed through the grid line gaps to form a sacrificial gap; The polysilicon at the bottom of the sacrificial gap and the gate line slot is subjected to oxidation treatment; A gate layer is formed within the sacrificial gap; A grid line isolation structure is formed within the grid line gaps.

9. The preparation method according to claim 8, characterized in that, The channel structure forming the channel structure through the initial stacked structure includes: Forming a channel hole that penetrates the initial stacked structure; The polycrystalline silicon at the bottom of the channel hole is subjected to oxidation treatment; A channel structure is formed within the channel hole.

10. The preparation method according to claim 9, characterized in that, After forming the gate isolation structure, the method further includes: The substrate, the first dielectric layer, the first barrier layer, the first polysilicon layer, and the second barrier layer are removed sequentially to expose the portion of the channel structure that extends into the first polysilicon layer.

11. The preparation method according to claim 10, characterized in that, During the removal of the second barrier layer, the third dielectric layer is also removed.

12. The preparation method according to claim 11, characterized in that, The channel structure includes a memory functional layer and a semiconductor channel layer formed sequentially. During the removal of the third dielectric layer, the storage function layer of the exposed portion of the channel structure is also removed to expose the semiconductor channel layer. After exposing the semiconductor channel layer, the fabrication method further includes: A source layer is formed on the side of the second polysilicon layer away from the initial stacked structure, and the source layer is electrically connected to the semiconductor channel layer.

13. A semiconductor structure, characterized in that, include: Source layer; A second polysilicon layer is disposed on one side of the source layer; The second polysilicon layer is in contact with the source layer; A fourth barrier layer is disposed on the side of the second polysilicon layer away from the source layer; the fourth barrier layer is in contact with the second polysilicon layer; A stacked structure is disposed on the side of the fourth barrier layer away from the second polysilicon layer; the stacked structure includes a plurality of alternately stacked second dielectric layers and a plurality of gate layers; The channel structure penetrates the stacked structure, the fourth barrier layer, the second polysilicon, and extends into the source layer.

14. The semiconductor structure according to claim 13, characterized in that, The material of the fourth barrier layer includes silicon nitride or aluminum oxide.

15. A semiconductor structure, characterized in that, include: Base; A first dielectric layer is disposed on one side of the substrate; A first barrier layer is disposed on the side of the first dielectric layer away from the substrate; The first barrier layer is configured to block oxide ions from passing through; A first polysilicon layer is disposed on the side of the first barrier layer away from the first dielectric layer; The second barrier layer is disposed on the side of the first polysilicon layer away from the first barrier layer; A stacked structure is disposed on the side of the second barrier layer away from the first polysilicon layer; the stacked structure includes a plurality of alternately stacked second dielectric layers and a plurality of gate layers; A third dielectric layer is disposed between the second barrier layer and the stacked structure; A third barrier layer is disposed between the third dielectric layer and the stacked structure; A second polysilicon layer is disposed between the third barrier layer and the stacked structure; A fourth barrier layer is disposed between the second polysilicon layer and the stacked structure.

16. The semiconductor structure according to claim 15, characterized in that, The material of the first barrier layer includes silicon nitride or aluminum oxide; and / or, the material of the second barrier layer includes silicon nitride or aluminum oxide; and / or, the material of the third barrier layer includes silicon nitride or aluminum oxide; Alternatively, the material of the fourth barrier layer may include silicon nitride or aluminum oxide.

17. A three-dimensional memory, characterized in that, include: A semiconductor structure, wherein the semiconductor structure is prepared by the method for preparing the semiconductor structure according to any one of claims 1 to 12, or is the semiconductor structure according to any one of claims 13 to 16; Peripheral devices are electrically connected to the semiconductor structure.

18. A storage system, characterized in that, It includes a controller and a three-dimensional memory as described in claim 17, the controller being coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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