Three-dimensional memory and methods of making the same

Abstract

The application discloses a three-dimensional memory and a preparation method thereof, relates to the technical field of semiconductor chips, and aims to improve the reliability of a three-dimensional memory preparation process and the structural stability of the three-dimensional memory. The preparation method comprises the following steps: forming a stack structure on a substrate; the stack structure comprises alternatingly stacked dielectric layers and gate sacrificial layers. A first contact pillar is formed on the stack structure. A peripheral device is bonded to a side of the stack structure away from the substrate. The substrate is removed, and a gate line gap is formed from a side of the stack structure away from the peripheral device; the gate line gap penetrates through the stack structure. The gate sacrificial layers are removed via the gate line gap, and a gate line layer is formed; the gate line layer is electrically connected with the first contact pillar. The application is used for preparing a three-dimensional memory.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor chip technology, and in particular to a three-dimensional memory and its fabrication method. Background Technology

[0002] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit.

[0003] To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory with a three-dimensional structure (3D NAND), which increases storage density by arranging storage cells three-dimensionally on a substrate.

[0004] Improving the reliability of the 3D memory fabrication process and enhancing the structural stability of 3D memory are urgent problems to be solved. Summary of the Invention

[0005] The embodiments of this disclosure provide a three-dimensional memory and a method for fabricating the same, aiming to improve the reliability of the three-dimensional memory fabrication process and the structural stability of the three-dimensional memory.

[0006] To achieve the above objectives, the embodiments of this disclosure adopt the following technical solutions: On one hand, a method for fabricating a three-dimensional memory is provided. The method includes: forming a stacked structure on a substrate; the stacked structure including alternating dielectric layers and gate sacrificial layers; forming a first contact post on the stacked structure; bonding peripheral devices to the side of the stacked structure away from the substrate; removing the substrate and forming a gate wire gap from the side of the stacked structure away from the peripheral devices; the gate wire gap penetrating the stacked structure; removing the gate sacrificial layer through the gate wire gap and forming a gate wire layer; the gate wire layer being electrically connected to the first contact post.

[0007] The method for fabricating a three-dimensional memory provided in the above embodiments of this disclosure first fabricates a first contact post within a protective capping layer, and then fabricates a gate wire gap from the side of the stacked structure away from the peripheral devices. This increases the spacing between the first contact post and the gate wire gap, thereby increasing the size of the first contact post and the contact area between the first contact post and the gate wire layer. This facilitates accurate placement of the first contact post on the gate sacrificial layer and its electrical connection with the subsequently formed gate wire layer, improving the connection stability between the first contact post and the gate wire layer. After bonding the peripheral devices, forming the gate wire layer through the gate wire gap improves the alignment accuracy between the peripheral devices and the first contact post, reducing the difficulty of bonding the protective capping layer (first contact post) to the peripheral devices, improving the stability of the three-dimensional memory fabrication process, and enhancing the connection reliability between the peripheral devices and the first contact post. A first stop portion is formed on the side of the step away from the substrate. The first stop portion is configured as a stop layer for fabricating the first contact pillar. The thickness of the first stop portion can be adjusted as needed. Moreover, it is not necessary to use the gate line layer as a stop layer to fabricate the first contact pillar. In this way, during the formation of the gate line layer, only a gate line material of normal thickness (enough to fill the gap between the gate line layers formed by removing the gate sacrificial layer) needs to be deposited. It is not necessary to deposit a thicker gate line material at the connection between the gate line layer and the first contact pillar. This is beneficial to improve the opening size during the gate line material etch-back process and improve the uniformity of the gate line material etch-back process.

[0008] In some embodiments, the stacked structure has multiple steps. Prior to forming the first contact post, the fabrication method further includes: forming a channel structure that extends through the stacked structure; forming a first stop portion at the end of the step; and forming a protective capping layer covering the stacked structure and the first stop portion.

[0009] In some embodiments, the first stop portion is formed on the gate sacrificial layer of the step. During the formation of the first contact post on the stacked structure, a second contact post and the first stop portion are formed; the second contact post is electrically connected to the channel structure, and the gate line gap stops at the second stop portion.

[0010] In some embodiments, forming a first contact post, a second contact post, and a first stop portion includes: forming a first mask layer on the side of the protective capping layer away from the substrate; the first mask layer exposes areas in the protective capping layer where the first contact hole, the second contact hole, and the groove are to be formed. Based on the first mask layer, the protective capping layer is etched to form the first contact hole, the second contact hole, and the groove; the first contact hole penetrates the protective capping layer and extends into the interior of the first stop portion, or extends into a gate sacrificial layer below the first stop portion; the second contact hole penetrates the protective capping layer and extends into the channel structure; the groove is located within the protective capping layer. A first contact post is formed in the first contact hole, a second contact post is formed in the second contact hole, and an initial second stop portion is formed in the groove; wherein the second contact post is electrically connected to the channel structure.

[0011] In some embodiments, removing the gate sacrificial layer and the first stop portion via the gate wire gap to form a gate wire layer includes: removing the gate sacrificial layer and the first stop portion via the gate wire gap to form a first cavity; the first cavity includes a first sub-cavity located outside the step and a second sub-cavity located at the step; the size of the first sub-cavity is smaller than the size of the second sub-cavity in a direction perpendicular to the plane of the stacked structure. Gate wire material is filled into the first cavity to form a gate wire layer; the gate wire layer includes a gate wire body located in the first sub-cavity and a gate wire connection portion located in the second sub-cavity, the gate wire connection portion covering the second sub-cavity and forming a first gap; the gate wire connection portion is electrically connected to the first contact post.

[0012] In some embodiments, after forming the gate line layer, the fabrication method further includes: depositing a first predetermined material on the surface of the gate line connection portion within the first gap via the gate line slot; removing the first predetermined material covering the side of the stacked structure away from the peripheral device, and the first predetermined material covering the sidewalls and bottom of the gate line slot, to form a first protective layer covering the gate line connection portion; removing the gate line material covering the side of the stacked structure away from the peripheral device, and the gate line material covering the sidewalls and bottom of the gate line slot; forming a gate line isolation structure within the gate line slot; the material of the gate line isolation structure further fills the first gap.

[0013] In some embodiments, the first stop portion is formed on the dielectric layer of the step. Between forming the protective capping layer and forming the first contact post, the fabrication method further includes: forming a second contact post and a second stop portion; the second contact post is electrically connected to the channel structure, and the gate line gap stops at the second stop portion.

[0014] In some embodiments, forming the second contact post and the second stop portion includes: forming a first mask layer on the side of the protective capping layer away from the substrate; the first mask layer exposes the area in the protective capping layer where the second contact hole and groove are to be formed. Based on the first mask layer, the protective capping layer is etched to form the second contact hole and the groove; the second contact hole penetrates the protective capping layer and extends to the channel structure, and the groove is located within the protective capping layer. A second contact post is formed in the second contact hole, and an initial second stop portion is formed in the groove; wherein the second contact post is electrically connected to the channel structure.

[0015] In some embodiments, forming the first contact post includes: forming a second mask layer on the side of the first mask layer away from the substrate; the second mask layer exposing the area in the first mask layer to be formed of the first contact hole. Based on the second mask layer, etching the first mask layer and the protective capping layer to form a first contact hole extending to the first stop portion. Etching the first stop portion at the bottom of the first contact hole, such that the first contact hole extends to a dielectric layer below the first stop portion. Forming a second protective layer covering the inner wall of the first contact hole. Etching the second protective layer and the dielectric layer at the bottom of the first contact hole, such that the first contact hole extends to a gate sacrificial layer below the dielectric layer. Forming the first contact post within the first contact hole.

[0016] In some embodiments, the step of removing the gate sacrificial layer and the first stop portion via the gate wire gap and forming a gate wire layer includes: removing the gate sacrificial layer via the gate wire gap to form a second cavity, and removing the first stop portion to form a third cavity; the second cavity and the third cavity are separated by the dielectric layer. Gate wire material is deposited to form a gate wire layer within the second cavity; the inner wall of the third cavity is covered by the gate wire material.

[0017] In some embodiments, the size of the second cavity is smaller than the size of the third cavity in a direction perpendicular to the plane of the stacked structure. The inner wall of the third cavity is covered with gate wire material, forming a second gap. After forming the gate wire layer, the method further includes: removing the gate wire material covering the side of the stacked structure away from the peripheral device, and the gate wire material covering the sidewalls and bottom of the gate wire gap; and removing the gate wire material covering the inner wall of the third cavity via the second gap. A gate wire isolation structure is formed within the gate wire gap; the material of the gate wire isolation structure also fills the third cavity.

[0018] In some embodiments, the material of the second stop portion is the same as the gate wire material. During the removal of gate wire material covering the side of the stacked structure away from the peripheral device, and the gate wire material covering the sidewalls and bottom of the gate wire gaps, the portion of the second stop portion away from the peripheral device is removed.

[0019] In some embodiments, the material of the first stop portion is the same as the material of the gate sacrificial layer.

[0020] On the other hand, a three-dimensional memory is provided. The three-dimensional memory includes a source layer, a stacked structure, a first contact post, a second stop portion, a gate isolation structure, and peripheral devices. The stacked structure is disposed on the source layer and includes alternately stacked dielectric layers and gate layers. The first contact post is electrically connected to the gate layer. The second stop portion is disposed on the side of the stacked structure away from the source layer. The gate isolation structure penetrates the stacked structure, extending one end to the source layer and the other end to the second stop portion. The peripheral devices are disposed on the side of the stacked structure away from the source layer and are electrically connected to the first contact post.

[0021] The beneficial effects of the three-dimensional memory provided in the above embodiments of this disclosure can be referred to the beneficial effects of the three-dimensional memory preparation method described above, and will not be repeated here.

[0022] In some embodiments, the stacked structure has multiple steps. The three-dimensional memory further includes a fill pattern and a protective capping layer. The fill pattern is located above the steps or is part of the steps. The protective capping layer covers the stacked structure. The first contact post penetrates the protective capping layer and extends at least to the fill pattern; the second stop portion is disposed within the protective capping layer; the peripheral device is disposed on the side of the protective capping layer away from the source layer.

[0023] In some embodiments, the fill pattern is disposed on the grid layer of the step; the fill pattern is part of the step. The grid layer includes a grid body located outside the step and a grid connection portion located at the step, the grid connection portion being part of the fill pattern. The fill pattern also includes a fill portion, the grid connection portion surrounding the fill portion. The first contact post extends to the fill pattern and is electrically connected to the grid connection portion.

[0024] In some embodiments, the filling portion includes a first protective layer and the material of the gate line isolation structure. The first protective layer is disposed within the gap enclosed by the gate line connection portion. The material of the gate line isolation structure fills the gap enclosed by the first protective layer.

[0025] In some embodiments, along a direction perpendicular to the source layer, the end of the first contact post near the source layer includes a gate line connection portion, a first protective layer, and the material of the gate line isolation structure between them and the dielectric layer. Alternatively, along a direction perpendicular to the source layer, the end of the first contact post near the source layer includes a gate line connection portion and a first protective layer between them and the dielectric layer. Alternatively, along a direction perpendicular to the source layer, the end of the first contact post near the source layer includes a gate line connection portion between it and the dielectric layer.

[0026] In some embodiments, the fill pattern is disposed on the dielectric layer of the step; the fill pattern is located above the step. The material of the fill pattern includes the material of the gate isolation structure. The first contact post penetrates the fill pattern and the dielectric layer below the fill pattern, and is electrically connected to the gate layer.

[0027] In some embodiments, the three-dimensional memory further includes a second protective layer. The second protective layer at least covers the sidewalls of the portion of the first contact post that extends through the filling pattern. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly introduced below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below are schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0029] Figures 1A-1E This is a flowchart illustrating a method for fabricating a three-dimensional memory according to some embodiments; Figures 2A-2D This is a structural diagram of the three-dimensional memory fabrication process; Figures 3A to 3M This is a structural diagram of the three-dimensional memory fabrication process when the dielectric layer is close to the first stopping part. Figures 4A to 4N This is a structural diagram of the three-dimensional memory fabrication process when the gate sacrificial layer is close to the first stopping part. Figure 5 This is a structural diagram of a three-dimensional memory according to some embodiments; Figure 6A for Figure 5 A magnified view of a portion of A in the image; Figure 6B for Figure 5 Another magnified view of part A in the image; Figure 6C for Figure 5 Another magnified view of part A; Figure 7 This is a structural diagram of another three-dimensional memory according to some embodiments; Figure 8 This is a schematic diagram showing the outline shape of the grid isolation structure and the channel structure according to some embodiments; Figure 9 This is a block diagram of a storage system according to some embodiments; Figure 10 This is a block diagram of a storage system according to some other embodiments. Detailed Implementation

[0030] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0031] In the description of this disclosure, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0032] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "exemplary," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0033] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0034] In describing some embodiments, the terms "coupled" and "connected," and their derivative expressions, may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. Similarly, the term "coupled" may be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content of this document.

[0035] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0036] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0037] The use of “applies to” or “configured to” in this article implies an open and inclusive language that does not preclude applicability to or configuration to devices that perform additional tasks or steps.

[0038] In addition, the use of “based on” implies openness and inclusivity, because processes, steps, calculations or other actions “based on” one or more of the stated conditions or values ​​may in practice be based on additional conditions or values ​​beyond those stated.

[0039] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0040] In this disclosure, the meanings of “on,” “above,” and “above” should be interpreted in the broadest possible sense, such that “on” means not only “directly on” something, but also includes “on” something with intermediate features or layers in between, and “above” or “above” means not only “above” or “above” something, but also “above” or “above” something without intermediate features or layers in between (i.e., directly on something).

[0041] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0042] In the fabrication process of three-dimensional memory (such as 3D NAND), gate gaps are typically formed on the stacked structure first. The gate sacrificial layer is then removed through the gate gaps to form the gate layer. Then, the gate layer is used as a stop layer to form contact pillars that are electrically connected to the gate layer. After that, peripheral devices are bonded on the side of the contact pillars away from the contact pillars.

[0043] As the number of layers in a 3D memory stack increases, the area on the gate layer where the contact pillars connect needs to be thicker to ensure accurate extension of the contact pillars to the gate layer and electrical connection. Consequently, a thicker layer of gate material needs to be deposited during gate layer formation, resulting in a thicker layer of gate material adhering to the sidewalls of the gate gaps. This makes subsequent removal of the gate material adhering to the sidewalls of the gate gaps more difficult and may lead to poor uniformity of the removed gate material at different locations.

[0044] For example, removing more gate wire material near the opening of the gate wire gap may reduce the conductive channels of the channel structure closer to the gate wire isolation structure, causing a problem of high local resistance; removing less gate wire material near the bottom of the gate wire gap may leave gate wire material on the sidewall of the gate wire gap, thereby increasing the risk of electrical connection between gate wire layers.

[0045] To address the aforementioned problems, embodiments of this disclosure provide a method for fabricating a three-dimensional memory, see reference. Figure 1A The preparation method includes steps S100 to S600. Wherein, Figure 1A This is a flowchart of a method for fabricating a three-dimensional memory.

[0046] S100, see reference Figure 2A A stacked structure 20 is formed on the substrate 10.

[0047] In some embodiments, the material of the substrate 10 may include single-crystal silicon (Si), single-crystal germanium (Ge), gallium arsenide, indium phosphide, or III. Group V compound semiconductor materials, II The substrate 10 may be made of a group VI compound semiconductor material or at least one of other semiconductor materials known in the art, or it may also be made of a non-conductive material such as glass, plastic or sapphire wafer.

[0048] In some embodiments, before forming the stacked structure 20 on the substrate 10, the fabrication method may further include sequentially forming an insulating material sacrificial layer 101, a semiconductor sacrificial layer 102, a first etch stop layer 103, and a second etch stop layer 104 on the substrate 10. Thus, the stacked structure 20 is formed on the side of the second etch stop layer 104 away from the substrate 10 (e.g., Figure 2A (As shown).

[0049] The insulating material sacrificial layer 101 can be made of an insulating material, such as silicon oxide or silicon nitride. The semiconductor sacrificial layer 102 can be made of a semiconductor material, such as amorphous silicon, polycrystalline silicon, or a combination of one or more of monocrystalline silicon. The etching rate of the material of the first etch stop layer 103 is different from that of the material of the second etch stop layer 104, so that etching can stop at the interface between the two during subsequent etching processes. For example, the material of the first etch stop layer 103 may include silicon oxide; the material of the second etch stop layer 104 may include polycrystalline silicon.

[0050] In some embodiments, the aforementioned insulating material sacrificial layer 101, semiconductor sacrificial layer 102, first etch stop layer 103, and second etch stop layer 104 may be formed on the substrate 10 using a thin film deposition process. Exemplarily, the thin film deposition process may include one or more combinations of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0051] The stacked structure 20 is formed on the side of the second etch stop layer 104 away from the substrate 10.

[0052] In some embodiments, the stacked structure 20 includes alternately stacked dielectric layers 21 and gate sacrificial layers 22. That is, the stacked structure 20 includes multiple dielectric layers 21 and multiple gate sacrificial layers 22, which are alternately arranged along a direction perpendicular to the substrate 11 (first direction Z). Exemplarily, the film layer closest to the substrate 11 in the stacked structure 20 may be a dielectric layer 21.

[0053] In the embodiments of this disclosure, the number of layers in the stacked structure 20 is not limited. For example, the number of layers in the stacked structure can be 8, 64, 128, etc. The more layers in the stacked structure 20, the higher the integration of the three-dimensional memory, and the more memory cells it forms.

[0054] The material of dielectric layer 21 may include an insulating material. Insulating materials may be, for example, one or more combinations of silicon oxide, silicon nitride, silicon oxynitride, doped silicon oxide, organosilicon glass, dielectric metal oxides (e.g., aluminum oxide, hafnium dioxide, etc.) and their silicates, and organic insulating materials. The materials of each dielectric layer 21 may be the same or different. For example, each dielectric layer 21 may be made of the same material, and all may be silicon oxide.

[0055] The material of the gate sacrificial layer 22 may include an insulating material. The insulating material may be, for example, a combination of one or more of silicon nitride, silicon oxide, and silicon oxynitride. Exemplarily, the material of the gate sacrificial layer 22 may include silicon nitride.

[0056] It should be noted that the materials of the dielectric layer 21 and the gate sacrificial layer 22 are different, so that the etching rate of the dielectric layer 21 is different from that of the gate sacrificial layer 22. This allows the gate sacrificial layer 22 to be removed while the dielectric layer 21 is retained during the subsequent formation of the gate line layer. For example, the material of the dielectric layer 21 includes silicon oxide, and the material of the gate sacrificial layer 22 includes silicon nitride.

[0057] In some embodiments, a stacked structure 20 may be formed on the substrate 10 using a thin film deposition process. Exemplarily, the thin film deposition process may include one or more combinations of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0058] In some embodiments, see Figure 1B and Figure 1C After forming the stacked structure 20 on the substrate 10, the fabrication method also includes steps S110 to S150.

[0059] S110, forming a channel structure 30.

[0060] See Figure 2A The channel structure 30 penetrates the stacked structure 20, the second etch stop layer 104 and the first etch stop layer 103 in a direction Z perpendicular to the substrate 10, and extends into the semiconductor sacrificial layer 102.

[0061] See Figure 2A The channel structure 30 may include a high-k (dielectric constant) dielectric layer 31, a storage function layer and a semiconductor channel layer 33 arranged sequentially; the storage function layer includes a barrier layer 321, a charge storage layer 322 and a tunneling layer 323.

[0062] For example, forming the channel structure 30 may include forming a channel hole through an etching process, and then sequentially forming a high-k dielectric layer 31, a barrier layer 321, a charge storage layer 322, a tunneling layer 323, and a semiconductor channel layer 33 within the channel hole through a thin film deposition process. An air gap 34 may be formed within the semiconductor channel layer 33 to reduce the stress on the semiconductor channel layer 33.

[0063] In some embodiments, the high-k dielectric layer 31 may be made of a material with a high dielectric constant, such as aluminum oxide. The barrier layer 321, charge storage layer 322, tunneling layer 323, and semiconductor channel layer 33 may be made of silicon oxide, silicon nitride, silicon oxide, and polysilicon, respectively.

[0064] S120 forms multiple steps 201.

[0065] In some embodiments, multiple steps 201 can be formed on the stacked structure through multiple trim-etch cycles. Each step 201 includes a dielectric layer and a gate sacrificial layer 22; wherein, the dielectric layer 21 forming the step 201 may be closer to the substrate 10 than the gate sacrificial layer 22 (e.g., Figure 3A (as shown); or, the gate sacrificial layer 22 forming step 201 may be closer to the substrate 10 than the dielectric layer 21 (as shown). Figure 2A (As shown).

[0066] S130, see reference Figure 2B and Figure 2C A first stop portion 23 is formed at the end of step 201.

[0067] A first stop portion 23 is formed on each step 201, and the first stop portion 23 is located at the end of the step 201. In this way, there is a gap between the first stop portion 23 and the side wall of the step 201 adjacent to the step where the first stop portion 23 is located, that is, the multiple first stop portions 23 are separated from each other.

[0068] In some embodiments, the material of the first stop portion 23 may include silicon nitride. Exemplarily, the etching rate of the first stop portion 23 is the same as the etching rate of the gate sacrificial layer 22, so that the first stop portion 23 can be removed simultaneously during the subsequent removal of the gate sacrificial layer 22. Exemplarily, both the material of the first stop portion 23 and the material of the gate sacrificial layer 22 are silicon nitride.

[0069] It is understandable that when the dielectric layer 21 forming the step 201 is closer to the substrate 10 than the gate sacrificial layer 22, a first stop portion 23 can be formed on the gate sacrificial layer 22 of the step 201 (e.g., Figure 3A(As shown). When the gate sacrificial layer 22 of the stepped 201 is closer to the substrate 10 than the dielectric layer 21, a first stop portion 23 can be formed on the dielectric layer 21 of the stepped portion (as shown). Figure 2C ).

[0070] In some embodiments, forming a first stop portion 23 at the end of step 201 in step S130 may include steps S131 and S132. See also Figure 2B and Figure 2C Taking the gate sacrificial layer 22 that forms the step 201 as being closer to the substrate 10 than the dielectric layer 21 as an example, the process of forming the first stop portion 23 will be explained.

[0071] S131, see also Figure 2B A first stop layer 23' is formed on the side of the stacked structure 20 away from the substrate 10.

[0072] The first stop layer 23' covers the upper surface of the stacked structure 20, the upper surface of the step 201, and the sidewall of the step 201.

[0073] For example, the first stop layer 23' can be formed by a thin film deposition process.

[0074] In some embodiments, the thickness of the first stop portion 23 may be less than the thickness of the gate sacrificial layer 22. This reduces the size of the subsequently formed second sub-cavity, thereby reducing the amount of gate line material and gate line filling structure consumed.

[0075] S132, see S132. Figure 2C The portion of the first stop layer 23' covering the surface of the stacked structure 20 and the portion of the first stop layer 23' covering the sidewalls of the multiple steps 201 are removed to form multiple separately arranged first stop portions 23.

[0076] For example, the aforementioned portion of the first stop layer 23' can be removed by an etching process (dry etching or wet etching).

[0077] S140, see S140. Figure 2D This forms a protective cover layer 24 that covers the stacked structure 20 and the first stop portion 23.

[0078] in, Figure 2D Taking the gate sacrificial layer 22 forming the step 201 as being closer to the substrate 10 than the dielectric layer 21, the aforementioned protective capping layer 24 is formed.

[0079] See Figure 2D The protective cover 24 fills the gap between the first stop portion 23 and the side wall of the step 201 adjacent to it, for example... Figure 2DThe gap between the first stop portion 23 and the sidewall of the step 201 on its right side; and the protective capping layer 24 covers the step 201 and the upper surface of the stacked structure 20. The surface of the protective capping layer 24 away from the substrate 10 is flat or substantially flat.

[0080] The protective capping layer 24 includes an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more high-dielectric-constant insulating materials, or other suitable materials. Furthermore, the etching rate of the material of the protective capping layer 24 differs from the etching rate of the material of the first stop portion 23, so that etching can stop at the interface between the two. Exemplarily, the material of the first stop portion 23 includes silicon nitride; the material of the protective capping layer 24 includes silicon oxide.

[0081] In some embodiments, after forming a protective capping layer 24 covering the stacked structure 20 and the first stop portion 23, the preparation method may further include S150.

[0082] S150, see reference Figure 2D A virtual channel structure 29 is formed in the area where step 201 is located.

[0083] The virtual channel structure 29 is configured to provide mechanical support for the stacked structure 20. Exemplarily, the virtual channel structure 29 may extend through the stacked structure 20 in a direction perpendicular to the substrate 10 and into the substrate 10. The virtual channel structure 29 may include an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high-dielectric-constant insulating materials, or other suitable materials.

[0084] It is immediately apparent that in the other drawings of the embodiments disclosed herein (except for...) Figure 2D Other figures (excluding those shown in the attached figures) do not depict the virtual channel structure 29 for the sake of brevity.

[0085] S200, a first contact post 40 is formed on the stacked structure 20.

[0086] The first contact post 40 penetrates the protective capping layer 24 and extends at least to the first stop portion 23, so that the first contact post 40 can be electrically connected to the subsequently formed grid line layer 28.

[0087] In some embodiments, when the dielectric layer 21 forming the step 201 is closer to the substrate 10 than the gate sacrificial layer 22, and a first stop portion 23 is formed on the gate sacrificial layer 22 of the step 201 (e.g.) Figure 3A As shown), the first contact post 40 penetrates the protective cap 24 and extends to the first stop portion 23, or the first contact post 40 penetrates the protective cap 24 and the first stop portion 23 and extends into the gate sacrificial layer 22 forming the step 201 (as shown). Figure 3D (As shown).

[0088] The first contact post 40 and the second contact post 60 penetrate the same film layer (protective capping layer 24), and the first contact post 40 and the second contact post 60 can be formed simultaneously. The second stop portion 50 is configured to be electrically connected to the channel structure 30. The second stop portion 50 can be embedded within the protective capping layer 24, so that the second stop portion 50 can also be formed simultaneously with the first contact post 40 and the second contact post 60. Therefore, during the formation of the first contact post 40 on the stacked structure 20, the second contact post 60 and the second stop portion 50 are also formed simultaneously. The second contact post 60 penetrates the protective capping layer 24 and is electrically connected to the semiconductor channel layer 33 of the channel structure 30. The second stop portion 50 is configured as a stop layer for subsequent formation of gate line gaps.

[0089] See Figure 1B After a virtual channel structure 29 is formed in the area where step 201 is located, a first contact post 40, a second contact post 60, and a second stop portion 50 are formed on the stacked structure 20. (See also...) Figure 1D S200, a first contact post 40, a second contact post 60 and a second stop portion 50 are formed on the stacked structure 20, including S210~S230.

[0090] S210, see reference Figure 3B A mask layer 25 is formed on the side of the protective capping layer 24 away from the substrate 10.

[0091] The mask layer 25 exposes the area 40' of the protective capping layer 24 where the first contact post 40 is to be formed, the area 60' of the second contact post 60 is to be formed, and the area 50' of the second stop portion 50 is to be formed.

[0092] In some embodiments, the material of the mask layer 25 includes an insulating material, and the etching rate of the material of the mask layer 25 is different from the etching rate of the material of the protective capping layer 24, so that etching can stop at the interface between the two. Exemplarily, the material of the mask layer 25 may include one or more of semiconductor materials (e.g., single-crystal silicon), high-k materials (e.g., alumina), or other insulating materials different from those of the protective capping layer 24.

[0093] For example, an initial mask layer covering the protective capping layer 24 can be formed by a thin film deposition process, and a portion of the initial mask layer can be removed by an etching process to expose the region 40' to be formed of the first contact post, the region 60' to be formed of the second contact post 60, and the region 50' to be formed of the second stop portion 50, thereby forming the mask layer 25.

[0094] S220, see S220. Figure 3C Based on the mask layer 25, the protective capping layer 24 is etched to form the first contact hole 41, the second contact hole 61, and the groove 51.

[0095] The first contact hole 41 extends to the first stop portion 23 or to the gate sacrificial layer 22 below the first stop portion 23 (on the side closer to the substrate 11). The second contact hole 61 penetrates the protective capping layer 24 and exposes at least a portion of the semiconductor channel layer 33 of the channel structure 30. The recess 51 is located within the protective capping layer 24.

[0096] For example, the first contact hole 41 may extend entirely to the first stop portion 23, or extend entirely to the gate sacrificial layer 22 below the first stop portion 23, or a portion of the first contact hole 41 may extend to the first stop portion 23; a portion of the first contact hole 41 may extend to the gate sacrificial layer 22 below the first stop portion 23.

[0097] S230, see S230. Figure 3D A first contact post 40 is formed in the first contact hole 41, a second contact post 60 is formed in the second contact hole 61, and a second stop portion 50 is formed in the groove 51.

[0098] The materials of the first contact post 40, the second contact post 60, and the second stop portion 50 can be the same, and the materials of the first contact post 40, the second contact post 60, and the second stop portion 50 can all include conductive materials. For example, the conductive material can be one or more combinations of tungsten, cobalt, copper, aluminum, doped silicon, and silicides.

[0099] For example, the first contact post 40 and the second contact post 60 can be formed simultaneously using a thin film deposition process. In the embodiments of this disclosure, simultaneously forming the first contact post 40, the second stop portion 50, and the second contact post 60 can simplify the fabrication process of the three-dimensional memory and reduce the difficulty of fabricating the three-dimensional memory.

[0100] In some embodiments, when the gate sacrificial layer 22 forming the step 201 is closer to the substrate 10 than the dielectric layer 21, and a first stop portion 23 is formed on the dielectric layer 21 of the step 201 (e.g.) Figure 4A (As shown). The first contact post 40 penetrates the first stop portion 23 of the protective cap layer 24 and the dielectric layer 21 forming the step 201, and extends into the gate sacrificial layer 22 forming the step 201 (as shown). Figure 4I (As shown).

[0101] Thus, the first contact post 40, the second stop part 50, and the second contact post 60 (which only need to pass through the protective cover layer 24 to be electrically connected to the channel structure 30) need to pass through different membrane structures. Therefore, the first contact post 40, the second stop part 50, and the second contact post 60 can be formed through different processes, that is, the first contact post 40, the second stop part 50, and the second contact post 60 are not formed simultaneously in the same step.

[0102] In some embodiments, see Figure 1C Between the formation of the virtual channel structure 29 (S150) and the formation of the first contact post 40 (S200) in the area where step 201 is located, the preparation method may further include S160, forming the second contact post 60 and the second stop portion 50. (See also...) Figure 1E S200 forms the first contact post 40, including S210' to S230'.

[0103] S160, forming a second contact post 60 and a second stop portion 50.

[0104] For example, see Figure 1E The above-mentioned S160 forms a second contact post 60 and a second stop portion 50, and may include S161 to S163.

[0105] S161, see S161. Figure 4A A first mask layer 26 is formed on the side of the protective capping layer 24 away from the substrate 10.

[0106] The first mask layer 26 exposes the region 60' of the protective capping layer 24 where the second contact post 60 is to be formed and the region 50' of the second stop portion 50 is to be formed.

[0107] In some embodiments, the material of the first mask layer 26 includes an insulating material, and the etching rate of the material of the first mask layer 26 is different from the etching rate of the material of the protective capping layer 24, so that etching can stop at the interface between the two. Exemplarily, the material of the first mask layer 26 may include one or more of semiconductor materials (e.g., single-crystal silicon), high-k materials (e.g., alumina), or other insulating materials different from those of the protective capping layer 24.

[0108] For example, an initial first mask layer covering the protective capping layer 24 can be formed by a thin film deposition process, and a portion of the initial first mask layer can be removed by an etching process, so that the initial first mask layer exposes the region 60' to be formed of the second contact hole 61 and the region 50' to be formed of the second stop portion 50, thereby forming the first mask layer 26.

[0109] S162, see S162. Figure 4B Based on the first mask layer 26, the protective capping layer 24 is etched to form the second contact hole 61 and the groove 51.

[0110] The second contact hole 61 penetrates the protective capping layer 24 and exposes at least a portion of the semiconductor channel layer 33 of the channel structure 30. The groove 51 is located within the protective capping layer 24.

[0111] S163, see S163. Figure 4C A second contact post 60 is formed in the second contact hole 61, and a second stop portion 50 is formed in the groove 51.

[0112] The material of the second contact post 60 may include a conductive material. For example, the material of the second contact post 60 may include one or more combinations of tungsten, cobalt, copper, aluminum, doped silicon, and silicides. The second contact post 60 is electrically connected to the semiconductor channel layer 33 of the channel structure 30.

[0113] See Figure 1E After the second contact post 60 and the second stop part 50 are formed, the first contact post 40 is formed in S200, which may include S210' to S230'.

[0114] S210', see Figure 4D A second mask layer 27 is formed on the side of the first mask layer 26 away from the substrate 10.

[0115] The second mask layer 27 exposes the area 26' on the first mask layer 26 covered by the protective capping layer 24, where the first contact post 40 is to be formed.

[0116] In some embodiments, the material of the second mask layer 27 includes an insulating material, and the etching rate of the material of the second mask layer 27 is different from that of the material of the first mask layer 26 (i.e., the materials are different) so that etching can stop at the interface between the two. Exemplarily, the material of the second mask layer 27 may include one or more of a semiconductor material (e.g., single-crystal silicon), a high-k material (e.g., alumina), or other insulating materials different from the protective capping layer 24 (e.g., silicon oxide). For example, the material of the first mask layer 26 includes alumina, and the material of the second mask layer 27 includes polycrystalline silicon.

[0117] For example, an initial second mask layer covering the first mask layer 26 can be formed by a thin film deposition process, and a portion of the initial second mask layer can be removed by an etching process, so that the initial second mask layer exposes the area 26' on the first mask layer 26 covered by a protective capping layer to be formed of the first contact hole 41, thereby forming the second mask layer 27.

[0118] S220', see Figures 4E to 4H Based on the second mask layer 27, the first contact hole 41 is etched to form.

[0119] See Figure 4H The first contact hole 41 penetrates the first mask layer 26, the protective capping layer 24, the first stop portion 23 and the dielectric layer 21 forming the step 201, and extends to the gate sacrificial layer 22 forming the step 201.

[0120] In some embodiments, the etching process in S220' to form the first contact hole 41 may include S221 to S224.

[0121] S221, see S221. Figure 4EA first contact hole 41 is formed based on the second mask layer 27, penetrating the protective cover layer 24 and extending to the first stop portion 23.

[0122] S222, see S222. Figure 4F The bottom of the first contact hole 41 is etched so that the first contact hole 41 extends to the dielectric layer 21 below the first stop portion 23.

[0123] S223, see S223. Figure 4G A second protective layer 42 is formed on the sidewall and bottom wall of the first contact hole 41 formed in S452.

[0124] The material of the second protective layer 42 includes an insulating material. For example, the material of the second protective layer 42 may include silicon oxide.

[0125] S224, see S224. Figure 4H The second protective layer 42 is etched to cover a portion of the bottom wall of the first contact hole 41 (the first contact hole 41 formed by S453) and the dielectric layer 21, so that the first contact hole 41 extends to the gate sacrificial layer 22 below the dielectric layer 21.

[0126] S230', see Figure 4I A first contact post 40 is formed in the first contact hole 41 (the first contact hole 41 formed by S454).

[0127] In the above preparation method, the second stop part 50 and the second contact post 60 are made of the same material and are formed simultaneously. In this way, the second stop part 50 can be formed using existing preparation processes, which helps to simplify the preparation process of the three-dimensional memory and reduce the adverse effects on the preparation process of the three-dimensional memory.

[0128] It should be understood that in other embodiments, the second stop portion 50 may also be formed by other methods.

[0129] For example, the second stop portion 50 may be located on the side of the protective capping layer 24 away from the substrate 10; that is, the second stop portion 50 may be formed on the side of the protective capping layer 24 away from the substrate 10 by adding a process. The second stop portion 50 may be a solid layer structure. Alternatively, the second stop portion 50 may be a patterned film layer structure; that is, the second stop portion 50 may be disposed in the region configured to form gate line gaps.

[0130] For example, if the dielectric layer 21 forming the step 201 is closer to the substrate 10 than the gate sacrificial layer 22, and a first stop portion 23 is formed on the gate sacrificial layer 22 of the step 201, an initial stop layer (a whole-layer structure covering the surface of the protective capping layer 24) can be formed before S210, and a second stop portion 50 can be formed from this initial stop layer. In this way, the second stop portion 50 can be a whole-layer structure, or the second stop portion 50 can be a structure formed by patterning the initial stop layer.

[0131] For example, the mask layers (one or more of mask layer 25, first mask layer 26, and second mask layer 27) used in the process of forming the first contact post 40 and / or the second contact post 60 can also be reused as the second stop portion 50. In this way, the manufacturing process of the three-dimensional memory can be reduced, and the manufacturing cost of the three-dimensional memory can be lowered.

[0132] For example, see Figure 3E In the case where the dielectric layer 21 forming the step 201 is closer to the substrate 10 than the gate sacrificial layer 22, and a first stop portion 23 is formed on the gate sacrificial layer 22 of the step 201, the fabrication method includes forming a mask layer 25, and a portion 25' of the mask layer 25 can be reused as a second stop portion 50.

[0133] Alternatively, for example, if the gate sacrificial layer 22 forming the step 201 is closer to the substrate 10 than the dielectric layer 21, and a first stop portion 23 is formed on the dielectric layer 21 of the step 201, the fabrication method includes forming a first mask layer 26 and a second mask layer 27. A portion of the first mask layer 26 and / or a portion of the second mask layer 27 can be reused as the second stop portion 50.

[0134] In some embodiments, after forming the first contact post 40, the second contact post 60, and the second stop portion 50, the preparation method further includes S290.

[0135] S290, see S290. Figure 3F and Figure 4I , forming an array interconnect layer 35.

[0136] The array interconnect layer 35 can be electrically connected to the second contact post 60. The array interconnect layer 35 may include one or more first interlayer insulating layers 351 and one or more first interconnect conductor layers 352. The first interlayer insulating layer 351 is made of an insulating material, such as silicon oxide, silicon nitride, and a combination of one or more high-dielectric-constant insulating materials, or other suitable materials. The first interconnect conductor layer 352 is made of a conductive material, such as tungsten, cobalt, copper, aluminum, and a combination of one or more metal silicides, or other suitable materials.

[0137] The first interconnect conductor layer 352 may include multiple contacts and multiple connection lines. For example, the first interconnect conductor layer 352 includes a bit line BL and a word line connection line WL-CL (not shown in the figure) coupled to the word line WL.

[0138] S300, see reference Figure 3G and Figure 4J Peripheral devices 70 are bonded on the side of the stacked structure 20 away from the substrate 10.

[0139] Peripheral device 70 may include peripheral circuitry. The peripheral circuitry is configured to control and sense the array device. The peripheral circuitry may be any suitable digital, analog, and / or mixed-signal control and sensing circuitry used to support the operation (or function) of the array device, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuitry may also include any other circuitry compatible with advanced logic processes, including logic circuitry (e.g., processors and programmable logic devices (PLDs)) or memory circuitry (e.g., static random-access memory (SRAM)).

[0140] In some embodiments, see Figure 3G The peripheral device 70 may include a substrate 71, a transistor 72 disposed on the substrate 71, and a peripheral interconnect layer 73 disposed on the substrate 71. The peripheral circuit may include a transistor 120.

[0141] The substrate 71 can be made of single-crystal silicon or other suitable materials, such as silicon-germanium, germanium or silicon-on-insulator thin film.

[0142] The peripheral interconnect layer 73 is coupled to the transistor 72 to transmit electrical signals between the transistor 72 and the peripheral interconnect layer 73. The peripheral interconnect layer 73 may include one or more second interlayer insulating layers 731, and may also include one or more second interconnect conductor layers 732. Different second interconnect conductor layers 732 may be coupled to each other via contacts. The materials of the second interconnect conductor layers 732 and the contacts may be conductive materials, such as tungsten, cobalt, copper, aluminum, and combinations of one or more metal silicides, or other suitable materials. The material of the second interlayer insulating layer 731 is an insulating material, such as silicon oxide, silicon nitride, and combinations of one or more high dielectric constant insulating materials, or other suitable materials.

[0143] The peripheral interconnect layer 73 can be coupled to the array interconnect layer 35. Specifically, since the peripheral interconnect layer 73 is coupled to the array interconnect layer 35, the peripheral circuits in the peripheral device 70 can be coupled to the memory cell string (channel structure 30) in the stacked structure 20 to realize the transmission of electrical signals between the peripheral circuits and the memory cell string. In some possible implementations, an adhesive interface can be provided between the peripheral interconnect layer 73 and the array interconnect layer 35, through which the peripheral interconnect layer 73 and the array interconnect layer 35 can be bonded and coupled to each other.

[0144] S400, see reference Figure 3H and Figure 4J Remove the substrate 10 and form a gate gap 80 from the side of the stacked structure 20 away from the peripheral device 70.

[0145] The gate line gap 80 extends through the stacked structure 20 in a direction Z perpendicular to the substrate 71 and stops at the second stop portion 50.

[0146] For example, the gate gap 80 can be formed by an etching process.

[0147] S500, see S500 Figures 3I to 3L ,and Figures 4K to 4M The gate sacrificial layer 22 is removed through the gate line gap 80, and the gate line layer 28 is formed.

[0148] The grid layer 28 is electrically connected to the first contact post 40.

[0149] In some embodiments, when a first stop portion 23 is formed on the gate sacrificial layer 22 of the step 201, that is, when the gate sacrificial layer 22 forming the step 201 is closer to the first stop portion 23 than the dielectric layer 21, S500 removes the gate sacrificial layer 22 and the first stop portion 23 through the gate line gap 80 and forms the gate line layer 28, including S510 to S530.

[0150] S510, see S510. Figure 3I The gate sacrificial layer 22 and the first stop portion 23 are removed through the gate line gap 80 to form the first cavity 81.

[0151] Since the gate sacrificial layer 22 is adjacent to the first stop portion 23, and both are removed simultaneously, therefore, along the direction Z (perpendicular to the plane of the stacked structure 20) Figure 3I The thickness of the first cavity 81 formed in the vertical direction at step 201 is greater than the thickness of the first cavity 81 in the area outside step 201.

[0152] The first cavity 81 includes a first sub-cavity 811 located outside the step 201 and a second sub-cavity 812 located at the step 201. Along the direction Z perpendicular to the plane of the stacked structure 20, the size of the first sub-cavity 811 is smaller than the size of the second sub-cavity 812.

[0153] After removing the gate sacrificial layer 22 and the first stop portion 23 to form the first cavity 81, the stacked structure 20 may be subjected to stress. The three-dimensional memory fabrication method provided in this disclosure first bonds the peripheral device 70 to the peripheral device 70, and then forms the first cavity 81. This reduces the alignment difficulty between the peripheral device 70 and the first contact post 40, and also reduces the difficulty of bonding the peripheral device 70. This improves the stability of the three-dimensional memory fabrication process.

[0154] S520, see S520. Figure 3J The first cavity 81 is filled with grid line material to form grid line layer 28.

[0155] The grid layer 28 includes a grid body 281 located in the first sub-cavity 811 and a grid connection portion 282 located in the second sub-cavity 812. The grid connection portion 282 covers the second sub-cavity 812 and forms a first gap 813. The grid connection portion 282 is electrically connected to the first contact post 40.

[0156] The method for fabricating a three-dimensional memory provided in this embodiment first forms a first contact post 40, and then forms a gate line layer 28. It is not necessary to form a first contact hole 41 using the gate line layer 28 as an etch stop layer, i.e., it is not necessary to form a thick gate line material within the second sub-cavity 812. Therefore, it is only necessary to fill the first cavity 81 with a gate line material of normal thickness, ensuring the gate line material completely fills the first sub-cavity 811. In this way, the gate line connection portion 282 only covers the sidewall of the second sub-cavity 812, and a first gap 813 is formed within the gate line connection portion 282 (e.g., ...). Figure 3J (As shown).

[0157] In some embodiments, the gate wire material may include one or more combinations of tungsten, cobalt, copper, aluminum, doped silicon, and silicides. Exemplarily, the gate wire material is the same as the material of the first contact post 40 and the second contact post 60, and both are metallic tungsten.

[0158] For example, gate line material can be deposited using a thin film deposition process.

[0159] It should be understood that the gate material also covers the sidewalls and bottom wall (283) of the gate gap 80, as well as the surface of the stacked structure 20 away from the peripheral device 70 (284).

[0160] In the embodiments of this disclosure, the first contact post 40 is formed first, and then the gate line layer 28 is formed. It is not necessary to use the gate line connection portion 282 as a stop layer to etch the first contact hole 41. Therefore, only a gate line material of normal thickness (enough to fill the first sub-cavity 811) needs to be deposited. This reduces the thickness of the gate line material covering the sidewalls of the gate line slot 80. In the subsequent process of removing the gate line material covering the sidewalls and bottom of the gate line slot 80 in S540, the opening size of the gate line slot 80 can be increased, allowing the etching solution to fully contact the gate line material on the sidewalls and bottom of the gate line slot 80, thus improving the uniformity of the etching process.

[0161] S530, see S530. Figure 3K and Figure 3L Within the first gap 813, a first protective layer 285 is formed to cover the grid line connection portion 282.

[0162] The first protective layer 285 can prevent the grid wire connection portion 282 from being removed during the subsequent removal of grid wire material in S540.

[0163] For example, S530 may include S531 and S532.

[0164] S531, see S531. Figure 3K A first preset material is deposited on the surface of the grid line connection portion 282 within the first gap 813 via the grid line gap 80.

[0165] The first preset material also covers the surface of the stacked structure 20 away from the peripheral device 70, as well as the sidewalls and bottom of the grid gap 80.

[0166] For example, a first preset material can be deposited on the surface of the gate line connection portion 282 within the first gap using a thin film deposition process.

[0167] S532, see S532. Figure 3L The first preset material 287 covering the side of the stacked structure 20 away from the peripheral device 70, and the first preset material 286 covering the sidewall and bottom of the gate wire gap 80 are removed to form a first protective layer 285 covering the gate wire connection portion 282.

[0168] That is, a first initial protective layer is first formed, which covers the sidewalls of the first gap 813, the sidewalls and bottom wall of the gate line gap 80, and the surface of the stacked structure 20 away from the peripheral device 70. Then, the portion of the first initial protective layer covering the sidewalls and bottom wall of the gate line gap 80 and the surface of the stacked structure 20 away from the peripheral device 70 can be removed by an etching process, leaving the portion of the first initial protective layer covering the gate line connection portion 282, to form the first protective layer 285.

[0169] The etching rate of the material of the first protective layer 285 is different from that of the gate line material, so that the first protective layer 285 is not removed during the subsequent removal of part of the gate line material. This avoids the removal of the gate line material located in the second sub-cavity 812. For example, the material of the first protective layer 285 may include silicon oxide.

[0170] Depending on the size of the first gap 813, the first protective layer 285 can fill the first gap 813; or, the first protective layer 285 can also form a third gap 284 (e.g., Figure 3L (As shown).

[0171] S540, see S540. Figure 3L Remove the gate line material from the side of the stacked structure 20 away from the peripheral device 70. Figure 3J 283 in the middle), and the grid material covering the sidewalls and bottom of the grid gap 80 (in the middle). Figure 3J (284 in the middle).

[0172] In some embodiments, when the material of the second stop portion 50 is the same as the material of the second contact post 60 and is embedded within the protective cover layer 24, during the process of removing the grid wire material covering the side of the stacked structure 20 away from the peripheral device 70, and the grid wire material covering the sidewalls and bottom of the grid wire gap 80, a portion of the material of the second stop portion 50 (such as...) is also removed. Figure 3L (As shown).

[0173] In some embodiments, taking the second stop portion 50 as an example, when the second stop portion 50 is disposed on the side of the protective capping layer 24 and the second contact post 60 away from the substrate 10, the second stop portion 50 is exposed in the gate wire gap 80 during the process of removing the gate wire material covering the side of the stacked structure 20 away from the peripheral device 70, and the gate wire material covering the sidewalls and bottom of the gate wire gap 80.

[0174] In some embodiments, when the dielectric layer 21 forming the step 201 is closer to the first stop portion 23 than the gate sacrificial layer 22, S500 removes the gate sacrificial layer 22 and the first stop portion 23 via the gate line gap 80 and forms the gate line layer 28, including S510' to S530'.

[0175] S510', see Figure 4K The gate sacrificial layer 22 is removed through the gate line gap 80 to form a second cavity 82, and the first stop portion 23 is removed to form a third cavity 83.

[0176] The etching rate of the material of the gate sacrificial layer 22 is the same as that of the material of the first stop portion 23. For example, both materials are silicon nitride.

[0177] The gate line gap 80 contacts the gate sacrificial layer 22 and the first stop portion 23. Exemplarily, the first stop portion 23 is removed simultaneously during the process of removing the gate sacrificial layer 22 by a wet etching process.

[0178] In some embodiments, the thickness of the first stop portion 23 is greater than the thickness of the gate sacrificial layer 22 along the direction Z perpendicular to the substrate 71. This facilitates stopping the etching at the first stop portion 23, reducing the risk that the first contact hole 41 may penetrate the first stop portion 23 during the formation of the first contact hole 41 (S221). Since the thickness of the first stop portion 23 is greater than the thickness of the gate sacrificial layer 22, the size of the third cavity 83 is greater than the size of the second cavity 82 along the direction Z perpendicular to the stacked structure 20.

[0179] The second cavity 82 and the third cavity 83 are separated by the dielectric layer 21.

[0180] S520', see Figure 4L A grid line material is deposited to form a grid line layer 28 within the second cavity 82. Simultaneously, the sidewalls of the third cavity 83 are covered with the grid line material, forming a second gap 831.

[0181] Since the portion of the first contact post 40 located within the third cavity 83 is covered by the second protective layer 42, the material of the first contact post 40 will not be removed during the subsequent removal of the gate line material. Therefore, whether the third cavity 83 is completely filled with gate material does not affect the electrical connection between the first contact post 40 and the gate line layer 28. Thus, during the deposition of the gate line material, only a gate line material of normal thickness needs to be deposited (the gate line material fills the second cavity 82). Based on this, the third cavity 83 may not be completely filled with gate line material, thereby forming a second gap 831 within the gate line material of the third cavity 83.

[0182] In some embodiments, the gate wire material may include one or more combinations of tungsten, cobalt, copper, aluminum, doped silicon, and silicides. Exemplarily, the gate wire material is the same as the material of the first contact post 40 and the second contact post 60, and both are metallic tungsten.

[0183] For example, gate line material can be deposited using a thin film deposition process.

[0184] It should be understood that the gate line material also covers the sidewalls and bottom wall of the gate line gap 80, as well as the surface of the stacked structure 20 away from the peripheral device 70.

[0185] It should be noted that the material deposited within the third cavity 83 does not affect the functionality of the final 3D memory; therefore, there is no need to install a partition to protect the material deposited within the third cavity 83. This reduces the fabrication process of the 3D memory and lowers its manufacturing cost.

[0186] S530', see Figure 4M The gate wire material covering the side of the stacked structure 20 away from the peripheral device 70, as well as the gate wire material covering the sidewalls and bottom of the gate wire gap 80, is removed. Furthermore, the gate wire material covering the inner wall of the third cavity 83 is removed via the second gap 831.

[0187] In some embodiments, see Figure 4M When the material of the second stop portion 50 is the same as the material of the second contact post 60 and is embedded in the protective cover layer 24, in the process of removing the grid line material covering the side of the stacked structure 20 away from the peripheral device 70, and the grid line material covering the sidewall and bottom of the grid line gap 80, a portion of the material of the second stop portion 50 is also removed.

[0188] In some embodiments, when the second stop portion 50 is disposed on the side of the protective capping layer 24 and the second contact post 60 away from the substrate 10, the second stop portion 50 is exposed in the gate wire gap 80 during the removal of gate wire material covering the side of the stacked structure 20 away from the peripheral device 70, and the gate wire material covering the sidewalls and bottom of the gate wire gap 80.

[0189] It should be understood that since the portion of the first contact post 40 located within the third cavity 83 is covered by the second protective layer 42, the first contact post 40 will not be etched through the third cavity 83 during the process of removing part of the gate line material.

[0190] S600, see S600. Figure 3M and Figure 4N A grid isolation structure 84 is formed within the grid gap 80.

[0191] In some embodiments, the gate isolation structure 84 may consist only of insulating material. The material of the gate isolation structure 84 may include one or more combinations of silicon oxide, silicon nitride, metal oxide, and organosilicon glass. In some embodiments, the material of the gate isolation structure 84 is silicon oxide.

[0192] In some embodiments, the gate isolation structure 84 can be a composite layer structure, meaning that the gate isolation structure 84 is formed from multiple materials. Exemplarily, the gate isolation structure 84 may include an insulating material layer, a conductive material layer, and a semiconductor material layer sequentially deposited within the gate gap 80. For example, the insulating material layer may include one or more combinations of silicon oxide, silicon nitride, metal oxides, and organosilicon glasses; the conductive material layer may include one or more combinations of tungsten, cobalt, copper, aluminum, doped silicon, and silicides; and the semiconductor material layer may include one or more of single-crystal silicon, single-crystal germanium, and polycrystalline silicon.

[0193] The embodiments disclosed herein do not specifically limit the structure and materials of the gate isolation structure 84.

[0194] See Figure 3L , Figure 3M and Figure 6A When the third gap 288 is formed in the first protective layer 285, the material of the grid isolation structure 84 is also filled in the third gap 288 (84') of the first protective layer 285.

[0195] See Figure 4M and Figure 4N When the grid material covering the inner wall of the third cavity 83 is removed via the second gap 831, the material of the grid isolation structure 84 is still filled in the third cavity 83 to form a filling pattern 85.

[0196] After forming the gate isolation structure 84, the fabrication method of the three-dimensional memory also includes: S710~S740.

[0197] S710, remove the insulating material sacrificial layer 101 to the semiconductor sacrificial layer 102.

[0198] For example, the insulating material sacrificial layer 101 can be removed by an etching process to expose the semiconductor sacrificial layer 102.

[0199] S720, etch the semiconductor sacrificial layer 102 to the first etch stop layer 103 to expose the high-K dielectric layer 31 on the outer side of the end of the channel structure 30 away from the peripheral device 70.

[0200] For example, the insulating material sacrificial layer 101 can be removed by an etching process, exposing the first etch stop layer 103 and the semiconductor sacrificial layer 102 of the channel structure 30.

[0201] S730, etch the first etch stop layer 103, the exposed high-k dielectric layer 31 and the storage function layer of the channel structure to the second etch stop layer 104 to expose the semiconductor channel layer 33 of the channel structure 30.

[0202] S740, a source layer 90 is formed on the side of the stacked structure 20 away from the peripheral device 70; the source layer 90 is electrically connected to the semiconductor channel layer 33 of the channel structure 30.

[0203] The source layer 90 may include a semiconductor material, such as single-crystal silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer 90 may be partially or completely doped. For example, the source layer SL may include doped regions doped with p-type dopant. The source layer 90 may also include undoped regions.

[0204] For example, with Figure 3M Taking the structure of the three-dimensional memory shown as an example, after the above steps S710~S740, the following is formed: Figure 5 The three-dimensional memory shown.

[0205] For example, with Figure 4N Taking the structure of the three-dimensional memory shown as an example, after the above steps S710~S740, the following is formed: Figure 7 The three-dimensional memory shown.

[0206] Because the stacked structure 20 has many layers and a large thickness, the opening of the grooves or holes gradually decreases during the etching process to form grooves or holes. Thus, as... Figure 8 As shown, the cross-sections of the formed channel structure 30, the first contact post 40 (not shown in the figure), and the grid isolation structure 84 are approximately trapezoidal.

[0207] The method for fabricating a three-dimensional memory provided in this disclosure first forms a channel hole and a first contact hole 41 on the side of the stacked structure 20 away from the substrate 10, and then forms a channel structure and a first contact post 40; then, a gate line gap 80 and a gate line isolation structure 84 filling the gate line gap 80 are formed on the side of the stacked structure 20 away from the peripheral device 70. Thus, see... Figure 8 This can increase the spacing between the channel structure 30 and the gate line isolation structure 84, as well as the spacing between the first contact post 40 and the gate line isolation structure 84 (not shown in the figure). It can also increase the size of the opening of the first contact post 40, increasing the contact area between the first contact post 40 and the gate line layer 28, thus reducing the fabrication difficulty of the first contact post 40. Alternatively, it can increase the size of the opening of the gate line gap 80, increasing the uniformity of etching during the removal of the gate line material (S540 and S520').

[0208] Some embodiments of this disclosure also provide a three-dimensional memory, see [link to relevant documentation]. Figure 5 and Figure 7 It includes a source layer 90, a stacked structure 20 disposed on the source layer 90, a filling pattern 85, a protective capping layer 24 covering the stacked structure 20, a first contact post 40, a second stop portion 50, a gate line isolation structure 84, and peripheral devices 70.

[0209] The stacked structure 20 includes alternating layers of dielectric layers 21 and gate lines 28, and has multiple steps 201. A fill pattern 85 is located above the steps 201 (e.g., ...). Figure 7 (as shown), or fill pattern 85 as part of the step (as shown) Figure 6A (As shown).

[0210] The first contact post 40 penetrates the protective capping layer 24 and extends at least to the fill pattern 85; the first contact post 40 is electrically connected to the gate line layer 28. The second stop portion 50 is disposed on the side of the protective capping layer 24 away from the source layer 90. The gate line isolation structure 84 penetrates the stacked structure 20, with one end extending to the source layer 90 and the other end extending to the second stop portion 50.

[0211] The peripheral device 70 is located on the side of the protective capping layer 24 away from the source layer 90 and is electrically connected to the first contact post 40. The structure of the peripheral device 70 can be referred to the description above, and will not be repeated here.

[0212] Some embodiments of this disclosure also provide a three-dimensional memory, the beneficial effects of which can be referred to the beneficial effects of the three-dimensional memory preparation method described above, and will not be repeated here.

[0213] In some embodiments, see Figure 6A The gate layer 28 includes a first conductive layer 28' and a second conductive layer 28"'. The bonding force between the first conductive layer 28' and the protective capping layer 24 is greater than the bonding force between the second conductive layer 28"' and the protective capping layer 24.

[0214] For example, the material of the first conductive layer 28' may include titanium nitride; the material of the second conductive layer 28" may include one or more combinations of tungsten, cobalt, copper, aluminum, doped silicon, and silicide.

[0215] In some embodiments, see Figure 5 and Figure 6A When the gate line layer 28 forming the step 201 is farther from the source layer 90 than the dielectric layer 21, i.e., the gate line layer 28 forming the step 201 is located above the dielectric layer 21, and the fill pattern 85 is disposed on the gate line layer 28 of the step 201, the fill pattern 85 is part of the step 201. The gate line layer 28 includes a gate line body 281 located outside the step 201 and a gate line connection portion 282 located at the step 201, the gate line connection portion 282 being part of the fill pattern 85. The fill pattern 85 also includes a fill portion 851, the gate line connection portion 282 surrounding the fill portion 851. The first contact post 40 extends to the fill pattern 85 and is electrically connected to the gate line connection portion 282.

[0216] In some embodiments, see Figure 6A Along the direction Z perpendicular to the source layer 90, the size of the filling pattern 85 is larger than the size of the gate line body 281.

[0217] In some embodiments, see Figure 6AThe film thickness D1 of the gate line connector 282 is less than the thickness D2 of the gate line body 281. The film thickness of the gate line connector 282 refers to the sidewall thickness D1 at any position of the gate line connector 282. Thus, during the fabrication of the 3D memory, only a gate line material of normal thickness (enough to form the gate line body 281) needs to be deposited, reducing the amount of gate line material used.

[0218] In some embodiments, the filler portion 851 includes a first protective layer 285 disposed within the gap enclosed by the gate line connection portion 282. The first protective layer 285 can prevent the gate line connection portion 282 from being etched away during the formation of the gate line layer 28.

[0219] In some embodiments, when the gap formed by the gate line connection portion 282 is large and the first protective layer 285 does not completely fill the gap formed by the gate line connection portion 282, the filling portion 851 further includes material 84' of the gate line isolation structure 84, and the material 84' of the gate line isolation structure 84 fills the gap formed by the first protective layer 285.

[0220] In some embodiments, the structure of the filling pattern 85 may vary depending on the length by which the first contact post 40 extends into the filling pattern 85.

[0221] For example, see Figure 6A Along the direction Z perpendicular to the source layer 90, the end of the first contact post 40 near the source layer 90 and the dielectric layer 21 (not shown) include a gate line connection 282, a first protective layer 285 and a material 84' of the gate line isolation structure.

[0222] Or, see Figure 6B Along the direction Z perpendicular to the source layer 90, the end of the first contact post 40 near the source layer 90 includes a gate line connection portion 282 and a first protective layer 285 between it and the dielectric layer 21.

[0223] Or, see Figure 6C Along the direction Z perpendicular to the source layer 90, the end of the first contact post 40 near the source layer 90 and the dielectric layer 21 includes only a gate line connection portion 282.

[0224] In some embodiments, the three-dimensional memory further includes a mask layer 25. The mask layer 25 is disposed between the stacked structure 20 and the peripheral device 70; a portion of the mask layer 25 serves as a second stop portion 50.

[0225] In some embodiments, see Figure 7In the case where the dielectric layer 21 forming the step 201 is farther from the source layer 90 than the gate line layer 28 (i.e., the dielectric layer 21 is located above the gate line layer 28), and the fill pattern 85 is disposed on the dielectric layer 21 of the step 201, the fill pattern 85 is located above the step 201, and the material of the fill pattern 85 includes the material of the gate line isolation structure 84. The first contact post 40 penetrates the fill pattern 85 and the dielectric layer 21 below the fill pattern 85, and is electrically connected to the gate line layer 28.

[0226] In some embodiments, see Figure 7 The 3D memory also includes a second protective layer 42. The second protective layer 42 at least covers the sidewalls of the portion of the first contact post 40 that passes through the fill pattern 85. The second protective layer 42 can prevent the portion of the first contact post 40 that passes through the fill pattern 85 from being removed during the removal of some gate line material in the 3D memory fabrication process.

[0227] In some embodiments, see Figure 7 Along the direction Z perpendicular to the source layer 90, the size of the filling pattern 85 is larger than the size of the gate layer 28.

[0228] In some embodiments, see Figure 7 The material of the second stop part 50 is the same as that of the first contact post 40, and the second stop part 50 is embedded in the protective cover layer 24.

[0229] The three-dimensional memory provided in the embodiments of this disclosure can achieve beneficial effects, which can be referred to the beneficial effects of the three-dimensional memory preparation method described above, and will not be repeated here.

[0230] Some embodiments of this disclosure also provide a storage system 1000. The storage system 1000 includes a controller and a three-dimensional memory as described in some of the embodiments above, the controller being coupled to the three-dimensional memory to control the storage of data in the three-dimensional memory.

[0231] The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). In other words, the storage system 1000 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., cell phones), desktop computers, tablets, laptops, servers, in-vehicle devices, game consoles, printers, positioning devices, wearable devices, smart sensors, power banks, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic device containing storage.

[0232] In some embodiments, see Figure 9 The storage system 1000 includes a controller and a three-dimensional memory, and the storage system 1000 can be integrated into a memory card.

[0233] Among them, memory cards include any one of the following: PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital Memory Card (SD) card, and UFS.

[0234] In other embodiments, see Figure 10 The storage system 1000 includes a controller and multiple three-dimensional storage devices, and the storage system 1000 is integrated into solid state drives (SSDs).

[0235] In some embodiments of the storage system 1000, the controller is configured to operate in a low duty cycle environment, such as an SD card, CF card, Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, and mobile phones.

[0236] In other embodiments, the controller is configured to operate in a high duty cycle environment using SSDs or eMMCs, which are used as data storage for mobile devices such as smartphones, tablets, and laptops, as well as enterprise storage arrays.

[0237] In some embodiments, the controller may be configured to manage data stored in the 3D memory and to communicate with external devices (e.g., a host). In some embodiments, the controller may also be configured to control operations of the 3D memory, such as read, erase, and program operations. In some embodiments, the controller may also be configured to manage various functions relating to data stored or to be stored in the 3D memory, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller is also configured to process error correction codes relating to data read from or written to the 3D memory.

[0238] Of course, the controller can also perform any other suitable functions, such as formatting the three-dimensional memory; for example, the controller can communicate with external devices (e.g., a host) through at least one of a variety of interface protocols.

[0239] It should be noted that interface protocols include USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, and PCI High Speed ​​(PCI) protocol. E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Device (IDE) protocol, Firewire protocol, or at least one of these protocols.

[0240] Some embodiments of this disclosure also provide an electronic device. The electronic device can be any of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle equipment, wearable device (e.g., smartwatch, smart bracelet, smart glasses, etc.), power bank, game console, digital multimedia player, etc.

[0241] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0242] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0243] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A stacked structure is formed on a substrate; the stacked structure includes alternating dielectric layers and gate sacrificial layers, and the stacked structure has multiple steps; A first stopping portion is formed at the end of the step; A protective cover layer is formed covering the stacked structure and the first stop portion; A first contact post is formed within the protective cover layer, and the first contact post extends at least to the first stop portion; A peripheral device is bonded to the side of the stacked structure away from the substrate, and the peripheral device is electrically connected to the first contact post; The substrate is removed, and a gate line slot is formed from the side of the stacked structure away from the peripheral device; the gate line slot extends through the stacked structure. The gate sacrificial layer is removed through the gate wire gap to form a gate wire layer; the gate wire layer is electrically connected to the first contact post.

2. The preparation method according to claim 1, characterized in that, Prior to forming the first contact column, the preparation method further includes: A channel structure is formed, which extends through the stacked structure.

3. The preparation method according to claim 2, characterized in that, The first stop portion is formed on the gate sacrificial layer of the step; During the process of forming the first contact post on the stacked structure, a second contact post and a second stop are formed; the second contact post is electrically connected to the channel structure, and the grid line gap stops at the second stop.

4. The preparation method according to claim 3, characterized in that, A first contact post, a second contact post, and a second stop portion are formed on the stacked structure, including: A first mask layer is formed on the side of the protective cap layer away from the substrate; the first mask layer exposes the areas in the protective cap layer where the first contact hole, the second contact hole, and the groove are to be formed; Based on the first mask layer, the protective capping layer is etched to form a first contact hole, a second contact hole, and a groove; the first contact hole penetrates the protective capping layer and extends into the interior of the first stop portion, or extends into the gate sacrificial layer below the first stop portion; the second contact hole penetrates the protective capping layer and extends into the channel structure; the groove is located within the protective capping layer; A first contact post is formed in the first contact hole, a second contact post is formed in the second contact hole, and a second stop portion is formed in the groove; wherein the second contact post is electrically connected to the channel structure.

5. The preparation method according to claim 3, characterized in that, The process of removing the gate sacrificial layer and the first stop portion through the gate wire gap and forming the gate wire layer includes: The gate sacrificial layer and the first stop portion are removed through the gate line gaps to form a first cavity; the first cavity includes a first sub-cavity located outside the step and a second sub-cavity located at the step; along the direction perpendicular to the plane of the stacked structure, the size of the first sub-cavity is smaller than the size of the second cavity; A grid material is filled into the first cavity to form a grid layer; the grid layer includes a grid body located in the first sub-cavity and a grid connection portion located in the second sub-cavity, the grid connection portion covering the second sub-cavity and forming a first gap; the grid connection portion is electrically connected to the first contact post.

6. The preparation method according to claim 5, characterized in that, After forming the gate layer, the process further includes: A first predetermined material is deposited on the surface of the grid line connection portion within the first gap via the grid line slot; Remove the first preset material covering the side of the stacked structure away from the peripheral device, and the first preset material covering the sidewalls and bottom of the gate wire gaps, to form a first protective layer covering the gate wire connection portion; Remove the gate wire material covering the side of the stacked structure away from the peripheral device, and the gate wire material covering the sidewalls and bottom of the gate wire gaps; A grid line isolation structure is formed within the grid line gap; the material of the grid line isolation structure is also filled within the first gap.

7. The preparation method according to claim 2, characterized in that, The first stop portion is formed on the dielectric layer of the step; Between the formation of the protective capping layer and the formation of the first contact pillar, the preparation method further includes: Forming a second contact post and a second stop section; The second contact post is electrically connected to the channel structure, and the grid line gap stops at the second stopping part.

8. The preparation method according to claim 7, characterized in that, The formation of the second contact post and the second stop portion includes: A first mask layer is formed on the side of the protective cap layer away from the substrate; the first mask layer exposes the area in the protective cap layer where the second contact hole and groove are to be formed; Based on the first mask layer, the protective capping layer is etched to form a second contact hole and a groove; the second contact hole penetrates the protective capping layer and extends to the channel structure, and the groove is located within the protective capping layer; A second contact post is formed in the second contact hole, and an initial second stop portion is formed in the groove; wherein the second contact post is electrically connected to the channel structure.

9. The preparation method according to claim 8, characterized in that, The formation of the first contact post includes: A second mask layer is formed on the side of the first mask layer away from the substrate; the second mask layer exposes the area in the first mask layer where the first contact hole is to be formed; Based on the second mask layer, the first mask layer and the protective capping layer are etched to form a first contact hole extending to the first stop portion; The first stop portion at the bottom of the first contact hole is etched so that the first contact hole extends to the dielectric layer below the first stop portion; A second protective layer is formed to cover the inner wall of the first contact hole; The second protective layer and the dielectric layer at the bottom of the first contact hole are etched so that the first contact hole extends to the gate sacrificial layer below the dielectric layer; A first contact post is formed within the first contact hole.

10. The preparation method according to claim 7, characterized in that, The process of removing the gate sacrificial layer and the first stop portion through the gate wire gap and forming the gate wire layer includes: The gate sacrificial layer is removed through the gate line gap to form a second cavity, and the first stop portion is removed to form a third cavity; the second cavity and the third cavity are separated by the dielectric layer; A grid line material is deposited to form a grid line layer in the second cavity; the inner wall of the third cavity is covered with the grid line material.

11. The preparation method according to claim 10, characterized in that, Along a direction perpendicular to the plane containing the stacked structure, the size of the second cavity is smaller than the size of the third cavity; The inner wall of the third cavity is covered with grid material, forming a second gap; After forming the gate layer, the process further includes: Remove the grid line material covering the side of the stacked structure away from the peripheral device, and the grid line material covering the sidewalls and bottom of the grid line gap; and remove the grid line material covering the inner wall of the third cavity via the second gap; A grid line isolation structure is formed within the grid line gaps; the material of the grid line isolation structure is also filled within the third cavity.

12. The preparation method according to claim 6 or 11, characterized in that, The material of the second stop portion is the same as the grid line material; During the process of removing the gate wire material covering the side of the stacked structure away from the peripheral device, and the gate wire material covering the sidewalls and bottom of the gate wire gaps, the portion of the second stop portion away from the peripheral device is removed.

13. The preparation method according to claim 2, characterized in that, The material of the first stop portion is the same as the material of the gate sacrificial layer.

14. A three-dimensional memory, characterized in that, include: Source layer; A stacked structure disposed on the source layer, the stacked structure comprising alternately stacked dielectric layers and gate lines, the stacked structure having multiple steps; A protective capping layer is disposed on the side of the stacked structure away from the source layer, and covers the stacked structure and the step; The first contact post is electrically connected to the portion of the grid layer located at the step, passing through the protective capping layer; The second stop portion is disposed on the side of the stacked structure away from the source layer, and at least a portion of the second stop portion is located within the protective capping layer; A gate line isolation structure extends through the stacked structure, with one end extending to the source layer and the other end extending to the second stop portion; The peripheral device is located on the side of the stacked structure away from the source layer and is electrically connected to the first contact post.

15. The three-dimensional memory according to claim 14, characterized in that, The stacked structure has multiple steps; the three-dimensional memory also includes: A fill pattern is located above the step or is part of the step; A protective capping layer covering the stacked structure; The first contact post penetrates the protective capping layer and extends at least to the filling pattern; the second stop portion is disposed within the protective capping layer; and the peripheral device is disposed on the side of the protective capping layer away from the source layer.

16. The three-dimensional memory according to claim 15, characterized in that, The filling pattern is disposed on the grid layer of the step; the filling pattern is part of the step; The grid layer includes a grid body located outside the step and a grid connection portion located at the step, the grid connection portion being part of the fill pattern; The filling pattern further includes a filling portion, and the grid line connecting portion surrounds the filling portion; The first contact post extends to the filling pattern and is electrically connected to the grid line connection portion.

17. The three-dimensional memory according to claim 16, characterized in that, The filling portion includes: The first protective layer is disposed within the gap formed by the grid wire connection portion; The material of the grid isolation structure is filled within the gaps enclosed by the first protective layer.

18. The three-dimensional memory according to claim 17, characterized in that, Along a direction perpendicular to the source layer, the end of the first contact post near the source layer and the dielectric layer includes the material of the gate line connection portion, the first protective layer, and the gate line isolation structure; Alternatively, along a direction perpendicular to the source layer, the end of the first contact post near the source layer includes a gate line connection and a first protective layer between it and the dielectric layer; Alternatively, along a direction perpendicular to the source layer, the end of the first contact post near the source layer includes a gate line connection between it and the dielectric layer.

19. The three-dimensional memory according to claim 15, characterized in that, The filling pattern is disposed on the dielectric layer of the step; the filling pattern is located above the step; The material of the filling pattern includes the material of the grid isolation structure; The first contact post penetrates the fill pattern and the dielectric layer below the fill pattern, and is electrically connected to the gate line layer.

20. The three-dimensional memory according to claim 19, characterized in that, The three-dimensional memory also includes: The second protective layer covers at least the sidewall of the portion of the first contact post that passes through the filling pattern.

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