Image sensor and method of forming a semiconductor device

Abstract

Various embodiments of the present disclosure relate to an image sensor and a method of forming a semiconductor device. The image sensor includes a plurality of photodetectors disposed within a substrate. A metal grid layer is disposed over the substrate. The metal grid layer includes a metal grid structure overlying a central pixel region of the substrate. The metal grid layer extends continuously from the central pixel region to a peripheral pixel region of the substrate laterally surrounding the central pixel region. An upper metal structure is disposed over the metal grid layer. The upper metal structure overlies the peripheral pixel region. The upper metal structure is laterally offset from the metal grid structure. A lower surface of the upper metal structure is disposed vertically above an upper surface of the metal grid structure.

Description

Technical Field

[0001] This invention relates to an image sensor and a method for forming a semiconductor device. Background Technology

[0002] Many modern electronic devices (e.g., digital cameras, optical imaging devices, etc.) include image sensors. Image sensors convert optical images into digital data that can be represented as digital images. Image sensors consist of an array of pixel sensors, which are unit devices used to convert optical images into digital data. Some types of pixel sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared to CCD pixel sensors, CMOS pixel sensors are favored due to their lower power consumption, smaller size, faster data processing speed, direct data output, and lower manufacturing cost. Summary of the Invention

[0003] This invention provides a method for forming a semiconductor device, comprising: forming a photodetector within a semiconductor substrate, wherein the semiconductor substrate includes opposing first and second surfaces; forming a metal mesh layer on the first surface of the semiconductor substrate; forming an upper metal layer on the metal mesh layer; performing a first etching process on the upper metal layer to define a plurality of elongated metal segments on the metal mesh layer, wherein the plurality of elongated metal segments are arranged parallel to each other and extend continuously in a first direction; forming a first masking layer on the plurality of elongated metal segments, such that the first masking layer includes a plurality of elongated masking segments, wherein the plurality of elongated masking segments are arranged parallel to each other and extend continuously in a second direction orthogonal to the first direction; and performing a second etching process on the metal mesh layer based on the first masking layer and the plurality of elongated metal segments to define a metal mesh structure and a plurality of mesh openings on the photodetector.

[0004] This invention provides an image sensor comprising a semiconductor substrate, a plurality of photodetectors, a metal mesh layer, and an upper metal structure. The semiconductor substrate includes a first surface and a second surface opposite to each other. The plurality of photodetectors are disposed within the semiconductor substrate. The metal mesh layer is overlaid on the first surface of the semiconductor substrate, comprising a metal mesh structure overlaid on a central pixel region of the semiconductor substrate and a peripheral metal structure overlaid on peripheral pixel regions of the semiconductor substrate, wherein the peripheral metal structure laterally surrounds the metal mesh structure, and wherein the metal mesh layer extends continuously from the central pixel region to the peripheral pixel regions. The upper metal structure is disposed on the metal mesh layer, overlaid on the peripheral metal structure, and laterally offset from the metal mesh structure, wherein the lower surface of the upper metal structure is vertically disposed on the upper surface of the metal mesh structure.

[0005] This invention provides a method for forming a semiconductor device, comprising: forming a metal mesh layer on a semiconductor substrate, wherein a plurality of photodetectors are disposed in the semiconductor substrate; forming a plurality of elongated metal segments and an annular upper metal structure on the metal mesh layer, wherein the annular upper metal structure laterally surrounds the plurality of elongated metal segments, and the plurality of elongated metal segments extend laterally between opposite sides of the annular upper metal structure in a first direction; forming a first masking structure on the plurality of elongated metal segments and the annular upper metal structure, wherein the first masking structure includes an overlying layer on the annular upper metal structure. The upper metal structure has an annular masking segment, wherein the first masking structure includes a plurality of elongated masking segments arranged parallel to each other and extending continuously between opposite sides of the annular masking segments in a second direction orthogonal to the first direction; and a first etching process is performed on a metal mesh layer according to the first masking structure and the plurality of elongated metal segments to define a metal mesh structure and an annular peripheral metal structure on a semiconductor substrate, wherein the annular peripheral metal structure laterally surrounds the metal mesh structure and is disposed vertically between the annular upper metal structure and the semiconductor substrate. Attached Figure Description

[0006] The best understanding of all aspects of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1A to 1B Various views of an image sensor with a metal grid structure are shown, which improves the quantum efficiency (QE) of multiple photodetectors.

[0008] Figure 2Show Figures 1A to 1B Top view of some embodiments of the metal mesh layer and upper metal structure of the image sensor shown.

[0009] Figure 3 Show Figures 1A to 1B Perspective views of some other embodiments of the image sensor shown.

[0010] Figure 4 Show Figures 1A to 1B Perspective views of some other embodiments of the image sensor shown.

[0011] Figure 5 Show Figures 1A to 1B Cross-sectional views of some other embodiments of the image sensor shown.

[0012] Figure 6 Show Figures 1A to 1B Cross-sectional views of some other embodiments of the image sensor shown.

[0013] Figure 7 Show Figure 6 Perspective views of some embodiments of the image sensor shown.

[0014] Figure 8 Show Figures 1A to 1B Cross-sectional views of some other embodiments of the image sensor shown.

[0015] Figures 9A to 9B to Figure 20 A series of various views illustrating some embodiments of a method for forming an image sensor with a metal mesh structure that improves the QE of multiple photodetectors.

[0016] Figure 21 The flowchart illustrates some embodiments of a method for forming an image sensor with a metal mesh structure that improves the QE of multiple photodetectors. Detailed Implementation

[0017] This disclosure will now be described with reference to the accompanying drawings, in which the same reference numerals are used throughout to refer to the same elements, and the structures shown are not necessarily drawn to scale. It should be understood that this detailed description and the corresponding figures do not limit the scope of this disclosure in any way, and the detailed description and figures are merely examples to illustrate some ways that may demonstrate the concept of the invention.

[0018] This disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate any relationship between the various embodiments and / or configurations discussed.

[0019] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0020] Some image sensors include multiple photodetectors disposed in a device region of a semiconductor substrate. Multiple pixel devices (e.g., transfer transistors, source follower transistors, reset transistors, etc.) and interconnect structures are disposed along a first surface (e.g., the front surface) of the semiconductor substrate. Isolation structures (e.g., deep trench isolation (DTI) structures) are disposed in / on a second surface (e.g., the back surface) of the semiconductor substrate and laterally positioned between adjacent photodetectors. The pixel devices can be electrically coupled to the photodetectors via the interconnect structures.

[0021] A metal mesh structure is disposed along a second surface of a semiconductor substrate. The metal mesh structure includes a plurality of first elongated mesh segments and a plurality of second elongated mesh segments. The first elongated mesh segments are arranged parallel to each other and each extends in a first direction. The second elongated mesh segments are arranged parallel to each other and each extends in a second direction orthogonal to the first direction. The first elongated mesh segments intersect with the second elongated mesh segments and define a plurality of mesh openings extending through the metal mesh structure. Each mesh opening is directly above a corresponding photodetector among the plurality of photodetectors, and a plurality of filters are disposed within the mesh opening. The metal mesh structure is configured to increase sensitivity (e.g., quantum efficiency (QE)) and reduce crosstalk between adjacent photodetectors.

[0022] In some embodiments, the metal mesh structure can be formed by depositing a metal mesh layer on a second surface of a semiconductor substrate. A masking layer is formed on the metal mesh layer. A single etching process is performed according to the masking layer to define the plurality of first elongated mesh segments and the plurality of second elongated mesh segments, thereby defining the metal mesh structure. The first elongated mesh segments and the second elongated mesh segments intersect at a plurality of intersection points and define a plurality of mesh openings extending through the metal mesh structure. However, after performing the single etching process according to the masking layer, residues of the metal mesh layer may extend from the sidewall of each first elongated mesh segment to the sidewall of the adjacent second elongated mesh segment at each intersection point. This results in the plurality of mesh openings having a rectangular shape (e.g., a square-rounded shape) with rounded corners when viewed from above. The residues of the metal mesh structure may overly cover the corresponding photodetectors disposed within the semiconductor substrate, causing the residues of the metal mesh structure to undesirably reflect incident light away from the corresponding photodetectors. This can reduce the QE of the plurality of photodetectors to some extent, thereby degrading the performance of the image sensor.

[0023] Therefore, various embodiments of this disclosure relate to an improved method for forming a metal mesh structure that improves the QE of multiple photodetectors. The method includes forming multiple photodetectors within a semiconductor substrate and forming a metal mesh structure on the semiconductor substrate. The process for forming the metal mesh structure includes depositing a first metal layer on a surface of the substrate (e.g., the back surface of the semiconductor substrate) and depositing a second metal layer on the first metal layer. A first etching process is performed on the second metal layer according to a first masking layer to define a plurality of elongated metal segments arranged parallel to each other and extending in a first direction. A second masking layer is formed on the plurality of elongated metal segments such that the second masking layer includes a plurality of elongated masking segments arranged parallel to each other and extending in a second direction orthogonal to the first direction. A second etching process is then performed on the first metal layer according to the masking layer and the plurality of elongated metal segments to define the metal mesh structure.

[0024] The metal mesh structure includes a plurality of first elongated mesh segments extending in a first direction and a plurality of second elongated mesh segments extending in a second direction. The first and second elongated mesh segments intersect and define a plurality of mesh openings extending through the metal mesh structure. Because the first metal layer is etched according to the masking layer and the plurality of elongated metal segments, the first and second elongated mesh segments intersect each other at substantially right angles, such that the mesh openings are rectangular when viewed from above. Furthermore, this prevents the presence of residues of the first metal layer extending between adjacent first and second elongated mesh segments, thereby reducing the reflection of incident light away from the photodetector. Therefore, the QE of the plurality of photodetectors can be increased.

[0025] Figures 1A to 1B Various views 100a to 100b of an image sensor with a metal mesh structure 114 are shown, which improves the quantum efficiency of multiple photodetectors 102. Figure 1A A cross-sectional view 100a shows some embodiments of an image sensor. Figure 1B Show Figure 1A Perspective view 100b of some embodiments of the image sensor shown. Figure 1A The sectional view 100a shown is along... Figure 1B The line AA shown is the cut.

[0026] like Figures 1A to 1BAs shown in the various views 100a to 100b, the image sensor includes a plurality of photodetectors 102 disposed in a semiconductor substrate 104. The plurality of photodetectors 102 are configured to absorb incident radiation (e.g., photons) and generate corresponding electrical signals corresponding to the incident radiation. In some embodiments, the plurality of photodetectors 102 are disposed in a photodetector array comprising multiple rows and columns. In yet other embodiments, the semiconductor substrate 104 comprises any type of semiconductor body (e.g., single-crystal silicon / CMOS block, germanium (Ge), silicon-germanium (SiGe), III-V semiconductors, silicon-on-insulator (SOI), etc.).

[0027] In some embodiments, an isolation structure 106 is disposed on / in the semiconductor substrate 104. The isolation structure 106 extends into the semiconductor substrate 104 and is located between the plurality of photodetectors 102. In some embodiments, the isolation structure 106 laterally surrounds each of the plurality of photodetectors 102. In still other embodiments, the isolation structure 106 extends from the back side 104b of the semiconductor substrate 104 into the semiconductor substrate 104. The back side 104b of the semiconductor substrate 104 is opposite to the front side 104f of the semiconductor substrate 104.

[0028] A plurality of filters 108 are disposed on a semiconductor substrate 104 and a photodetector 102. The plurality of filters 108 are arranged in a filter array comprising a plurality of rows and a plurality of columns. In some embodiments, each of the plurality of filters 108 covers and corresponds to a photodetector in the plurality of photodetectors 102. For example, a first filter 108a covers and corresponds to a first photodetector in the plurality of photodetectors 102, a second filter 108b covers and corresponds to a second photodetector in the plurality of photodetectors 102 that is different from the first photodetector, and a third filter 108c covers and corresponds to a third photodetector in the plurality of photodetectors 102 that is different from both the first and second photodetectors.

[0029] The plurality of filters 108 are configured to transmit specific wavelengths (or a specific range of wavelengths). For example, a first filter 108a is configured to transmit light having wavelengths within a first range (e.g., photons having wavelengths between about 10 nm and about 1 mm), a second filter 108b is configured to transmit light having wavelengths within a second range different from the first range, and a third filter 108c is configured to transmit light having wavelengths within a third range different from both the first and second ranges. In some embodiments, the plurality of filters 108 may be color filters. For example, the first filter 108a may be a red filter, the second filter 108b may be a green filter, and the third filter 108c may be a blue filter. In some embodiments, the plurality of filters 108 may be IR filters configured to filter incident radiation having infrared (IR) wavelengths. In still other embodiments, the plurality of filters 108 may include a combination of color filters and / or IR filters.

[0030] A filter grid structure 110 is disposed on the semiconductor substrate 104 and the photodetector 102. The filter grid structure 110 laterally surrounds the plurality of filters 108. In other words, the filter grid structure 110 includes an array of openings in which the plurality of filters 108 are disposed.

[0031] Multiple filters 108 are or comprise filtering materials. In some embodiments, the filtering material is or comprises, for example, photoresist (e.g., positive photoresist / negative photoresist), which comprises dyes / pigments, dispersant polymers, polymeric monomers, and / or other chemicals (e.g., chemicals for polymerization reactions). The filter mesh structure 110 is or comprises a dielectric material. For example, the filter mesh structure 110 may be or comprise, for example, oxides (e.g., silicon dioxide (SiO2)), nitrides (e.g., silicon nitride (SiN)), or oxynitrides (e.g., silicon oxynitride (SiO2)). X N Y In some embodiments, the filter material has a first refractive index, and the dielectric material of the filter mesh structure 110 has a second refractive index less than the first refractive index. In still other embodiments, the dielectric material is a low refractive index (low-n) material (e.g., a material having a refractive index less than about 1.5).

[0032] A metal mesh layer 112 is disposed on a semiconductor substrate 104 and a photodetector 102. The metal mesh layer 112 includes a metal mesh structure 114. The metal mesh structure 114 is overlaid on the central pixel region 116 of the semiconductor substrate 104. The metal mesh structure 114 includes a first plurality of elongated mesh segments 114a and a second plurality of elongated mesh segments 114b. The first plurality of elongated segments 114a are arranged parallel to each other and extend laterally in a first direction (along the z-axis). The second plurality of elongated segments 114b are arranged parallel to each other and extend laterally in a second direction orthogonal to the first direction (along the x-axis).

[0033] A plurality of elongated segments 114a and a plurality of elongated segments 114b intersect and define a plurality of grid openings 118 extending vertically through the metal mesh structure 114. The first plurality of elongated segments 114a and the second plurality of elongated segments 114b intersect each other at substantially right angles, such that the grid openings 118 are rectangular when viewed from above. In this way, the metal mesh structure 114 reflects less incident radiation away from the photodetector 102 compared to a typical metal mesh structure (e.g., a metal mesh structure with rounded corners when viewed from above). Therefore, the metal mesh structure 114 can improve the quantum efficiency (QE) of the photodetector 102, thereby improving the performance of the image sensor.

[0034] In some embodiments, the metal mesh layer 112 further includes a peripheral metal structure 120. The peripheral metal structure 120 is overlaid on the peripheral pixel region 122 of the semiconductor substrate 104. Unlike the metal mesh structure 114, the peripheral metal structure 120 does not have mesh openings. The metal mesh structure 114 extends continuously from the central region 116 to the peripheral metal structure 120. In other words, the metal mesh layer 112 is a continuous layer, and the metal mesh structure 114 and the peripheral metal structure 120 are portions of the metal mesh layer 112. In some embodiments, the upper surface of the metal mesh structure 114 is substantially coplanar with the upper surface of the peripheral metal structure 120. In other embodiments, the upper surface of the metal mesh structure 114 is disposed above or below the upper surface of the peripheral metal structure 120. The metal mesh layer 112 is or comprises, for example, tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), some other metals, or combinations of the foregoing materials.

[0035] An upper metal structure 124 is disposed above the peripheral metal structure 120. The upper metal structure 124 covers the peripheral metal structure 120 and the peripheral pixel area 122. The upper metal structure 124 is offset laterally (along the x-axis) from the metal mesh structure 114. In some embodiments, the lower surface of the upper metal structure 124 is disposed vertically above the upper surface of the metal mesh structure 114. Similar to the peripheral metal structure 120, the upper metal structure 124 does not have mesh openings. The upper metal structure 124 and the peripheral metal structure 120 are configured to block incident radiation from being transmitted to the photodetector 102 disposed in the peripheral pixel area 122 of the semiconductor substrate 104.

[0036] The upper metal structure 124 is or comprises, for example, tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), some other metals, or combinations thereof. In some embodiments, the upper metal structure 124 and the metal mesh layer 112 are or comprise the same metal. For example, both the upper metal structure 124 and the metal mesh layer 112 are tungsten (W). In other embodiments, the upper metal structure 124 may be or comprise a different metal than the metal mesh layer 112.

[0037] A dielectric structure 126 is disposed on the upper metal structure 124 and the peripheral metal structure 120. The dielectric structure 126 covers the peripheral pixel area 122. In some embodiments, a portion of the dielectric structure 126 is laterally disposed between the plurality of filters 108 and the upper metal structure 124 (directly disposed between the plurality of filters 108 and the upper metal structure 124). In still other embodiments, the portion of the dielectric structure 126 is also laterally disposed between the plurality of filters 108 and the peripheral metal structure 120 (directly disposed between the plurality of filters 108 and the peripheral metal structure 120).

[0038] In some embodiments, the upper surface of the dielectric structure 126 is substantially coplanar with the upper surface of the filter mesh structure 110. In other embodiments, the upper surface of the dielectric structure 126 is disposed below or above the upper surface of the filter mesh structure 110. In some embodiments, the dielectric structure 126 may be or comprise, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), or oxynitrides (e.g., SiO2). X N Y (or its analogues). In some other embodiments, the dielectric structure 126 may be or comprise the same material as the filter mesh structure 110. In other embodiments, the dielectric structure 126 may be or comprise a different dielectric material than the filter mesh structure 110.

[0039] Figure 2 Show Figures 1A to 1BA top view 200 of some embodiments of the metal mesh layer 112 and upper metal structure 124 of the image sensor shown. In order to... Figure 2 For clarity, Figure 2 The top view 200 shown is not shown. Figures 1A to 1B Some of the features shown (e.g., semiconductor substrate 104, photodetector 102, etc.) are intended to be used in Figure 2 For clarity, only the metal mesh layer 112 and the upper metal structure 124 are shown. In some embodiments, Figure 1A The sectional view 100a shown is along... Figure 2 The line AA shown is the cut.

[0040] like Figure 2 As shown in the top view 200, the metal mesh layer 112 includes a metal mesh structure 114 and a peripheral metal structure 120. The metal mesh structure 114 is overlaid on the central pixel region 116 of the semiconductor substrate 104. The peripheral metal structure 120 is overlaid on the peripheral pixel region 122 of the semiconductor substrate 104.

[0041] like Figure 2 As shown in the top view 200, in some embodiments, the peripheral pixel region 122 laterally surrounds the central pixel region 116. The peripheral metal structure 120 extends laterally along a closed-loop path, such that the peripheral metal structure 120 laterally surrounds the metal mesh structure 114. In some embodiments, the peripheral metal structure 120 has a ring-shaped layout (e.g., a square ring-shaped layout). In this embodiment, the peripheral metal structure 120 may be referred to as a ring-shaped peripheral metal structure.

[0042] The upper metal structure 124 is disposed above the metal mesh layer 112 and covers both the peripheral metal structure 120 and the peripheral pixel area 122. In some embodiments, the upper metal structure 124 is laterally offset from the metal mesh structure 114 (along both the z-axis and x-axis). The upper metal structure 124 extends laterally along a closed-loop path, such that the upper metal structure 124 laterally surrounds the metal mesh structure 114. In some embodiments, the upper metal structure 124 has a ring-shaped layout (e.g., a square ring-shaped layout). In this embodiment, the upper metal structure 124 may be referred to as a ring-shaped upper metal structure.

[0043] The metal mesh structure 114 is configured to reduce crosstalk and increase sensitivity (e.g., quantum efficiency (QE)) between adjacent photodetectors 102 disposed in the central pixel region 116 of the semiconductor substrate 104. The upper metal structure 124 and the peripheral metal structure 120 are configured to block (e.g., completely block) incident radiation transmitted to the photodetectors 102 disposed in the peripheral pixel region 122 of the semiconductor substrate 104. In some embodiments, the upper metal structure 124 and the peripheral metal structure 120 ensure sufficient blocking of incident radiation into the photodetectors 102 in the peripheral pixel region 122 of the semiconductor substrate 104 (e.g., because the combined thickness of the upper metal structure 124 and the peripheral metal structure 120 is greater than a threshold thickness). In other words, if only one of the upper metal structure 124 or the peripheral metal structure 120 is disposed above the peripheral pixel region 122, some incident radiation will undesirably pass through the upper metal structure 124 (or the peripheral metal structure 120) and be absorbed by the photodetectors 102 disposed in the peripheral pixel region 122 of the semiconductor substrate 104. For example, in some embodiments, a photodetector 102 disposed in the peripheral pixel region 122 of the semiconductor substrate 104 is configured to provide a reference signal for black-level correction (BLC) of the image sensor. Thus, if incident radiation passes through the upper metal structure 124 (or the peripheral metal structure 120) (e.g., since only one of the upper metal structure 124 or the peripheral metal structure 120 is disposed above the peripheral pixel region 122), the BLC of the image sensor may be affected, thereby degrading the performance of the image sensor.

[0044] Figure 3 Show Figures 1A to 1B Perspective view 300 of some other embodiments of the image sensor shown.

[0045] like Figure 3 As shown in perspective view 300, the metal mesh structure 114 includes a first plurality of elongated mesh segments 114a and a second plurality of elongated mesh segments 114b. The first plurality of elongated segments 114a and the second plurality of elongated segments 114b intersect each other at an intersection point 302. In some embodiments, the intersection point 302 has a square footprint.

[0046] Intersection points 302 each have an upper surface 304. In some embodiments, the upper surfaces of intersection points 302 are the upper surfaces of the metal mesh layer 112. In some embodiments, the upper surfaces 304 of intersection points 302 are offset in the vertical direction (along the y-axis) from the upper surfaces of the first plurality of elongated segments 114a and the second plurality of elongated segments 114b. For example, as Figure 3As shown in perspective view 300, the upper surface 304 of the intersection point 302 is disposed below the upper surfaces of the first plurality of elongated segments 114a and the second plurality of elongated segments 114b. In some embodiments, the upper surface 304 of the intersection point 302 is substantially flat (e.g., level). In other embodiments, the upper surface 304 of the intersection point 302 is concave. In still other embodiments, the upper surfaces of the first plurality of elongated segments 114a and the upper surfaces of the second plurality of elongated segments 114b are substantially coplanar.

[0047] Figure 4 Show Figures 1A to 1B Perspective view 400 of some other embodiments of the image sensor shown.

[0048] like Figure 4 As shown in perspective view 400, the upper surface 304 of the intersection point 302 is offset in the vertical direction (along the y-axis) from the upper surfaces of the first plurality of elongated segments 114a and the second plurality of elongated segments 114b. For example, as Figure 4 As shown in perspective view 400, the upper surface 304 of the intersection point 302 is disposed above the upper surfaces of the first plurality of elongated segments 114a and the upper surfaces of the second plurality of elongated segments 114b.

[0049] Figure 5 Show Figures 1A to 1B The image sensor shown is illustrated in cross-sectional view 500 of some other embodiments.

[0050] like Figure 5 As shown in the cross-sectional view 500, a dielectric layer 502 is disposed on the semiconductor substrate 104. The dielectric layer 502 is disposed vertically between the metal mesh layer 112 and the semiconductor substrate 104, vertically between the filter mesh structure 110 and the semiconductor substrate 104, vertically between the upper metal structure 124 and the semiconductor substrate 104, and vertically between the dielectric structure 126 and the semiconductor substrate 104. In some embodiments, the dielectric layer 502 is disposed vertically between the plurality of filters 108 and the semiconductor substrate 104, such as... Figure 5 As shown in the cross-sectional view 500, the dielectric layer 502 extends continuously across both the central pixel region 116 and the peripheral pixel region 122 of the semiconductor substrate 104. In some embodiments, the dielectric layer 502 may have the same layout (e.g., the same footprint) as the filter mesh structure 110 and the dielectric structure 126.

[0051] The dielectric layer 502 may be or contain, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), or oxynitrides (e.g., SiO2). X N YIn some embodiments, the dielectric layer 502 is silicon dioxide (SiO2). In some embodiments, the thickness of the dielectric layer 502 is between about 200 angstroms (Å) and about 5000 Å.

[0052] Figure 6 Show Figures 1A to 1B The image sensor shown is a cross-sectional view 600 of some other embodiments.

[0053] like Figure 6 As shown in the cross-sectional view 600, a first etch stop structure 602 is disposed on the semiconductor substrate 104. The first etch stop structure 602 is disposed vertically between the metal mesh layer 112 and the semiconductor substrate 104. The first etch stop structure 602 has the same layout (e.g., area) as the metal mesh layer 112. In some embodiments, the first etch stop structure 602 is or comprises an oxide (e.g., SiO2), a nitride (e.g., SiN), or an oxide oxynitride (e.g., SiO2). X N Y The materials may include metal nitrides (e.g., tantalum nitride (TaN), titanium nitride (TiN), etc.), some other etch stop materials, or combinations thereof. In some embodiments, the first etch stop structure 602 has a thickness between about 200 Å and about 1000 Å.

[0054] A second etch stop structure 604 may also be disposed on the semiconductor substrate 104. The second etch stop structure 604 is disposed vertically between the peripheral metal structure 120 and the upper metal structure 124. In some embodiments, the second etch stop structure 604 has the same layout (e.g., area) as the upper metal structure 124.

[0055] In some embodiments, the second etch stop structure 604 is or comprises an oxide (e.g., SiO2), a nitride (e.g., SiN), or an oxynitride (e.g., SiO2). X N Y The materials used may include metal nitrides (e.g., tantalum nitride (TaN), titanium nitride (TiN), etc.), other etch stop materials, or combinations thereof. In some embodiments, the first etch stop structure 602 and the second etch stop structure 604 are made of the same material. For example, both the first etch stop structure 602 and the second etch stop structure 604 are titanium nitride (TiN). In some embodiments, the second etch stop structure 604 has a thickness between about 200 Å and about 1000 Å.

[0056] The metal mesh layer 112 has a thickness between approximately 200 Å and approximately 5000 Å. The upper metal structure 124 has a thickness between approximately 200 Å and approximately 5000 Å. The combined thickness 606 of the first etch stop structure 602, the peripheral metal structure 120, the second etch stop structure 604, and the upper metal structure 124 is at least approximately 2000 Å. More specifically, the thickness 606 is between approximately 2000 Å and approximately 5000 Å. If the thickness 606 is less than approximately 2000 Å, it may not be sufficient to block incident radiation from reaching the photodetector 102 disposed in the peripheral pixel region 122 of the semiconductor substrate 104 due to the thickness 606 (e.g., due to the small thickness that allows incident radiation to pass through the first etch stop structure 602, the peripheral metal structure 120, the second etch stop structure 604, and the upper metal structure 124). Therefore, if the thickness of 606 is less than about 2000 Å, the BLC of the image sensor may be damaged, thereby reducing the performance of the image sensor.

[0057] Figure 7 Show Figure 6 Perspective view 700 of some embodiments of the image sensor shown.

[0058] like Figure 7 As shown in perspective view 700, the metal mesh structure 114 includes a first plurality of elongated mesh segments 114a and a second plurality of elongated mesh segments 114b. The first plurality of elongated segments 114a and the second plurality of elongated segments 114b intersect each other at an intersection point 302. In some embodiments, the intersection point 302 has a square-shaped area.

[0059] An etch stop residue structure 702 is provided above the intersection point 302 (e.g., directly above the intersection point 302). The etch stop residue structure 702 is a portion of the second etch stop layer remaining after the etching process that forms the second etch stop structure 604, which will be described in more detail below. Figure 7 As shown in perspective view 700, the etch stop residual structure 702 may have the same occupied area as the intersection point 302. In other embodiments, the etch stop residual structure 702 may have a different occupied area than the intersection point 302. For example, the etch stop residual structure 702 may only cover a portion of the upper surface of the intersection point 302.

[0060] In some embodiments, the thickness of the etch stop residual structure 702 is less than the thickness of the portion of the second etch stop structure 604 that covers the peripheral pixel region 122. In still other embodiments, the upper surface 704 of the etch stop residual structure 702 is substantially flat (e.g., level). In other embodiments, the upper surface 704 of the etch stop residual structure 702 is concave.

[0061] Figure 8 Show Figures 1A to 1B Cross-sectional view 800 of some other embodiments of the image sensor shown.

[0062] like Figure 8 As shown in the cross-sectional view 800, a plurality of microlenses 802 are disposed on the semiconductor substrate 104 and the plurality of filters 108. The plurality of microlenses 802 are respectively overlying the plurality of filters 108. Each of the plurality of microlenses 802 is configured to focus incident radiation toward a lower photodetector among the plurality of photodetectors 102. In some embodiments, the plurality of microlenses 802 are overlying (e.g., only overlying) the central pixel region 116 of the semiconductor substrate 104. In other embodiments, the plurality of microlenses 802 are overlying both the central pixel region 116 and the peripheral pixel region 122 of the semiconductor substrate 104. In this embodiment, some of the plurality of microlenses 802 are overlying the plurality of filters 108 and some of the other microlenses 802 are overlying the dielectric structure 126.

[0063] In some embodiments, the dielectric layer 502 is disposed vertically between the first etch stop structure 602 and the semiconductor substrate 104. In some embodiments, the dielectric layer 502 has a first thickness in the central pixel region 116 and a second thickness greater than the first thickness in the peripheral pixel region 122, such as... Figure 8 As shown in the cross-sectional view 800.

[0064] Figures 9A to 9B to Figure 20 A series of various views illustrating some embodiments of a method for forming an image sensor having a metal mesh structure 114 that improves the QE of multiple photodetectors 102. Figures with the suffix "A" (e.g., Figures 9A to 17A The figures 900a to 1700a show a series of cross-sectional views of some embodiments for forming an image sensor with a metal mesh structure 114 that improves the performance of the image sensor. Figures with the suffix "B" (e.g., Figures 9B to 17B ) shows Figures 9A to 17A The corresponding series of perspective views 900b to 1700b (e.g., Figure 9B Show Figure 9APerspective view 900b of the structure shown. Section views 900a to 1700a are taken along line AA of their corresponding perspective views (e.g., Figure 9A The sectional view 900a shown is along... Figure 9B The perspective view 900b shown is taken from line AA. (Figures without suffixes (e.g., Figures 18 to 20 This shows a series of sectional views 1800 to 2000, which are continuous. Figure 17A The diagram shows a series of various views in section view 1700a. Section views 1800 to 2000 are along the [section / section]. Figure 17A The same line AA is used to cut the section view 1700a shown. Although Figures 9A to 9B to Figure 20 This is an explanation based on one method, but it should be understood that... Figures 9A to 9B to Figure 20 The structure shown is not limited to the method described, but can be used independently of the method.

[0065] like Figure 9A Sectional view 900a and Figure 9B As shown in perspective view 900b, a first etch stop layer 902 is formed on a semiconductor substrate 104. A plurality of photodetectors 102 are disposed in the semiconductor substrate 104. In some embodiments, an isolation structure 106 is disposed within the semiconductor substrate 104, and the isolation structure 106 laterally surrounds the plurality of photodetectors 102. Although in Figure 9A Sectional view 900a and Figure 9B Not explicitly shown in perspective view 900b, but it should be understood that the plurality of photodetectors 102 and isolation structure 106 can be formed in semiconductor substrate 104 prior to the formation of first etch stop layer 902 by known complementary metal oxide semiconductor (CMOS) processes.

[0066] In some embodiments, the process for forming the first etch stop layer 902 includes depositing the first etch stop layer 902 on the semiconductor substrate 104 and the isolation structure 106. The first etch stop layer 902 can be deposited by, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), some other deposition processes, or a combination of the foregoing processes. The first etch stop layer 902 may be or contain oxides (e.g., SiO2), nitrides (e.g., SiN), or oxide oxynitrides (e.g., SiO2). X N YThe first etch stop layer 902 may be deposited with metal nitrides (e.g., tantalum nitride (TaN), titanium nitride (TiN), etc.), some other etch stop materials, or combinations thereof. In some embodiments, the first etch stop layer 902 is deposited to have a thickness between about 200 Å and about 1000 Å. In some embodiments, a dielectric layer (see, for example, dielectric layer 502) may be formed on the semiconductor substrate 104 and the isolation structure 106 (e.g., by CVD, PVD, ALD, thermal oxidation, etc.) prior to the formation of the first etch stop layer 902. In this embodiment, the first etch stop layer 902 is formed on the dielectric layer (e.g., deposited on dielectric layer 502).

[0067] Also in Figure 9A Sectional view 900a and Figure 9B As shown in perspective view 900b, a metal mesh layer 112 is formed over a first etch stop layer 902, a second etch stop layer 904 is formed over the metal mesh layer 112, and an upper metal layer 906 is formed over the second etch stop layer 904. In some embodiments, the first etch stop layer 902 and / or the second etch stop layer 904 are omitted, and therefore no first etch stop layer 902 and / or the second etch stop layer 904 are formed. In some embodiments, the process for forming the metal mesh layer 112 includes depositing the metal mesh layer 112 over the first etch stop layer 902. The metal mesh layer 112 can be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing processes. In some embodiments, the metal mesh layer 112 is deposited to have a thickness between about 200 Å and about 5000 Å.

[0068] In some embodiments, the process for forming the second etch stop layer 904 includes depositing or growing the second etch stop layer 904 on the metal mesh layer 112. The second etch stop layer 904 can be deposited or grown by, for example, CVD, PVD, ALD, thermal oxidation, some other deposition processes, or a combination of the foregoing processes. The second etch stop layer 904 may be or contain oxides (e.g., SiO2), nitrides (e.g., SiN), or oxynitrides (e.g., SiO2). X N Y The etching stop layer 902 may be a metal nitride (e.g., tantalum nitride (TaN), titanium nitride (TiN), etc.), some other etching stop materials, or a combination of the foregoing materials. In some embodiments, the first etching stop layer 902 and the second etching stop layer 904 are made of the same material. For example, both the first etching stop layer 902 and the second etching stop layer 904 are titanium nitride (TiN). In some embodiments, the second etching stop layer 904 is deposited to have a thickness between about 200 Å and about 1000 Å.

[0069] In some embodiments, the process for forming the upper metal layer 906 includes depositing the upper metal layer 906 on the second etch stop layer 904. The upper metal layer 906 can be deposited by, for example, CVD, PVD, ALD, sputtering, electrochemical plating, electroless plating, some other deposition processes, or combinations thereof. The upper metal layer 906 may be or comprise, for example, tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), some other metals, or combinations thereof. In some embodiments, the upper metal layer 906 and the metal mesh layer 112 are or comprise the same metal. For example, both the upper metal layer 906 and the metal mesh layer 112 are tungsten (W). In other embodiments, the upper metal layer 906 may be or comprise a different metal than the metal mesh layer 112. In some embodiments, the upper metal layer 906 is deposited to have a thickness between about 200 Å and about 5000 Å.

[0070] like Figure 10A Sectional view 1000a and Figure 10B As shown in perspective view 1000b, a plurality of elongated metal segments 1002 and an upper metal structure 124 are formed on a metal mesh layer 112. The plurality of elongated metal segments 1002 and the upper metal structure 124 are formed by a first patterning process. The first patterning process includes an upper metal layer 906 (see 9A to 9B). Figure 9B A patterned masking layer 1004 (e.g., positive / negative photoresist, hard mask, etc.) is formed on the upper metal layer 906. The patterned masking layer 1004 can be formed by: forming a masking layer (not shown) on the upper metal layer 906 (e.g., by spin coating); exposing the masking layer to the pattern by a photolithography process (e.g., photolithography, extreme ultraviolet lithography, etc.); and developing the masking layer to form the patterned masking layer 1004 on the upper metal layer 906.

[0071] Subsequently, with the patterned masking layer 1004 in place above the upper metal layer 906, a first etching process (e.g., anisotropic etching process) is performed on the upper metal layer 906 to selectively etch the upper metal layer 906 according to the patterned masking layer 1004. The first etching process removes some unmasked portions of the upper metal layer 906, thereby forming the plurality of elongated metal segments 1002 and the upper metal structure 124. In some embodiments, the first etching process may be, for example, a dry etching process, a reactive ion etching (RIE) process, a wet etching process, some other etching process, or a combination of the foregoing processes. In still other embodiments, the first etching process is a dry etching process (or RIE process) using chlorine-based etching chemicals (e.g., chlorine (Cl2) / argon (Ar), etc.).

[0072] The plurality of elongated metal segments 1002 extend continuously over the central region 116 to the upper metal structure 124. In other words, the plurality of elongated metal segments 1002 and the upper metal structure 124 are portions of a continuous metal layer. In some embodiments, the upper metal structure 124 has an annular arrangement (e.g., a square annular arrangement). In this embodiment, the upper metal structure 124 may be referred to as an annular upper metal structure. The plurality of elongated metal segments 1002 extend continuously between opposing inner sidewalls of the annular upper metal structure.

[0073] Also in Figure 10A Sectional view 1000a and Figure 10B As shown in perspective view 1000b, a second etch stop structure 604 and a plurality of elongated etch stop segments 1006 are formed on the metal mesh layer 112. The second etch stop structure 604 has a layout (e.g., area) substantially the same as the upper metal structure 124. The plurality of elongated etch stop segments 1006 each have a layout (e.g., area) substantially the same as the plurality of elongated metal segments 1002.

[0074] In some embodiments, the process for forming the second etch stop structure 604 and the plurality of elongated etch stop segments 1006 includes forming a second etch stop layer 904 (see...). Figures 9A to 9BA second etching process (e.g., anisotropic etching) is performed. With the patterned masking layer 1004 in place over the plurality of elongated metal segments 1002, the upper metal structure 124, and the second etch stop layer 904, the second etch stop layer 904 is etched selectively according to the patterned masking layer 1004. The second etching process removes some unmasked portions of the second etch stop layer 904, thereby forming the second etch stop structure 604 and the plurality of elongated etch stop segments 1006. In some embodiments, the second etching process may be, for example, a dry etching process, a RIE process, a wet etching process, some other etching process, or a combination of the foregoing processes. In some other embodiments, the second etching process is a dry etching process (or RIE process) that uses fluorine-based etching chemicals (e.g., carbon tetrafluoride (CF4), trifluoromethane (CHF3), octafluorocyclobutane (C4F8), etc.).

[0075] In some embodiments, the patterned masking layer 1004 is stripped after the second etching process. In other embodiments, the patterned masking layer 1004 is stripped after the first etching process but before the second etching process. In this embodiment, the plurality of elongated metal segments 1002 and the upper metal structure 124 can be used as masking layers during the second etching process, thereby selectively etching the second etch stop layer 904 according to the plurality of elongated metal segments 1002 and the upper metal structure 124 (and thus forming the second etch stop structure 604 and the plurality of elongated etch stop segments 1006).

[0076] like Figure 11A Sectional view 1100a and Figure 11B As shown in perspective view 1100b, a first masking layer 1102 is formed over the metal mesh layer 112, the upper metal structure 124, and the plurality of elongated metal segments 1002. A second masking layer 1104 is then formed over the first masking layer 1102. Subsequently, a patterned masking layer 1106 is formed over the second masking layer 1104. In some embodiments, the first masking layer 1102, the second masking layer 1104, and the patterned masking layer 1106 are collectively referred to as a three-layer masking structure.

[0077] In some embodiments, the process for forming the first masking layer 1102 includes depositing the first masking layer 1102 over the metal mesh layer 112, the upper metal structure 124, and the plurality of elongated metal segments 1002. The first masking layer 1102 can be deposited by, for example, spin coating, spray coating, CVD, PVD, some other deposition processes, or combinations thereof. The first masking layer 1102 may be or contain, for example, a photoresist material, an anti-reflective material, spin-coated carbon, etc. Figure 11ASectional view 1100a and Figure 11B As shown in perspective view 1100b, in some embodiments, the first masking layer 1102 is formed with a substantially flat upper surface.

[0078] In some embodiments, the process for forming the second masking layer 1104 includes depositing the second masking layer 1104 on the first masking layer 1102. The second masking layer 1104 can be deposited by, for example, spin coating, CVD, PVD, ALD, some other deposition processes, or combinations thereof. The second masking layer 1104 may be or contain, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), oxynitrides (e.g., silicon oxynitride (SiO2)). X N Y (e.g., spin-coated glass, silicon-containing materials). In some embodiments, the second masking layer 1104 has a substantially flat upper surface.

[0079] In some embodiments, the process for forming the patterned masking layer 1106 includes forming a third masking layer (not shown) (e.g., a positive / negative photoresist material) on the second masking layer 1104 (e.g., by spin coating). The third masking layer is then exposed to the pattern by a photolithography process (e.g., optical lithography, extreme ultraviolet lithography, etc.). Development is performed on the third masking layer (e.g., by applying a developer to the masking layer), thereby forming the patterned masking layer 1106 over the second masking layer 1104. In some embodiments, the patterned masking layer 1106 is formed to have a thickness smaller than that formed by the first masking layer 1102.

[0080] like Figure 12A Sectional view 1200a and Figure 12B As shown in perspective view 1200b, a patterned masking layer 1106 (see...) Figures 11A to 11B The pattern of the patterned masking layer 1106 is transferred to the second masking layer 1104 and the first masking layer 1102. An etching process is then used to transfer the pattern of the patterned masking layer 1106 to the second masking layer 1104 and the first masking layer 1102. For example, with the patterned masking layer 1106 in place on the second masking layer 1104, an etching process is performed on the first masking layer 1102 and the second masking layer 1104 to selectively remove some unmasked portions of the first masking layer 1102 and some unmasked portions of the second masking layer 1104. The etching process can be, for example, dry etching, RIE, wet etching, some other etching processes, or a combination of the foregoing. The patterned masking layer 1106 is then stripped away.

[0081] Since the pattern from the patterned masking layer 1106 is transferred to the first masking layer 1102, after the etching process, the first masking layer 1102 has a plurality of elongated masking portions 1102a and peripheral masking portions 1102b. In other words, the patterned masking layer 1106 has corresponding elongated portions and corresponding peripheral masking portions transferred to the first masking layer 1102 by the etching process. The plurality of elongated masking portions 1102a are overlaid on the central pixel region 116 of the semiconductor substrate 104. The peripheral masking portions 1102b are overlaid on the peripheral pixel region 122 of the semiconductor substrate 104. In some embodiments, after the etching process, the second masking layer 1104 has a layout substantially the same as the first masking layer 1102.

[0082] The plurality of elongated masking portions 1102a are arranged parallel to each other and extend laterally in a first direction (along the z-axis). In some embodiments, the peripheral masking portion 1102b extends laterally in a closed-loop path such that the peripheral masking portion 1102b laterally surrounds the plurality of elongated masking portions 1102a. In some embodiments, the peripheral masking portion 1102b has an annular arrangement (e.g., a square annular arrangement). In this embodiment, the peripheral masking portion 1102b may be referred to as an annular masking portion of the first masking layer 1102. The elongated masking portions 1102a extend continuously between opposing inner sidewalls of the annular masking portion of the first masking layer 1102. In other words, the first masking layer 1102 is a continuous layer, and both the peripheral masking portion 1102b and the plurality of elongated masking portions 1102a are portions of a continuous layer. In some embodiments, the peripheral masking portion 1102b covers the inner sidewalls of the upper metal structure 124 and the inner sidewalls of the second masking structure 604. In this embodiment, the peripheral shielding portion 1102b extends vertically along the inner wall of the upper metal structure 124 and the inner wall of the second shielding structure 604 to the upper surface of the metal mesh layer 112.

[0083] like Figure 13A Sectional view 1300a and Figure 13B As shown in perspective view 1300b, the metal mesh layer 112 is etched by a first etching process (e.g., anisotropic etching process), such that the metal mesh layer 112 includes a metal mesh structure 114 covering the central pixel region 116 and a peripheral metal structure 120 covering the peripheral pixel region 122. In the first masking layer 1102, the metal mesh layer 112 and a plurality of elongated metal segments 1002 (see...) Figures 12A to 12BThe first etching process is performed with the metal mesh layer 112 in place on the upper metal structure 124, thereby selectively etching the metal mesh layer 112 according to the first masking layer 1102. Furthermore, a plurality of elongated metal segments 1002 serve as masking structures during the first etching process, such that the first etching process also selectively etches the metal mesh layer 112 according to the plurality of elongated metal segments 1002. The first etching process removes some unmasked portions of the metal mesh layer 112 (e.g., not covered by the first masking layer 1102 or any of the plurality of elongated metal segments 1002), thereby forming the metal mesh structure 114 and the peripheral metal structure 120. In other words, the first etching process etches the metal mesh layer 112 according to the first masking layer 1102 and the plurality of elongated metal segments 1002, thereby defining the metal mesh structure 114 and the peripheral metal structure 120 on the semiconductor substrate 104.

[0084] In some embodiments, the first etching process may be, for example, a dry etching process, a reactive ion etching (RIE) process, a wet etching process, some other etching processes, or a combination of the foregoing processes. In still other embodiments, the first etching process is a dry etching process (or a RIE process) having a chlorine-based etching chemical substance (e.g., Cl2 / Ar, etc.).

[0085] like Figure 13A Sectional view 1300a and Figure 13B As shown in perspective view 1300b, after the first etching process, residual metal structures 1302 of the plurality of elongated metal segments 1002 remain on the metal mesh structure 114. The residual metal structures 1302 are portions of the plurality of elongated metal segments 1002 remaining on the metal mesh structure 114 after the first etching process. Because the first masking layer 1102 covers some portions of the plurality of elongated metal segments 1002 during the first etching process, the residual metal structures 1302 remain on the metal mesh structure 114, and unlike the first masking layer 1102, the first etching process removes the exposed portions of the plurality of elongated metal segments 1002 (e.g., due to the etching chemistry of the first etching process).

[0086] The metal mesh structure 114 includes a first plurality of elongated mesh segments 114a and a second plurality of elongated mesh segments 114b. The first plurality of elongated segments 114a are arranged parallel to each other and extend laterally in a first direction (along the z-axis). The second plurality of elongated segments 114b are arranged parallel to each other and extend laterally in a second direction orthogonal to the first direction (along the x-axis). The first plurality of elongated segments 114a and the second plurality of elongated segments 114b intersect and define a plurality of mesh openings 118 extending vertically through the metal mesh structure 114. The first plurality of elongated segments 114a and the second plurality of elongated segments 114b intersect at a point (see [reference]). Figure 3 The metal residual structures 1302 intersect each other at the intersection point (e.g., directly above the intersection point). In some embodiments, the metal residual structures 1302 have the same layout (e.g., area) as the intersection point (e.g., square-shaped area).

[0087] In some embodiments, the peripheral pixel region 122 laterally surrounds the central pixel region 116. The peripheral metal structure 120 extends laterally along a closed-loop path, such that the peripheral metal structure 120 laterally surrounds the metal mesh structure 114. In some embodiments, the peripheral metal structure 120 has a ring-shaped layout (e.g., a square ring-shaped layout). Unlike the metal mesh structure 114, the peripheral metal structure 120 does not have mesh openings.

[0088] Also in Figure 13A Sectional view 1300a and Figure 13B As shown in perspective view 1300b, a first etch stop structure 602 is formed in the vertical direction between the metal mesh layer 112 and the semiconductor substrate 104. The first etch stop structure 602 has a layout (e.g., area) that is substantially the same as the metal mesh structure 114 of the metal mesh layer 112 and the peripheral metal structure 120.

[0089] In some embodiments, the process for forming the first etch stop structure 602 includes forming a first etch stop layer 902 (see [link to documentation]). Figures 12A to 12BA second etching process (e.g., anisotropic etching) is performed. With the first masking layer 1102 in place over the first plurality of elongated segments 114a, the residual metal structure 1302, the second etch stop structure 604, the upper metal structure 124, and the peripheral metal structure 120, the second etch stop layer 902 is selectively etched according to the first masking layer 1102. Furthermore, the first plurality of elongated mesh segments 114a serve as masking structures during the second etching process, causing the second etching process to also selectively etch the first etch stop layer 902 according to the first plurality of elongated mesh segments 114a. The second etching process removes some unmasked portions of the first etch stop layer 902 (e.g., portions not covered by the first masking layer 1102 or any of the first plurality of elongated mesh segments 114a), thereby forming the first etch stop structure 602.

[0090] In some embodiments, the second etching process may be, for example, a dry etching process, a RIE process, a wet etching process, some other etching processes, or a combination of the foregoing processes. In still other embodiments, the second etching process is a dry etching process (or a RIE process) having fluorine-based etching chemicals (e.g., carbon tetrafluoride (CF4), trifluoromethane (CHF3), octafluorocyclobutane (C4F8), etc.).

[0091] like Figure 13A Sectional view 1300a and Figure 13B As shown in perspective view 1300b, the residual structure 1304 of the plurality of elongated etch stop segments 1006 remains vertically between the metal residual structure 1302 and the metal mesh structure 114. The residual structure 1304 of the plurality of elongated etch stop segments 1006 is a portion of the plurality of elongated etch stop segments 1006 remaining between the metal residual structure 1302 and the metal mesh structure 114. Because the first masking layer 1102 covers some portions of the plurality of elongated etch stop segments 1006 during the second etching process, the residual structure 1304 of the plurality of elongated etch stop segments 1006 remains between the metal residual structure 1302 and the metal mesh structure 114. Unlike the first masking layer 1102, the second etching process removes some exposed portions of the plurality of elongated etch stop segments 1006 (e.g., due to the etching chemicals of the second etching process).

[0092] The residual structures 1304 of a plurality of elongated etch stop segments 1006 are disposed above (e.g., at intersection points) where the first plurality of elongated segments 114a and the second plurality of elongated segments 114b intersect. The residual structures 1304 of the plurality of elongated etch stop segments 1006 have the same layout (e.g., area) as the intersection points (e.g., square-shaped area). The first masking layer 1102 can be stripped after the second etching process.

[0093] like Figure 14A Sectional view 1400a and Figure 14B As shown in perspective view 1400b, a masking layer 1402 is formed over the semiconductor substrate 104, the first etch stop structure 602, the metal mesh layer 112, the second etch stop structure 604, and the upper metal structure 124. The masking layer 1402 is also formed in the mesh openings 118. The masking layer 1402 has a non-flat upper surface. The non-flat upper surface of the masking layer 1402 is different from that after the first masking layer 1102 has been peeled off. Figures 13A to 13B The morphology of the structure shown corresponds to that of the masking layer 1402. The masking layer 1402 covers (e.g., completely covers) the first etch stop structure 602, the metal mesh layer 112, the second etch stop structure 604, and the upper metal structure 124. For clarity in the figures, portions of the first etch stop structure 602 covered by the masking layer 1402, portions of the metal mesh layer 112 covered by the masking layer 1402, portions of the metal residual structure 1302 covered by the masking layer 1402, and portions of the residual structure 1304 of the plurality of elongated etch stop segments 1006 covered by the masking layer 1402 are shown in the figures. Figure 14A The cross-sectional view 1400a shown is illustrated as a phantom (e.g., by dashed lines).

[0094] In some embodiments, the process for forming the masking layer 1402 includes depositing the masking layer 1402 on the semiconductor substrate 104, the first etch stop structure 602, the metal mesh layer 112, the second etch stop structure 604, and the upper metal structure 124. The masking layer 1402 can be deposited by, for example, spin coating, spray coating, CVD, PVD, ALD, some other deposition processes, or combinations thereof. The masking layer 1402 may be, or contain, for example, a photoresist material, an anti-reflective material, spin-coated carbon, etc. In some embodiments, the masking layer is a bottom anti-reflective coating (BARC).

[0095] like Figure 15A Sectional view 1500a and Figure 15BAs shown in perspective view 1500b, a first etch-back process is performed on masking layer 1402 to remove the upper portion of masking layer 1402. By removing the upper portion of masking layer 1402, the upper portion of the metal residual structure 1302 is exposed. The first etch-back process includes performing an etching process on masking layer 1402 to remove the upper portion of masking layer 1402. In some embodiments, the etching process reduces the thickness of masking layer 1402 over both the central pixel region 116 and the peripheral pixel region 122 of semiconductor substrate 104. In other embodiments, the etching process may selectively remove portions of masking layer 1402 disposed over the central pixel region 116 of semiconductor substrate 104 (e.g., by forming a patterned masking layer over masking layer 1402 prior to performing the etching process).

[0096] In some embodiments, the etching process may be, for example, a dry etching process, a RIE process, a wet etching process, some other etching process, or a combination of the foregoing processes. In still other embodiments, the etching process is a dry etching process (or a RIE process). The etching chemical substance of the etching process may be, or contain, for example, oxygen (e.g., oxygen gas (O2)), nitrogen (e.g., nitrogen gas (N2)), hydrogen (e.g., hydrogen gas (H2)), some other suitable elements, or a combination of the foregoing elements.

[0097] like Figure 16A Sectional view 1600a and Figure 16B As shown in perspective view 1600b, a second etch-back process is performed on the metal residual structure 1302, thereby removing the metal residual structure 1302 and the residual structure 1304 of the multiple elongated etch stop segments 1006 from above the metal mesh structure 114. By removing the metal residual structure 1302 and the residual structure 1304 of the multiple elongated etch stop segments 1006, a plurality of openings 1602 are formed within the masking layer 1402. For clarity in the figure, the plurality of openings are... Figure 16A The cross-sectional view 1600a is shown in phantom form (e.g., through dashed lines).

[0098] The second etching process includes performing a first etching process on the residual metal structure 1302. The first etching process is more selective on the residual metal structure 1302 than on the masking layer 1402. Thus, the first etching process selectively removes the residual metal structure 1302 (e.g., etches it back). In some embodiments, the first etching process may be, for example, a dry etching process, a RIE process, a wet etching process, some other etching process, or a combination of the foregoing. In still other embodiments, the first etching process is a dry etching process (or a RIE process) using a chlorine-based etching chemical (e.g., Cl2 / Ar, etc.).

[0099] Subsequently, a second etching process is performed to remove the residual structure 1304 of the plurality of elongated etch stop segments 1006. Like the first etching process, the second etching process is more selective for the residual structure 1304 of the plurality of elongated etch stop segments 1006 than for the masking layer 1402. Thus, the second etching process selectively removes the residual structure 1304 of the plurality of elongated etch stop segments 1006. In some embodiments, the second etching process may be, for example, a dry etching process, a RIE process, a wet etching process, some other etching process, or a combination of the foregoing processes. In still other embodiments, the second etching process is a dry etching process (or a RIE process) having fluorine-based etching chemicals (e.g., carbon tetrafluoride (CF4), trifluoromethane (CHF3), octafluorocyclobutane (C4F8), etc.).

[0100] In some embodiments, the second etching process may not remove all of the residual structure 1304 of the plurality of elongated etch stop segments 1006, thereby leaving an etch stop residual structure 702 on the metal mesh layer 114 (e.g., directly on the intersection point 302) (see, for example). Figure 7 In other embodiments, the second etching process may remove the upper portion of the metal mesh layer 114 such that the point where the first plurality of elongated segments 114a intersects with the second plurality of elongated segments 114b (e.g., intersection point 302) has an upper surface disposed below the upper surface of the first plurality of elongated segments 114a and the upper surface of the second plurality of elongated segments 114b (see, for example, Figure 3 The second etch stop layer 904 is omitted (see, for example). Figures 9A to 9B In one embodiment, the first etching process may not remove all of the metal residual structure 1302, such that the point where the first plurality of elongated segments 114a and the second plurality of elongated segments 114b intersect (e.g., intersection point 302) has an upper surface disposed above the upper surface of the first plurality of elongated segments 114a and the upper surface of the second plurality of elongated segments 114b (see, for example, Figure 4 The second etch stop layer 904 is omitted (see, for example). Figures 9A to 9B In other embodiments, the first etching process may remove the upper portion of the metal mesh layer 114, such that the points where the first plurality of elongated segments 114a and the second plurality of elongated segments 114b intersect (e.g., intersection point 302) have an upper surface disposed below the upper surface of the first plurality of elongated segments 114a and the upper surface of the second plurality of elongated segments 114b (see, for example, Figure 3 ).

[0101] The upper surface of the intersection point 302 is located above or below the upper surfaces of the first plurality of elongated segments 114a and the second plurality of elongated segments 114b, and the etching stop residual structure 702 is disposed on the metal mesh layer 114 at the intersection point 302, which indicates that Figures 17A to 17B The structure shown may have been formed in the manner described above (e.g., because the method described above utilizes a second etching process to remove the residual metal structure 1302 and the residual structure 1304 of the plurality of elongated etching stop sections 1006). In some other embodiments, the second etching process (or the first etching process) stops directly at the upper surfaces of the first plurality of elongated sections 114a and the second plurality of elongated sections 114b, such that the point where the first plurality of elongated sections 114a and the second plurality of elongated sections 114b intersect (e.g., intersection point 302) has an upper surface that is substantially coplanar with the upper surfaces of the first plurality of elongated sections 114a and the second plurality of elongated sections 114b.

[0102] By forming the metal mesh structure 114 in the manner described above (e.g., by forming the metal mesh layer 112 based on the first masking layer 1102 and a plurality of elongated metal segments 1002), and then etching back the metal residual structure 1302 (and the residual structure 1304 of the plurality of elongated etch stop segments 1006), the first plurality of elongated mesh segments 114a and the second plurality of elongated mesh segments 114b can intersect each other substantially at right angles, such that the mesh opening 118 is rectangular when viewed from above. Furthermore, this prevents the presence of residues (which are present on typical metal mesh structures) extending between adjacent first and second elongated mesh segments of the metal mesh layer 112, thereby reducing the reflection of incident light away from the plurality of photodetectors 102. Therefore, the QE of the plurality of photodetectors 102 can be increased.

[0103] In some embodiments, a typical metal mesh structure includes remnants of the metal mesh layer extending between adjacent first and second elongated mesh segments, because typical metal mesh structures are formed by other methods subject to intrinsic optical resolution effects and / or etching effects. For example, a typical metal mesh structure is typically patterned using a photolithographic mask. Light diffraction can cause pattern distortion at the intersections of adjacent lines. Thus, while the mask pattern may have straight sidewalls, the photoresist pattern may have curved sidewalls. Additionally, deformation may also occur at the intersections due to the etching process.

[0104] like Figure 17A Sectional view 1700a and Figure 17BAs shown in perspective view 1700b, the masking layer 1402 is peeled off. After the masking layer 1402 is peeled off, a first etch stop structure 602 is formed on the semiconductor substrate 104. A metal mesh layer 112, including a metal mesh structure 114 and a peripheral metal structure 120, is formed on the semiconductor substrate 104 and the first etch stop structure 602. A second etch stop structure 604 is formed on the semiconductor substrate 104 and the peripheral metal structure 120 of the metal mesh layer 112, and the upper metal structure 124 covers the second etch stop structure 604.

[0105] like Figure 18 As shown in the cross-sectional view 1800, a filter grid layer 1802 is formed on a semiconductor substrate 104, a first etch stop structure 602, a metal mesh layer 112, a second etch stop structure 604, and an upper metal structure 124. The filter grid layer 1802 may also be formed within a mesh opening 118. In some embodiments, the process for forming the filter grid layer 1802 includes depositing the filter grid layer 1802 on the semiconductor substrate 104, the first etch stop structure 602, the metal mesh layer 112, the second etch stop structure 604, and the upper metal structure 124 by, for example, CVD, PVD, ALD, sputtering, some other deposition processes, or a combination of the foregoing processes. In some embodiments, the filter grid layer 1802 may comprise, for example, oxides (e.g., SiO2), nitrides (e.g., SiN), or oxynitrides (e.g., SiO2). X N Y )wait.

[0106] like Figure 19 As shown in cross-sectional view 1900, a filter mesh structure 110 is formed on a semiconductor substrate 104 and a metal mesh structure 114. The filter mesh structure 110 includes a plurality of filter mesh openings arranged in an array including rows and columns. Similarly, Figure 19 As shown in the cross-sectional view 1900, a plurality of filters 108 are formed in a plurality of filter grid openings and in a plurality of grid openings 118.

[0107] In some embodiments, the process for forming the filter mesh structure 110 and the plurality of filters 108 includes processing the filter mesh layer 1802 (see, for example) Figure 18 Selective etching can be performed. The filter grid layer 1802 can be selectively etched by forming a patterned masking layer (not shown) on the filter grid layer 1802 and subsequently performing an etching process on the filter grid layer 1802 to remove some unmasked portions of the filter grid layer 1802, thereby forming a filter grid structure 110 with multiple filter grid openings. In some embodiments, the masking layer is then stripped.

[0108] Subsequently, a plurality of filters 108 are formed in the plurality of filter grid openings and grid openings 118. In some embodiments, the process for forming the plurality of filters 108 includes depositing a filter material in the plurality of filter grid openings and grid openings 118 (e.g., by CVD, PVD, ALD, sputtering, spin coating, etc.) to form the plurality of filters 108. The filter material is a material that allows radiation (e.g., light) with a specific wavelength range to pass through while blocking light of wavelengths outside the specific range. Subsequently, in some embodiments, a planarization process (e.g., chemical-mechanical planarization, CMP) may be performed on the plurality of filters 108 to planarize the upper surfaces of the plurality of filters 108.

[0109] Also in Figure 19 As shown in cross-sectional view 1900, a dielectric structure 126 is formed over a semiconductor substrate 104, a first etch stop structure 602, a peripheral metal structure 120, a second etch stop structure 604, and an upper metal structure 124. In some embodiments, the dielectric structure 126 is part of a filter mesh layer 1802 and is formed using the same process as the filter mesh structure 110. In other embodiments, the dielectric structure 126 may be formed using a different process than the filter mesh structure 110. For example, in some embodiments, the dielectric structure 126 may be or contain a material different from that of the filter mesh structure 110. In such embodiments, a dielectric layer may be deposited over multiple filters 108, the filter mesh structure 110, and the upper metal structure 124 (e.g., via CVD, PVD, ALD, sputtering, spin coating, etc.). Subsequently, the dielectric layer may be selectively etched and / or planarized (e.g., by CMP) to selectively remove portions of the dielectric layer, thereby forming dielectric structure 126.

[0110] like Figure 20As shown in the cross-sectional view 2000, a plurality of microlenses 802 are formed over a plurality of filters 108. The plurality of microlenses 802 can be formed by depositing microlens material on the filter mesh structure 110, the plurality of filters 108, and on the dielectric structure 126 (e.g., by CVD, PVD, ALD, sputtering, spin coating, etc.). A microlens template (not shown) having a curved upper surface is patterned over the microlens material. In some embodiments, the microlens template may comprise a photoresist material that is exposed using a distributed exposure light dose (e.g., for negative photoresist, more light is exposed at the bottom of the curvature and less light at the top of the curvature), developed, and baked to form a circular shape. The plurality of microlenses 802 are then formed by selectively etching the microlens material according to the microlens template. In some embodiments, after the formation of the plurality of microlenses 802, the formation of an image sensor having a metal mesh structure 114 is completed. The metal mesh structure 114 improves the QE of multiple photodetectors 102.

[0111] Figure 21 A flowchart 2100 illustrates some embodiments of a method for forming an image sensor with a metal mesh structure 114, which improves the QE of multiple photodetectors 102. Although Figure 21 The flowchart 2100 is shown and illustrated herein as a series of actions or events; however, it should be understood that the order in which such actions or events are shown should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those shown and / or illustrated herein. Furthermore, not all of the shown actions may be required to implement one or more aspects or embodiments described herein, and one or more of the actions illustrated herein may be performed by one or more separate actions and / or stages.

[0112] At action 2102, a metal mesh layer is formed on the semiconductor substrate, and an upper metal layer is formed on the metal mesh layer. Figures 9A to 9B Various views 900a to 900b are shown for some embodiments corresponding to action 2102.

[0113] At action 2104, the upper metal layer is selectively etched to form multiple elongated metal segments and an upper metal structure. Figures 10A to 10B Various views 1000a to 1000b are shown for some embodiments corresponding to action 2104.

[0114] At action 2106, a first masking layer having multiple elongated masking portions is formed on the metal mesh layer, on the plurality of elongated metal segments, and on the upper metal structure, wherein the plurality of elongated masking portions cover portions of the plurality of elongated metal segments. Figures 11A to 11B to Figures 12A to 12B A series of various views are shown for some embodiments corresponding to action 2106.

[0115] At action 2108, the metal mesh layer is selectively etched according to the first masking layer and the plurality of elongated metal segments, thereby forming a metal mesh structure and a peripheral metal structure on the semiconductor substrate. Figures 13A to 13B Various views 1300a to 1300b are shown for some embodiments corresponding to action 2108.

[0116] At action 2110, an etch-back process is performed to remove portions of the plurality of elongated metal segments from the metal mesh structure. Figures 14A to 14B to Figures 17A to 17B A series of various views are shown for some embodiments corresponding to action 2110.

[0117] At action 2112, a filter grid structure, multiple filters, and multiple microlenses are formed on the metal grid structure, the outer metal structure, and the upper metal structure. Figures 18 to 20 A series of various views are shown for some embodiments corresponding to action 2112.

[0118] In some embodiments, this application provides a method for forming a semiconductor device. The method includes: forming a photodetector within a semiconductor substrate, wherein the semiconductor substrate includes a first surface opposite to a second surface; forming a metal mesh layer over the first surface of the semiconductor substrate; forming an upper metal layer over the metal mesh layer; performing a first etching process on the upper metal layer to define a plurality of elongated metal segments over the metal mesh layer, wherein the elongated metal segments are arranged parallel to each other and extend continuously in a first direction; forming a first masking layer over the plurality of elongated metal segments, such that the first masking layer includes a plurality of elongated masking segments, wherein the elongated masking segments are arranged parallel to each other and extend continuously in a second direction orthogonal to the first direction; and performing a second etching process on the metal mesh layer according to the first masking layer and the plurality of elongated metal segments to define a metal mesh structure and a plurality of mesh openings over the photodetector.

[0119] The method for forming a semiconductor device described above further includes forming a plurality of filters within the plurality of grid openings.

[0120] The method for forming a semiconductor device described above further includes forming a plurality of microlenses on the plurality of filters.

[0121] In the above method for forming a semiconductor device, the metal mesh layer and the upper metal layer contain the same material.

[0122] In the above method for forming a semiconductor device, wherein: after etching the metal mesh layer, some portions of the plurality of elongated metal segments remain on the metal mesh structure; and some portions of the plurality of elongated metal segments are removed from the metal mesh structure by an etch-back process.

[0123] In the above-described method for forming a semiconductor device, the etching process includes: forming a second masking layer over the metal mesh structure, over portions of the plurality of elongated metal segments, and in the plurality of mesh openings; removing an upper portion of the second masking layer to expose portions of the plurality of elongated metal segments; and performing a third etching process on portions of the plurality of elongated metal segments after the second masking layer is in place and after portions of the plurality of elongated metal segments have been exposed.

[0124] In the above method for forming a semiconductor device, the metal mesh structure includes: a plurality of first elongated mesh segments, the plurality of first elongated mesh segments being parallel to each other and each extending in a first direction; and a plurality of second elongated mesh segments, the plurality of second elongated mesh segments being parallel to each other and each extending in a second direction, wherein the plurality of first elongated mesh segments intersect with the plurality of second elongated mesh segments at a plurality of intersection points, and wherein some portions of the plurality of elongated metal segments are respectively disposed on the plurality of intersection points.

[0125] In some embodiments, this application provides an image sensor. The image sensor includes: a semiconductor substrate including a first surface opposite to a second surface. A plurality of photodetectors are disposed within the semiconductor substrate. A metal mesh layer is overlaid on the first surface of the semiconductor substrate, wherein the metal mesh layer includes a metal mesh structure overlaid on a central pixel region of the semiconductor substrate, wherein the metal mesh layer extends continuously from the central pixel region to a peripheral pixel region of the semiconductor substrate that laterally surrounds the central pixel region. An upper metal structure is disposed on the metal mesh layer, wherein the upper metal structure is overlaid on the peripheral metal structure, wherein the upper metal structure is laterally offset from the metal mesh structure, and wherein the lower surface of the upper metal structure is disposed vertically on the upper surface of the metal mesh structure.

[0126] In the aforementioned image sensor, the upper metal structure and the metal mesh layer contain the same material.

[0127] The image sensor described above also includes: a plurality of filters covering the plurality of photodetectors, wherein the metal mesh structure surrounds the plurality of filters laterally.

[0128] In the aforementioned image sensor, the plurality of photodetectors are disposed in both the central pixel region and the peripheral pixel region of the semiconductor substrate; the metal mesh structure extends between the photodetectors disposed in the central pixel region of the semiconductor substrate; and the peripheral metal structure covers the plurality of photodetectors disposed in the peripheral pixel region of the semiconductor substrate.

[0129] In the aforementioned image sensor, wherein: the peripheral metal structure has a ring-shaped layout that surrounds the metal mesh structure laterally; and the peripheral metal structure extends continuously from the inner sidewall of the peripheral metal structure to the outer sidewall of the peripheral metal structure; and the outer sidewall of the peripheral metal structure extends laterally around the metal mesh structure in a closed-loop path.

[0130] In the aforementioned image sensor, the upper metal structure has a ring-shaped layout that laterally surrounds the metal mesh structure.

[0131] In the aforementioned image sensor, the metal mesh structure includes: a first elongated mesh segment extending laterally in a first direction; a second elongated mesh segment extending laterally in a second direction orthogonal to the first direction; and an intersection point where the first elongated mesh segment and the second elongated mesh segment intersect, wherein the upper surface of the intersection point is offset in a vertical direction from both the upper surfaces of the first elongated mesh segment and the upper surfaces of the second elongated mesh segment.

[0132] In the aforementioned image sensor, the upper surface of the intersection point has a square-shaped occupied area.

[0133] In the aforementioned image sensor, the upper surface of the first elongated grid segment is coplanar with the upper surface of the second elongated grid segment.

[0134] In some embodiments, this application provides a method for forming a semiconductor device. The method includes: forming a metal mesh layer on a semiconductor substrate, wherein a plurality of photodetectors are disposed in the semiconductor substrate; forming a plurality of elongated metal segments and an annular upper metal structure on the metal mesh layer, wherein the annular upper metal structure laterally surrounds the plurality of elongated metal segments and the plurality of elongated metal segments extend laterally between opposite sides of the annular upper metal structure in a first direction; forming a first masking structure on the plurality of elongated metal segments and on the annular upper metal structure, wherein the first masking structure includes an annular masking segment overlying the annular upper metal structure, and wherein the first masking structure includes a plurality of elongated masking segments arranged parallel to each other and extending continuously between opposite sides of the annular masking segments in a second direction orthogonal to the first direction. A first etching process is performed on the metal mesh layer according to the first masking structure and the plurality of elongated metal segments to define a metal mesh structure and an annular peripheral metal structure on the semiconductor substrate, wherein the annular peripheral metal structure surrounds the metal mesh structure laterally and is disposed between the annular upper metal structure and the semiconductor substrate in the vertical direction.

[0135] In the above-described method for forming a semiconductor device, forming the plurality of elongated metal segments and the annular upper metal structure includes: forming an upper metal layer on the metal mesh layer; forming a second masking structure on the upper metal layer; and performing a second etching process on the upper metal layer according to the first masking structure.

[0136] In the above-described method for forming a semiconductor device, forming the first masking structure includes: forming a first masking layer over the plurality of elongated metal segments and the annular upper metal structure; forming a second masking layer over the first masking layer; and performing a second etching process on the first masking layer according to the second masking layer to transfer a pattern from the second masking layer to the first masking layer.

[0137] In the above method for forming a semiconductor device, the annular masking section is formed to cover the inner sidewall of the annular upper metal structure.

[0138] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a semiconductor device, the method comprising: A photodetector is formed within a semiconductor substrate, wherein the semiconductor substrate includes opposing first and second surfaces; A metal mesh layer is formed on the first surface of the semiconductor substrate; An upper metal layer is formed on top of the metal mesh layer; A first etching process is performed on the upper metal layer to define a plurality of elongated metal segments above the metal mesh layer, wherein the plurality of elongated metal segments are arranged parallel to each other and extend continuously in a first direction. A first masking layer is formed on the plurality of elongated metal segments, such that the first masking layer includes a plurality of elongated masking segments, wherein the plurality of elongated masking segments are arranged parallel to each other and extend continuously in a second direction orthogonal to the first direction; as well as A second etching process is performed on the metal mesh layer based on the first masking layer and the plurality of elongated metal segments to define a metal mesh structure and a plurality of mesh openings on the photodetector.

2. The method for forming a semiconductor device according to claim 1, further comprising: Multiple filters are formed within the multiple grid openings.

3. The method according to claim 2, further comprising: Multiple microlenses are formed on the multiple filters.

4. The method of forming a semiconductor device according to claim 1, wherein the metal mesh layer and the upper metal layer comprise the same material.

5. The method for forming a semiconductor device according to claim 1, wherein: After etching the metal mesh layer, some portions of the plurality of elongated metal segments remain on the metal mesh structure; and Some portions of the plurality of elongated metal segments were removed from the metal mesh structure by an etching process.

6. The method for forming a semiconductor device according to claim 5, wherein the etch-back process comprises: A second masking layer is formed on the metal mesh structure, on some portions of the plurality of elongated metal segments, and in the plurality of mesh openings; Remove the upper portion of the second masking layer to expose portions of the plurality of elongated metal segments; as well as With the second masking layer in place and after some portions of the plurality of elongated metal segments have been exposed, a third etching process is performed on some portions of the plurality of elongated metal segments.

7. The method for forming a semiconductor device according to claim 5, wherein the metal mesh structure comprises: Multiple first elongated grid segments, the multiple first elongated grid segments being parallel to each other and each extending in the first direction; as well as A plurality of second elongated mesh segments, the plurality of second elongated mesh segments being parallel to each other and each extending in the second direction, wherein the plurality of first elongated mesh segments intersect the plurality of second elongated mesh segments at a plurality of intersection points, and wherein some portions of the plurality of elongated metal segments are respectively disposed on the plurality of intersection points.

8. An image sensor, comprising: A semiconductor substrate, comprising opposing first and second surfaces; Multiple photodetectors and isolation structures are disposed within the semiconductor substrate; A metal mesh layer is overlaid on the first surface of the semiconductor substrate and in direct contact with the semiconductor substrate and the isolation structure. The metal mesh layer includes a metal mesh structure overlaid on a central pixel area of ​​the semiconductor substrate and a peripheral metal structure overlaid on a peripheral pixel area of ​​the semiconductor substrate. The peripheral metal structure laterally surrounds the metal mesh structure, and the metal mesh layer extends continuously from the central pixel area to the peripheral pixel area. as well as An upper metal structure is disposed on the metal mesh layer, wherein the upper metal structure covers the outer metal structure, wherein the upper metal structure is offset from the metal mesh structure in the lateral direction, and wherein the lower surface of the upper metal structure is disposed on the upper surface of the metal mesh structure in the vertical direction, and the lower surface of the upper metal structure is separated from the upper surface of the outer metal structure in the vertical direction.

9. The image sensor of claim 8, wherein the upper metal structure and the metal mesh layer comprise the same material.

10. The image sensor according to claim 8, further comprising: Multiple filters are overlaid on the multiple photodetectors, wherein the metal mesh structure surrounds the multiple filters laterally.

11. The image sensor according to claim 8, wherein: The plurality of photodetectors are disposed in both the central pixel region and the peripheral pixel region of the semiconductor substrate; The metal mesh structure extends between the photodetectors disposed in the central pixel region of the semiconductor substrate; and The peripheral metal structure covers the plurality of photodetectors disposed in the peripheral pixel region of the semiconductor substrate.

12. The image sensor according to claim 8, wherein: The peripheral metal structure has a ring-shaped layout that laterally surrounds the metal mesh structure; and The peripheral metal structure extends continuously from the inner wall of the peripheral metal structure to the outer wall of the peripheral metal structure; and The outer wall of the peripheral metal structure extends laterally around the metal mesh structure in a closed-loop path.

13. The image sensor of claim 8, wherein the upper metal structure has an annular layout that laterally surrounds the metal mesh structure.

14. The image sensor according to claim 8, wherein the metal mesh structure comprises: The first slender grid segment extends laterally in the first direction; The second elongated grid segment extends laterally in a second direction orthogonal to the first direction; as well as The first elongated grid segment and the second elongated grid segment intersect at the intersection point, wherein the upper surface of the intersection point is offset from the upper surfaces of both the first elongated grid segment and the second elongated grid segment in the vertical direction.

15. The image sensor according to claim 14, wherein: The upper surface of the intersection point has a square-shaped area.

16. The image sensor according to claim 14, wherein: The upper surface of the first elongated grid segment is coplanar with the upper surface of the second elongated grid segment.

17. A method of forming a semiconductor device, the method comprising: A metal mesh layer is formed on a semiconductor substrate, wherein multiple photodetectors are disposed in the semiconductor substrate; A plurality of elongated metal segments and an annular upper metal structure are formed on the metal mesh layer, wherein the annular upper metal structure laterally surrounds the plurality of elongated metal segments, and the plurality of elongated metal segments extend laterally between opposite sides of the annular upper metal structure in a first direction. A first masking structure is formed on the plurality of elongated metal segments and the annular upper metal structure, wherein the first masking structure includes an annular masking segment covering the annular upper metal structure, and wherein the first masking structure includes a plurality of elongated masking segments arranged parallel to each other and extending continuously between opposite sides of the annular masking segments in a second direction orthogonal to the first direction; as well as A first etching process is performed on the metal mesh layer according to the first masking structure and the plurality of elongated metal segments to define a metal mesh structure and an annular peripheral metal structure on the semiconductor substrate, wherein the annular peripheral metal structure surrounds the metal mesh structure laterally and is disposed between the annular upper metal structure and the semiconductor substrate in the vertical direction.

18. The method of forming a semiconductor device according to claim 17, wherein forming the plurality of elongated metal segments and the annular upper metal structure comprises: An upper metal layer is formed on top of the metal mesh layer; A second masking structure is formed on top of the upper metal layer; as well as A second etching process is performed on the upper metal layer according to the first masking structure.

19. The method of forming a semiconductor device according to claim 17, wherein forming the first masking structure comprises: A first masking layer is formed on the plurality of elongated metal segments and on the annular upper metal structure; A second shielding layer is formed on top of the first shielding layer; as well as A second etching process is performed on the first masking layer according to the second masking layer to transfer the pattern from the second masking layer to the first masking layer.

20. The method of forming a semiconductor device according to claim 17, wherein the annular masking section is formed to cover the inner sidewall of the annular upper metal structure.

Images