Display device and method of manufacturing the same

Abstract

A display device includes a substrate including a light emitting area forming an open area and a non-light emitting area adjacent to the light emitting area, a circuit element layer formed in the non-light emitting area, and a bank layer covering a top of the circuit element layer, wherein the bank layer is not formed in the light emitting area.

Description

Technical Field

[0001] The present invention relates to a display device and a method for manufacturing the display device. Background Technology

[0002] Organic light-emitting elements (hereinafter referred to as light-emitting elements) are self-emissive components that do not require a separate light source, thereby reducing the thickness and weight of display devices. Furthermore, organic light-emitting display devices are characterized by low power consumption, high brightness, and high responsiveness, among other features.

[0003] Typically, the light-emitting element has a structure in which an anode, a dam surrounding the edge region of the anode, a light-emitting layer formed on top of the anode inside the dam, and a cathode covering the light-emitting layer and the dam are stacked on top of each other.

[0004] When the embankment and cathode are arranged in an overlapping manner, light escapes into adjacent pixel areas due to internal reflection, which can cause inconvenience to users.

[0005] The above content is only used to help understand the background of this disclosure and does not mean that this disclosure falls within the scope of related technologies known to those skilled in the art. Summary of the Invention

[0006] One objective of the embodiments is to provide a display device having a half-embankment structure, wherein the embankment is omitted from the light-emitting area to prevent light escape between pixels.

[0007] Another objective of the embodiments is to provide a display device with a semi-embankment structure in which the anode does not overlap with the data wiring and thereby reduces light loss in non-light-emitting areas, thus improving light efficiency.

[0008] According to one embodiment, a display device is provided, comprising: a substrate including a light-emitting region forming an opening region and a non-light-emitting region adjacent to the light-emitting region; a circuit element layer formed in the non-light-emitting region; and a dam layer covering the top of the circuit element layer, wherein the dam layer is not formed in the light-emitting region.

[0009] In the display device, the circuit element layer may include: a first conductive layer disposed on top of the substrate; a buffer layer covering the first conductive layer; an active layer disposed on top of the buffer layer; a gate insulating layer covering the active layer; and a second conductive layer disposed on top of the gate insulating layer and comprising at least one electrode of a transistor.

[0010] The display device may further include: a passivation layer disposed on top of the gate insulating layer; and an overcoat layer disposed on top of the passivation layer, wherein the passivation layer and the overcoat layer are formed on all regions of the substrate, including light-emitting regions and non-light-emitting regions.

[0011] The display device may further include: an anode disposed on top of the outer coating; a light-emitting layer disposed on top of the anode; and a cathode disposed on top of the light-emitting layer, wherein the embankment layer may be inserted between the anode and the light-emitting layer.

[0012] The display device may further include: data lines and sensing lines extending in the direction of pixels arranged in columns, the pixels displaying white, red, green or blue, wherein the data lines or the sensing lines are arranged between columns of the pixels.

[0013] In the display device, the anode does not overlap with the data line or the sensing line.

[0014] The display device may further include a color filter that displays red, green, or blue, wherein the color filter may be arranged in the light-emitting area and may be inserted between the passivation layer and the outer coating layer.

[0015] In the display device, the at least one transistor may include a drive transistor configured to control the amount of current flowing to the anode, and the drive transistor may include a source disposed on the second conductive layer and electrically connected to a power line; a cathode disposed in the second conductive layer and electrically connected to the lower electrode of a storage capacitor; and a drain disposed on the second conductive layer and electrically connected to the upper electrode of the storage capacitor.

[0016] In the display device, the passivation layer may be inserted between the lower electrode and the upper electrode of the storage capacitor.

[0017] In the display device, the embankment layer can be implemented in the display device as a striped pattern.

[0018] These embodiments can be implemented using a semi-embankment structure, which prevents light escape caused by the light-emitting elements in the light-emitting area.

[0019] Furthermore, these embodiments can improve optical efficiency by preventing the anode from overlapping with the data wiring in the semi-embankment structure. Attached Figure Description

[0020] The above and other objects, features and other advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 This is a block diagram illustrating the configuration of a display device according to one embodiment;

[0022] Figure 2 It shows Figure 1 A circuit view of an embodiment of the pixel shown;

[0023] Figure 3A and 3B These are views showing the planar layout of pixels according to one embodiment;

[0024] Figure 4 It is along Figure 3B A cross-sectional view taken by line I-I' in the middle;

[0025] Figure 5 This shows a cross-sectional view of a storage capacitor according to another embodiment;

[0026] Figures 6A to 6C It shows along Figure 3A The sectional views taken from lines II-II', III-III', and IV-IV'; and

[0027] Figure 7 This is a flowchart illustrating a method for manufacturing a display device according to one embodiment. Detailed Implementation

[0028] The embodiments will now be described with reference to the accompanying drawings. In this specification, if a constituent element (or region, layer, or portion, etc.) is described as "existing" on, "connected to" or "combined" with different constituent elements, it means that the constituent element can be directly connected / combined with different constituent elements, or a third constituent element can be arranged therein.

[0029] The same reference numerals refer to the same constituent elements. Furthermore, to effectively describe the technical content, the thickness, scale, and dimensions of the constituent elements are exaggerated in the accompanying drawings. The phrase "and / or" is used to include one or more combinations that may be defined by the relevant components.

[0030] The terms "first," "second," etc., can be used to describe various constituent elements, but should not impose any limitations on their meaning. These terms are only used to distinguish one constituent element from another. For example, without departing from the scope of the claimed invention, a first constituent element can be named a second constituent element. Similarly, a second constituent element can be named a first constituent element. Unless explicitly stated in the context, the indefinite article "a / an" is used to indicate one or more, not just one.

[0031] The terms “below,” “under,” “above,” and “on top,” etc., are used to describe the physical relationships between the constituent elements shown in the accompanying drawings. These terms have relative conceptual meanings and are used with reference to the directions indicated in the accompanying drawings.

[0032] It should be understood that the terms "comprising" and "having," etc., are intended to indicate the presence of the features, quantities, steps, operations, constituent elements, components, or combinations thereof described in this specification. Therefore, it should be understood that these terms do not preclude the possibility of the presence or addition of one or more other features, quantities, steps, operations, constituent elements, components, or combinations thereof.

[0033] Figure 1 This is a block diagram illustrating the configuration of a display device according to one embodiment.

[0034] refer to Figure 1 The display device 1 includes a timing controller 10, a gate driving unit 20, a data driving unit 30, a power supply unit 40, and a display panel 50.

[0035] The timing controller 10 can receive an image signal RGB and a control signal CS from an external source. The image signal RGB may include multiple color level data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a master clock signal.

[0036] The timing controller 10 can process the image signal RGB and the control signal CS in a manner suitable for the conditions of operating the display panel 50, and can generate and output image data DATA, gate drive control signal CONT1, data drive control signal CONT2 and power control signal CONT3.

[0037] The gate driving unit 20 can be connected to the pixel PX (or sub-pixel) of the display panel 50 via multiple first gate lines GL11 to GL1n. The gate driving unit 20 can generate a gate signal based on the gate driving control signal CONT1 output from the timing controller 10. The gate driving unit 20 can provide the generated gate signal to the pixel PX via the multiple first gate lines GL11 to GL1n.

[0038] In different embodiments, the gate driving unit 20 may be further connected to the pixels PX of the display panel 50 via multiple second gate lines GL21 to GL2n. The gate driving unit 20 may provide sensing signals to the pixels PX via the multiple second gate lines GL21 to GL2n. These sensing signals may be provided to measure the characteristics of the driving transistors and / or light-emitting elements provided within each pixel PX.

[0039] The data driving unit 30 can be connected to the pixel PX of the display panel 50 via multiple data lines DL1 to DLm. The data driving unit 30 can generate a data signal based on the image data DATA output from the timing controller 10 and the data driving control signal CONT2. The data driving unit 30 can provide the generated data signal to the pixel PX via multiple data lines DL1 to DLm.

[0040] In different embodiments, the data driving unit 30 may be further connected to the pixel PX of the display panel 50 via multiple sensing lines (or reference lines) SL1 to SLm. The data driving unit 30 may provide a reference voltage (or sensing voltage or initialization voltage) to the pixel PX via the multiple sensing lines SL1 to SLm, or it may sense the state of the pixel PX based on the electrical signal fed back from the pixel PX.

[0041] The power supply unit 40 can be connected to the pixels PX of the display panel 50 via multiple power lines PL1 and PL2. The power supply unit 40 can generate a driving voltage supplied to the display panel 50 based on the power control signal CONT3. As an example, this driving voltage may include a high-level driving voltage ELVDD and a low-level driving voltage ELVSS. The power supply unit 40 can supply the generated driving voltages ELVDD and ELVSS to the pixels PX respectively via the corresponding power lines PL1 and PL2.

[0042] Multiple pixels PX (or "subpixels") are arranged in the display panel 50. As an example, the pixels PX can be arranged in a matrix at the top of the display panel 50.

[0043] Each pixel PX can be electrically connected to a corresponding gate line and data line. Pixel PX can emit light with a brightness corresponding to the gate signal and data signal provided through the first gate lines GL11 to GL1n and the data lines DL1 to Dlm, respectively.

[0044] Each pixel PX can display one of the first to third colors. In one embodiment, each pixel PX can display one of red, green, and blue. In another embodiment, each pixel PX can display one of cyan, magenta, and yellow. In various embodiments, each pixel PX can be configured to display one of four or more colors. For example, each pixel PX can display one of red, green, blue, and white.

[0045] The timing controller 10, gate drive unit 20, data drive unit 30, and power supply unit 40 can be configured as separate integrated circuits (ICs), or at least one of these components can be configured to be combined with one or more other components (as a single integrated circuit). For example, at least one of the data drive unit 30 and power supply unit 40 can be configured to be integrated with the timing controller 10 (as a single integrated circuit).

[0046] In addition, Figure 1 In the illustration, the gate driving unit 20 and the data driving unit 30 are shown as constituent elements separate from the display panel 50. However, at least one of the gate driving unit 20 and the data driving unit 30 can be configured to be integrally formed with the display panel 50 using an in-panel method. For example, the gate driving unit 20 can be integrally formed with the display panel 50 using a gate in-panel (GIP) method.

[0047] Figure 2 It shows Figure 1 The diagram shows a circuit view of an embodiment of the pixels shown. As an example, Figure 2 A pixel Pxij is shown that is connected to the i-th first gate line GL1i and the j-th data line DLj.

[0048] refer to Figure 2 The pixel PX includes a switching transistor ST, a driving transistor DT, a sensing transistor SST, a storage capacitor Cst, and a light-emitting element LD.

[0049] The first electrode (e.g., the source) of the switching transistor ST is electrically connected to the j-th data line Dlj, and the second electrode (e.g., the drain) is electrically connected to the first node N1. The gate of the switching transistor ST is electrically connected to the i-th first gate line GL1i. When a gate signal at a gate-on level is applied to the i-th first gate line GL1i, the switching transistor ST is turned on, thereby transmitting the data signal applied to the j-th data line Dlj to the first node N1.

[0050] The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode is supplied with a high-potential drive voltage ELVDD. The storage capacitor Cst can be charged with a voltage corresponding to the difference between the voltage applied to the first node N1 and the high-potential drive voltage ELVDD.

[0051] The first electrode (e.g., the source) of the driving transistor DT is configured to be supplied with a high-potential driving voltage ELVDD, and the second electrode (e.g., the drain) is electrically connected to the first electrode (e.g., the anode) of the light-emitting element LD. The gate of the driving transistor DT is electrically connected to a first node N1. When a voltage at the gate conduction level is applied through the first node N1, the driving transistor DT is turned on, thereby allowing control over the amount of driving current flowing through the light-emitting element LD in a manner corresponding to the voltage supplied to the gate (i.e., the voltage stored in the storage capacitor).

[0052] The first electrode (e.g., source) of the sensing transistor SST is electrically connected to the j-th sensing line SLj, and the second electrode (e.g., drain) is electrically connected to the first electrode (e.g., anode) of the light-emitting element LD. The gate of the sensing transistor SST is electrically connected to the i-th second gate line GL2i. When a sensing signal at a gate-on level is applied to the i-th second gate line GL2i, the sensing transistor SST is turned on, thereby transmitting the reference voltage applied to the j-th sensing line SLj to the anode of the light-emitting element LD.

[0053] The light-emitting element (LD) outputs light corresponding to the driving current. The LD can output light corresponding to one of the colors white, red, green, and blue. The LD can be an organic light-emitting diode (OLED) or a micro-inorganic light-emitting diode with a micrometer to nanometer scale, and this disclosure is not limited to these diodes. The following describes embodiments resulting from the LD being configured with an organic light-emitting diode.

[0054] The structure of each pixel PX according to this disclosure is not limited to Figure 2 The structure shown. In one embodiment, pixel PX may further include at least one element for compensating the threshold voltage of the driving transistor DT or initializing the gate voltage of the driving transistor DT and / or the voltage of the anode of the light-emitting element LD.

[0055] exist Figure 2 The example shown is of a switching transistor ST, a driving transistor DT, and a sensing transistor SST being an NMOS transistor; however, this disclosure is not limited to this example. For instance, at least one transistor constituting each pixel PX may be configured to have a PMOS transistor. In various embodiments, each of the switching transistor ST, the driving transistor DT, and the sensing transistor SST may be implemented as a low-temperature polycrystalline silicon (LTPS) thin-film transistor, an oxide thin-film transistor, or a low-temperature polycrystalline oxide (LTPO) thin-film transistor.

[0056] Figure 3A and 3B These are views showing the planar layout of pixels according to one embodiment.

[0057] refer to Figures 3A to 3B as well as Figure 2 The display panel 50 includes a pixel region PXA. The pixel region PXA is defined by the area where a data line DL extending in a first direction DR1 (e.g., pixel column direction) intersects with first and second gate lines GL1 and GL2 extending in a second direction DR2 (e.g., pixel row direction). Pixels PX are respectively arranged in the pixel region PXA.

[0058] Each pixel region PXA may include a light-emitting region EA and a non-light-emitting region NEA. The light-emitting element LD of the pixel PX is arranged in the light-emitting region EA. Circuit elements for driving the light-emitting element LD (e.g., switching transistor ST, driving transistor DT, sensing transistor SST, and storage capacitor Cst) are arranged in the non-light-emitting region NEA. The light-emitting element LD can be driven by the circuit elements arranged in the non-light-emitting region NEA and can emit light of a specific color. The pixel region PXA may include an opening area that transmits light from the light-emitting element LD and displays an image externally. This opening area may be formed in a manner corresponding to a pixel PX displaying one of the colors red, green, blue, and white.

[0059] A wiring area WA can be defined between pixel columns. Data lines DL and sensing lines SL extending in the first direction DR1 are arranged in each wiring area WA. Data signals from the data driving unit 30 can be applied to the data lines DL. A reference voltage from the data driving unit 30 can be applied to the sensing lines SL, or the sensing lines SL can transmit electrical signals output by the corresponding pixel PX to the data driving unit 30.

[0060] In one embodiment, a first power line PL1 may be further formed in one or more wiring regions WA. The first power line PL1 is used to apply a high-potential drive voltage ELVDD to the pixel PX. The first power line PL1 may extend in a first direction DR1 in a manner substantially parallel to the data line DL and the sensing line SL.

[0061] The first gate line GL1 and the second gate line GL2 extend along the second direction DR2 and pass through the non-light-emitting region NEA. In this case, the first gate line GL1 and the second gate line GL2 can be arranged to be spaced a predetermined distance along the first direction DR1.

[0062] Data line DL, sensing line SL, first power line PL1, first gate line GL1, and second gate line GL2 can be electrically connected to circuit elements via contact holes. Specifically, data line DL can be electrically connected to one electrode (e.g., the source) of switching transistor ST, and sensing line SL can be electrically connected to one electrode (e.g., the source) of sensing transistor SST. First gate line GL1 is electrically connected to the gate of switching transistor ST, and second gate line GL2 is electrically connected to the gate of sensing transistor SST.

[0063] For reference Figure 2 The pixel PX described may include a switching transistor ST, a driving transistor DT, a sensing transistor SST, a storage capacitor Cst, and a light-emitting element LD.

[0064] The switching transistor ST may include a first gate GE1, a first source SE1, and a first drain DE1.

[0065] The first gate GE1 may be arranged to overlap with the first channel CH1 formed in the active layer ACT. The first channel CH1 may be a semiconductor pattern inside the active layer ACT that is undoped. The first gate GE1 may be electrically connected to the first gate line GL1. For example, the first gate GE1 may be a region that overlaps with the first channel CH1 in the first gate line GL1.

[0066] The first source SE1 can be connected to the first source region SA1 formed on one side of the first channel CH1 of the active layer ACT. The first source SE1 can be further connected to the data line DL through the first contact hole CT1.

[0067] The first drain DE1 can be connected to the first drain region DA1 formed on the other side of the first channel CH1 of the active layer ACT. The first drain DE1 can be electrically connected to the lower electrode BE of the storage capacitor Cst through the second contact hole CT2.

[0068] The driving transistor DT may include a second gate GE2, a second source SE2, and a second drain DE2.

[0069] The second gate GE2 can be arranged to overlap with the second channel CH2 formed in the active layer ACT. The second gate GE2 can be electrically connected to the lower electrode BE of the storage capacitor Cst through the third contact hole CT3.

[0070] The second source SE2 can be connected to a second source region SA2 formed on one side of the second channel CH2 in the active layer ACT. The second source SE2 can be electrically connected to the first power line PL1, which is subjected to a high-potential drive voltage ELVDD, through the fourth contact hole CT4. In this embodiment, the second source SE2 can be configured as a conductive pattern substantially provided on the wiring region WA.

[0071] The second drain DE2 can be connected to the second drain region DA2 formed on the other side of the second channel CH2 of the active layer ACT. The second drain DE2 can be electrically connected to the upper electrode UE through the storage capacitor Cst. For example, the second drain DE2 can be integrally formed with the upper electrode UE of the storage capacitor Cst, and thus can form a pattern. As described below, the upper electrode UE2 of the storage capacitor Cst is connected to the anode AE ​​of the light-emitting element LD through the first via VIA1. Therefore, the second drain DE2 of the driving transistor DT is electrically connected to the anode AE ​​of the light-emitting element LD via the upper electrode UE of the storage capacitor Cst.

[0072] Furthermore, the second drain DE2 can be connected to the light-blocking layer LS through the fifth contact hole CT5. Accordingly, when a defective pixel PX is repaired using the repair pattern RP, the repair pattern RP and the light-blocking layer LS are connected to each other by laser welding, thereby electrically connecting the anode AEj of the adjacent pixel Px(i+1) to the second drain DE2 of the driving transistor DT.

[0073] The sensing transistor SST may include a third gate GE3, a third source SE3, and a third drain DE3.

[0074] The third gate GE3 can be arranged to overlap with the third channel CH3 formed in the active layer ACT. The third gate GE3 can be electrically connected to the second gate line GL2. For example, the third gate GE3 can be a region that overlaps with the third channel CH3 in the second gate line GL2.

[0075] The third source electrode SE3 can be connected to the third source region SA3 formed on one side of the third channel CH3 of the active layer ACT. The third source electrode SE3 can be electrically connected to the bridging pattern BRP through the sixth contact hole CT6. The bridging pattern BRP is electrically connected to the sensing line SL through the eighth contact hole CT8. Thus, the third source electrode SE3 can be connected to the sensing line SL through the bridging pattern BRP.

[0076] The third drain DE3 can be connected to the third drain region DA3 formed on the other side of the third channel CH3 of the active layer ACT. Furthermore, the third drain DE3 can be connected to the light-blocking layer LS through the seventh contact hole CT7. According to this embodiment, the light-blocking layer LS is connected to the second drain DE2 of the driving transistor DT through the fifth contact hole CT5. Thus, the third drain DE3 is electrically connected to the second drain DE2 of the driving transistor DT through the light-blocking layer LS.

[0077] The storage capacitor Cst may include a lower electrode BE and an upper electrode UE.

[0078] The lower electrode BE can be electrically connected to the first drain DE1 of the switching transistor ST through the second contact hole CT2. Furthermore, the lower electrode BE can be electrically connected to the second gate GE2 of the driving transistor DT through the third contact hole CT3.

[0079] In one embodiment, the lower electrode BE may include an extension EXT necessary for connection to the second gate GE2 of the driving transistor DT. The lower electrode BE overlaps with the second gate GE2 in a region of the extension EXT and is electrically connected to the second gate GE2 through a third contact hole CT3.

[0080] At least one region of the upper electrode UE is formed to cover the lower electrode BE. A potential corresponding to the potential difference between the opposing electrodes can be stored between the upper electrode UE and the lower electrode BE, and thus the upper electrode UE and the lower electrode BE can function as a storage capacitor Cst.

[0081] The corresponding overlapping area of ​​the upper electrode UE and the lower electrode BE can determine the capacitance of the storage capacitor Cst. Therefore, the upper electrode UE and the lower electrode BE can have an area (size) that satisfies the required capacitance of the storage capacitor Cst.

[0082] The upper electrode UE can be electrically connected to the second drain DE2 of the driving transistor DT through the fifth contact hole CT5. Furthermore, the upper electrode UE can be electrically connected to the anode AE ​​of the light-emitting element LD through the first through hole VIA1.

[0083] As described above, the storage capacitor Cst is connected to the second gate GE2 of the driving transistor DT via its lower electrode BE. The cathode CE of the light-emitting element LD, described below, can be formed on top of the driving transistor DT. In this case, an electric field is formed between the second gate GE2 of the driving transistor DT and the cathode CE, thereby reducing the charging rate of the storage capacitor Cst electrically connected to the second gate GE2. In other words, a parasitic capacitance may be formed, where one electrode of the parasitic capacitance is the second gate GE2 and the other electrode is the cathode CE. According to this embodiment, if the second gate GE2 is electrically connected to the lower electrode BE of the storage capacitor Cst instead of the upper electrode UE, the electrical path from the parasitic capacitance to the storage capacitor Cst is arranged relatively far, thereby reducing the effect of the parasitic capacitance. Furthermore, the lower electrode BE of the storage capacitor Cst is formed on top of the substrate of the display panel 50. This prevents the formation of an electric field between the second gate GE2 and the cathode CE, thereby eliminating the parasitic capacitance.

[0084] The light-emitting element LD may include an anode AE, a cathode CE, and a light-emitting layer EML disposed between the anode AE ​​and the cathode CE. In one embodiment, the anode AE, the light-emitting layer EML, and the cathode CE may be arranged in a manner that allows them to be in direct contact with each other in the light-emitting region EA.

[0085] The anode AE ​​can be connected to the upper electrode UE of the storage capacitor Cst through the first through-hole VIA1. In the non-light-emitting region NEA described below, a dam layer BNK, a light-emitting layer EML, and a cathode CE can be disposed on top of the anode AE. In most cases, the anode AE ​​is formed in the light-emitting region EA. However, at least one region of the anode AE ​​can extend into the non-light-emitting region NEA so that the anode AE ​​contacts the upper electrode UE of the storage capacitor Cst.

[0086] In the luminescent region EA and the non-luminescent region NEA, a light-emitting layer EML and a cathode CE are widely formed, and in this case, the light-emitting layer EML covers the anode AE.

[0087] In one embodiment, pixel PX may further include a repair pattern RP. A region of the repair pattern RP is arranged to overlap with the light-blocking layer LS rather than with the anode AE ​​of the adjacent pixel PX(i+1)j.

[0088] In this case, another area of ​​the repair pattern RP is electrically connected to the anode AE ​​of the adjacent pixel Px(i+1)j through the second via VIA2. In order to be electrically connected to the anode AE ​​of the adjacent pixel Px(i+1)j, the repair pattern RP can be arranged inside the non-light-emitting area NEA close to the anode AE ​​of the adjacent pixel Px(i+1)j.

[0089] Since the repair pattern RP is arranged close to the anode AE ​​of the adjacent pixel Px(i+1)j inside the non-light-emitting region NEA, the light-blocking layer LS arranged in a manner that overlaps with a region of the repair pattern RP can have an area that extends extensively from the portion of it that overlaps with the driving transistor DT to said region of the repair pattern RP.

[0090] The repair pattern RP described above can have an island-shaped electrode in the form of a strip that generally extends along the second direction DR2. However, the repair pattern RP is not limited to this shape, and its shape can vary widely depending on the arrangement of other constituent elements, including the light-blocking layer LS and the anode AE, relative to each other.

[0091] exist Figure 3A and 3B The example shown is a display device 1 having a WRGB structure including a white pixel W. However, the above embodiments are not limited to display device 1 having a WRGB structure. That is, in the above embodiments, various features unrelated to the white pixel W can be applied in display devices having an RGB structure or an RGBG structure that does not include a white pixel W. Furthermore, in the above embodiments, different features associated with the white pixel W can be applied in display devices having different structures including white pixels as well as in display device 1 having a WRGB structure.

[0092] The following description, with reference to the accompanying drawings, details the stacking structure (cross-sectional structure) of pixels PX according to one embodiment.

[0093] Figure 4 This is a cross-sectional view of pixels according to one embodiment. Specifically, Figure 4 It is along Figure 3B The cross-sectional view taken from line I-I' in the diagram.

[0094] refer to Figure 4 as well as Figure 3A and 3B The display panel 50 may include a substrate SUB, a circuit element layer, and a light-emitting element layer.

[0095] The substrate SUB serves as the base substrate of the display panel 50 and can be a transparent substrate. The substrate SUB can be a rigid substrate made of glass or tempered glass, or a flexible substrate made of plastic materials. For example, the substrate SUB can be formed from plastic materials such as polyimide, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polycarbonate (PC). However, the substrate SUB is not limited to these materials.

[0096] A pixel region PXA is defined on the top of the substrate SUB. The pixel region PXA can be defined as a region comprising at least one circuit element disposed on a circuit element layer and a light-emitting element LD disposed on a light-emitting element layer. At least one circuit element and at least one light-emitting element LD can constitute a pixel PX.

[0097] The circuit element layer may include circuit elements (such as switching transistors ST, driving transistors DT, sensing transistors SST, and storage capacitors Cst, etc.) and wiring lines formed on top of the substrate SUB to constitute the pixel PX.

[0098] First, a first conductive layer may be disposed on top of the substrate SUB. This first conductive layer may include a light-blocking layer LS and the lower electrode BE of the storage capacitor Cst.

[0099] The light-blocking layer LS can be arranged to overlap with the semiconductor pattern of the driving transistor DT (specifically, the second channel CH2 in the plane), thereby protecting the oxide semiconductor element from external light. In one embodiment, the light-blocking layer LS can be further connected to the second drain DE2 of the driving transistor DT through a fifth contact hole CT5. Accordingly, when a defective pixel PX is repaired using a repair pattern RP, the repair pattern RP and the light-blocking layer LS are laser-welded together, thereby electrically connecting the anode AE ​​of adjacent pixel Px(i+1)j and the second drain DE2 of the driving transistor DT to each other.

[0100] The lower electrode BE can be electrically connected to the first drain DE1 of the switching transistor ST through the second contact hole CT2. Furthermore, the lower electrode BE can be electrically connected to the second gate GE2 of the driving transistor DT through the third contact hole CT3.

[0101] In one embodiment, the lower electrode BE may include an extension EXT required for connection to the second gate GE2 of the driving transistor DT. The lower electrode BE overlaps with the second gate GE2 in a region of the extension EXT and is electrically connected to the second gate GE2 via a third contact hole CT3. Other regions of the extension EXT are configured not to overlap with other electrodes of the circuit elements or the anode AE ​​of the light-emitting element LD. Accordingly, when repairing defective pixels PX by laser cutting the extension EXT and thereby electrically separating the second gate GE2 and the anode AE, electrical short circuits between other electrodes and / or between the anode AE ​​and cathode CE of the light-emitting element LD can be prevented.

[0102] The first conductive layer may further include a data line DL, a sensing line SL, and a first power line PL1 located in the wiring region WA. The data line DL is connected to the first source SE1 of the switching transistor ST through a first contact hole CT1. The sensing line SL is connected to the third source SE3 of the sensing transistor SST through a bridging pattern BRP. The first power line PL1 is connected to the second source SE2 of the driving transistor DT through a fourth contact hole CT4.

[0103] In different embodiments, wiring and / or electrodes (not shown) may be further provided on top of the substrate SUB, such as a second power line PL2 for applying a low-potential drive power supply ELVSS and auxiliary electrodes, etc.

[0104] A buffer layer BUF is disposed on top of the substrate SUB, covering the light-blocking layer LS, the lower electrode BE of the storage capacitor Cst, and the wiring. This buffer layer BUF prevents ions and impurities from diffusing from the substrate SUB and blocks water penetration. Furthermore, the buffer layer BUF improves the surface flatness of the substrate SUB. The buffer layer BUF can comprise inorganic materials (e.g., oxides or nitrides), organic materials, or organic or inorganic compounds, and can be formed in a single-layer or multi-layer structure. For example, the buffer layer BUF can have a three-layer structure, comprising a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer, or it can have a four-layer or more structure. In another embodiment, the buffer layer BUF may be omitted.

[0105] An active layer ACT can be formed on top of the buffer layer BUF. This active layer ACT can be formed from a silicon-based semiconductor material or an oxide-based semiconductor material. The silicon-based semiconductor material can be amorphous silicon or polycrystalline silicon. The oxide-based semiconductor material can be a four-element metal oxide, such as indium tin gallium zinc oxide (InSnGaZnO). Furthermore, as an oxide-based semiconductor material, a three-element metal oxide can be used, such as indium gallium zinc oxide (InGaZnO), indium tin zinc oxide (InSnZnO), indium aluminum zinc oxide (InAlZnO), tin gallium zinc oxide (SnGaZnO), aluminum gallium zinc oxide (AlGaZnO), or tin aluminum zinc oxide (SnAlZnO). Furthermore, oxide-based semiconductor materials can be based on two-element metal oxides, such as indium zinc oxide (InZnO), zinc tin oxide (SnZnO), zinc aluminum oxide (AlZnO), zinc magnesium oxide (ZnMgO), magnesium tin oxide (SnMgO), indium magnesium oxide (InMgO), or indium gallium oxide (InGaO). Additionally, oxide-based semiconductor materials can be indium oxide (InO), tin oxide (SnO), or zinc oxide (ZnO), etc.

[0106] The active layer ACT may include first to third source regions SA1 to SA3, first to third drain regions DA1 to DA3, and first to third channels CH1 to CH3. The first to third source regions SA1 to SA3 and the first to third drain regions DA1 to DA3 contain p-type or n-type impurities. The first channel CH1 is formed between the first source region SA1 and the first drain region DA1. The second channel CH2 is formed between the second source region SA2 and the second drain region DA2. The third channel CH3 is formed between the third source region SA3 and the third drain region DA3.

[0107] A second conductive layer is disposed on top of the active layer ACT. A gate insulating layer GI can be inserted between the active layer ACT and the second conductive layer. The gate insulating layer GI can be a silicon oxide (SiOx) layer, a silicon oxide (SiNx) layer, or a combination of these layers.

[0108] The second conductive layer may include gates GE1, GE2, and GE3, sources SE1, SE2, and SE3, and drains DE1, DE2, and DE3. Gates GE1, GE2, and GE3 may be arranged in an overlapping manner on top of the corresponding channels CH1, CH2, and CH3 of the active layer ACT. At least one electrode (e.g., electrodes GE1 and GE3 in gates GE1, GE2, and GE3) may be integrally formed with wirings GL1 and GL2 electrically connected to electrodes GE1 and GE3, respectively, and thereby form a pattern.

[0109] The second conductive layer may further include an upper electrode UE of a storage capacitor Cst. At least one region of the upper electrode UE is formed to cover the lower electrode BE. A potential corresponding to the potential difference between the opposing electrodes can be stored between the upper electrode UE and the lower electrode BE, and thus the upper electrode UE and the lower electrode BE can function as a storage capacitor Cst.

[0110] The upper electrode UE can be electrically connected to the second drain DE2 of the driving transistor DT through the fifth contact hole CT5. Furthermore, the upper electrode UE can be electrically connected to the anode AE ​​of the light-emitting element LD through the first through hole VIA1.

[0111] As described above, the storage capacitor Cst is connected to the second gate GE2 of the driving transistor DT via its lower electrode BE. The cathode CE of the light-emitting element LD can be formed on top of the driving transistor DT. In this case, an electric field is formed between the second gate GE2 and the cathode CE of the driving transistor DT, thereby reducing the charging rate of the storage capacitor Cst electrically connected to the second gate GE2. In other words, a parasitic capacitance may form where one electrode is the second gate GE2 and the other is the cathode CE. According to this embodiment, when the second gate GE2 is electrically connected to the lower electrode BE of the storage capacitor Cst instead of the upper electrode UE, the electrical path from the parasitic capacitance to the storage capacitor Cst is arranged relatively far, thereby reducing the impact of the parasitic capacitance. Furthermore, the lower electrode BE of the storage capacitor Cst is formed on top of the substrate of the display panel 50. This prevents the formation of an electric field between the second gate GE2 and the cathode CE, thereby eliminating the parasitic capacitance.

[0112] The second conductive layer may further include a bridging pattern BRP. This bridging pattern BRP can electrically connect the third source SE3 of the sensing transistor SST to the sensing line SL.

[0113] The second conductive layer may further include a repair pattern RP. One region of the repair pattern RP is arranged to overlap with the light-blocking layer LS rather than with the anode AE ​​of the adjacent pixel PX(i+1)j. In this case, another region of the repair pattern RP is electrically connected to the anode AE ​​of the adjacent pixel Px(i+1)j through a second via VIA2.

[0114] The first and second conductive layers can be formed from an element selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or from an alloy of these elements. Furthermore, the first and second conductive layers can be multilayered, with each layer formed from an element selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or from an alloy of these elements. As an example, the first and second conductive layers can be bilayered, with each layer formed from molybdenum / aluminum-neodymium or molybdenum / aluminum.

[0115] The circuit element layer can be covered by a passivation layer PAS. The passivation layer PAS can cover the corresponding exposed areas of the second conductive layer, the buffer layer BUF, and the active layer ACT, where the exposed areas are not covered by the second conductive layer. The passivation layer PAS acts as an insulating film protecting the underlying components and can be a silicon oxide film (SiOx), a silicon nitride film, or multiple layers composed of these films. In different embodiments, the passivation layer PAS can be omitted.

[0116] An outer coating OC can be formed on top of the passivation layer PAS. This outer coating OC can be a flat film used to reduce the height difference in the underlying structure, and can be formed from organic materials such as polyimide, benzocyclobutene series resins, or acrylates.

[0117] In one embodiment, a color filter (not shown) may be formed between the passivation layer PAS and the capping layer OC. This color filter may be formed within the emitting region EA. A color filter is a wavelength-selective filter that selectively transmits incident light within a specific wavelength band by transmitting light in a specific band and blocking light in another specific band, and may be formed from a photosensitive resin containing a colorant (e.g., pigment or dye). Light passing through the color filter in the emitting region EA may have one of the colors red, green, and blue. If pixel PX displays white, then the color filter for that pixel PX may be omitted.

[0118] As described above, the color filter is formed between the passivation layer PAS and the protective layer OC; however, this embodiment is not limited to this location. That is, if the light-emitting element LD is a front-surface emitting type, then the color filter can be formed on the upper layer of the light-emitting element layer.

[0119] The light-emitting element layer is formed on top of the outer coating OC and includes the light-emitting element LD. The light-emitting element LD includes an anode AE, a light-emitting layer EML, and a cathode CE.

[0120] At least one of the anode AE ​​and cathode CE can be a transmission electrode, and at least the other can be a reflection electrode. For example, if the light-emitting element LD is a back-emitting type, then the anode AE ​​can be a transmission electrode, and the cathode CE can be a reflection electrode. Conversely, if the light-emitting element LD is a front-surface emitting type, then the anode AE ​​can be a reflection electrode, and the cathode CE can be a transmission electrode. In another embodiment, if the light-emitting element LD is a double-sided emitting type, then both the anode AE ​​and the cathode CE can be transmission electrodes. The detailed configuration of the light-emitting element LD will be described below using the case of a back-emitting type as an example.

[0121] The anode AE ​​is formed on top of the outer coating OC. This anode AE ​​is electrically connected to the upper electrode UE of the storage capacitor Cst via a first via VIA1 passing through the outer coating OC and the passivation layer PAS. This anode AE ​​can also be electrically connected to the second drain DE2 of the drive transistor DT via the storage capacitor Cst. By forming the first via VIA1 as described above in contact with the upper electrode UE of the storage capacitor Cst, which has a larger area compared to the other electrodes, the effects of the height difference near the first via VIA1 can be reduced.

[0122] The anode AE ​​can be formed of a transparent conductive material, such as indium tin oxide (ITO) or zinc oxide (ZnO). If the anode AE ​​is a reflective electrode, then the anode AE ​​may include a reflective layer. This reflective layer can be formed of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or alloys thereof. In one embodiment, the reflective layer can be formed of APC (silver / palladium / copper alloy).

[0123] In the non-luminescent region NEA, a levee layer BNK is formed on top of the anode AE. However, the luminescent layer EML is formed on top of the anode AE ​​in the luminescent region EA in a manner that is in direct contact with the anode AE. That is, the levee layer BNK has a semi-levee structure that covers the non-luminescent region NEA but does not cover the luminescent region EA.

[0124] As an example, for a structure in which the embankment layer BNK is provided in all areas of the substrate SUB, including the light-emitting area EA and the non-light-emitting area NEA, the manufacturing cost will increase, and the overall opening ratio of the display panel 50 will decrease. Conversely, for a structure without any embankment, color mixing may occur, where different colors of light emitted from one pixel PX and another adjacent pixel PX in the light-emitting area EA will be output in a mixed manner. Therefore, according to this disclosure, a half-embankment structure is used, in which the embankment layer BNK covers the non-light-emitting area NEA but does not cover the light-emitting area EA.

[0125] Specifically, in the light-emitting region EA, where multiple pixels PX are arranged in a row, the embankment layer BNK is not arranged in the pixel column direction. However, in the non-light-emitting region NEA, which is located below the light-emitting region EA and has a circuit element layer arranged therein, the embankment layer BNK is arranged along the pixel column direction. Subsequently, in the light-emitting region EA, which is located below the non-light-emitting region NEA and has a circuit element layer arranged therein, the embankment layer BNK is not arranged along the pixel column direction. However, in the non-light-emitting region NEA, which is located below the light-emitting region EA and has a circuit element layer arranged therein, the embankment layer BNK is arranged along the pixel column direction. As a result, on the display device 1, the embankment layer BNK is implemented as a striped pattern.

[0126] In one embodiment, the area not covered by the embankment layer BNK can be defined as the luminescent area EA. In the non-luminescent area NEA, the embankment layer BNK can cover the corresponding exposed areas of the anode AE ​​and the outer coating OC. In this embodiment, the first through-hole VIA1 formed in the non-luminescent area NEA is filled with the embankment layer BNK.

[0127] The dam layer BNK can contain organic materials, such as benzocyclobutene (BCB)-based materials or polyimide (Pi)-based materials. In one embodiment, the dam layer BNK can be formed from a photosensitive material containing black pigment. In this case, the dam layer BNK can function as a light-blocking member (or black matrix).

[0128] An emissive layer (EML) is extensively formed in the luminescent region EA and the non-luminescent region NEA. In the luminescent region EA, the EML is formed by covering the anode. In the non-luminescent region NEA, the EML is formed on top of the embankment layer BNK. In one embodiment, the EML may have a multilayer thin-film structure including a light-generating layer. In this case, the color of the light generated in the light-generating layer can be white, red, blue, green, etc. However, the light is not limited to these colors.

[0129] For example, the light-generating layer may include a hole transport layer (HTL), an organic light-emitting layer (OLED), and an electron transport layer (ETL). The hole transport layer serves to smoothly transport holes injected from the anode (AE) to the OLED. The OLED can be formed of an organic material containing phosphors or fluorescent materials. The electron transport layer serves to smoothly transport electrons injected from the cathode (CE) to the OLED. In addition to the hole transport layer, OLED, and electron transport layer, the light-emitting layer (EML) may also include a hole injection layer (HIL), a hole blocking layer (HBL), an electron injection layer (EIL), and an electron blocking layer (EBL).

[0130] The formed luminescent layer (EML) can have two or more stacked tandem structures. In this case, each stack can include a hole transport layer, an organic luminescent layer, and an electron transport layer. If the formed EML has two or more stacked tandem structures, a potential generation layer can be formed between these stacks. This potential generation layer can include an n-type potential generation layer and a p-type potential generation layer. The n-type potential generation layer is adjacent to the lower stack. The p-type potential generation layer is formed on top of the n-type potential generation layer, adjacent to the upper stack. The n-type potential generation layer injects electrons into the lower stack, while the p-type potential generation layer injects holes into the upper stack. The n-type potential generation layer can be an organic layer obtained by doping an electron-transporting organic host material with an alkali metal (e.g., lithium (Li), sodium (Na), potassium (K), or cesium (Cs)) or an alkaline earth metal (e.g., magnesium (Mg), strontium (Sr), barium (Ba), or radium (Ra)). The p-type potential generation layer can be an organic layer generated by doping an electron-transporting organic host material with a dopant.

[0131] A cathode (CE) is formed on top of the light-emitting layer (EML). This cathode (CE) can be widely formed in the light-emitting region (EA) and the non-light-emitting region (NEA).

[0132] The cathode (CE) can be formed from either a transparent conductive material (TCO) that transmits light or a semi-transmissive conductive material, such as molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or their alloys. If the cathode (CE) is formed from a semi-transmissive conductive material, then a microcavity can be used to improve the light output efficiency.

[0133] refer to Figure 4 as well as Figure 3A and 3B According to this embodiment, at least one region of the anode AE ​​extends into the non-light-emitting region NEA so that the anode AE ​​comes into contact with the circuit elements. Because the embankment layer BNK covers the entire region of the anode AE ​​in the non-light-emitting region NEA, light escape in the non-light-emitting region NEA can be prevented.

[0134] In this embodiment, a light-absorbing layer LA is further included between the light-passivating layer PAS and the outer coating OC. The light-absorbing layer LA may include a colorant, such as a pigment or dye, that selectively transmits light in a specific wavelength band and blocks light in another specific wavelength band. To absorb the light generated in the light-emitting element LD, the light-absorbing layer LA may have a structure in which at least two pigment layers are stacked on top of each other. For example, the light-absorbing layer LA may include a first absorption layer and a second absorption layer. The first absorption layer contains a pigment of a first color. The second absorption layer contains a pigment of a second color different from the first color. In one embodiment, the first color may be red and the second color may be blue. However, the first and second absorption layers are not limited to these colors. When absorption layers containing different colored pigments as described above overlap, light escape phenomena (e.g., black visibility effect) can be effectively prevented by the reflection visibility effect.

[0135] As described above, the light-absorbing layer LA can be formed from the same material as the color filter and can be formed using the same process as the color filter. That is, a color filter with pigments of the same color and the light-absorbing layer LA can be formed together using a single masking process. For example, when forming a color filter containing a first-color pigment, the first absorption layer of the light-absorbing layer LA can be formed together, and when forming a color filter containing a second-color pigment, the second absorption layer of the light-absorbing layer LA can be formed together. Therefore, according to this embodiment, light escape from the non-emitting region NEA can be more completely prevented without requiring a separate additional process to produce the light-absorbing layer LA.

[0136] The light-absorbing layer LA can be formed throughout the entire non-emitting region NEA. However, this embodiment is not limited to this location. Depending on how this embodiment is implemented, the light-absorbing layer LA can be formed on top of the anode AE ​​inside the non-emitting region NEA. In one embodiment, if pixel PX displays white, then the light-absorbing layer LA is not formed on the corresponding pixel PX.

[0137] When the light-absorbing layer LA is formed throughout the non-emitting region NEA, the first via VIA1 and the second via VIA2 can be formed in a manner that passes through the light-absorbing layer LA. Alternatively, the light-absorbing layer LA can be configured not to be formed near each of the first via VIA1 and the second via VIA2.

[0138] Figure 5 This is a cross-sectional view of a storage capacitor according to another embodiment.

[0139] For reference Figure 4 as well as Figure 3A and 3B In one embodiment, the storage capacitor Cst may be configured to have a lower electrode BE formed on a first conductive layer and an upper electrode UE formed on a second conductive layer. A buffer layer BUF and a gate insulating layer GI are inserted between the lower electrode BE and the upper electrode UE.

[0140] When two insulating layers are inserted between the lower electrode BE and the upper electrode, the distance between the upper and lower electrodes BE and UE is relatively large, which reduces the capacitance of the storage capacitor Cst. The corresponding areas of the lower electrode BE and the upper electrode UE need to be increased to ensure the required capacitance. However, the larger the area of ​​the storage capacitor Cst, the larger the size of the pixel PX. This makes it difficult to achieve a high-resolution display device. Furthermore, if the pixel PX displays white, it will be difficult to ensure the aperture ratio.

[0141] To address these issues, in one embodiment, the upper electrode UE of the storage capacitor Cst may have a multilayer structure with an active layer ACT overlapping a second conductive layer TGA. In this case, a buffer layer BUF is inserted between the lower electrode BE and the upper electrode UE.

[0142] and Figure 4 Compared to the embodiments shown, in Figure 5 In the illustrated embodiment, only an insulating layer is inserted between the lower electrode BE and the upper electrode UE of the storage capacitor Cst, thereby relatively reducing the distance between the electrodes. Accordingly, the capacitance of the storage capacitor Cst can be increased. This prevents an increase in the area of ​​the storage capacitor Cst. As a result, the size of the pixel PX can be significantly reduced while ensuring a high aperture ratio.

[0143] Figures 6A to 6CBoth show cross-sectional views of pixels according to one embodiment. Specifically, Figures 6A to 6C They are along Figure 3A The cross-sectional view taken from lines II-II', III-III' and IV-IV'.

[0144] refer to Figure 3A , 3B In order to display the colors required for the pixels, the light generated in the light-emitting element LD needs to be emitted to the outside of the display panel 50 through various color filters. However, in the pixel area with the structure in the related art, the light is reflected by the cathode CA overlapping with the embankment layer BNK, which may cause the light to escape into adjacent pixel areas.

[0145] Many events that occur during the manufacturing process of the display panel 50 can lead to this light escape phenomenon. In one embodiment, light escape occurs when the pigment of the color filter is positioned further inward in the pixel direction than normally in a pixel displaying one of the colors red, blue, and green; when the outer coating OC has a thickness greater than normal; or when the embankment layer BNK is positioned further outward in the pixel direction than normally.

[0146] The events that occur when the color filter, the overlay layer OC, and the embankment layer BNK are stacked on top of each other have been described above, and this embodiment is not limited to these events.

[0147] To improve light escape and color mixing phenomena in pixel areas, in one embodiment, pixels displaying red, white, blue, and green can have respectively... Figures 6A-6C The structure shown in the figure.

[0148] Specifically, regarding Figures 6A to 6C The outer coating OC is extensively formed in the luminescent region EA in the form of pigments covering color filters that display red, blue, and green, respectively. (Compared to...) Figure 4 Compared to the non-luminous region NEA in the pixel, the embankment layer BNK is removed from the luminous region EA of the pixel.

[0149] In one embodiment, the outer coating OC formed in the light-emitting region EA has a thickness that varies with the color filter CF. Compared to the outer coating OC in the region where the color filter CF is arranged between the outer coating OC and the passivation layer PAS, the outer coating OC formed in the region where the color filter CF is not arranged has a greater thickness.

[0150] After the outer coating OC is formed, the anodized AE can be patterned. The anodized AE for each pixel is formed on top of the outer coating OC in each pixel area that displays red, white, blue, and green respectively. In a pixel, except for white pixel W, in each area of ​​red pixel R, blue pixel B, and green pixel G, color filters and anodized AEs for displaying each color can be arranged in an overlapping manner, with the outer coating inserted in between.

[0151] According to this embodiment, the anode is arranged in a manner that does not overlap with the data line DL or the sensing line SL arranged along the edge of the light-emitting region EA. In the related art, the data line DL or the sensing line SL overlaps with the anode AE, and current is consumed in the area where the anode AE ​​overlaps with the data line DL or the sensing line SL, but this area cannot be used as the light-emitting region EA. As a result, the overall luminous efficiency is reduced.

[0152] To improve the light efficiency of the light-emitting region EA, according to this embodiment, the anode AE ​​is arranged in a manner that does not overlap with the data line DL arranged along the edge of the light-emitting region EA. In one embodiment, the anode AEs of the red pixel R, white pixel W, blue pixel B, and green pixel G can be arranged at the same distance L from the adjacent data line DL or sensing line SL, without overlapping with the adjacent data line DL or sensing line SL.

[0153] After the anode (AE) is formed, the light-emitting layer (EML) and the cathode (CE) are stacked sequentially on top of each other. The light-emitting layer (EML) and the cathode (CE) can be extensively formed on the top of the display panel 50.

[0154] The light-emitting layer (EML) can have a multilayer thin-film structure including a light-generating layer. In this case, the color of the light generated in the light-generating layer can be white, red, blue, green, etc. However, the light is not limited to these colors.

[0155] The cathode (CE) can be widely disposed on top of the display panel 50. In one embodiment, the light-emitting layer (EML) can be formed using an evaporation deposition method. Alternatively, the cathode (CE) can be formed using a physical vapor deposition method, such as sputtering. However, this embodiment is not limited to these methods.

[0156] refer to Figure 6A Light emitted from the light-emitting electrode LD of the red pixel R is reflected by the cathode CE, thus propagating towards the lower part of the display panel 50. Due to the curved edges of the light-emitting area EA caused by the thickness variation of the outer coating OC, the reflected light is blocked from reaching the adjacent white pixel W.

[0157] refer to Figure 6BLight emitted from the light-emitting element LD of the white pixel W is reflected by the cathode CE, thus propagating towards the lower part of the display panel 50. Due to the curved edges of the light-emitting area EA caused by the thickness variation of the outer coating OC, the reflected light is blocked from reaching the adjacent blue pixel B.

[0158] refer to Figure 6C The light emitted from the light-emitting element LD of the blue pixel B is reflected by the cathode CE, and thus propagates to the lower part of the display panel 50. Due to the curvature of the light-emitting area EA caused by the thickness variation of the outer coating OC, the reflected light is blocked from reaching the adjacent green pixel G.

[0159] As described above, in the display panel 50 according to one embodiment, by eliminating the embankment layer BNK in the light-emitting region EA, the phenomenon of light escaping into adjacent pixel regions can be improved. Simultaneously, by arranging the anodes AE of the pixels in a manner that does not overlap with the data lines DL or the sensing lines SL, the overall light efficiency can be improved.

[0160] Figure 7 This is a flowchart illustrating a method for manufacturing a display device according to one embodiment. Specifically, Figure 7 A reference is shown. Figure 4 and Figure 5 The method described is for displaying the pixel PXij on the display panel 50.

[0161] refer to Figure 7 as well as Figure 3A , 3B First, a circuit element layer can be formed on top of the substrate SUB. Specifically, a first conductive layer (1501) can be formed on top of the substrate SUB. A conductive film is formed on top of the substrate using processes such as printing, sputtering, chemical vapor deposition, pulsed laser deposition (PLD), vacuum deposition, and atomic layer deposition. Then, the conductive film is patterned using an etching process with a mask to form the first conductive layer. A first mask can be used at this time.

[0162] Subsequently, a buffer layer BUF (1502) can be formed on top of the first conductive layer. The buffer layer BUF can be formed by chemical vapor deposition, spin coating, plasma-enhanced chemical vapor deposition, sputtering, vacuum deposition, high-density plasma chemical vapor deposition, and printing processes, etc.

[0163] An active layer ACT (1503) can be formed on top of the buffer layer BUF. As an example, an amorphous silicon layer can be formed on top of the buffer layer BUF, which can be crystallized to form a polycrystalline silicon layer. Subsequently, the active layer ACT can be formed by patterning the polycrystalline silicon layer using photolithography, etc. A second mask for the photolithography process can be used at this time. The polycrystalline silicon layer constituting the active layer ACT can be doped with impurities, thereby forming source regions SA1, SA2, and SA3, drain regions DA1, DA2, and DA3, and channels CH1, CH2, and CH3. Contact holes for contacting the first conductive layer and higher layers can be further formed in the buffer layer BUF.

[0164] A gate insulating layer GI (1504) can be formed on top of the active layer ACT. The gate insulating layer GI can be selectively formed in the region where the second conductive layer described below is formed. In particular, the gate insulating layer can be formed using photolithography, etc., so that a mask can be used to expose and develop the gate insulating layer GI. A third mask can be used at this time.

[0165] A second conductive layer (1505) can be formed on top of the gate insulating layer GI. A conductive film is formed on the gate insulating layer GI using processes such as printing, sputtering, chemical vapor deposition, pulsed laser deposition (PLD), vacuum deposition, and atomic layer deposition. Then, the conductive film is patterned using an etching process with a mask to generate the second conductive layer. A fourth mask can be used at this point.

[0166] Subsequently, the passivation layer PAS can be formed by covering the second conductive layer (1506). A color filter can be formed on top of the passivation layer PAS (1507). As an example, for the color filter, a first color filter can be patterned using a first mask, a second color filter can be patterned using a second mask, and a third color filter can be patterned using a third mask. A light-absorbing layer LA can be formed simultaneously with the color filter. To form the color filter and the light-absorbing layer LA, three masks for the first to third colors, namely the fifth to seventh masks, can be used respectively.

[0167] Subsequently, the outer coating OC can be formed by covering the color filter and the light-absorbing layer LA (1508). The outer coating OC can be exposed and developed on the passivation layer PAS using a mask. This mask may include openings corresponding to vias VIA1 and VIA2, respectively. An eighth mask can be used at this time.

[0168] Light-emitting elements can be formed on top of the cover layer OC. In particular, a ninth mask with openings corresponding to the light-emitting regions EA is used on the outer coating OC to pattern the anode AE ​​(1509).

[0169] After the anode AE ​​is formed, a dam layer BNK (1510) is extensively formed on top of the anode AE ​​and the exposed outer coating OC in a manner that covers the non-light-emitting area NEA. The vias VIA1 and VIA2 formed in the non-light-emitting area NEA can be filled with the dam layer BNK. After the dam layer BNK is formed, a light-emitting layer EML and a cathode CE (1511) are extensively formed in a manner that covers the entire area of ​​the display panel 50.

[0170] According to this disclosure, a semi-embankment structure is used, in which the embankment layer BNK covers the non-light-emitting region NEA but does not cover the light-emitting region EA. That is, in the light-emitting region EA, where multiple pixels PX are arranged in a row, the embankment layer BNK is not arranged in the pixel column direction. However, in the non-light-emitting region NEA, which is located below the light-emitting region EA and has a circuit element layer, the embankment layer BNK is arranged along the pixel column direction. Subsequently, in the light-emitting region EA, located below the non-light-emitting region NEA, the embankment layer BNK is arranged along the pixel column direction. However, in the non-light-emitting region NEA, which is located below the light-emitting region EA and has a circuit element layer, the embankment layer BNK is arranged along the pixel column direction. As a result, the embankment layer BNK is implemented in a striped pattern on the display device 1.

[0171] While specific embodiments of this disclosure have been described for illustrative purposes, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope and spirit of this disclosure as disclosed in the appended claims.

Claims

1. A display device, comprising: A substrate, the substrate comprising a plurality of pixel regions, each pixel region comprising a light-emitting region and a non-light-emitting region adjacent to the light-emitting region in a first direction; A layer of circuit elements formed in the non-light-emitting region; as well as A dike layer covering the top of the circuit element layer, The embankment layer is not formed in the luminescent region. The embankment layer is not formed between the luminescent regions that are adjacent to each other along the second direction.

2. The display device of claim 1, wherein the circuit element layer comprises: A first conductive layer disposed on top of the substrate; A buffer layer covering the first conductive layer; An active layer disposed on top of the buffer layer; A gate insulating layer covering the active layer; as well as A second conductive layer disposed on top of the gate insulating layer and containing at least one electrode of the transistor.

3. The display device as claimed in claim 2, further comprising: A passivation layer disposed on top of the gate insulating layer; as well as An outer coating disposed on top of the passivation layer, The passivation layer and the outer coating are formed on all areas of the substrate, including the light-emitting area and the non-light-emitting area.

4. The display device as claimed in claim 3, further comprising: An anode is disposed on top of the outer coating; A light-emitting layer disposed on top of the anode; as well as The cathode is arranged on top of the light-emitting layer. The anode is formed in the light-emitting region, and at least one region of the anode extends into the non-light-emitting region. The embankment layer is placed between the anode and the light-emitting layer in the non-light-emitting region.

5. The display device as claimed in claim 4, further comprising: Data lines and sensing lines extending along the first direction, The data lines or sensing lines are arranged between columns of pixels that display white, red, green, or blue.

6. The display device of claim 5, wherein the anode does not overlap with the data line or the sensing line.

7. The display device of claim 3, further comprising: Displays red, green, or blue color filters. The color filter is arranged in the light-emitting area and inserted between the passivation layer and the outer coating.

8. The display device of claim 4, wherein the at least one transistor includes a drive transistor configured to control the amount of current flowing to the anode, and The driving transistor includes: The source electrode is disposed on the second conductive layer and electrically connected to the power line; A gate, which is contained in the second conductive layer and electrically connected to the lower electrode of the storage capacitor; as well as The drain electrode is disposed on the second conductive layer and electrically connected to the upper electrode of the storage capacitor.

9. The display device of claim 8, wherein the passivation layer is inserted between the lower electrode and the upper electrode of the storage capacitor.

10. The display device of claim 1, wherein the embankment layer is implemented in the form of a striped pattern in the display device.

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