Super junction RC-IGBT device structure

Abstract

The application discloses a super-junction RC-IGBT device structure, which comprises IGBT regions, first isolation regions, FRD regions and second isolation regions arranged in sequence laterally, wherein the four regions each comprise a front metal layer, a back metal layer, an insulating dielectric layer, a groove located below the insulating dielectric layer and a Pwell region located between adjacent grooves; in the IGBT regions, a collector P+ region, an N-type FS buffer region and a first N-base region are sequentially arranged from bottom to top between the Pwell region and the back metal layer; in the FRD regions, an anode N+ region and a second N-base region are sequentially arranged from bottom to top between the Pwell region and the back metal layer; and in the first isolation regions and the second isolation regions, an anode N+ region and a P-region are sequentially arranged from bottom to top between the Pwell region and the back metal layer. The application can avoid the snapback phenomenon of the RC-IGBT device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, and in particular to the structure of superjunction RC-IGBT devices. Background Technology

[0002] IGBTs are typically unidirectional semiconductor power devices, lacking reverse conduction capability. In most IGBT applications, an anti-parallel freewheeling diode (FRD) is required for protection. Reverse-conducting IGBTs (RC-IGBTs) integrate the IGBT and FRD onto a single chip, eliminating the need for a separate freewheeling FRD during packaging and effectively reducing costs. However, due to the introduction of the N+ region on the back of the diode in RC-IGBTs, at lower collector voltages, the diode formed by the P-collector region and the drift region does not conduct, and the device operates in unipolar mode. As the collector voltage gradually increases, the diode forms the P-collector region and the drift region, conducting, and holes are injected into the drift region from the P-collector region, resulting in conductivity modulation, and the device operates in bipolar mode. When the RC-IGBT transitions from unipolar to bipolar mode, a voltage foldback phenomenon occurs in the output current-voltage curve, leading to unstable device performance and hindering parallel operation.

[0003] Therefore, there is a current need for an RC-IGBT device structure that avoids the snapback phenomenon without affecting the working performance of the RC-IGBT. Summary of the Invention

[0004] To address the technical problem of snapback during RC-IGBT operation, this invention provides a superjunction RC-IGBT device structure, the specific technical solution of which is as follows:

[0005] The superjunction RC-IGBT device structure provided by this invention includes:

[0006] The IGBT area, the first isolation area, the FRD area, and the second isolation area are arranged horizontally in sequence.

[0007] The IGBT region, the first isolation region, the FRD region, and the second isolation region each include a front metal layer, a back metal layer, an insulating dielectric layer located between the front metal layer and the back metal layer and adjacent to the front metal layer, a trench located below the insulating dielectric layer, and a Pwell region located between adjacent trenches.

[0008] Within the IGBT region, a collector P+ region, an N-type FS buffer zone, and a first N-base region are sequentially disposed from bottom to top between the Pwell region and the back metal layer;

[0009] Within the FRD region, an anode N+ region and a second N-base region are sequentially disposed from bottom to top between the Pwell region and the back metal layer;

[0010] Within the first isolation zone and the second isolation zone, the anode N+ region and P- region are sequentially disposed from bottom to top between the Pwell region and the back metal layer.

[0011] The superjunction RC-IGBT device structure provided by this invention integrates the IGBT region and the FRD region into the same device, which is beneficial to improving the system integration. By setting a first isolation region and a second isolation region, the IGBT region and the FRD region are separated. The P- region in the first isolation region and the second isolation region effectively blocks the flow of electrons to the anode N+ region in the FRD region, thereby suppressing the snapback phenomenon. At the same time, the adjacent N-base regions and P- regions in the IGBT region, the first isolation region, the FRD region and the second isolation region arranged laterally form a lateral PN junction. When the IGBT device is subjected to withstand voltage, the lateral PN junction can share part of the withstand voltage, thereby improving the withstand voltage level of the IGBT device.

[0012] In some embodiments, the height of the collector P+ region within the IGBT region is the same as the height of the anode N+ region within the FRD region, the first isolation region, and the second isolation region.

[0013] The superjunction RC-IGBT device structure provided by this invention can further improve the suppression effect of the snapback phenomenon.

[0014] In some implementations, each cell includes one active trench and four complete dummy trenches;

[0015] The IGBT region includes one effective trench and two partial dummy trenches, and the FRD region, the first isolation region, and the second isolation region each include two partial dummy trenches;

[0016] The two dummy grooves within the IGBT region are respectively located on both sides of the effective groove;

[0017] The adjacent portions of the dummy trench between the IGBT region, the FRD region, the first isolation region and the second isolation region constitute a complete dummy trench.

[0018] Both the effective trench and the dummy trench include a gate oxide region and a polysilicon region.

[0019] In some embodiments, a first connection hole is provided within the polysilicon region of the dummy trench;

[0020] The first connection hole penetrates the insulating dielectric layer and connects to the front metal layer. The first connection hole is filled with the metal material in the front metal layer to form a dummy trench gate.

[0021] The superjunction RC-IGBT device structure provided by the present invention provides a first connection hole in the polysilicon region of the dummy trench, so that the dummy trench gate is connected to the front metal material, which effectively reduces the saturation current and ensures short-circuit capability.

[0022] In some implementations, the Pwell region within the IGBT region is provided with a first Pplus region and an N+ emitter region located above the first Pplus region;

[0023] The N+ emitter region is adjacent to the insulating dielectric layer.

[0024] In some embodiments, a second connection hole is provided in the N+ emitter region within the IGBT region, the second connection hole dividing the N+ emitter region into two adjacent N+ emitter regions;

[0025] The second connection hole penetrates the insulating dielectric layer and connects to the front metal layer. The second connection hole is filled with the metal material in the front metal layer.

[0026] In one embodiment, the Pwell region within the FRD region is provided with a second Pplus region;

[0027] A third connection hole is provided in the Pwell region within the FRD region. The third connection hole penetrates the insulating dielectric layer and connects the second Pplus region and the front metal layer. The third connection hole is filled with the metal material in the front metal layer.

[0028] In one embodiment, an N-type carrier storage region is further disposed below the Pwell region within the IGBT region, and the N-type carrier storage region is disposed between adjacent trenches in the IGBT region.

[0029] The superjunction RC-IGBT device structure provided by this invention adds a carrier storage layer in the IGBT region, which can effectively reduce the saturation voltage drop of the IGBT device.

[0030] The superjunction RC-IGBT device structure provided by this invention has at least one of the following technical advantages:

[0031] (1) Integrating the IGBT region and FRD region into the same device is beneficial to improving the system integration. By setting the first isolation region and the second isolation region, the IGBT region and the FRD region are separated. The P- region in the first isolation region and the second isolation region effectively blocks the flow of electrons to the anode N+ region in the FRD region, thereby suppressing the snapback phenomenon. At the same time, the adjacent N-base regions and P- regions in the IGBT region, the first isolation region, the FRD region and the second isolation region arranged laterally form a lateral PN junction. When the IGBT device is subjected to withstand voltage, the lateral PN junction can share part of the withstand voltage, thereby improving the withstand voltage level of the IGBT device.

[0032] (2) By setting the first connection hole in the polysilicon region of the dummy trench, the dummy trench gate is connected to the front metal material, which effectively reduces the saturation current and ensures short-circuit capability.

[0033] (3) By adding a carrier storage layer in the IGBT region, the saturation voltage drop of the IGBT device can be effectively reduced. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is an example diagram of the superjunction RC-IGBT device structure provided by the present invention;

[0036] Figure 2 Another example diagram of the superjunction RC-IGBT device structure provided by the present invention;

[0037] Figure 3 This is an example diagram showing the superjunction RC-IGBT device structure provided by the present invention, which includes an N-type carrier storage region.

[0038] The diagram labels are as follows: IGBT region-100, first isolation region-200, FRD region-300, second isolation region-400, back metal layer-1, collector P+ region-2, anode N+ region-3, N-type FS buffer region-4, first N-base region-5, first P- region-6, second N-base region-7, second P- region-8, effective trench-9.1, dummy trench-9.2, gate oxide region-10, polysilicon region-11, Pwell region-12, first Pplus region-13.1, second Pplus region-13.2, N+ emitter region-14, first connection hole-15.1, second connection hole-15.2, third connection hole-15.3, insulating dielectric layer-16, front metal layer-17, and N-type carrier storage region-18. Detailed Implementation

[0039] In the following description, specific details such as particular system architectures and technologies are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of the hierarchy and block structure in well-known IGBT devices are omitted to avoid unnecessary detail from hindering the description of this application.

[0040] It should be understood that, when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or sets.

[0041] To keep the drawings concise, only the parts relevant to the invention are shown schematically in each figure, and they do not represent the actual structure of the product. Furthermore, for ease of understanding, in some figures, components with the same structure or function are shown only schematically, or only one is labeled. In this document, "a" not only means "only one," but can also mean "more than one."

[0042] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0043] Furthermore, in the description of this application, the terms "first," "second," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0044] It should be noted that the illustrations provided in the specification are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the specific implementation methods of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings and other implementation methods can be obtained based on these drawings without any creative effort.

[0046] One embodiment of the present invention, such as Figure 1 and Figure 2 As shown, the superjunction RC-IGBT device structure provided by the present invention includes an IGBT region 100, a first isolation region 200, an FRD region 300, and a second isolation region 400.

[0047] The IGBT area 100, the first isolation area 200, the FRD area 300, and the second isolation area 400 are arranged horizontally in sequence.

[0048] IGBT region 100, first isolation region 200, FRD region 300 and second isolation region 400 each include a front metal layer 17, a back metal layer 1, an insulating dielectric layer 16 located between the front metal layer 17 and the back metal layer 1 and adjacent to the front metal layer 17, a trench located below the insulating dielectric layer 16, and a Pwell region 12 located between adjacent trenches.

[0049] Within the IGBT region 100, the collector P+ region 2, the N-type FS buffer zone 4, and the first N-base region 5 are arranged sequentially from bottom to top between the Pwell region 12 and the back metal layer 1.

[0050] Within the FRD region 300, an anode N+ region 3 and a second N-base region 7 are sequentially disposed from bottom to top between the Pwell region 12 and the back metal layer 1.

[0051] Within the first isolation zone 200 and the second isolation zone 400, the anode N+ region 3 and the P- region are arranged sequentially from bottom to top between the Pwell region 12 and the back metal layer 1.

[0052] Specifically, the IGBT device is composed of multiple cells. Within each cell, there are horizontally arranged IGBT regions 100, first isolation regions 200, FRD regions 300, and second isolation regions 400. The IGBT regions 100, 200, 300, and 400 share a back metal layer 1. A collector P+ region 2 and an anode N+ region 3 are arranged side-by-side on the back metal layer 1. The collector P+ region 2 is located within the IGBT region 100. The first isolation regions 200, 300, and 400 share the anode N+ region 3. An N-type FS buffer 4 is provided on the collector P+ region 2 within GBT region 100, a first N-base region 5 is provided on the N-type FS buffer 4, a first P-region 6 is provided on the anode N+ region 3 within the first isolation region 200, a second N-base region 7 is provided on the anode N+ region 3 within the FRD region 300, and a second P-region 8 is provided on the anode N+ region 3 within the second isolation region 400, so that IGBT region 100 and FRD region 300 within the same cell are separated by the first isolation region 200, and IGBT region 100 and FRD region 300 within adjacent cells are separated by the second isolation region 400.

[0053] The superjunction RC-IGBT device structure provided in this embodiment integrates the IGBT region and the FRD region into the same device, which is beneficial to improving the system integration. By setting a first isolation region and a second isolation region, the IGBT region and the FRD region are separated. The P- region in the first isolation region and the second isolation region effectively blocks the flow of electrons to the anode N+ region in the FRD region, thereby suppressing the snapback phenomenon. At the same time, the adjacent N-base regions and P- regions in the IGBT region, the first isolation region, the FRD region and the second isolation region arranged laterally form a lateral PN junction. When the IGBT device is subjected to withstand voltage, the lateral PN junction can share part of the withstand voltage, thereby improving the withstand voltage level of the IGBT device.

[0054] In one embodiment, such as Figure 1 and Figure 2 As shown, the height of the collector P+ region 2 in IGBT region 100 is the same as the height of the anode N+ region 3 in FRD region 300, first isolation region 200 and second isolation region 400.

[0055] In one embodiment, such as Figure 1 and Figure 2 As shown, each cell includes one effective groove 9.1 and four complete dummy grooves 9.2.

[0056] The IGBT region 100 includes one effective trench 9.1 and two partially dummy trenches 9.2. The FRD region 300, the first isolation region 200, and the second isolation region 400 each include two partially dummy trenches 9.2.

[0057] Two partial dummy grooves 9.2 are respectively located on both sides of the effective groove 9.1 within the IGBT area 100.

[0058] The adjacent dummy grooves 9.2 between IGBT area 100, FRD area 300, first isolation area 200 and second isolation area 400 constitute a complete dummy groove 9.2.

[0059] Both the effective trench 9.1 and the dummy trench 9.2 contain a gate oxide region 10 and a polysilicon region 11.

[0060] Specifically, Figure 1 and Figure 2 The cell shown includes one effective trench 9.1 and three complete dummy trenches 9.2. Partial dummy trenches 9.2 are provided on the leftmost and rightmost sides of the cell shown. These two partial dummy trenches 9.2 are equivalent to one complete dummy trench 9.2. The effective trench 9.1 and the dummy trenches 9.2 are connected to the insulating dielectric layer 16 on one side and the gate oxide region 10 is covered on the remaining surface.

[0061] In one embodiment, a first connection hole 15.1 is provided in the polysilicon region 11 of the dummy trench 9.2.

[0062] The first connection hole 15.1 penetrates the insulating dielectric layer 16 and is connected to the front metal layer 17. The first connection hole 15.1 is filled with the metal material in the front metal layer 17 to form a dummy trench gate.

[0063] The superjunction RC-IGBT device structure provided in this embodiment provides a first connection hole in the polysilicon region of the dummy trench, which connects the dummy trench gate to the front metal material, effectively reducing saturation current and ensuring short-circuit capability.

[0064] In one embodiment, a portion of the dummy groove 9.2 includes a portion of the first connection hole 15.1, and adjacent portions of the first connection hole 15.1 constitute a complete first connection hole 15.1.

[0065] In one embodiment, the Pwell region 12 within the IGBT region 100 is provided with a first Pplus region 13.1 and an N+ emitter region 14 located on the upper layer of the first Pplus region 13.1, the N+ emitter region 14 being adjacent to the insulating dielectric layer 16.

[0066] In one embodiment, the N+ emitter region 14 within the IGBT region 100 is provided with a second connection hole 15.2, which divides the N+ emitter region 14 into two adjacent N+ emitter regions 14.

[0067] The second connection hole 15.2 penetrates the insulating dielectric layer 16 and is connected to the front metal layer 17. The second connection hole 15.2 is filled with the metal material in the front metal layer 17.

[0068] Specifically, no holes are made in the effective trench 9.1 within the IGBT region 100.

[0069] In some implementations, the Pwell region 12 within the FRD region 300 is provided with a second Pplus region 13.2.

[0070] A third connection hole 15.3 is provided in the Pwell area 12 within the FRD area 300. The third connection hole 15.3 penetrates the insulating dielectric layer 16 and connects the second Pplus area 13.2 and the front metal layer 17. The third connection hole 15.3 is filled with the metal material in the front metal layer 17.

[0071] In some implementations, such as Figure 3 As shown, an N-type carrier storage region 18 is also provided below the Pwell region 12 in the IGBT region 100. The N-type carrier storage region 18 is located between adjacent trenches in the IGBT region 100.

[0072] The superjunction RC-IGBT device structure provided in this embodiment can effectively reduce the saturation voltage drop of the IGBT device by adding a carrier storage layer in the IGBT region.

[0073] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0074] Those skilled in the art will recognize that the units and steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0075] In the embodiments provided in this application, it should be understood that the disclosed superjunction RC-IGBT device structure can be implemented in other ways. For example, the superjunction RC-IGBT device structure embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or modules may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the communication connections shown or discussed may be through some interfaces, communication connections of devices or units, or integrated circuits, and may be electrical, mechanical, or other forms.

[0076] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0077] Furthermore, the functional units in the various embodiments of this application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The integrated unit described above can be implemented in hardware or as a software functional unit.

[0078] It should be noted that the above description is only a preferred embodiment of the present invention. It should be pointed out that for those skilled in the art, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A superjunction RC-IGBT device structure, characterized in that, include: The IGBT area, the first isolation area, the FRD area, and the second isolation area are arranged horizontally in sequence. The IGBT region, the first isolation region, the FRD region, and the second isolation region each include a front metal layer, a back metal layer, an insulating dielectric layer located between the front metal layer and the back metal layer and adjacent to the front metal layer, a trench located below the insulating dielectric layer, and a Pwell region located between adjacent trenches. Within the IGBT region, a collector P+ region, an N-type FS buffer zone, and a first N-base region are sequentially disposed from bottom to top between the Pwell region and the back metal layer; Within the FRD region, an anode N+ region and a second N-base region are sequentially disposed from bottom to top between the Pwell region and the back metal layer; Within the first isolation zone and the second isolation zone, the anode N+ region and P- region are sequentially disposed from bottom to top between the Pwell region and the back metal layer; Each cell includes one active groove and four complete dummy grooves; The IGBT region includes one effective trench and two partial dummy trenches, and the FRD region, the first isolation region, and the second isolation region each include two partial dummy trenches; The two dummy grooves within the IGBT region are respectively located on both sides of the effective groove; The adjacent portions of the dummy trench between the IGBT region, the FRD region, the first isolation region and the second isolation region constitute a complete dummy trench. Both the effective trench and the dummy trench include a gate oxide region and a polysilicon region. A first connection hole is provided within the polysilicon region of the dummy trench; The first connection hole penetrates the insulating dielectric layer and connects to the front metal layer. The first connection hole is filled with the metal material in the front metal layer to form a dummy trench gate.

2. The superjunction RC-IGBT device structure according to claim 1, characterized in that, The height of the collector P+ region within the IGBT region is the same as the height of the anode N+ region within the FRD region, the first isolation region, and the second isolation region.

3. The superjunction RC-IGBT device structure according to claim 1, characterized in that, The Pwell region within the IGBT region is provided with a first Pplus region and an N+ emitter region located above the first Pplus region. The N+ emitter region is adjacent to the insulating dielectric layer.

4. The superjunction RC-IGBT device structure according to claim 3, characterized in that, The N+ emitter region within the IGBT region is provided with a second connection hole, which divides the N+ emitter region into two adjacent N+ emitter regions. The second connection hole penetrates the insulating dielectric layer and connects to the front metal layer. The second connection hole is filled with the metal material in the front metal layer.

5. The superjunction RC-IGBT device structure according to claim 1, characterized in that, The Pwell region within the FRD region is provided with a second Pplus region; A third connection hole is provided in the Pwell region within the FRD region. The third connection hole penetrates the insulating dielectric layer and connects the second Pplus region and the front metal layer. The third connection hole is filled with the metal material in the front metal layer.

6. The superjunction RC-IGBT device structure according to any one of claims 1 to 5, characterized in that, An N-type carrier storage region is further provided below the Pwell region within the IGBT region, and the N-type carrier storage region is located between adjacent trenches in the IGBT region.

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