Apparatus and method for reducing current overshoot in a power regulator

Abstract

The present invention relates to apparatuses and methods for reducing current overshoot in a power regulator. An example implementation includes a method of reducing current overshoot in a power regulator apparatus by: detecting an input current of an inductive charger apparatus in response to a load change on the inductive charger apparatus; in response to detecting the change in input current, modifying an operating state of the inductive charger apparatus according to a first input current limit parameter based on a total input current limit parameter and a shunt parameter; operating the inductive charger apparatus according to the first input current limit during a current limit period following the detection of the change in input current; after the current limit period, modifying the operating state of the inductive charger apparatus according to a second input current limit parameter based on the total input current limit parameter and the shunt parameter; and operating the inductive charger apparatus according to the second input current limit after the current limit period.

Description

Technical Field

[0001] This implementation generally relates to chargers, and more specifically to reducing current overshoot in power regulators. Background Technology

[0002] Electronic devices are becoming increasingly prevalent in many personal and interpersonal activities. Additionally, these devices are increasingly exposed to unpredictable changes in power delivery and consumption driven by the proliferation of mobile device architectures and peripherals. However, conventional systems may not be able to effectively adapt to the various rapid changes, overshoots, or spikes in power characteristics in response to load demand variations. Therefore, technical solutions for reducing current overshoot in power regulators are needed. Summary of the Invention

[0003] An example implementation includes a method for reducing current overshoot in a power regulator device by: detecting the input current of the inductive charger device in response to a load change on the inductive charger device; modifying the operating state of the inductive charger device according to a first input current limit parameter based on a total input current limit parameter and a shunt parameter in response to the detected input current change; operating the inductive charger device according to the first input current limit during a current-limiting period following the detection of the input current change; modifying the operating state of the inductive charger device according to a second input current limit parameter based on the total input current limit parameter and the shunt parameter after the current-limiting period; and operating the inductive charger device according to the second input current limit after the current-limiting period.

[0004] The example implementation also includes a power regulator device having: an inductive charger device; a limiting amplitude controller device operatively coupled to the inductive charger device and configured to modify the operating state of the inductive charger device according to a first input current limiting parameter based on a total input current limiting parameter and a shunt parameter in response to a change in input current; a step amplitude controller device operatively coupled to the inductive charger device and configured to modify the operating state of the inductive charger device according to a second input current limiting parameter after a current limiting period, the second input current limiting parameter based on the total input current limiting parameter and the shunt parameter; and a loop selector device operatively coupled to the inductive charger device, the limiting amplitude controller device, and the step amplitude controller device and configured to detect a change in the input current of the inductive charger device in response to a change in the load on the inductive charger device, operate the inductive charger device according to the first input current limiting during a current limiting period after the input current change, and operate the inductive charger device according to the second input current limiting after the current limiting period.

[0005] The example implementation also includes a power regulator system having: an inductive charger device; a limiting amplitude controller device operably coupled to the inductive charger device and configured to modify the operating state of the inductive charger device in response to a change in input current, based on a first input current limiting parameter, the first input current parameter being based on a total input current limiting parameter and a shunt parameter; and a step amplitude controller device operably coupled to the inductive charger device and configured to modify the operating state of the inductive charger device based on a second input current limiting parameter following a current limiting period, the second input current limiting parameter being based on the total input current limiting parameter and a shunt parameter. The device includes: a current parameter; a loop selector device operatively coupled to an inductive charger device, a limit amplitude controller device, and a step amplitude controller device, and configured to detect changes in the input current of the inductive charger device in response to load changes on the inductive charger device, operate the inductive charger device according to a first input current limit during a current limiting period following the input current change, and operate the inductive charger device according to a second input current limit after the current limiting period; and a step delay device operatively coupled to the loop selector device and configured to recoverably store step delay parameters, wherein the current limiting period is based on the step delay parameters. Attached Figure Description

[0006] These and other aspects and features of this implementation will become apparent to those skilled in the art after reading the following description of the specific implementation in conjunction with the accompanying drawings, wherein:

[0007] Figure 1 An example power regulator system according to this implementation is illustrated.

[0008] Figure 2 The diagram shows... Figure 1 Example power regulator system and further example power regulator device.

[0009] Figure 3 The diagram shows... Figure 1 The example power regulator system is further illustrated by the example current limiting controller.

[0010] Figure 4 The figure shows an example timing diagram of the input current of an example power regulator according to this implementation.

[0011] Figure 5 The diagram shows Figure 4 Example timing diagrams for further system current and battery current.

[0012] Figure 6 The illustration shows an example method for reducing current overshoot in an example power regulator according to this implementation.

[0013] Figure 7 The illustration shows that in Figure 6 Further example methods for reducing current overshoot in power regulators. Detailed Implementation

[0014] The present implementation will now be described in detail with reference to the accompanying drawings, which are provided as illustrative examples of the implementation to enable those skilled in the art to practice implementations and alternatives that are obvious to them. Note that the following figures and examples are not intended to limit the scope of the present implementation to a single implementation, but rather other implementations are possible by exchanging some or all of the elements described or illustrated. Furthermore, where certain elements of the present implementation can be implemented partially or entirely using known components, only those portions of such known components necessary for understanding the present implementation will be described, and detailed descriptions of other portions of such known components will be omitted to avoid obscuring the present implementation. Unless otherwise stated herein, it will be apparent to those skilled in the art that an implementation described as software-based is not limited thereto, but may include implementations implemented in hardware, or a combination of software and hardware, and vice versa. In this specification, implementations showing a single component should not be considered limiting; rather, unless expressly stated otherwise herein, this disclosure is intended to cover other implementations including multiple identical components, and vice versa. Furthermore, unless expressly stated otherwise, the applicant does not intend to assign any terminology in the specification or claims an uncommon or special meaning. Furthermore, this implementation covers the current and future known equivalents of the known components mentioned herein by way of example.

[0015] Figure 1 An example power regulator system according to this implementation is illustrated. Figure 1 As shown in the example, the example power regulator system 100 includes an input 102, an output 104, a charger 106, a battery 108, a loop selector 110, and a current limiting controller 120.

[0016] Input 102 is, includes, is operatively coupled to, is integrated with, or can be integrated with power supplies, voltages, currents, etc., to power the example power regulator system 100. In some implementations, input 102 includes, but is not limited to, a regulated 120V AC power supply, a regulated 220V AC power supply, a 5V DC power supply, a 12V DC power supply, a 20V DC power supply, etc. In some implementations, input 102 includes a wired power connection, a wireless direct-contact power connection, a wireless and contactless power connection, etc., or any power connection known or potentially known. In some implementations, input 102 includes one or more USB terminals or ports (e.g., USB-C, USB-PD).

[0017] Output 104 includes one or more electrical, electronic, electromechanical, electrochemical, or other devices or systems for receiving power, voltage, current, etc., from one or more of the charger 106 and battery 108 to perform one or more actions. In some implementations, output 104 includes at least one battery, electronic display, electronic computer, electronic input device, electromechanical input device, electronic output device, electromechanical output device, etc. Examples of such devices include laptop computers, desktop computers, tablet computers, smartphones, printers, scanners, telephone endpoints, video conferencing endpoints, keyboards, mice, touchpads, gaming peripherals, monitors, televisions, etc. In some implementations, output 104 includes one or more devices that are partially or completely separable from the example power regulator system 100. In some implementations, output 104 includes one or more devices that are partially or completely integrated into or can be integrated into the example power regulator system 100 or separable from the example power regulator system 100.

[0018] Charger 106 includes one or more electrical, electronic, electromechanical, electrochemical, or similar devices or systems for charging or discharging a load operatively coupled to output 104, etc. In some implementations, charger 106 includes a DC-DC power converter. In some implementations, charger 106 includes an inductive charger. The inductive charger can be, but is not limited to, a buck charger, a boost charger, a buck-boost charger, combinations thereof, etc.

[0019] Battery 108 includes one or more electrical, electronic, electromechanical, electrochemical, or other devices or systems for receiving, storing, and distributing at least one of input power. In some implementations, battery 108 includes one or more battery stacks. In some implementations, battery 108 includes lithium-ion or similar energy storage devices. In some implementations, battery 108 is integrated with, can be integrated with, or can be decoupled from the example power regulator system 100. In some implementations, battery 108 includes multiple battery cells that are partially or fully integrated with, can be integrated with, or can be decoupled from the example power regulator system 100.

[0020] In some implementations, the example power regulator system 100 includes at least one system processor operable to execute one or more instructions associated therewith. In some implementations, the system processor is an electronic processor, integrated circuit, etc., including one or more of digital logic, analog logic, digital sensors, analog sensors, communication buses, volatile memory, non-volatile memory, etc. In some implementations, the system processor includes, but is not limited to, at least one microcontroller unit (MCU), microprocessor unit (MPU), central processing unit (CPU), graphics processing unit (GPU), physical processing unit (PPU), embedded controller (EC), etc. In some implementations, the system processor includes memory operable to store or store components for an operating system processor and to operate one or more instructions of components coupled to the system processor. In some implementations, the one or more instructions include at least one of firmware, software, hardware, operating system, embedded operating system, etc. It should be understood that the system processor may typically include at least one communication bus controller to enable communication between the system processor and other components of the example power regulator system 100.

[0021] The loop selector 110 is operable to operate the charger 106 according to one or more regulation modes and according to one or more current limiting conditions. In some implementations, the loop selector 110 includes one or more logic devices to control the operation of the charger 106 in one or more of a buck mode, a boost mode, and a buck-boost operation mode. In some implementations, the logic devices include, but are not limited to, one or more gate driver circuits, each gate driver circuit operably coupled to at least one transistor of the charger 106. In some implementations, the logic devices include, but are not limited to, a driver controller operable to switch one or more transistors of the charger 106 between an active or "on" state and a deactivated or "off" state. In some implementations, the loop selector 110 is operable to switch one or more transistors of the charger 106 to maintain at least one electrical characteristic of at least one of the charger 106 and the example power regulator device 100. In some implementations, the electrical characteristic includes a charging current to the battery 108. In some implementations, the electrical characteristic includes an output voltage at one or more of the outputs of the output 104 and the output of the charger 106. In some implementations, the electrical characteristics include input current at one or more of the inputs to input 102 and charger 106. In some implementations, the electrical characteristics include input voltage at one or more of the inputs to input 102 and charger 106. In some implementations, loop selector 110 includes one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device or component associated with loop selector 110 may also be associated with, integrated with, integrable with, replace, complement, or be complementary to the system processor or any component thereof.

[0022] The current limiting controller 120 is operable to apply, control, generate, enforce, implement, or otherwise limit at least one current limiting characteristic at input 102. In some implementations, the current limiting controller 120 includes at least one non-volatile and non-transitory computer-readable medium operable to store at least one current limiting characteristic. In some implementations, the medium is or includes at least one gate array, flip-flop, register, accumulator, etc. In some implementations, the current limiting controller 120 is operablely coupled to a loop selector via at least one communication line, bus, etc. In some implementations, the communication line, bus, etc., includes a communication bus comprising one or more bit channels operable to transmit one or more current limiting characteristics to the loop selector 110. In some implementations, the current limiting controller 120 includes one or more logic devices, arithmetic units, etc., operable to perform one or more mathematical operations, transformations, substitutions, replacements, etc., relative to at least one current limiting characteristic. As an example, the current limiting controller is operable to generate at least one current limiting characteristic based on another current limiting characteristic stored thereon or retrieved therefrom. In some implementations, the current limiting controller 120 includes one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar devices or components associated with the current limiting controller 120 may also be associated with, integrated with, integrable with, replace, supplement, complement, etc., the system processor or any of its components.

[0023] Figure 2 The diagram shows Figure 1 Another example power regulator device of the example power regulator system. For example... Figure 2The example power regulator device 200, illustrated by way of example, includes an input 102, an output 104, a charger 106, a battery 108, a battery transistor 208, a loop selector 110, and a current limiting controller 120. In some implementations, the input 102 includes an input node 202. In some implementations, the output 104 includes an output node 204. In some implementations, the charger 106 includes an inductor 210, a high-side buck transistor 212, a low-side buck transistor 214, a high-side boost transistor 216, and a low-side boost transistor 218. In some implementations, the loop selector 110 includes a charging current feedback line 220, a charging current sensor 222, an output voltage feedback line 230, an input current feedback line 240, an input current sensor 242, an input voltage feedback line 250, and a charging control line 260. In some implementations, the loop selector 110 is operatively coupled to the current limiting controller 120 via a current limiting control line 270. It should be understood that, according to this embodiment, the above-mentioned components can be directly connected or indirectly connected through the intervention of electronic components.

[0024] Input node 202 is operable to receive input power from an input operably coupled thereto and to transmit the received input power to charger 106. In some implementations, input node 202 is operably coupled to input capacitor 206, input current sensor 232, and the drain terminal of high-side buck transistor 212. Output node 204 is operable to transmit output power to an output operably coupled thereto and to receive output power from charger 106. In some implementations, output node 204 is operably coupled to output capacitor 206, the positive terminal of battery 108, and the drain terminal of high-side boost transistor 216.

[0025] Inductor 210 can operate in DC-DC converter modes under one or more of buck, boost, and buck-boost modes. In some implementations, inductor 210 is operatively coupled at its input node to the source terminal of high-side buck transistor 212 and the drain terminal of low-side buck transistor 214. In some implementations, inductor 210 is operatively coupled at its output node to the source terminal of high-side boost transistor 216 and the drain terminal of low-side boost transistor 218. It should be understood that the inductor node may alternatively be directly coupled to one or more of ground, input node 202, and output node 204, depending on one or more of buck, boost, and buck-boost configurations. It should be understood that charger 106 can operate in buck-boost mode. It should also be understood that charger 106 may optionally include or operate only a subset of transistors 212, 214, 216, and 218, depending on operation in buck or boost mode. Battery transistor 208 is operable to operatively and switchably couple and decouple battery 108 to at least one of charger 106, high-side boost transistor 216, and output node 204. In some implementations, one or more of battery transistor 208, high-side buck transistor 212, low-side buck transistor 214, high-side boost transistor 216, and low-side boost transistor 218 are or include field-effect transistors (“FETs”), metal-oxide-semiconductor field-effect transistors (“MOSFETs”), etc.

[0026] The charging current feedback line 220 is operable to provide a charging current feedback signal from the charging current sensor 222 to the loop selector 110. The charging current sensor 222 is operable to generate the charging current feedback signal based on at least one of the amplitude and direction of the battery current flowing into or out of the battery 108. In some implementations, the charging current sensor 222 is operable to generate a response voltage having at least one amplitude and direction corresponding to the amplitude and direction of the battery current.

[0027] Output voltage feedback line 230 is operable to provide an output voltage feedback signal from output node 204 to loop selector 110. In some implementations, output voltage feedback line 230 is directly and operably coupled to output node 204. Alternatively, in some implementations, output voltage feedback line 230 is operably coupled to output node 204 via one or more intervening electrical, electronic, or similar devices. As an example, output voltage feedback line 230 can be operably coupled to output node 204 via a voltage divider circuit. In this example, output voltage feedback line 230 can receive a stepped-down voltage from the voltage divider circuit, wherein the voltage operating range at loop selector 110 is smaller than the voltage operating range at output node 204.

[0028] Input current feedback line 240 is operable to provide an input current feedback signal from input current sensor 242 to loop selector 110. Input current sensor 242 is operable to generate the input current feedback signal based on at least one of the amplitude and direction of the input current flowing into or out of input node 202. In some implementations, input current sensor 242 is operable to generate a response voltage having at least one of the amplitude and direction corresponding to the amplitude or direction of the input current.

[0029] The input voltage feedback line 250 is operable to provide an input voltage feedback signal from the input node 202 to the loop selector 110. In some implementations, the input voltage feedback line 250 is directly and operably coupled to the input node 202. Alternatively, in some implementations, the input voltage feedback line 250 is operably coupled to the input node 202 via one or more intervening electrical, electronic, or similar devices. As an example, the input voltage feedback line 250 may be operably coupled to the input node 202 via a voltage divider circuit corresponding to the output voltage feedback line 250, or alternatively, to the corresponding structure associated with the output voltage feedback line 250.

[0030] Charger control line 260 is operable to communicatively couple loop selector 110 to charger 106. In some implementations, charger control line 260 is operable to communicate one or more commands, signals, conditions, states, etc., between loop selector 110 and one or more of charger 106. In some implementations, loop selector 110 is operable to drive one or more of transistors 212, 214, 216, and 218 of charger 106 via charger control line 260. In some implementations, loop selector 110 is operable according to at least one of buck mode, boost mode, and buck-boost operation mode, driving one or more of transistors 212, 214, 216, and 218 of charger 106 via charger control line 260. In some implementations, loop selector 110 is operable to drive one or more of transistors 212, 214, 216, and 218 of charger 106 via charger control line 260 to maintain at least one electrical characteristic of at least one of charger 106 and example power regulator device 100. In some implementations, charger control line 260 includes one or more digital, analog, or other communication channels, lines, traces, etc. As an example, charger control line 260 is at least one of a plurality of communication lines including a communication interface, either serial or parallel.

[0031] The current limiting control line 270 is operable to communicatively couple the loop selector 110 to the current limiting controller 120. In some implementations, the current limiting control line 270 is operable to communicate one or more commands, signals, conditions, states, etc., between the loop selector 110 and one or more of the current limiting controller 120. In some implementations, the current limiting controller 120 is operable to provide one or more limits on the current at the charger 106 to the loop selector 110 via the current limiting control line 270 based on at least one current limiting characteristic. In some implementations, the current limiting control line 270 includes one or more digital, analog, or other communication channels, lines, traces, etc. As an example, the current limiting control line 270 is at least one of a plurality of communication lines including a communication interface, either serial or parallel.

[0032] Figure 3 Further illustrations Figure 1 An example current-limiting controller for an example power regulator system. For example... Figure 3 As shown in the example, the example current limiting controller 300 includes a control input line 302, a limiting amplitude controller 310, a limiting amplitude control line 312, a step amplitude controller 320, a step amplitude control line 322, a step delay controller 330, and a step delay control line 332.

[0033] Control input line 302 is operable to communicatively couple current limiting controller 120 to an external device. In some implementations, control input line 302 is operable to communicate one or more instructions, signals, conditions, states, etc., from the external device to current limiting controller 120. In some implementations, current limiting controller 120 is operable to receive one or more values, etc., from an external device to at least one of limiting amplitude controller 310, step amplitude controller 320, and step delay controller 330 via control input line 302. In some implementations, control input line 302 is operable to transmit values ​​based on flash memory, download, reset, initialization, etc., of at least one of current limiting controller 120, limiting amplitude controller 310, step amplitude controller 320, and step delay controller 330. As an example, control input line 302 can receive current limiting parameters, step amplitude parameters, and step delay parameters from an external device. In this example, each of the limiting amplitude controller 310, the step amplitude controller 320, and the step delay controller 330 can be set using a corresponding one of the current limiting parameter, step amplitude parameter, and step delay parameter from an external device. In some implementations, the control input line 302 includes one or more digital, analog, or other communication channels, lines, traces, etc. As an example, the control input line 302 is at least one of a plurality of communication lines including a communication interface, either serial or parallel.

[0034] The amplitude limiting controller 310 is operable to store, provide, receive, and transmit current limiting parameters, etc. In some implementations, the amplitude limiting controller 310 is operable to store a value representing the current limiting parameter. In some implementations, the amplitude limiting controller 310 is or includes a physical or logical non-transitory and non-volatile memory device. In some implementations, the amplitude limiting controller 310 is or includes a physical memory device that is different from and separate from one or more of the step amplitude controller 320 and step delay controller 330. Alternatively, in some implementations, the amplitude limiting controller 310 includes a physical memory device that is integrated, integrable, etc., with one or more of the step amplitude controller 320 and step delay controller 330. In some implementations, the amplitude limiting controller 310 includes one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or similar device or component associated with the amplitude limiting controller 310 may also be associated with, integrated with, integrable with, replace, supplement, complement, etc., the system processor or any component thereof. The amplitude limiting control line 312 is operable to communicatively couple the amplitude limiting controller 310 to the loop selector 110. In some implementations, the amplitude limiting control line 312 includes one or more digital, analog, or other communication channels, lines, traces, etc. As an example, the amplitude limiting control line 312 is at least one of a plurality of communication lines that include a communication interface, either serial or parallel.

[0035] The step amplitude controller 320 is operable to store, provide, receive, transmit, etc., shunt parameters. In some implementations, the step amplitude controller 320 is operable to store values ​​representing shunt parameters. In some implementations, the step amplitude controller 320 is or includes a physical or logical non-transitory and non-volatile memory device. In some implementations, the step amplitude controller 320 is or includes a physical memory device that is different from and separate from one or more of the limiting amplitude controller 310 and the step delay controller 330. Alternatively, in some implementations, the step amplitude controller 320 includes a physical memory device that is integrated, integrable, etc., with one or more of the limiting amplitude controller 310 and the step delay controller 330. In some implementations, the step amplitude controller 320 includes one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, etc., devices or components associated with the step amplitude controller 320 may also be associated with, integrated with, integrable with, replace, supplement, complement, etc., the system processor or any component thereof. The step amplitude control line 322 is operable to communicatively couple the step amplitude controller 320 to the loop selector 110. In some implementations, the step amplitude control line 322 includes one or more digital, analog, or other communication channels, lines, traces, etc. As an example, the step amplitude control line 322 is at least one of a plurality of communication lines that includes a communication interface, either serial or parallel.

[0036] The step delay controller 330 is operable to store, provide, receive, and transmit step delay parameters, etc. In some implementations, the step delay controller 330 is operable to store values ​​representing step delay parameters. In some implementations, the step delay controller 330 is or includes a physical or logical non-transitory and non-volatile memory device. In some implementations, the step delay controller 330 is or includes a physical memory device that is different from and separate from one or more of the limiting amplitude controller 310 and the step amplitude controller 320. Alternatively, in some implementations, the step delay controller 330 includes a physical memory device that is integrated with, integrable with, etc., one or more of the limiting amplitude controller 310 and the step amplitude controller 320. In some implementations, the step delay controller 330 includes one or more logic or electronic devices, including but not limited to integrated circuits, logic gates, flip-flops, gate arrays, programmable gate arrays, etc. It should be understood that any electrical, electronic, or other devices or components associated with the step delay controller 330 may also be associated with, integrated with, integrable with, replace, supplement, complement, etc., the system processor or any component thereof. The step delay control line 332 is operable to communicatively couple the step delay controller 330 to the loop selector 110. In some implementations, the step delay control line 332 includes one or more digital, analog, or other communication channels, lines, traces, etc. As an example, the step delay control line 332 is at least one of a plurality of communication lines that include a communication interface, either serial or parallel. It should be understood that one or more of the control input line 302, the limiting amplitude control line 312, the step amplitude control line 322, and the step delay control line 332 may be arranged as a communication bus, etc., or included in a communication bus, etc.

[0037] Figure 4 The illustration shows an example timing diagram of the input current of an example power regulator according to this implementation. Figure 4 As illustrated in the example, example timing diagram 400 includes an input current waveform 410, a first current limit 420, a second current limit 422, a first current overshoot level 430, and a second current overshoot level 432. In some implementations, the input current waveform 410 includes a first current overshoot peak value 440 and a second current overshoot peak value 442. In some implementations, the example power regulator operates in response to a load step change under system voltage. In some implementations, the load step change occurs at any time in response to the connection, disconnection, activation, deactivation, etc., of one or more electronic, electrical, or similar components operatively coupled to the example power regulator. It should be understood that timing diagram 400 illustrates an example response to an example operating state. It should be further understood that the system and device according to this implementation are not limited to those according to... Figure 4 The operation of timing diagram 400.

[0038] Before time t0 402, the example power regulator operates by receiving an input current at a first current level according to the input current waveform 410. In some implementations, the first current level is less than at least one of a first current limit 420, a second current limit 422, a first current overshoot level 430, and a second current overshoot level 432. In some implementations, the first current level is less than all of the first current limit 420, the second current limit 422, the first current overshoot level 430, and the second current overshoot level 432. In some implementations, before time t0 402, the input current of the input current waveform 410 remains substantially constant in at least one of the DC and AC components.

[0039] At time t0 402, the example power regulator responds to a load step change and increases the input current of input current waveform 410. In some implementations, the load step change causes the example power regulator to switch from a power regulation mode to an input current regulation mode. In some implementations, the input current regulation mode includes one or more of a first current limit 420 and a second current limit 422. In some implementations, the input current begins to increase toward the first current limit 420. In some implementations, the input current of input current waveform 410 increases linearly in at least one of a DC component and an AC component between times t0 402 and t1 404. In some implementations, the step delay begins at time t0 402.

[0040] At time t1 404, the input current of the example power regulator reaches the first current limit 420 and continues to increase toward the first current overshoot level 430. In some implementations, as the input current continues to increase, it reaches the first current overshoot level 430 at the first current peak 440 and does not reach the second current overshoot level 432. In some implementations, the input current of the input current waveform 410 increases at a decreasing rate in at least one of the DC and AC components between time t1 404 and the subsequent time when the input current reaches the first current overshoot level 430. In some implementations, at the first current peak 440, the input current stops increasing and its rate is zero. In some implementations, the input current of the input current waveform 410 decreases at an increasing rate in at least one of the DC and AC components between the time when the input current reaches the first current overshoot level 430 and the subsequent time when the input current reaches the first current limit 420. In some implementations, the input current waveform 410, after decreasing to the first current limit 420, remains at or substantially equal to the amplitude of the first current limit 420. In some implementations, the step delay begins at time t1 404. In some implementations, the period 412 between time t1 404 and time t2 406 is the first overshoot period, during which the input current waveform 410 stabilizes at the first current limit 422 after the load step change.

[0041] At time t2 406, the input current of the example power regulator begins at the first current limit 420 and increases toward the second current overshoot level 432. In some implementations, the example power regulator switches the current limit from the first current limit 420 to the second current limit 422 at t2 406. In some implementations, the example power regulator switches the current limit in response to the expiration of a delayed timer indicating the end of period 412 and the start of period 414. In some implementations, period 414 between times t2 406 and t3 408 is the second overshoot period, during which the input current waveform 410 stabilizes at the second current limit 422 after a load step change.

[0042] In some implementations, as the input current continues to increase, it reaches a second current overshoot level 432 at a second current peak 442 that is above the first current overshoot level 430. In some implementations, the input current of the input current waveform 410 decreases at a decreasing rate in at least one of the DC and AC components between time t2 406 and the subsequent time after the input current reaches the second current overshoot level 432. In some implementations, at the second current peak 442, the input current stops increasing, and its rate is zero. In some implementations, the input current of the input current waveform 410 decreases at an increasing rate in at least one of the DC and AC components between the time the input current reaches the second current overshoot level 432 and the subsequent time after the input current reaches the second current limit 422. In some implementations, the input current of the input current waveform 410, after decreasing to the second current limit 422, remains at or substantially equal to the magnitude of the second current limit 422.

[0043] At time t3 408, the example power regulator responds to a load step change relative to the load step change at time t0 402. As an example, the load step change at time t3 408 could be the removal or deactivation of electronic or electrical equipment that was attached, activated, etc., at time t0 402. In some implementations, the input current decreases accordingly to a first current level or another current level below the first current limit 420. In some implementations, the input current decreases instantaneously or substantially instantaneously at time t3 408. After time t3 408, the input current of the input current waveform 410 remains at the first current level.

[0044] Figure 5 Further illustrations Figure 4 Example timing diagrams for system current and battery current. (Example timing diagrams are provided.) Figure 5 As shown in the example, the example timing diagram 500 includes a system current waveform 510, a battery current waveform 520, a system peak current level 530, and a battery current peak level 540. It should be understood that the timing diagram 500 illustrates an example response to an example operating state. It should be further understood that the system and device according to this implementation are not limited to those according to... Figure 5 The operation of timing diagram 500.

[0045] Before time t0 402, the system current according to system current waveform 510 is at a first system current level, and the battery current according to battery current waveform 520 is at a first battery current level. In some implementations, the first system current is at a level lower than both the battery peak current and the system peak current. In some implementations, the battery current is at a level that is essentially zero, with no current flowing to battery 108.

[0046] At time t0 402, the system current increases in response to a load step change, causing the example power regulator to switch from power regulation mode to input current regulation mode. In some implementations, the system current increases instantaneously or substantially instantaneously at time t0 402. In some implementations, the battery current remains substantially zero. In some implementations, the load step change at time t0 is caused at least in part by activating battery 108 to receive charging power from the example power regulator. In some implementations, the example power regulator receives one or more commands for operatively coupling battery 108 to output voltage node 204 by activating battery transistor 208.

[0047] At time tl 404, the system current remains at the system peak current level 530. In some implementations, the battery current increases at a decreasing rate starting from time tl 404. In some implementations, the battery current increases toward the battery peak current 522. In some implementations, the battery current of the battery current waveform 520 increases at a decreasing rate in at least one of the DC and AC components between time tl 404 and the subsequent time after the battery current reaches the battery current peak level 540.

[0048] At time t2 406, the battery current reaches its peak value 522, and then stops increasing at a rate of zero. In some implementations, the battery current of waveform 520 decreases at a decreasing rate in at least one of the DC and AC components between times t2 406 and t3 408. In some implementations, the system current of waveform 510 remains at an amplitude equal to or substantially equal to the system peak current 530.

[0049] At time t3 408, the example power regulator responds to a load step change relative to the load step change at time t0 402. As an example, the load step change at time t3 408 could be the removal or deactivation of battery 108, such as when it was attached, activated, etc., at time t0 402. In some implementations, the system current correspondingly decreases to a first system current level or another current level below the system peak current level 530. In some implementations, the system current decreases instantaneously or substantially instantaneously at time t3 408. After time t3 408, the system current of system current waveform 510 maintains its current level, and the battery current of battery current waveform 520 decreases at a decreasing rate in at least one of the DC and AC components between times t2 406 and t3 408. In some implementations, the battery current decreases after time t3 408 at a second decreasing rate greater than the decreasing rate between times t2 406 and t3 408.

[0050] Therefore, in some implementations, the example power regulator can reduce the total overshoot current in a system experiencing a load step change. As an example, the example power regulator can switch from output voltage regulation mode to input current regulation mode in response to a load step change. In this example, the example power regulator operates at a 20V input voltage, a 12.6V system voltage, a 12V battery voltage, and an initial battery charging current of 0A. In this example, the load current step response can vary depending on the implementation, based on a single current limit and multiple current limits. In this example, the example power regulator switches from output voltage regulation mode to input current regulation mode in response to a load step change. Under the single current limit example in this example, the load current changes from 0.5A to 6A, where the single step current limit is 3A. In this example, the peak overshoot current is 4.3A, resulting in a 1.3A overshoot. In this example, the 1.3A overshoot is 44% higher than the current limit. Alternatively, in several current-limiting examples in this instance, the load current changes from 0.5A to 6A, where the first step current limit is 2.4A and the second step current limit is 3A. In this example, the first overshoot current peak is 3.4A, resulting in an overshoot of 1.0A beyond the first current limit, and the second overshoot current peak is 3.3A, resulting in an overshoot of 0.3A beyond the first current limit. In this example, the highest overshoot current is 3.4A, which is 1.4A overshoot compared to the second current limit of 3.0A. In this example, the overshoot is 14% higher than the current limit. Therefore, in this example, the two step current limits result in a total reduction of 0.9A in overshoot current, and the difference in the percentage reduction of overshoot between a single step current limit and two step current limits is 30%.

[0051] As another example, the example power regulator can switch from battery current regulation mode to input current regulation mode in response to a load step change. In this example, the example power regulator operates at a 20V input voltage, a 12.6V system voltage, a 12V battery voltage, and an initial battery charging current of 2A. In this example, the load current step response can vary depending on the implementation, based on a single current limit and multiple current limits. Under the single current limit example in this example, the load current changes from 0.5A to 6A, where the single step current limit is 3A. In this example, the overshoot current peak is 4.2A, resulting in a 1.2A overshoot. In this example, the 1.2A overshoot is 40% higher than the current limit. Alternatively, under the multiple current limit example in this example, the load current changes from 0.5A to 6A, where the first step current limit is 2.4A, and the second step current limit is 3A. In this example, the first overshoot current peak is 2.8A, resulting in an overshoot (or undershoot) exceeding the first current limit by -0.2A, and the second overshoot current peak is 3.2A, resulting in an overshoot exceeding the first current limit by 0.2A. In this example, the highest overshoot current is 3.2A, which is 0.2A overshoot compared to the second current limit of 3.0A. In this example, the overshoot exceeds the current limit by 7%. Therefore, in this example, the two-step current limits result in a total reduction of 1.0A in the overshoot current, and the difference in the percentage reduction of overshoot between the single-step and two-step current limits is 33%.

[0052] Figure 6 An example of an example method for reducing current overshoot in an example power regulator according to the present implementation is illustrated. In some implementations, at least one of the example power regulator system 100 and the example power regulator device 200 performs method 600 according to the present implementation. In some implementations, method 600 begins at step 610.

[0053] At step 610, the example system obtains at least one current limiting parameter. In some implementations, loop selector 110 obtains the current limiting parameter from current limiting controller 120. In some implementations, step 610 includes at least one of steps 612, 614, and 616. At step 612, the example system obtains at least one current amplitude parameter. In some implementations, loop selector 110 obtains the current amplitude parameter from limiting amplitude controller 310. At step 614, the example system obtains at least one shunt parameter. In some implementations, loop selector 110 obtains the shunt parameter from step amplitude controller 320. At step 616, the example system obtains at least one step delay parameter. In some implementations, loop selector 110 obtains the current amplitude parameter from step delay controller 330. Method 600 then continues to step 620.

[0054] At step 620, the example system enters a power regulation mode. In some implementations, the example system enters the power regulation mode based on one or more predetermined operating parameters associated with one or more system loads operatively coupled to output node 204. As an example, the operating parameters may include predetermined current or voltage levels associated with one or more peripheral devices operatively coupled or integrated with the example system. In some implementations, step 620 includes at least one of steps 622, 624, 626, and 628. At step 622, the example system selects a charging current regulation mode. In some implementations, the charging current regulation mode causes charger 106 to provide a specific charging current to output node 204. In some implementations, charger 106 operates in the charging current regulation mode by switching one or more of transistors 212, 214, 216, and 218, depending on one or more of buck mode, boost mode, and buck-boost operation modes. At step 624, the example system selects an output voltage regulation mode. In some implementations, the output voltage regulation mode causes the charger 106 to provide a specific output voltage to the output node 204. In some implementations, the charger 106 operates in the output voltage regulation mode by switching one or more of transistors 212, 214, 216, and 218, depending on one or more of buck mode, boost mode, and buck-boost operation mode. At step 626, the example system selects the input current limiting regulation mode. In some implementations, the input current limiting regulation mode causes the charger 106 to maintain a specific input current limit at the input node 202. In some implementations, the charger 106 operates in the input current limiting regulation mode by switching one or more of transistors 212, 214, 216, and 218, depending on one or more of buck mode, boost mode, and buck-boost operation mode. At step 628, the example system selects the input voltage regulation mode. In some implementations, the input voltage regulation mode causes the charger 106 to maintain a specific input voltage at the input node 202. In some implementations, charger 106 operates in input voltage regulation mode by switching one or more of transistors 212, 214, 216, and 218, depending on one or more of buck mode, boost mode, and buck-boost operation mode. In some implementations, method 600 then proceeds to step 630.

[0055] Figure 7 The diagram shows Figure 6The example method further reduces current overshoot in the example power regulator. In some implementations, at least one of the example power regulator system 100 and the example power regulator device 200 performs method 700 according to this implementation. In some implementations, method 700 begins at step 630. Method 700 then continues to step 710.

[0056] At step 710, the example system generates primary current limiting parameters. In some implementations, the primary current limiting parameters include a limit on at least one of the DC current and AC current amplitude. In some implementations, the primary current limiting parameters are lower than a total current limiting parameter stored or associated by at least one of the current limiting controller 120 and the limiting amplitude controller 310. In some implementations, at least one of the current limiting controller 120 and the limiting amplitude controller 310 generates the primary current limiting parameters. In some implementations, step 710 includes step 712. At step 712, the example system generates the primary current limiting parameters based at least on the current limiting parameters and the shunt parameters. In some implementations, at least one of the current limiting controller 120 and the limiting amplitude controller 310 divides the current limiting parameters by the shunt parameters, or divides the current limiting parameters by a value equal to 1 minus the shunt parameters. Method 700 then continues to step 720.

[0057] At step 720, the example system generates secondary current limiting parameters. In some implementations, the secondary current limiting parameters include a limit on at least one of the DC current and AC current amplitude. In some implementations, the secondary current limiting parameters are lower than a total current limiting parameter stored or associated by at least one of the current limiting controller 120 and the limiting amplitude controller 310. In some implementations, at least one of the current limiting controller 120 and the limiting amplitude controller 310 generates the secondary current limiting parameters. In some implementations, step 720 includes step 722. At step 722, the example system generates the secondary current limiting parameters based at least on the current limiting parameters and the primary current limiting parameters. In some implementations, contrary to the operation associated with the primary current limiting parameters, at least one of the current limiting controller 120 and the limiting amplitude controller 310 divides the current limiting parameters by a shunt parameter, or divides the current limiting parameters by 1 minus a value equal to the shunt parameter. Therefore, in some implementations, the sum of the primary current limiting parameters and the secondary current limiting parameters equals the total current limiting parameters. Method 700 then continues to step 730.

[0058] At step 730, the example system detects a change in the charger's input current. In some implementations, the loop selector 110 detects the change via at least one of the following: charging current feedback line 220, charging current sensor 222, output voltage feedback line 230, input current feedback line 240, input current sensor 242, and input voltage feedback line 250. In some implementations, step 730 includes step 732. At step 732, the example system switches from a first power regulation mode to a second power regulation mode. In some implementations, the first power regulation mode and the second power regulation mode are different modes among charging current regulation mode, output voltage regulation mode, input current limiting regulation mode, and input voltage regulation mode, respectively. Method 700 then proceeds to step 740.

[0059] At step 740, the example system starts a timer period at least in part based on a current delay parameter. In some implementations, at least one of the current limit controller, step delay controller 330, and loop selector 110 starts the timer period via a timer device integrated with, operatively coupled to, or associated with it. Method 700 then proceeds to step 750.

[0060] At step 750, the example system operates the charger according to primary current limit parameters. In some implementations, loop selector 110 operates charger 106 according to primary current limit parameters. In some implementations, the example system operates charger 106 according to one or more states associated with at least one of timing diagrams 400 and 500. Method 700 then proceeds to step 760.

[0061] At step 760, the example system determines whether the time period has expired. In some implementations, at least one of the current limiting controller, step delay controller 330, and loop selector 110 determines whether the time period has expired based on a timer device integrated with, operatively coupled to, or associated with it. Based on the determination that the time period has not expired, method 700 continues to step 750. Alternatively, based on the determination that the time period has expired, method 700 continues to step 770.

[0062] At step 770, the example system operates the charger according to secondary current limiting parameters. In some implementations, loop selector 110 operates charger 106 according to secondary current limiting parameters. In some implementations, the example system operates charger 106 according to one or more states associated with at least one of timing diagrams 400 and 500. In some implementations, method 700 ends at step 770. Alternatively, in some implementations, method 700 then continues to step 730. In some implementations, the example system operates in cyclic, continuous, repetitive, standby, or other modes until one or more instructions, commands, etc., are received to stop operation according to a power regulation mode.

[0063] The topics described herein sometimes illustrate different components contained within or connected to different other components. It should be understood that the architectures depicted are exemplary, and many other architectures can actually be implemented to achieve the same functionality. Conceptually, any arrangement of components that achieve the same functionality is effectively “associated” to achieve the desired function. Therefore, regardless of the architecture or intermediate components, any two components combined in this document to achieve a particular function can be considered “associated” with each other so that the desired function is achieved. Similarly, any two such associated components can also be considered “operably connected” or “operably coupled” to each other to achieve the desired function, and any two components that can be suchly associated can also be considered “operably coupled” to each other to achieve the desired function. Specific examples of operational coupling include, but are not limited to, physically matable and / or physically interactive components and / or wirelessly interactive and / or logically interactive and / or logically interactive components.

[0064] Regarding the use of plural and / or singular terms in this document, those skilled in the art can translate plural to singular and / or from singular to plural depending on the context and / or application. For clarity, various singular / plural permutations may be explicitly described herein.

[0065] Those skilled in the art will understand that, in general, the terms used herein, and especially those used in the appended claims (e.g., the body of the appended claims), are generally intended to be “open” terms (e.g., the term “comprising” should be interpreted as “including but not limited to”, the term “having” should be interpreted as “at least having”, the term “comprising” should be interpreted as “including but not limited to”, etc.).

[0066] Although the accompanying drawings and descriptions may illustrate a specific order of method steps, the order of these steps may differ from that depicted and described unless otherwise specified above. Furthermore, unless otherwise stated above, two or more steps may be performed simultaneously or partially simultaneously. For example, such variations may relate to the chosen software and hardware system and the designer's choices. All such variations are within the scope of this disclosure. Similarly, the software implementation of the described methods can be accomplished using standard programming techniques combined with rule-based logic and other logic to perform various connection steps, processing steps, comparison steps, and decision steps.

[0067] Those skilled in the art will further understand that if a particular number of claim citations are to be introduced, the intent is explicitly stated in the claims, and if no such citations are present, the intent does not exist. For example, to aid understanding, the appended claims may contain the use of introductory phrases “at least one” and “one or more” to introduce the statement of the claims. However, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles (such as “a(a)” or “an(an)” (e.g., “a(a)” and / or “an(an)” should generally be interpreted as “at least one” or “one or more”), the use of such phrases should not be construed as implying that introducing claim citations by the indefinite article “a(a)” or “an(an)” limits any particular claim containing such introduced claim citations to an invention containing only one such citation; the same applies to the use of definite articles to introduce claims. Additionally, even if a specific number of claim citations are explicitly cited, those skilled in the art will recognize that such citations should generally be interpreted as indicating at least the number of citations (e.g., an empty citation of "two citations" in the absence of other modifiers generally refers to at least two citations, or two or more citations).

[0068] Furthermore, in cases where a convention similar to "at least one of A, B, and C, etc." is used, generally, such a construction is intended to convey the meaning of the convention as would be understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" would include, but is not limited to, systems having only A, only B, only C, having A and B, having A and C, having B and C, and / or systems having A, B, and C, etc.). In cases where a convention similar to "at least one of A, B, or C, etc." is used, generally, such a construction is intended to convey the convention as would be understood by a person skilled in the art (having only A, only B, only C, having A and B, having A and C, having B and C, and / or systems having A, B, and C, etc.). A person skilled in the art will further understand that any separate words and / or phrases presenting two or more alternative terms, whether in the specification, claims, or drawings, should be understood to contemplate the possibility of including one, one, or both of these terms. For example, the phrase "A or B" would be understood to include the possibility of "A" or "B" or "A and B".

[0069] In addition, unless otherwise stated, the use of words such as “approximately,” “about,” “around,” and “basically” implies plus or minus ten percent.

[0070] The foregoing description of illustrative implementations has been presented for purposes of illustration and description. It is not intended to be exhaustive or limiting of the precise forms disclosed, and modifications and variations may be made in accordance with the foregoing teachings or may be obtained from practice of the disclosed implementations. The scope of the invention is intended to be defined by the appended claims and their equivalents.

Claims

1. A method for reducing current overshoot in a power regulator device, comprising: In response to load changes on the inductive charging device, the change in the input current of the inductive charger device is detected; In response to the detection of the change in the input current, the operating state of the inductive charger device is modified according to the first input current limit parameter based on the total input current limit parameter and the shunt parameter; During the current limiting period following the detection of the change in the input current, the inductive charger device is operated according to the first input current limit; After the current limiting period, the operating state of the inductive charger device is modified according to the second input current limiting parameter based on the total input current limiting parameter and the shunt parameter. as well as After the current limiting period, the inductive charger device is operated according to the second input current limit.

2. The method according to claim 1, further comprising: The first input limiting current is generated based on a first ratio of the total input current limiting parameter to the shunt parameter.

3. The method according to claim 1, further comprising: The second input current limit parameter is generated based on a second ratio of the total input current limit parameter to the shunt parameter.

4. The method according to claim 1, further comprising: The second input current limit parameter is generated based on the difference between the total input current limit parameter and the first input current limit parameter.

5. The method according to claim 1, further comprising: The total input current limit parameter and the shunt parameter are retrieved from the current limit controller integrated with the inductive charger device.

6. The method according to claim 1, further comprising: In response to detecting the change in the input current, the power regulation mode of the inductive charger device is switched from a first power regulation mode to a second power regulation mode.

7. The method of claim 6, wherein the first power regulation mode is an output voltage regulation mode and the second power regulation mode is an input current limiting regulation mode.

8. The method of claim 6, wherein the first power regulation mode is a charging current regulation mode and the second power regulation mode is an input current limiting regulation mode.

9. The method according to claim 1, further comprising: Retrieve the step delay parameter from the current limit controller integrated with the inductive charger device. The current limiting period is based on the step delay parameter.

10. A power regulator device, comprising: Inductive charger equipment; A limiting amplitude controller device is operatively coupled to the inductive charger device and configured to modify the operating state of the inductive charger device in response to changes in input current, according to a first input current limiting parameter, the first input current parameter being based on a total input current limiting parameter and a shunt parameter; A step amplitude controller device is operatively coupled to the inductive charger device and configured to modify the operating state of the inductive charger device after a current limiting period, based on a second input current limiting parameter, the second input current limiting parameter being based on the total input current limiting parameter and the shunt parameter; as well as A loop selector device, operably coupled to the inductive charger device, the limiting amplitude controller device, and the step amplitude controller device, is configured to: detect a change in the input current of the inductive charger device in response to a load change on the inductive charger device; operate the inductive charger device according to a first input current limit during a current limiting period following the change in the input current; and operate the inductive charger device according to a second input current limit after the current limiting period.

11. The device of claim 10, wherein the limiting amplitude controller device is further configured to: The first input limit current is generated based on a first ratio of the total input current limit parameter and the shunt parameter.

12. The device of claim 10, wherein the step amplitude controller device is further configured to: The second input current limit parameter is generated based on a second ratio of the total input current limit parameter and the shunt parameter.

13. The device of claim 10, wherein the step amplitude controller device is further configured to: The second input current limit parameter is generated based on the difference between the total input current limit parameter and the first input current limit parameter.

14. The device of claim 10, wherein the loop selector device is further configured to: In response to the change in the input current, the power regulation mode of the inductive charger device is switched from a first power regulation mode to a second power regulation mode.

15. The device of claim 14, wherein the first power regulation mode is an output voltage regulation mode and the second power regulation mode is an input current limiting regulation mode.

16. The device of claim 14, wherein the first power regulation mode is a charging current regulation mode and the second power regulation mode is an input current limiting regulation mode.

17. The apparatus of claim 10, further comprising: A step delay device is operatively coupled to the loop selector device and configured to retrievably store step delay parameters. The current limiting period is based on the step delay parameter.

18. The device of claim 17, wherein the limiting amplitude controller device, the step amplitude controller device, and the step delay device are integrated into the current limiting controller device.

19. A power regulator system, comprising: Inductive charger equipment; A limiting amplitude controller device is operatively coupled to the inductive charger device and configured to modify the operating state of the inductive charger device in response to changes in input current, according to a first input current limiting parameter, the first input current parameter being based on a total input current limiting parameter and a shunt parameter; A step amplitude controller device is operatively coupled to the inductive charger device and configured to modify the operating state of the inductive charger device after a current limiting period, based on a second input current limiting parameter, the second input current limiting parameter being based on the total input current limiting parameter and the shunt parameter; A loop selector device, operably coupled to the inductive charger device, the limiting amplitude controller device, and the step amplitude controller device, is configured to: detect a change in the input current of the inductive charger device in response to a load change on the inductive charger device; operate the inductive charger device according to a first input current limit during a current limiting period following the change in the input current; and operate the inductive charger device according to a second input current limit after the current limiting period. as well as A step delay device is operatively coupled to the loop selector device and configured to retrievably store step delay parameters. The current limiting period is based on the step delay parameter.

20. The system of claim 19, wherein the limiting amplitude controller device, the step amplitude controller device, and the step delay device are integrated into the current limiting controller device.

Images