Voltage converter with loop control

Abstract

A voltage converter system (100) includes a switch (102) configured to operate in a first state and a second state. A timer circuitry (110) is configured to generate a timing signal representing a duration of the first state based on input and output voltages of the voltage converter system (100). Control logic (114) is coupled to the switch (102) and the timer circuitry (110) and is configured to generate a first control signal to cause the switch (102) to switch between the first state and the second state based on a second control signal generated based on a feedback voltage and a reference voltage. Timer control circuitry (116) is coupled to the control logic (114) and the timer circuitry (110) and is configured to: detect a phase difference between the first control signal and the second control signal; and adjust the timer circuitry (110) to change the duration based on the phase difference.

Description

Technical Field

[0001] This specification generally relates to integrated circuits, and more specifically, to a voltage converter system with loop control. Background Technology

[0002] A DC-DC voltage converter can be used to convert an input DC voltage into a desired output DC voltage to drive a load. The DC-DC converter may include a feedback loop that determines the on or off time of a switch in each switching cycle based on a feedback voltage and a reference voltage, thereby regulating the output voltage of the DC-DC converter. In a conventional adaptive on-time or off-time mode DC-DC converter, a pulse-width modulation (PWM) signal controlling the switch is adjusted based on the feedback voltage, and the on or off time is determined based on the input and output voltages of the DC-DC converter. Summary of the Invention

[0003] A voltage converter system includes a switch configured to switch between the first state and the second state in response to a first control signal. A timer circuit system is configured to generate a timing signal representing the duration of the first state based on the input and output voltages of the voltage converter system. Control logic is coupled to the switch and the timer circuit system and configured to generate the first control signal based on a second control signal. The second control signal is based on a feedback voltage and a reference voltage. A timer control circuit system is coupled to the control logic and the timer circuit system and configured to: detect a phase difference between the first control signal and the second control signal; and adjust the timer circuit system to change the duration based on the phase difference. Attached Figure Description

[0004] Figure 1 This is a schematic block diagram of a DC-DC converter system according to the implementation scheme of this specification.

[0005] Figure 2 yes Figure 1 A schematic circuit diagram of the timer circuit system and timer control circuit system of the DC-DC converter system.

[0006] Figure 3A , 3B 3C and 3D are Figure 1 A diagram of the analog waveform of the DC-DC converter.

[0007] Figure 4 This is a schematic block diagram of an adaptive turn-on time buck DC-DC converter system.

[0008] Figure 5 yes Figure 4Illustrative diagrams of the waveforms of the DC-DC converter.

[0009] Figure 6A and 6B yes Figure 4 A diagram of the analog waveform of the DC-DC converter.

[0010] Figure 7 This is a flowchart of a method for operating a DC-DC converter system according to the implementation scheme described herein. Detailed Implementation

[0011] This specification pertains to DC-DC converter systems with loop control.

[0012] Figure 1 This is a schematic block diagram of a DC-DC converter system 100 according to an embodiment of this description. More specifically, Figure 1 This demonstrates a buck DC-DC converter system for converting input voltage VIN to output voltage VOUT at a target voltage level.

[0013] System 100 includes: (a) a first switch 102 coupled between a switching terminal SW and a voltage terminal (e.g., an input terminal 1001 configured to receive the input voltage VIN of system 100); and (b) a second switch 104 coupled between the switching terminal SW and a voltage supply terminal (e.g., a ground terminal GND), thereby allowing current to flow from the input terminal 1001 to the switching terminal SW when the first switch 102 is in a first state (e.g., an ON state) and the second switch 104 is in a second state (e.g., an OFF state), and allowing current to flow from the switching terminal SW to the ground terminal when the second switch 104 is ON. The first switch 102 and the second switch 104, also referred to as a high-side switch and a low-side switch, may be transistors (e.g., metal-oxide-semiconductor field-effect transistors MOSFETs), which are controlled by gate drive signals HSD_ON and LSD_ON, respectively, to operate alternately in the first and second states. System 100 also includes: an output inductor 106 coupled between the switching terminal SW and the output voltage terminal 1002; and an output capacitor 108 coupled between the output voltage terminal 1002 and the ground terminal GND.

[0014] In one example, system 100 includes a timer circuit system 110 configured to receive an input voltage VIN and an output voltage VOUT of system 100, and configured to determine a first duration Ton of a first state of a first switch 102 based on the input voltage VIN and the output voltage VOUT of system 100 and a target switching frequency Fsw_target. The timer circuit system 110 is configured to generate a timing signal when the first duration expires. In one example, the timing signal is a single-shot signal One_shot. The timing signal One_shot is configured to switch the first switch 102 from the first state to the second state. In one example, the timer circuit system 110 includes a timing capacitor (not shown), and the first duration Ton is determined by charging the timing capacitor based on the input voltage VIN and the output voltage VOUT. The first duration Ton of the on state of the first switch 102 is provided according to the following equation:

[0015]

[0016] Where Tsw_target is the target switching cycle of system 100, Tsw_target = 1 / Fsw_target, and Fsw_target is the target switching frequency of system 100. The ratio between the first duration Ton and the actual switching cycle of system 100 defines the switching operating cycle of system 100. The output voltage VOUT is generated based on the switching operating cycle and the input voltage VIN.

[0017] System 100 further includes a loop control circuit system 112, configured to generate a loop control signal LoopRaw based on a feedback voltage VFB proportional to the output voltage VOUT and a specific reference voltage VREF. In one example, the loop control circuit system 112 includes a comparator 113 configured to: receive the feedback voltage VFB and the specific reference voltage VREF; and generate the loop control signal LoopRaw. The loop control signal LoopRaw is configured to switch the first switch 102 between a first state and a second state, for example, from the second state to the first state. The phase difference between a timing signal One_shot and the loop control signal LoopRaw defines a target second duration of the second state of the first switch 102. The loop control circuit system 112 determines the target second duration Toff_target of the second state of the first switch 102 based on the feedback voltage VFB. The target second duration Toff_target is provided according to the following equation:

[0018] Toff_target=Tsw_target–Ton (2)

[0019] System 100 further includes: control logic 114 coupled to timer circuit system 110 and loop control circuit system 112 to receive timing signal One_shot and loop control signal LoopRaw, respectively; and driver unit 115 coupled between control logic 114 and first switch 102 and second switch 104. Control logic 114 is configured to generate control signal S based on timing signal One_shot and loop control signal LoopRaw. ON and S OFF Control signal S ON Configured to assert the gate drive signal HSD_ON and deassert the gate drive signal LSD_ON. Control signal S OFF The gate drive signal HSD_ON is deasserted and the gate drive signal LSD_ON is asserted. Control logic 114 includes a minimum time control unit 117 configured to time the minimum duration Toff_min of the second state of the first switch 102. The minimum duration Toff_min is configured based on various factors of the DC-DC converter system 100, such as the blanking time of the inductor current IL sensing and delays caused by the loop control circuitry system 112, control logic 114, and / or driver unit 115. In one example, control logic 114 is configured to set the control signal S in response to the timing signal One_shot. OFF Assert to turn off the first switch 102, and when the loop control signal LoopRaw is asserted and the minimum duration Toff_min of the second state of the first switch 102 expires, the control signal S will be turned off. ON Assert that the first switch 102 is turned on. Therefore, when the minimum duration Toff_min is greater than the target second duration Toff_target determined by the loop control circuit system 112, the control signal S is turned on based on the minimum duration Toff_min. ON Assertion. Therefore, the minimum duration Toff_min determines the actual second duration Toff of the first switch. When the control signal S ON When lagging behind the loop control signal LoopRaw, the actual duration Toff of the second state of the first switch 102 is greater than the target second duration Toff_target. The first duration Ton of the first state of the first switch 102 arrives later than the time determined by the loop control signal LoopRaw, which leads to a reduction in the switching duty cycles of the DC-DC converter system 100. Therefore, the energy generated by turning on the first switch 102 will be insufficient to maintain the output voltage VOUT at the target voltage level.

[0020] In one example, system 100 further includes a timer control circuit system 116 coupled to timer circuit system 110, loop control circuit system 112, and control logic 114. Timer control circuit system 116 is configured to: (a) detect control signal S ON The phase difference between the loop control signal LoopRaw and (b) the response to the detection of the control signal S ON The first duration Ton, which lags behind the loop control signal LoopRaw, is altered (e.g., extended) by an additional duration proportional to the phase difference to ensure that the switching duty cycle of the DC-DC converter system 100 is large enough to maintain the output voltage VOUT at a specific voltage level. Therefore, in the converter system 100, when the minimum duration Toff_min determines the actual duration Toff of the second state of the first switch 102: (a) the actual second duration Toff of the converter system 100 is fixed based on the minimum duration Toff_min, (b) the first duration Ton is extended proportionally to the phase difference, and (c) the switching frequency Fsw of the DC-DC converter system 100 is smoothly reduced.

[0021] In one example, the timer control circuit system 116 includes a phase detector 118, which is configured to receive a control signal S. ON and loop control signal LoopRaw; detection control signal S ON The timer control circuitry 116 includes a phase difference with the loop control signal LoopRaw and generates a charging signal Sc with a duration proportional to the phase difference. The timer control circuitry 116 further includes a charge pump circuitry 120 coupled to the phase detector 118 and configured to generate a second current Is proportional to the width of the charging signal Sc. In one example, the charge pump circuitry 120 is configured to discharge the capacitor of the timer circuitry 110 with the second current Is to extend the first duration Ton.

[0022] Figure 2 It is the timer circuit system 200 and the timer control circuit system 202 (e.g. Figure 1 An exemplary schematic circuit diagram of the timer circuit system 110 and the timer control circuit system 116 of the DC-DC converter system 100.

[0023] The timer circuit system 200 includes a first comparator 204 having: a first input terminal (e.g., a non-inverting input terminal) configured to receive a voltage K·Vout proportional to the output voltage VOUT; a second input terminal (e.g., an inverting input terminal); and an output terminal configured to generate a timing signal One_shot. The timer circuit system 200 further includes: (a) a first resistor Rs 206 coupled between a switching terminal SW and the inverting input terminal of the first comparator 204; and (b) a first capacitor Cs 208 having a first terminal coupled to the inverting input terminal of the first comparator 204 and a second terminal coupled to a voltage supply (e.g., a ground terminal). The timer circuit system 200 further includes a control switch 210 coupled in parallel with the first capacitor Cs 208 and configured to short-circuit the first capacitor Cs 208 when the first switch 102 is in a second state. In one example, when the first switch 102 is in a first state (e.g., the ON state), the charging current I0 (provided from the input terminal 1001 via the switching terminal SW and the first resistor Rs 206) charges the first capacitor Cs 208. The first comparator 204 generates a timing signal when the voltage at the first terminal of the first capacitor Cs 208 increases to the voltage K·VOUT. The assertion of the timing signal One_shot causes the control logic 114 to control the signal S. OFF The assertion states that the first switch 102 is turned off and the control switch 210 is turned on to discharge the first terminal of the first capacitor Cs 208 to ground. The timing signal One_shot generated by the first comparator 204 is a single-shot signal. The first duration Ton of the on state of the first switch 102 is provided according to the following equation:

[0024]

[0025] K·Rs·Cs is configured based on the target switching cycle Tsw_target = 1 / Fsw_target of system 100, where Fsw_target is the target switching frequency of system 100.

[0026] The timer control circuit system 202 includes a phase detector 212, for example Figure 1 The phase detector 118 of the DC-DC converter system 100. In one example, the phase detector 212 is a D flip-flop having: a data input terminal configured to receive a loop control signal LoopRaw from the loop control circuit system 112; and a clock input terminal configured to receive a control signal S from the control logic 114. ON Phase detector 212 determines the loop control signal LoopRaw and the control signal S. ONThe phase detector 212 may also include a first edge (e.g., a rising edge) of the charging signal Sc generated in response to an assertion of the loop control signal LoopRaw and in response to a control signal S. ON Other logic that generates the second edge (e.g., the falling edge) of the charging signal Sc based on the assertion.

[0027] The timer control circuit system 202 includes a charge pump circuit system 214, for example... Figure 1 The DC-DC converter system 100 includes a charge pump circuit system 120. The charge pump circuit system 214 includes a first current source 216 providing a first current Ic, a charging switch 218 coupled to the first current source Ic 216, and a second capacitor Cpd 220 having a first terminal coupled to the charging switch 218 and a second terminal coupled to a voltage supply (e.g., ground terminal GND). The charging switch 218 is controlled by a charging signal Sc to couple the first current source Ic 216 to the second capacitor Cpd 220 for a duration based on a phase difference detected by a phase detector 212. In one example, the charging signal Sc is a pulse signal having a loop control signal LoopRaw and a control signal S. ON The phase difference between them is proportional to the width. In one example, the charging switch 218 is configured to turn on during a period from the first edge to the second edge of the charging signal Sc. The charge pump circuit system 214 also includes an amplifier (e.g., a transconductance amplifier) ​​222 coupled between a first terminal of the second capacitor Cpd 220 and the inverting input terminal of the first comparator 204. The transconductance amplifier 222 is configured to provide a second current source Is proportional to the voltage Vpd across the second capacitor Cpd 220. The second current Is provided by the second current source: (a) cancels the charging current I0 received by the first capacitor 208; and (b) delays the change of the first control signal. In one example, the second current Is discharges the first capacitor Cs 208, thereby proportionally extending the first duration Ton. Therefore, in the converter system 100, when the minimum duration Toff_min determines the actual duration Toff of the second state of the first switch 102: the actual second duration Toff of the converter system 100 is fixed based on the minimum duration Toff_min; the first duration Ton is extended proportionally with the phase difference; and the switching frequency Fsw of the DC-DC converter system 100 is smoothly reduced.

[0028] In one example, the first current source Ic, the capacitance of the second capacitor Cpd 220, and the gain of the transconductance amplifier 222 are provided according to the following equations:

[0029]

[0030] Where I0 is the original charging current passing through the first resistor Rs 206 to charge the first capacitor Cs 208, α is the target step size used to adjust the first duration Ton to ensure a smooth change (e.g., α = 0.03%), Gain is the gain of the transconductance amplifier 222, and T pd The minimum duration Toff_min of the second state of the first switch 102 can be maximized.

[0031] In one example, the charge pump circuit system 214 further includes a first clamping circuit system 224 coupled to a first terminal of the second capacitor Cpd 220. In a preferred example, the first clamping circuit system 224 includes a first diode 226 having a cathode terminal coupled to the first terminal of the second capacitor Cpd 220 and an anode terminal coupled to ground, such that the voltage at the first terminal of the second capacitor Cpd 220 is clamped by the first diode 226 to a first specific voltage above to prevent the second current signal Is from charging the first capacitor 208. In a preferred example, the timer control circuit system 202 includes a second resistor 228 coupled in parallel with the second capacitor Cpd 220. When the minimum duration Toff_min determines the actual duration Toff of the second state of the first switch 102, the second resistor 228 is configured to provide a slower discharge path to discharge the second capacitor Cpd 220 more slowly, thereby keeping the DC-DC converter system 100 in a steady state.

[0032] In another preferred embodiment, the charge pump circuit system 214 further includes a second clamping circuit system 229 having a second diode 230 (with an anode terminal coupled to a first terminal of a second capacitor Cpd 220 and a cathode terminal coupled to a voltage supply) such that the voltage at the first terminal of the second capacitor Cpd 220 is clamped below a second specific voltage (based on the voltage supply and threshold voltage of the second diode 230) to clamp the second current signal Is below a maximum value based on the second specific voltage, so as to limit the switching frequency Fsw of the DC-DC converter system 100 above a specific minimum value.

[0033] Figure 3A During the input voltage VIN transition state Figure 1The diagram 300 shows the analog waveforms of the DC-DC converter system 100, where the target output voltage VOUT_target is set to 5V, the target switching frequency Fsw_target is set to approximately 600kHz, and the minimum off-time Toff_min is set to 190ns. The input voltage VIN302 of the DC-DC converter system 100 decreases from a voltage level relatively higher than the target output voltage VOUT_target to a voltage slightly higher than the target output voltage VOUT_target. Figure 3B During the first cycle P1, when the input voltage VIN is relatively higher than the target output voltage VOUT_target. Figure 3A A partially enlarged diagram of the simulated waveform, shown in Figure 320. Figure 3C During the second cycle P2, when the input voltage VIN is slightly higher than the target output voltage VOUT_target. Figure 3A A partially enlarged diagram of the simulated waveform, diagram 340.

[0034] like Figure 3A As shown in the image, for reference Figure 1 As the input voltage VIN decreases, the minimum duration Toff_min begins to determine the actual duration Toff of the second state of the first switch 102, and the control signal S ON The phase difference between the loop control signal LoopRaw and the phase difference increases. As described above, the phase difference is detected and converted into a charging signal Sc to charge the second capacitor Cpd 220. The voltage Vpd 304 across the second capacitor Cpd 220 increases proportionally with the increase in phase difference. The voltage Vpd 304 is converted into a second current signal Is to discharge the first capacitor 208 when the first switch 102 is in the first state, thereby extending the first duration Ton of the first state of the first switch 102. When the actual second duration Toff is fixed based on the minimum duration Toff_min, the switching cycle Tsw is extended. The switching duty cycle of system 100 is increased to maintain the output voltage VOUT at the target output voltage VOUT_target.

[0035] like Figure 3B As shown, when the input voltage VIN is approximately 5.8V (which is relatively higher than the target output voltage VOUT_target): the target second duration Toff of the second state of the first switch 102 (determined by the loop control circuit system 112) is greater than the minimum duration Toff_min; and the first control signal S is essentially simultaneously with the assertion of the loop control signal LoopRaw. ONAssertion. At time T1, in response to the assertion of the loop control signal LoopRaw 326 and substantially simultaneously with the assertion of the loop control signal LoopRaw 326, the control signal S is... ON Assertion 324. The charging signal 328 is a substantially periodic pulse signal due to the delay of control logic 114. The output voltage VOUT 330 remains substantially approximately 5V, and the voltage Vpd 332 at the first terminal of the second capacitor Cpd 220 remains 0V because there is no current charging the second capacitor Cpd 220. The first duration Ton is approximately 1.632μs.

[0036] like Figure 3C As shown, when the input voltage VIN 342 decreases to approximately 5.6V, which is relatively closer to the target output voltage VOUT_target, the first control signal S is applied after the assertion of the loop control signal LoopRaw. ON It is asserted that the target second duration Toff_target of the second state of the first switch 102 (determined by the loop control circuit system 112) is less than the minimum duration Toff_min. Therefore, the minimum duration Toff_min determines the actual second duration Toff of the second state of the first switch 102. At time T3: the loop control signal LoopRaw 346 is asserted, and the control signal S is asserted later at time T4 due to the minimum turn-off time control. ON Assertion 344 establishes a phase difference ΔT relative to the loop control signal LoopRaw 346. In response to the phase difference ΔT, the charging signal Sc 348 is asserted within a time period, allowing the first current source Ic to charge the second capacitor Cpd, thereby increasing the voltage Vpd 352. As described above, the voltage Vpd 352 is converted into a second current source Is to discharge the first capacitor Cs 208 when the first switch 102 is in the ON state, thereby extending the first duration Ton of the first switch 102. Figure 3C As shown, the first duration Ton is extended to approximately 2.334 μs, thus keeping the output voltage VOUT 350 essentially at approximately 5V. The switching cycle Tsw is extended to approximately 2.524 μs, thus reducing the switching frequency Fsw to approximately 400 kHz.

[0037] Figure 3D In the steady state of the input voltage VIN Figure 1The analog waveform diagram 360 of the DC-DC converter system 100 is shown, where the input voltage VIN is set to 5.5V, the target output voltage VOUT_target = 5V, the target switching frequency Fsw_target is approximately 600kHz, and the minimum off-time Toff_min is 190ns. In the steady state, by extending as reference... Figure 1 The first duration Ton of the first switch 102, as described, keeps the output voltage VOUT 368 substantially at the target output voltage of 5V, and reduces the switching frequency Fsw to 292kHz. The control signal S is switched substantially simultaneously with the assertion of the loop control signal LoopRaw 364. ON Assume 362 that the charging signal Sc 366, due to the delay in control logic 114, is again a substantially periodic pulse signal, causing voltage Vpd 370 to increase. Voltage Vpd 370 then decreases through the discharge path provided by the second resistor 228.

[0038] Figure 4 This is a schematic block diagram of an adaptive on-time buck DC-DC converter system 400. System 400 is basically similar to... Figure 1 System 100, except for system 400, does not include the timer control circuit system 116 of system 100. Control logic 414 is configured to: (a) turn off the first switch 402 based on a timing signal One_shot (which is generated by timer circuit system 410 based on the input voltage VIN and output voltage VOUT of system 400 and the target switching frequency Fsw_target), and (b) turn on the first switch 402 based on the minimum duration of the off state of the first switch and the loop control signal LoopRaw. The loop control signal LoopRaw is generated by loop control circuit system 412 based on the difference between a feedback voltage proportional to the output voltage VOUT and a specific reference voltage VREF.

[0039] Figure 5 yes Figure 4Illustrative diagram 500 shows the waveforms of the DC-DC converter 400. The voltage VSW502 at the switching terminal SW switches to the input voltage VIN during the first duration Ton of the first switch 402. The inductor current IL504 through inductor 406 and the feedback voltage VFB506 ramp up. At time T1, the timer circuit system 410 expires, causing the first switch 402 to turn off. The voltage VSW502 at the switching terminal SW switches to ground GND during the second duration Toff of the first switch 402. The inductor current IL504 through inductor 406 and the feedback voltage VFB506 ramp down. At time T2, the feedback voltage VFB506 drops to a specific reference voltage VREF508. When the input voltage VIN is sufficiently higher than the target output voltage VOUT_target, the second duration Toff is greater than the minimum duration Toff_min of the second state of the first switch 402, and the first switch 402 is turned on again at time T2.

[0040] Figure 6A This is when the input voltage VIN is relatively higher than the target output voltage VOUT. Figure 4 The analog waveform diagram 600 of the DC-DC converter shows that the second duration Toff of the second state of the first switch 102 (determined by the loop control circuit system 412) is greater than the minimum duration Toff_min. Figure 6A In this configuration, the input voltage VIN is 12V, the target output voltage is set to 5V, the target switching frequency Fsw_target is approximately 600kHz, and the minimum off-time Toff_min is 190ns. At time T1, the control signal S is switched on substantially simultaneously with the assertion of the loop control signal LoopRaw 602. ON 606 asserts. The output voltage VOUT 604 remains approximately 5V.

[0041] Figure 6B When the input voltage VIN is relatively close to the target output voltage VOUT Figure 4 The analog waveform of the DC-DC converter is shown in diagram 610, where the second duration Toff of the second state of the first switch 402 (determined by the loop control circuit system 412) is less than the minimum duration Toff_min. Figure 6B In the middle, the input voltage VIN decreases to 5.6V, while the target output voltage remains set to 5V. At time T1: (a) the loop control signal LoopRaw 612 is asserted, and later at time T2, the control signal S is asserted due to minimum turn-off time control. ONAssertion 616 establishes a phase difference ΔT relative to the loop control signal LoopRaw 612. Therefore, the actual second duration Toff of the first switch 402 is greater than the target second duration Toff_target (determined based on the loop control signal LoopRaw 612), and as the actual second duration Toff increases, the first switch 402 switches from the second state to the first state later than the assertion of the loop control signal LoopRaw 612. The first duration Ton is not large enough to provide sufficient energy through the inductor 406. The reduction in the switching duty cycle of system 400 causes the output voltage VOUT 614 to drop to approximately 4.81V.

[0042] Figure 7 This is a flowchart of a method for operating a DC-DC converter system according to the implementation scheme described herein.

[0043] Starting at step 702, refer to Figure 1 DC-DC converter system 100 and Figure 2 The timer circuit system 200 and timer control circuit system 202 are configured. The timer circuit system 110 determines the first duration Ton of the first state (e.g., on state) of the first switch 102 by charging the first capacitor Cs 208 to a voltage K·VOUT proportional to the output voltage VOUT with a charging current I0 when the first switch 102 is turned on. The charging current I0 is generated based on the input voltage VIN. When the first duration Ton expires, the timer circuit system 110 generates a timing signal One_shot to switch the first switch 102 from the first state to a second state (e.g., off state). When the first switch 102 is turned off, the first capacitor Cs 208 is discharged to ground.

[0044] At step 704, the loop control circuit system 112: (a) determines a target second duration Toff_target for the second state of the first switch 102 based on a feedback voltage VFB proportional to the output voltage VOUT and based on a specific reference voltage VREF, and (b) generates a loop control signal LoopRaw to switch the first switch 102 from the second state to the first state.

[0045] At step 706, control logic 114 generates a first control signal S based on the loop control signal LoopRaw and the minimum duration Toff_min of the second state of the first switch 102. ON In one instance, the first control signal S is set when the loop control signal LoopRaw is asserted and the minimum duration Toff_min expires. ON assertion.

[0046] At step 708, the phase detector 212 of the timer control circuit system 202 detects the loop control signal LoopRaw and the first control signal S. ON The phase difference between them. In one example, phase detector 212 generates a charging signal Sc with a duration based on the phase difference.

[0047] At step 710, the charge pump circuit system 214 generates a second current Is proportional to the duration of the charging signal Sc. In one example, the charge pump circuit system 214 includes: (a) a first current source Ic configured to charge a second capacitor Cpd 220 based on the charging signal Sc to generate a voltage Vpd at a first terminal of the capacitor Cpd 220; and (b) a transconductance amplifier 222 configured to convert the voltage Vpd into the second current Is. In one example, the voltage Vpd is clamped above (a) a first specific voltage level to prevent the second current Is from charging the first capacitor Cs 208 and below a second specific voltage level to limit the switching frequency Fsw of the DC-DC converter system 100 above a specific minimum value.

[0048] At step 712, when the first switch is turned on, the first capacitor Cs 208 is discharged with a second current Is, thereby reducing the current charged to the first capacitor Cs 208 and extending the first duration Ton of the first switch 102. Therefore, in the converter system 100, when the minimum duration Toff_min determines the actual duration Toff of the second state of the first switch 102, (a) the actual second duration Toff of the converter system 100 is fixed based on the minimum duration Toff_min, (b) the first duration Ton is extended proportionally to the phase difference, and (c) the switching frequency Fsw of the DC-DC converter system 100 is smoothly reduced.

[0049] In this specification, the term "coupled" may encompass a connection, communication, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection, or (b) in a second instance, device A is coupled to device B via an intervening component C (without altering the functional relationship between device A and device B) such that the control signal generated by device B via device A is controlled by device A.

[0050] In the described examples, modifications are possible, and other examples are possible within the scope of the claims.

Claims

1. A voltage converter system comprising: A switch configured to switch between a first state and a second state in response to a first control signal; A timer circuit system configured to generate a timing signal representing the duration of the first state based on the input and output voltages of the voltage converter system; Control logic coupled to the switch and the timer circuit system and configured to generate the first control signal based on a second control signal, wherein the second control signal is based on a feedback voltage and a reference voltage; and A timer control circuit system coupled to the control logic and the timer circuit system, and configured to: detect the phase difference between the first control signal and the second control signal, and adjust the timer circuit system to change the duration based on the phase difference.

2. The voltage converter system according to claim 1, further comprising: A loop control circuit system having a comparator configured to generate the second control signal based on the feedback voltage and the reference voltage.

3. The voltage converter system of claim 2, wherein the comparator is a first comparator, and the timer circuit system comprises: A second comparator has: a first input, a second input, and a comparator output configured to receive the output voltage, wherein the second comparator is configured to provide the timing signal at the comparator output; and A capacitor, which is coupled to the second input and configured to receive current.

4. The voltage converter system according to claim 3, wherein: The current is the first current; The timer control circuit system includes a phase detector configured to receive the first control signal and the second control signal, and generate a charging signal based on the phase difference between the first control signal and the second control signal. and The timer control circuit system is configured to generate a second current based on the charging signal.

5. The voltage converter system according to claim 4, wherein the timer control circuit system comprises: A control switch configured to receive the charging signal; and An amplifier coupled to the switch and configured to provide the second current.

6. The voltage converter system of claim 5, wherein the capacitor is configured to receive the first current canceled by the second current and to delay changes in the first control signal.

7. The voltage converter system of claim 5, wherein the capacitor is a first capacitor, and the timer control circuit system comprises: Current source; and A second capacitor is coupled to the amplifier, wherein the control switch is coupled between the current source and the second capacitor.

8. The voltage converter system according to claim 7, wherein the timer control circuit system comprises: A clamping circuit system coupled to the second capacitor and configured to clamp the voltage at the second capacitor within a voltage range.

9. The voltage converter system of claim 4, wherein the phase detector comprises a D flip-flop having: a data input configured to receive the second control signal, a clock input configured to receive the first control signal, and a flip-flop output, wherein the D flip-flop output is configured to provide the charging signal.

10. A controller for a voltage converter system having a switch configured to switch between a first state and a second state in response to a first control signal, the controller comprising: A timer circuit system configured to generate a timing signal representing the duration of the first state based on the input and output voltages of the voltage converter system; Control logic coupled to the timer circuit system and adapted to be coupled to the switch, and configured to generate the first control signal based on a second control signal, wherein the second control signal is based on a feedback voltage and a reference voltage; and A timer control circuit system coupled to the control logic and the timer circuit system, and configured to: detect the phase difference between the first control signal and the second control signal, and adjust the timer circuit system to change the duration based on the phase difference.

11. The controller of claim 10, wherein the timer circuit system comprises: A comparator having: a first input, a second input, and a comparator output configured to receive the output voltage, wherein the comparator is configured to provide the timing signal at the comparator output; and A capacitor, which is coupled to the second input and configured to receive current.

12. The controller according to claim 11, wherein: The current is the first current; The timer control circuit system includes a phase detector configured to receive the first control signal and the second control signal, and generate a charging signal based on the phase difference between the first control signal and the second control signal. and The timer control circuit system is configured to generate a second current based on the charging signal.

13. The controller according to claim 12, wherein the timer control circuit system comprises: A control switch configured to receive the charging signal; and An amplifier adapted to be coupled to the switch and configured to provide the second current.

14. The controller of claim 13, wherein the capacitor is configured to receive the first current canceled by the second current and to delay changes in the first control signal.

15. The controller of claim 13, wherein the capacitor is a first capacitor, and the timer control circuit system comprises: Current source; and A second capacitor is coupled to the amplifier, wherein the control switch is coupled between the current source and the second capacitor.

16. The controller of claim 15, wherein the timer control circuit system comprises: A clamping circuit system coupled to the second capacitor and configured to clamp the voltage at the second capacitor within a voltage range.

17. The controller of claim 12, wherein the phase detector comprises a D flip-flop having: a data input configured to receive the second control signal, a clock input configured to receive the first control signal, and a flip-flop output, wherein the D flip-flop output is configured to provide the charging signal.

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