Power switch device driver and driving method

Abstract

The application discloses a power switch device driver and a driving method. The power switch device driver comprises a first switch, a second switch, a third switch, a fourth switch and a logic controller. The power switch device driver and the driving method realize energy recovery without sacrificing the switching speed and reduce the loss.

Description

Technical Field

[0001] This invention relates to an electronic circuit, and more specifically, to a power switching device driver and driving method. Background Technology

[0002] Controllable power switching devices, such as MOSFETs and IGBTs, require drive circuits to control their on / off states. Existing technologies typically employ... Figure 1 The single-bridge driver 50 (also known as a totem-pole driver) shown drives the power switching device S1. The driver 50 charges and discharges the gate capacitance of the power switching device S1 through fixed power supplies VDD and GND. Therefore, energy is lost twice on the gate capacitance in each switching cycle, which greatly reduces efficiency. Summary of the Invention

[0003] Therefore, the purpose of this invention is to solve the above-mentioned technical problems of the prior art and to propose an improved power switching device driver and driving method.

[0004] According to an embodiment of the present invention, a power switching device driver is provided for driving a power switching device having a first terminal, a second terminal, a control terminal, and an effective capacitor formed between the first terminal and the control terminal. The power switching device driver includes: a first switch coupled between a supply voltage and a first terminal of an inductor; a second switch coupled between the first terminal of the inductor and a reference voltage; a third switch coupled between a second terminal of the inductor and the supply voltage; a fourth switch coupled between the second terminal of the inductor and the reference voltage; and a logic controller that controls the first to fourth switches in response to a logic control signal, an inductor current, and a voltage across the effective capacitor. When the logic control signal goes high, the logic controller controls the first switch to turn on and controls the second, third, and fourth switches to turn off to charge the effective capacitor.

[0005] According to an embodiment of the present invention, a power switching device driver is also provided for driving a controllable power switching device, the controllable power switching device having a first terminal, a second terminal, a control terminal, and an effective capacitor formed between the first terminal and the control terminal. The power switching device driver includes: a first switch coupled between a supply voltage and a first terminal of an inductor; a second switch coupled between the first terminal of the inductor and a reference voltage; a third switch coupled between a second terminal of the inductor and the supply voltage; a fourth switch coupled between the second terminal of the inductor and the reference voltage; and a logic controller having: a first current comparator comparing a sampled signal characterizing the inductor current with a first current threshold; a first voltage comparator comparing the voltage across the effective capacitor with a first voltage limit; a second current comparator comparing the sampled signal with a second current threshold; and a second voltage comparator comparing the voltage across the effective capacitor with a second voltage limit; and a logic unit controlling the first to fourth switches in response to a logic control signal and the comparison results of the first current comparator, the first voltage comparator, the second current comparator, and the second voltage comparator.

[0006] According to an embodiment of the present invention, a driving method for driving a power switching device is also proposed. The power switching device has a first terminal, a second terminal, a control terminal, and an effective capacitor formed between the first terminal and the control terminal. The method includes: driving the power switching device using a first switch, a second switch, a third switch, a fourth switch, and an inductor, wherein the first switch is coupled between a first terminal of the inductor and a supply voltage, the second switch is coupled between a first terminal of the inductor and a reference voltage, the third switch is coupled between a second terminal of the inductor and the supply voltage, and the fourth switch is coupled between a second terminal of the inductor and the reference voltage; controlling the first switch, the second switch, the third switch, and the fourth switch in response to a logic control signal, an inductor current, and a voltage across the effective capacitor; and turning on the first switch and turning off the second, third, and fourth switches when the logic control signal goes high, so as to charge the effective capacitor.

[0007] According to the above-described power switching device driver and driving method of various aspects of the present invention, energy recovery is achieved without sacrificing switching speed, thereby reducing losses. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of the circuit structure of an existing single-bridge arm driver 50;

[0009] Figure 2 This is a schematic diagram of the circuit structure of a power switching device driver 100 according to an embodiment of the present invention;

[0010] Figure 3 A schematic diagram of the circuit structure of the logic controller 106 according to an embodiment of the present invention is shown;

[0011] Figure 4 The schematic diagram illustrates the logic control signal PWM and the first to fourth control signals G. Q1 ~G Q4 Sampling signal I L And the voltage V across the effective capacitor 14 C Waveform diagram;

[0012] Figure 5 A schematic flowchart 500 of a driving method for driving a power switching device according to an embodiment of the present invention is shown. Detailed Implementation

[0013] Specific embodiments of the present invention will now be described in detail. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that these specific details are not necessary to practice the invention. In other instances, well-known circuits, materials, or methods have not been specifically described to avoid obscuring the invention.

[0014] Throughout this specification, references to “an embodiment,” “an example,” or “an example” mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the invention. Therefore, the phrases “in an embodiment,” “in an embodiment,” “an example,” or “an example” appearing in various places throughout the specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics can be combined in one or more embodiments or examples in any suitable combination and / or sub-combination. Moreover, those skilled in the art will understand that the accompanying drawings provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an element is referred to as “coupled to” or “connected to” another element, it can be directly coupled to or coupled to the other element, or there may be intermediate elements. Conversely, when an element is referred to as “directly coupled to” or “directly connected to” another element, there are no intermediate elements. The same reference numerals indicate the same elements. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items.

[0015] Figure 2 This is a schematic diagram of the circuit structure of a power switching device driver 100 according to an embodiment of the present invention. Figure 2In the illustrated embodiment, the power switching device driver 100 is used to drive a power switching device M1. The power switching device M1 has a first terminal 11, a second terminal 12, a control terminal 13, and an effective capacitor 14 formed between the first terminal 11 and the control terminal 13. The power switching device driver 100 includes: a first switch Q1, coupled between the supply voltage VDD and the first terminal 111 of the inductor 101; a second switch Q2, coupled between a reference voltage (such as ground or a negative voltage rail) and the first terminal 111 of the inductor 101; a third switch Q3, coupled between the supply voltage VDD and the second terminal 112 of the inductor 101; and a fourth switch Q4, coupled between the reference voltage and the second terminal 112 of the inductor 101.

[0016] exist Figure 2 In the illustrated embodiment, the power switching device driver 100 further includes: a logic controller 106, which responds to a logic control signal PWM and an inductor current (such as a sampling signal I characterizing the inductor current). L and the voltage V across the effective capacitor 14 C This is used to control the first to fourth switches Q1 to Q4.

[0017] In one embodiment of the present invention, when the logic control signal PWM goes high, the logic controller 106 controls the first switch Q1 to turn on and controls the second to fourth switches Q2 to Q4 to turn off, so as to charge the effective capacitor 14.

[0018] In one embodiment of the present invention, the power switching device may include a MOSFET or an IGBT. In other embodiments of the present invention, the power switching device may also include other switching devices, such as BJTs.

[0019] In one embodiment of the present invention, when the first condition is met, the logic controller 106 controls the first switch Q1 and the third switch Q3 to turn on, and controls the second switch Q2 and the fourth switch Q4 to turn off, so as to pull the voltage across the effective capacitor 14 to the supply voltage. In one embodiment of the present invention, the first condition is met when the inductor current reaches a first current limit or the voltage across the effective capacitor 14 reaches a first voltage limit. In another embodiment of the present invention, the first condition is met when the preset timer reaches a predetermined duration.

[0020] In one embodiment of the present invention, when the voltage V across the effective capacitor 14... C Approximately the supply voltage VDD (e.g., voltage V) C When the supply voltage VDD is reached, the logic controller 106 controls the second switch Q2 and the third switch Q3 to turn on, and controls the first switch Q1 and the fourth switch Q4 to turn off.

[0021] In one embodiment of the present invention, when the inductor current drops to zero, the logic controller 106 controls the first switch Q1 and the third switch Q3 to turn on, and controls the second switch Q2 and the fourth switch Q4 to turn off.

[0022] In one embodiment of the present invention, when the logic control signal PWM goes low, the logic controller 106 controls the second switch Q2 to turn on and controls the first switch Q1, the third switch Q3 and the fourth switch Q4 to turn off, so as to discharge the effective capacitor 14.

[0023] In one embodiment of the present invention, when the second condition is met, the logic controller 106 controls the second switch Q2 and the fourth switch Q4 to be turned on, and controls the first switch Q1 and the third switch Q3 to be turned off, so as to reduce the voltage V across the effective capacitor 14. C It is pulled to the reference voltage via the fourth switch Q4. In one embodiment of the invention, when the inductor current reaches the second current limit, or the voltage V across the effective capacitor 14... C When the voltage drops to the second voltage limit, the second condition is satisfied. In another embodiment of the invention, the second condition is satisfied when a preset timer reaches a predetermined duration.

[0024] In one embodiment of the present invention, when the voltage V across the effective capacitor 14... C Approximate reference voltage (e.g., V) C When the voltage drops to the reference voltage, the logic controller 106 controls the first switch Q1 and the fourth switch Q4 to turn on, and controls the second switch Q2 and the third switch Q3 to turn off.

[0025] In one embodiment of the present invention, when the inductor current drops to zero, the logic controller 106 controls the first switch Q1 and the third switch Q3 to open, and controls the second switch and the fourth switch Q4 to open.

[0026] In one embodiment of the invention, a first voltage limit is lower than the Miller plateau voltage of the MOSFET, and a second voltage limit is higher than the Miller plateau voltage. The so-called Miller plateau voltage is generated by the irrational characteristics of semiconductor switches. During charging and discharging at the control terminal (e.g., the gate) of a semiconductor switch, there exists a horizontal voltage portion known as the Miller plateau. When the switching device is about to be turned on / off, the voltage at the control terminal is effectively clamped at the plateau voltage until sufficient charge accumulates / discharges on the control terminal before the control terminal voltage can continue to increase / decrease.

[0027] Figure 3 A schematic diagram of the circuit structure of a logic controller 106 according to an embodiment of the present invention is shown. Figure 3 In the illustrated embodiment, the logic controller 106 includes: a first current comparator 61, which compares the sampled signal I. L With the first current threshold I TH1Size; First voltage comparator 71, compares the voltage V across effective capacitor 14. C With the first voltage limit V L1 The magnitude; the second current comparator 62, compares the sampled signal I. L With the second current threshold I TH2 The size; the second voltage comparator 72 compares the voltage V across the effective capacitor 14. C With the second voltage limit V L2 Size.

[0028] exist Figure 3 In the illustrated embodiment, the logic controller 106 further includes: a logic unit 63, which generates a first control signal G in response to the logic control signal PWM and the comparison results of a first current comparator, a first voltage comparator, a second current comparator, and a second voltage comparator. Q1 Second control signal G Q2 Third control signal G Q3 and the fourth control signal G Q4 To control the first switch Q1, the second switch Q2, the third switch Q3 and the fourth switch Q4 respectively.

[0029] In other words, logic unit 63 responds to the logic control signal PWM and the sampling signal I. L With the first current threshold I TH1 Comparison results, 2) Voltage V across effective capacitor 14 C With the first voltage limit V L1 Comparison results, 3) Sampled signal I L With the second current threshold I TH2 Comparison results, 4) Voltage V across effective capacitor 14 C With the second voltage limit V L2 The comparison results are used to control the on / off state of the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4.

[0030] In one embodiment of the present invention, the logic controller 106 further includes: a first logic OR unit 64, for sampling signal I) L With the first current threshold I TH1 The comparison results are consistent with the voltage V across the effective capacitor 14 in step 2). C With the first voltage limit V L1 The comparison result is used to perform a logical OR operation.

[0031] In one embodiment of the present invention, the logic controller 106 further includes: a logic OR unit 65, for sampling signal I (3). L With the second current threshold I TH2 The comparison results are consistent with the voltage V across the effective capacitor 14 in step 4). CWith the second voltage limit V L2 The comparison result is used to perform a logical OR operation.

[0032] Figure 4 The schematic diagram illustrates the logic control signal PWM and the first to fourth control signals G. Q1 ~G Q4 Sampling signal I L And the voltage V across the effective capacitor 14 C The waveform diagram.

[0033] Time period t0-t1: At time t0, the logic control signal PWM changes from low to high. Correspondingly, the first control signal G... Q1 The signal increases to turn on the first switch Q1; the fourth control signal G... Q4 The signal decreases to disconnect the fourth switch Q4; the second control signal G... Q2 and the third control signal G Q3 The current is kept low to maintain the open state of the second switch Q2 and the third switch Q3, respectively. At this time, the supply voltage VDD, the first switch Q1, the inductor 101, and the effective capacitor 14 form a current loop. The inductor current (e.g., the sampling signal I...) L Starting from zero, the effective capacitance 14 is charged, causing the voltage V to increase. C rise.

[0034] Time period t1-t2: At time t1, the sampled signal I L Increase to the first current threshold I TH1 This indicates that the inductor current has reached the first current limit. The third control signal G Q3 The signal increases to turn on the third switch Q3, and the first control signal G... Q1 Keep it high to maintain the conducting state of the first switch Q1; the second control signal G Q2 and the fourth control signal G Q4 The current is kept low to maintain the open state of the second switch Q2 and the fourth switch Q4. At this time, the supply voltage VDD, the first switch Q1, the inductor 101, the third switch Q3, and the effective capacitor 14 form a current loop. The inductor current (such as the sampling signal I) L As the voltage continues to increase, the voltage across the effective capacitor 14 increases by V. C It was quickly pulled up to the supply voltage.

[0035] In one embodiment of the invention, if the voltage V is lower than the inductor current before the inductor current reaches a first current limit... C Reaching the first voltage limit V L1 Then the third control signal G Q3 The signal will immediately rise to turn on the third switch Q3; at this time, the first control signal G... Q1 Keep it high, second control signal G Q2and the fourth control signal G Q4 Keep it low.

[0036] Time period t2-t3: At time t2, the voltage V C Approximately the supply voltage VDD (i.e., voltage V) C The voltage difference between the supply voltage VDD and the drain-source voltage of the third switch Q3 is high enough to turn on the power switching device M1. The third control signal G... Q3 Keep it high to maintain the conducting state of the third switch Q3; the first control signal G Q1 The signal decreases to disconnect the first switch Q1; the second control signal G... Q2 The voltage increases, and at this time, because the inductor current flows through the body diode of the second switch Q2, the second switch Q2 is turned on with zero voltage; the fourth control signal G Q4 It remains low to keep the fourth switch Q4 in the open state. Therefore, the remaining energy of inductor 101 (i.e., the non-zero inductor current) is returned to the supply voltage VDD.

[0037] Time period t3-t4: At time t3, the inductor current drops to zero. Second control signal G. Q2 The value decreases, allowing the second switch Q2 to be turned off with zero current. First control signal G Q1 The signal increases to turn on the first switch Q1; the third control signal G... Q3 Keep it high to maintain the on state of the third switch Q3 and ensure voltage V. C Approximate the supply voltage VDD to provide sufficient drive capability; fourth control signal G Q4 Keep it low to maintain the open state of the fourth switch Q4.

[0038] Time period t4-t5: At time t4, the logic control signal PWM changes from high to low. Correspondingly, the second control signal G... Q2 The signal increases to turn on the second switch Q2; the first control signal G... Q1 and the third control signal G Q3 The signal decreases to disconnect the first switch Q1 and the third switch Q3; the fourth control signal G... Q4 The current remains low to maintain the open state of the fourth switch Q4. At this time, the effective capacitor 14, inductor 101, and second switch Q2 form a current loop. The inductor current (e.g., the sampling signal I)... L Starting from zero and increasing in the negative (reverse) direction, the effective capacitance 14 is discharged, causing the voltage V to increase. C decline.

[0039] Time period t5-t6: At time t5, the sampled signal I... L Negative increase to the second current threshold I TH2This indicates that the inductor current has reached the second current limit. The fourth control signal G... Q4 The signal increases to activate the fourth switch Q4; the second control signal G... Q2 Keep it high to maintain the conducting state of the second switch Q2; the first control signal G Q1 and the third control signal G Q3 The value remains low to maintain the open state of the first switch Q1 and the third switch Q3. At this time, the effective capacitor 14, the fourth switch Q4, the inductor 101, and the second switch Q2 form a current loop. The inductor current (i.e., the sampling signal I)... L The voltage V across the effective capacitor 14 continues to increase negatively. C It is quickly pulled to the reference voltage (such as ground voltage).

[0040] In one embodiment of the invention, if the voltage V is lower than the inductor current before the second current limit is reached... C Drop to the second voltage limit V L2 Then the fourth control signal G Q4 The signal immediately increases to activate the fourth switch Q4; at this time, the second control signal G... Q2 Keep it high, first control signal G Q1 and the third control signal G Q3 Keep it low.

[0041] Time period t6-t7: At time t6, the voltage V C The voltage is close to the reference voltage, low enough to disconnect power switching device M1. Fourth control signal G Q4 Keep it high to maintain the conducting state of the fourth switch Q4; the second control signal G Q2 The signal decreases to disconnect the second switch Q2, and the first control signal G... Q1 The voltage increases, and at this time, because the inductor current flows through the body diode of the first switch Q1, the first switch Q1 is turned on with zero voltage; the third control signal G Q3 It remains low to keep the third switch Q3 in the open state. Therefore, the remaining energy on inductor 101 is returned to the supply voltage VDD.

[0042] Time period t7-t8: At time t7, the inductor current drops to zero. First control signal G. Q1 The current decreases, thus the first switch Q1 is disconnected by zero current; the second control signal G... Q2 The signal increases to turn on the second switch Q2; the fourth control signal G... Q4 Keep it high to maintain the on state of the fourth switch Q4 and ensure voltage V. C Approaching the reference voltage to fully disconnect power switching device M1; third control signal G Q3 Keep it low to maintain the open state of the third switch Q3.

[0043] Then at time t8, the logic control signal PWM changes from low to high again, a new switching cycle begins, and it operates as discussed above.

[0044] Figure 5 A schematic flowchart 500 of a driving method for driving a power switching device according to an embodiment of the present invention is shown. The power switching device has a first terminal, a second terminal, a control terminal, and an effective capacitor formed between the first terminal and the control terminal. The method includes:

[0045] Step 501: A power switching device is driven by a first switch, a second switch, a third switch, a fourth switch, and an inductor, wherein the first switch is coupled between the first terminal of the inductor and the supply voltage, the second switch is coupled between the first terminal of the inductor and the reference voltage, the third switch is coupled between the second terminal of the inductor and the supply voltage, and the fourth switch is coupled between the second terminal of the inductor and the reference voltage.

[0046] Step 502: In response to the logic control signal, inductor current and voltage across the effective capacitor, control the first switch, the second switch, the third switch and the fourth switch.

[0047] Step 503: When the logic control signal goes high, the first switch is turned on, and the second, third and fourth switches are turned off to charge the effective capacitor.

[0048] In one embodiment of the present invention, the method further includes: when a first condition is met, turning on a third switch, maintaining the on state of the first switch, and maintaining the off state of the second and fourth switches, so as to pull the voltage across the effective capacitor to close to the supply voltage. In one embodiment of the present invention, the first condition includes: the inductor current reaching a first current limit or the voltage across the effective capacitor reaching a first voltage limit.

[0049] In one embodiment of the present invention, the method further includes: when the voltage across the effective capacitor is close to the supply voltage, disconnecting the first switch, turning on the second switch, maintaining the on state of the third switch and the off state of the fourth switch, so as to return the remaining energy of the inductor to the supply voltage.

[0050] In one embodiment of the present invention, the method further includes: when the inductor current drops to zero, turning on the first switch, turning off the second switch, maintaining the third switch in the on state and the fourth switch in the off state.

[0051] In one embodiment of the present invention, the method further includes: when the logic control signal goes low, turning on the second switch and turning off the first switch, the third switch and the fourth switch to discharge the effective capacitor.

[0052] In one embodiment of the present invention, the method further includes: when a second condition is met, turning on a fourth switch, maintaining the on state of the second switch, and keeping the first and third switches off. In one embodiment of the present invention, the second condition includes: the inductor current reaching a second current limit or the voltage across the effective capacitor dropping to a second voltage limit.

[0053] In one embodiment of the present invention, the method further includes: when the voltage across the effective capacitor drops to near the reference voltage, turning on the first switch, turning off the second switch, maintaining the third switch in the off state and the fourth switch in the on state, so as to return the remaining inductor energy to the supply voltage.

[0054] In one embodiment of the present invention, the method further includes: when the inductor current drops to zero, disconnecting the first switch, turning on the second switch, maintaining the disconnected state of the third switch and the on state of the fourth switch.

[0055] The aforementioned power switching device driver according to various embodiments of the present invention achieves energy recovery without sacrificing switching speed. Unlike the prior art, the aforementioned power switching device according to embodiments of the present invention includes a resonant inductor and four switches. By properly controlling the four switches, the effective capacitor is charged without delay when the logic control signal goes high and discharged without delay when the logic control signal goes low, ensuring switching speed. Furthermore, when the effective capacitor is charged to the desired voltage level or discharged to the desired voltage level, the remaining energy is returned to the supply voltage, thereby reducing losses and requiring only half the rated voltage supply of existing drivers.

[0056] Although the invention has been described with reference to several exemplary embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Since the invention can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A power switching device driver for driving a power switching device, the power switching device having a first terminal, a second terminal, a control terminal, and an effective capacitance formed between the first terminal and the control terminal, the power switching device driver comprising: The first switch is coupled between the supply voltage and the first terminal of the inductor; The second switch is coupled between the first terminal of the inductor and the reference voltage; The third switch is coupled between the second terminal of the inductor and the supply voltage; The fourth switch is coupled between the second terminal of the inductor and the reference voltage; A logic controller responds to a logic control signal, inductor current, and voltage across an effective capacitor to control a first to a fourth switch. When the logic control signal goes high, the logic controller turns on the first switch and turns off the second, third, and fourth switches to charge the effective capacitor. When the inductor current reaches a first current limit or the voltage across the effective capacitor reaches a first voltage limit, the logic controller turns on the first and third switches and turns off the second and fourth switches.

2. The power switching device driver as claimed in claim 1, wherein the logic controller: When the voltage across the effective capacitor reaches the supply voltage, the second and third switches are turned on, and the first and fourth switches are turned off. When the inductor current drops to zero, the first and third switches are turned on, and the second and fourth switches are turned off.

3. The power switching device driver as claimed in claim 1, wherein the logic controller: When the logic control signal goes low, the second switch is turned on, and the first, third, and fourth switches are turned off.

4. The power switching device driver as claimed in claim 3, wherein the logic controller: When the inductor current reaches the second current limit or the voltage across the effective capacitor drops to the second voltage limit, control the second and fourth switches to turn on, and control the first and third switches to turn off. When the voltage across the effective capacitor drops to the reference voltage, the first and fourth switches are turned on, and the second and third switches are turned off. When the inductor current drops to zero, the second and fourth switches are turned on, and the first and third switches are turned off.

5. A power switching device driver for driving a controllable power switching device, the controllable power switching device having a first terminal, a second terminal, a control terminal, and an effective capacitance formed between the first terminal and the control terminal, the power switching device driver comprising: The first switch is coupled between the supply voltage and the first terminal of the inductor; The second switch is coupled between the first terminal of the inductor and the reference voltage; The third switch is coupled between the second terminal of the inductor and the supply voltage; The fourth switch is coupled between the second terminal of the inductor and the reference voltage; A logic controller, having: The first current comparator compares the sampled signal representing the inductor current with the magnitude of the first current threshold. The first voltage comparator compares the voltage across the effective capacitor with the first voltage limit. The second current comparator compares the sampled signal with the magnitude of the second current threshold. The second voltage comparator compares the voltage across the effective capacitor with the second voltage limit. The logic unit responds to logic control signals and the comparison results of the first current comparator, the first voltage comparator, the second current comparator, and the second voltage comparator to control the first to fourth switches.

6. The power switching device driver of claim 5, wherein the logic controller: When the logic control signal goes high, the first switch is turned on, and the second, third, and fourth switches are turned off to charge the effective capacitor. When the sampling signal reaches the first current threshold or the voltage across the effective capacitor reaches the first voltage limit, the first and third switches are turned on, and the second and fourth switches are turned off. When the voltage across the effective capacitor reaches the supply voltage, the second and third switches are turned on, and the first and fourth switches are turned off. When the inductor current drops to zero, the first and third switches are turned on, while the second and fourth switches are turned off.

7. The power switching device driver of claim 5, wherein the logic controller: When the logic control signal goes low, the second switch is turned on, and the first, third, and fourth switches are turned off. When the sampling signal reaches the second current threshold or the voltage across the effective capacitor drops to the second voltage limit, the second and fourth switches are controlled to turn on, and the first and third switches are controlled to turn off. When the voltage across the effective capacitor drops to the reference voltage, the first and fourth switches are turned on, and the second and third switches are turned off. When the inductor current drops to zero, the second and fourth switches are turned on, and the first and third switches are turned off.

8. A driving method for driving a power switching device, the power switching device having a first terminal, a second terminal, a control terminal, and an effective capacitance formed between the first terminal and the control terminal, the method comprising: A power switching device is driven by a first switch, a second switch, a third switch, a fourth switch, and an inductor, wherein the first switch is coupled between the first terminal of the inductor and the supply voltage, the second switch is coupled between the first terminal of the inductor and the reference voltage, the third switch is coupled between the second terminal of the inductor and the supply voltage, and the fourth switch is coupled between the second terminal of the inductor and the reference voltage. In response to logic control signals, inductor current, and voltage across the effective capacitor, the first switch, second switch, third switch, and fourth switch are controlled. When the logic control signal goes high, the first switch is turned on, and the second, third, and fourth switches are turned off to charge the effective capacitor. When the inductor current reaches the first current limit or the voltage across the effective capacitor reaches the first voltage limit, the third switch is turned on, the first switch is kept on, and the second and fourth switches are kept off.

9. The driving method as described in claim 8, further comprising: When the voltage across the effective capacitor is close to the supply voltage, the first switch is disconnected, the second switch is turned on, the third switch is kept on, and the fourth switch is kept off. When the inductor current drops to zero, the first switch is turned on, the second switch is turned off, the third switch remains on, and the fourth switch remains off.

10. The driving method as described in claim 8, further comprising: When the logic control signal goes low, the second switch is turned on, and the first, third, and fourth switches are turned off to discharge the effective capacitor. When the inductor current reaches the second current limit or the voltage across the effective capacitor drops to the second voltage limit, the fourth switch is turned on, the second switch is kept on, and the first and third switches are kept off. When the voltage across the effective capacitor drops to near the reference voltage, the first switch is turned on, the second switch is turned off, the third switch remains off, and the fourth switch remains on. When the inductor current drops to zero, the first switch is disconnected, the second switch is turned on, the third switch remains open, and the fourth switch remains on.

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