Analog-to-digital conversion circuit

Abstract

The embodiment of the present application discloses an analog-digital conversion circuit. The circuit comprises N input circuits and an analog-digital converter, wherein N is a natural number greater than 1, for each of the N input circuits: the input circuit comprises a signal acquisition circuit and a sample-and-hold circuit; the signal acquisition circuit is used for converting other signals into a voltage signal; the sample-and-hold circuit is connected with the signal acquisition circuit and is used for amplifying the voltage signal to obtain an output voltage signal; and the analog-digital converter is connected with the output ends of the N input circuits in time domain in sequence and is used for converting the output voltage signals output by the N input circuits into digital signals respectively.

Description

Technical Field

[0001] This application relates to the field of signal processing, and in particular to an analog-to-digital conversion circuit. Background Technology

[0002] The application-specific integrated circuits (ASICs) in a CT (Computed Tomography) imaging system mainly include photoelectric conversion circuits and pixel readout circuits. The former converts light signals into voltage signals, and the latter converts voltage signals into digital signals. The pixel readout circuit is a multi-channel input analog-to-digital conversion system, and its power consumption affects the overall chip performance. Therefore, it is necessary to propose an analog-to-digital conversion circuit to reduce the power consumption of the entire readout circuit. Summary of the Invention

[0003] One embodiment of this application provides an analog-to-digital converter circuit. The circuit includes N input circuits and an analog-to-digital converter, where N is a natural number greater than 1. For each of the N input circuits: the input circuit includes a signal acquisition circuit and a sample-and-hold circuit; the signal acquisition circuit is used to convert other signals into voltage signals; the sample-and-hold circuit is connected to the signal acquisition circuit and is used to amplify the voltage signals to obtain an output voltage signal; the analog-to-digital converter is sequentially connected to the output terminals of the N input circuits in the time domain, and is used to convert the output voltage signals output by the N input circuits into digital signals respectively.

[0004] One embodiment of this application provides an analog-to-digital converter circuit. The circuit includes an input circuit and an analog-to-digital converter. The input circuit includes a signal acquisition circuit and a sample-and-hold circuit. The signal acquisition circuit converts other signals into voltage signals. The sample-and-hold circuit is connected to the signal acquisition circuit and amplifies the voltage signals to obtain an output voltage signal. The sample-and-hold circuit includes a first amplification circuit and a second amplification circuit. The second amplification circuit includes a third switch, the conduction of which is related to the load state of the sample-and-hold circuit. The analog-to-digital converter is connected to the output terminal of the input circuit and converts the output voltage signal from the input circuit into a digital signal.

[0005] The analog-to-digital converter circuit provided in this application uses one analog-to-digital converter to process N input circuits respectively, reducing the number of analog-to-digital converters (ADCs) and thus reducing system cost. Moreover, the sequential processing method can also reduce system power consumption compared to multiple ADCs processing multiple channels simultaneously.

[0006] The analog-to-digital converter circuit provided in this application, through the structure of a two-stage amplifier circuit in the sample-and-hold circuit, achieves better voltage amplification, thereby enhancing the ability to drive the analog-to-digital converter. Furthermore, when driving the analog-to-digital converter is required, a bias current is introduced by closing the third switch, further increasing the current input to the analog-to-digital converter and achieving a better driving effect; conversely, when driving the analog-to-digital converter is not required, the third switch is open, reducing the power consumption of the sample-and-hold circuit and achieving power saving. Attached Figure Description

[0007] This application will be further described by way of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting; in these embodiments, the same reference numerals denote the same structures, wherein:

[0008] Figure 1 This is a schematic diagram of the structure of an analog-to-digital conversion circuit according to some embodiments of this application;

[0009] Figure 2 This is a schematic diagram of the sample-and-hold circuit according to some embodiments of this application. Detailed Implementation

[0010] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of this application. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0011] It should be understood that the terms "system," "device," "unit," and / or "module" used herein are a method of distinguishing different components, elements, parts, sections, or assemblies at different levels. However, if other terms can achieve the same purpose, they may be replaced by other expressions.

[0012] As indicated in this application and claims, unless the context clearly indicates otherwise, the words "a," "an," "an," and / or "the" are not specifically singular and may include plural forms. Generally speaking, the terms "comprising" and "including" only indicate the inclusion of explicitly identified steps and elements, which do not constitute an exclusive list, and the method or apparatus may also include other steps or elements.

[0013] Flowcharts are used in this application to illustrate the operations performed by the system according to embodiments of this application. It should be understood that the preceding or following operations are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from them.

[0014] It should be understood that the application scenarios of the system and method of this application are merely some examples or embodiments of this application. For those skilled in the art, without creative effort, this application can be applied to other similar scenarios based on these drawings.

[0015] It should be noted that the analog-to-digital conversion circuit provided in this application embodiment is a circuit architecture that inputs analog signals through multiple channels and sequentially converts them into digital signals for readout, and it has various application scenarios. In some embodiments, the analog-to-digital conversion circuit provided in this application embodiment can be applied to CT (Computed Tomography) imaging systems, CMOS image sensor systems, CCD image sensor systems, infrared thermal imaging systems, cooling systems, heating systems, and cooling-heating conversion systems, etc.

[0016] Figure 1 This is a schematic diagram of the structure of an analog-to-digital conversion circuit 1000 according to some embodiments of this application. For example... Figure 1 As shown, the analog-to-digital conversion circuit 1000 may include N input circuits 100 and an analog-to-digital converter (ADC) 110, where N is a natural number greater than 1.

[0017] In some embodiments, the N input circuits 100 are N parallel input circuits 100, wherein the N input circuits 100 are electrically connected to the analog-to-digital converter 110. In some embodiments, the output of each of the N input circuits 100 is sequentially electrically connected to the analog-to-digital converter 110 in the time domain. In some embodiments, each of the N input circuits 100 may include a signal acquisition circuit 10 and a sample-and-hold circuit 20, which are connected together. In some embodiments, the signal acquisition circuit 10 and the sample-and-hold circuit 20 may be directly electrically connected. In some embodiments, the signal acquisition circuit 10 and the sample-and-hold circuit 20 may be electrically connected via a first switch 30. In some embodiments, the signal acquisition circuit 10 and the sample-and-hold circuit 20 may be electrically connected via the first switch 30 and a first capacitor 40.

[0018] The signal acquisition circuit 10 is used to convert other signals into voltage signals. In some embodiments, the other signals converted into voltage signals may include, but are not limited to, light signals, infrared signals, temperature signals, and sound signals. In some embodiments, the signal acquisition circuit 10 may be a photoelectric converter (such as a pixel array in an imaging system) for converting light signals into voltage signals. In some embodiments, the signal acquisition circuit 10 may be an infrared sensor for converting infrared signals into voltage signals. In some embodiments, the signal acquisition circuit 10 may be a temperature sensor (such as a resistance temperature sensor or a thermocouple temperature sensor) for converting temperature signals into voltage signals. In some embodiments, the signal acquisition circuit 10 may be a sound sensor (such as a piezoelectric ceramic sensor, a capacitive sensor, or a magnetoelectric sensor) for converting sound signals into voltage signals. In some embodiments, the signal acquisition circuit 10 may be an electrode for converting human physiological signals into voltage signals. In some embodiments, each signal acquisition circuit 10 of the N input circuits 100 obtains its own voltage signal at the same time. In some embodiments, the values ​​of the voltage signals obtained by each signal acquisition circuit 10 of the N input circuits 100 at the same time may be different.

[0019] In some embodiments, the sample-and-hold circuit 20 can be a unity-gain buffer or a sample-and-hold amplifier (SHA). The sample-and-hold amplifier SHA can be used to track or hold the level value of the input analog signal, amplifying the signal value at a fixed time and storing it for a period of time for analog-to-digital conversion. In some embodiments, the sample-and-hold circuit 20 can be used to amplify the voltage signal transmitted by the signal acquisition circuit 10 to obtain an output voltage signal, and transmit the obtained output voltage signal to the analog-to-digital converter 110. It can be understood that the output voltage signals output by the N sample-and-hold circuits 20 of the N input circuits 100 are the N output voltage signals sequentially output by the N input circuits 100 to the analog-to-digital converter 110. In some embodiments, the sample-and-hold circuit 20 can be a series sample-and-hold amplifier, a feedback sample-and-hold amplifier, or a capacitor-corrected sample-and-hold amplifier. More information about the sample-and-hold circuit 20 can be found in [link to relevant documentation]. Figure 2 And its description.

[0020] In some embodiments, the analog-to-digital converter (ADC) 110 is an electronic component that converts analog signals into digital signals, including multiple input channels. In some embodiments, the ADC 110 can be a successive approximation ADC including a comparator, a digital-to-analog converter, a successive approximation register (SAR), and a logic control unit; a double-integration ADC including an analog integrator, a comparator, and a counting unit; a parallel comparison ADC; a voltage-to-frequency conversion ADC; a Σ-Δ ADC; or a pipelined ADC. In some embodiments, the outputs of the N input circuits 100 are sequentially electrically connected to the ADC 110 in the time domain, and the ADC 110 sequentially converts the output voltage signals from the N input circuits 100 into digital signals according to the time-domain sequence. It should be noted that using one analog-to-digital converter 110 to process N input circuits 100 separately can reduce the number of analog-to-digital converters (ADCs), thereby reducing system cost. Moreover, the sequential processing method can also reduce system power consumption compared to multiple ADCs processing multiple channels simultaneously.

[0021] In some embodiments, each of the N input circuits 100 may further include a first switch 30, in which the sample-and-hold circuit 20 and the signal acquisition circuit 10 can be connected via the first switch 30. In some embodiments, by simultaneously closing the first switches 30 of the N input circuits 100, the voltage signals (e.g., voltage signals from pixels in the N imaging systems) acquired by the N signal acquisition circuits 10 at the same time can be transmitted to the corresponding sample-and-hold circuit 20 and the first capacitor 40 respectively. Then, by opening the first switches 30 of the N input circuits 100 and sequentially connecting each sample-and-hold circuit 20 and the analog-to-digital converter 110, the analog-to-digital converter 110 can process the voltage signals acquired by the N signal acquisition circuits 10 at the same time sequentially.

[0022] In some embodiments, the output terminal of the signal acquisition circuit 10 is connected to the first terminal of the first switch 30, and the second terminal of the first switch 30 is connected to the input terminal of the sample-and-hold circuit 20. In some embodiments, each first switch 30 of the N input circuits 100 controls the conduction between each signal acquisition circuit 10 and each sample-and-hold circuit 20 according to a first control signal. In some embodiments, the N first switches 30 of the N input circuits 100 are simultaneously turned on according to the first control signal, so that the N voltage signals obtained by the N signal acquisition circuits 10 at the same time can be simultaneously transmitted to the N sample-and-hold circuits 20; the N first switches 30 of the N input circuits 100 are simultaneously turned off according to the first control signal, so as to avoid the voltage signals held by the sample-and-hold circuits 20 from being changed due to the influence of the corresponding signal acquisition circuits 10.

[0023] In some embodiments, the analog-to-digital conversion circuit 1000 may further include a control circuit for generating a first control signal. In some embodiments, the control circuit may be a circuit or processor (including an internal processor or an external processor) including a timing control module. In some embodiments, the first control signal may be a periodic timing signal. In some embodiments, the timing signal may be a timing signal using synchronous control, a timing signal using asynchronous control, or a timing signal using combined control (i.e., a combination of synchronous and asynchronous control). Specifically, if the timing signal uses synchronous control, it is executed once every fixed period, meaning the first switch 30 can be controlled to turn on or off every fixed period; if the timing signal uses asynchronous control, its execution does not have a fixed period, meaning the time at which the first switch 30 can be controlled to turn on or off does not have a fixed period. In some embodiments, the first switch 30 may be turned on or off according to the control signal, including but not limited to one or more combinations of switching diodes, transistors, field-effect transistors, IGBTs, and MOSFETs.

[0024] In some embodiments, each of the N input circuits 100 may further include a first capacitor 40. In each input circuit, the first capacitor 40 is used to sample the voltage signal input from the signal acquisition circuit 10 to the sample-and-hold circuit 20. In some embodiments, when the first switch 30 is turned on, the signal acquisition circuit 10 outputs voltage to the first capacitor 40 (i.e., charges the first capacitor 40) and simultaneously outputs voltage to the sample-and-hold circuit 20. In some embodiments, when the first switch 30 is turned on, the signal acquisition circuit 10 only outputs voltage to the first capacitor 40, which stores the voltage transmitted from the signal acquisition circuit 10 and transmits the voltage to the sample-and-hold circuit 20 at an appropriate time (for example, a switch can be provided between the first capacitor 40 and the sample-and-hold circuit 20 so that the first capacitor 40 can transmit voltage to the sample-and-hold circuit 20 when the switch is closed). The first capacitor 40 is connected to the second terminal of the first switch 30. In some embodiments, the first capacitor 40 can serve as a noise reduction device. To achieve better sampling and noise reduction effects, the value of the first capacitor 40 can be on the order of pF. In some embodiments, the first capacitor 40 may be a paper capacitor, a metallized paper capacitor, a ceramic capacitor, a film capacitor, an oil-impregnated paper capacitor, an aluminum electrolytic capacitor, a semi-variable capacitor, or a variable capacitor.

[0025] In some embodiments, each of the N input circuits 100 may further include a second switch 50. In each input circuit, the output terminal of the sample-and-hold circuit 20 is connected to the first terminal of the second switch 50, and the second terminal of the second switch 50 is connected to the input terminal of the analog-to-digital converter 110. The N second switches 50 of the N input circuits 100 control the conduction of the N input circuits 100 and the analog-to-digital converter 110 according to a second control signal. In some embodiments, the N second switches 50 of the N input circuits 100 are turned on sequentially according to the second control signal, so that the N input circuits 100 sequentially output voltage signals to the analog-to-digital converter 110. In some embodiments, the N input circuits 100 are numbered 1, 2, 3...N, and the N second switches 50 of the N input circuits 100 are turned on sequentially from 1 to N according to their numbers.

[0026] In some embodiments, the second control signal can be generated by a control circuit. In some embodiments, the control circuit that generates the second control signal can be the same control circuit that generates the first control signal. In some embodiments, the first control signal and the second control signal can each be generated by different control circuits. In some embodiments, the control circuit that generates the second control signal can be a circuit or processor including a timing control module (the processor includes an internal processor or an external processor). In some embodiments, the timing signal can be a timing signal using synchronous control, a timing signal using asynchronous control, or a timing signal using combined control (i.e., a combination of synchronous and asynchronous control). Specifically, if it is a timing signal using synchronous control, the timing signal is executed once every fixed period, that is, the second switch 50 can be controlled to be turned on or off every fixed period; if it is a timing signal using asynchronous control, the execution of the timing signal does not have a fixed period, that is, the time when the second switch 50 can be controlled to be turned on or off does not have a fixed period.

[0027] In some embodiments, the second switch 50 may be turned on or off according to a control signal, including but not limited to one or more combinations of switching diodes, transistors, field-effect transistors, IGBTs and MOSFETs.

[0028] It is understood that by adopting the structure of the embodiment of this application, the voltage signals output by the N signal acquisition circuits 10 in the N input circuits 100 are converted into digital signals in sequence by an analog-to-digital converter 110, thereby reducing the number of analog-to-digital converters 110 and thus reducing the cost of the entire system.

[0029] Figure 2 This is a schematic diagram of the sample-and-hold circuit 20 according to some embodiments of this application. For example... Figure 2 As shown, the sample-and-hold circuit 20 includes a first amplifier circuit 201 and a second amplifier circuit 202. The second amplifier circuit 202 includes a third switch 12, the conduction of which is related to the load state of the sample-and-hold circuit 20. In some embodiments, the third switch 12 can be turned on or off according to a control signal, including but not limited to one or more combinations of switching diodes, transistors, field-effect transistors, IGBTs, and MOSFETs.

[0030] In some embodiments, the analog-to-digital conversion circuit 1000 includes only one input circuit and one analog-to-digital converter 110. The analog-to-digital converter 110 is connected to the output terminal of the input circuit and is used to convert the output voltage signal output by the input circuit into a digital signal.

[0031] In some embodiments, the analog-to-digital converter 1000 includes N input circuits 100 and an analog-to-digital converter 110, where N is a natural number greater than 1. In some embodiments, the N input circuits 100 are N parallel input circuits 100, and the N input circuits 100 and the analog-to-digital converter 110 are electrically connected. In some embodiments, the analog-to-digital converter 110 is sequentially connected to the output terminals of the N input circuits 100 in the time domain, for converting the output voltage signals output by the N input circuits 100 into digital signals sequentially. In some embodiments, the analog-to-digital converter 110 converts the output voltage signals output by the N input circuits 100 into digital signals in a time-domain order. In some embodiments, the N input circuits 100 are numbered 1, 2, 3...N, and the N input circuits 100 are sequentially turned on by the analog-to-digital converter 110 in the order of their numbers from 1 to N.

[0032] In some embodiments, the analog-to-digital conversion circuit 1000 includes N input circuits 100 and N analog-to-digital converters 110, where N is a natural number greater than 1. The N analog-to-digital converters 110 and the N input circuits 100 are electrically connected in a one-to-one correspondence, and are used to convert the output voltage signals output by the N input circuits 100 into digital signals respectively.

[0033] In some embodiments, each input circuit includes a signal acquisition circuit 10 and a sample-and-hold circuit 20, which are connected together. In some embodiments, the signal acquisition circuit 10 and the sample-and-hold circuit 20 can be directly electrically connected. In some embodiments, the signal acquisition circuit 10 and the sample-and-hold circuit 20 can be electrically connected via a first switch 30. In some embodiments, the signal acquisition circuit 10 and the sample-and-hold circuit 20 can be electrically connected via the first switch 30 and a first capacitor 40. In some embodiments, the sample-and-hold circuit 20 is connected to an analog-to-digital converter 110, and the connection method includes, but is not limited to: the sample-and-hold circuit 20 and the analog-to-digital converter 110 can be directly electrically connected, or they can be electrically connected via a second switch 50. It should be understood that the output terminal of the input circuit is the output terminal of the sample-and-hold circuit 20.

[0034] In some embodiments, the sample-and-hold circuit 20 can be a unity-gain buffer or a sample-and-hold amplifier (SHA). The sample-and-hold amplifier SHA can be used to track or hold the level value of the input analog signal, amplifying the signal value at a fixed time and storing it for a period of time for analog-to-digital conversion. In some embodiments, the sample-and-hold circuit 20 can be used to amplify the voltage signal transmitted by the signal acquisition circuit 10 to obtain an output voltage signal, and transmit the obtained output voltage signal to the analog-to-digital converter 110. It can be understood that the output voltage signals output by the N sample-and-hold circuits 20 of the N input circuits 100 are the N output voltage signals sequentially output by the N input circuits 100 to the analog-to-digital converter 110. In some embodiments, the sample-and-hold circuit 20 can be a series sample-and-hold amplifier, a feedback sample-and-hold amplifier, or a capacitor-corrected sample-and-hold amplifier.

[0035] In some embodiments, in each input circuit, when the output of the sample-and-hold circuit 20 is connected to the analog-to-digital converter 110 (i.e., the second switch 50 is on), the sample-and-hold circuit 20 is in a heavy-load state requiring the analog-to-digital converter 110 to be driven. To meet the current requirements of the sample-and-hold circuit 20 under heavy-load conditions, the third switch 12 is on. When the output of the sample-and-hold circuit 20 is disconnected from the analog-to-digital converter 110 (i.e., the second switch 50 is off), the sample-and-hold circuit 20 is in an unloaded state where the analog-to-digital converter 110 does not need to be driven, and the third switch 12 is off. It should be noted that the current of the sample-and-hold circuit 20 when the third switch 12 is on is greater than the current of the sample-and-hold circuit 20 when the third switch 12 is off. This ensures that the sample-and-hold circuit 20 can reach the current required to drive the analog-to-digital converter 110 under heavy-load conditions, while reducing the current under unload conditions, thereby reducing system power consumption. Thus, by turning the third switch 12 on and off, the sample-and-hold circuit 20 can consume different currents, thereby achieving the switching between high and low power consumption of the system.

[0036] In some embodiments, the sample-and-hold circuit 20 amplifies the voltage signal transmitted from the signal acquisition circuit 10 and the first capacitor 40 to obtain an output voltage signal, and transmits the obtained output voltage signal to the analog-to-digital converter 110. The first amplification circuit 201 performs a first-stage amplification on the voltage signal transmitted from the signal acquisition circuit 10 and the first capacitor 40, and the second amplification circuit 202 performs a second-stage amplification on the voltage signal after the first-stage amplification. In some embodiments, the first amplification circuit 201 includes a first current source transistor M0 and a plurality of first-stage amplifiers. The first current source transistor M0 provides a first current (e.g., DC current) to the first amplification circuit. This first current, acting as an operating current, enables the plurality of first-stage amplifiers to operate, thereby amplifying the voltage signal transmitted from the signal acquisition circuit 10 and the first capacitor 40 to obtain a second voltage signal.

[0037] In some embodiments, the plurality of first-stage amplifiers include a first amplifier M1, a second amplifier M2, a third amplifier M3, a fourth amplifier M4, a fifth amplifier M5, and a sixth amplifier M6. The first amplifier M1 and the second amplifier M2 amplify the voltage signal transmitted by the signal acquisition circuit 10. The third amplifier M3, the fourth amplifier M4, the fifth amplifier M5, and the sixth amplifier M6 form a common-source, common-gate structure to increase the gain of the first amplifier circuit 201, further amplifying the voltage signal after amplification by the first amplifier M1 and the second amplifier M2 to obtain a second voltage signal. In some embodiments, the plurality of first-stage amplifiers include a first amplifier M1 and a second amplifier M2, which amplify the voltage signal transmitted by the signal acquisition circuit 10. It should be noted that the structure of the first amplifier circuit 201 is not limited to... Figure 2 As shown, other multi-stage amplification structures may also be included. In some embodiments, the multiple first-stage amplifiers may be one or more combinations of vacuum tube amplifiers, transistor amplifiers, solid-state amplifiers, and magnetic amplifiers.

[0038] In some embodiments, the first amplifier circuit 201 further includes a first load M7 and a second load M8 to enhance the stability of the first amplifier circuit 201. In some embodiments, the first load M7 and the second load M8 may be PMOS loads.

[0039] like Figure 2As shown, the input terminal of the sample-and-hold circuit 20, composed of the first amplifier circuit 201 and the second amplifier circuit 202, is the gate of the first amplifier M1 and the second amplifier M2, and also the input of the first amplifier circuit 201. The output of the first amplifier circuit 201 is the drain of the fourth amplifier M4 and the sixth amplifier M6. In some embodiments, the sources of the first amplifier M1 and the second amplifier M2 are connected to the first current source transistor M0 to receive the operating current provided by the first current source transistor M0. In some embodiments, the first amplifier M1 and the second amplifier M2 can convert the voltage signal input to the sample-and-hold circuit 20 into a current signal, which is then converted into a voltage signal after passing through the third amplifier M3, the fourth amplifier M4, the fifth amplifier M5, the sixth amplifier M6, and the first load M7 and the second load M8, i.e., the obtained second voltage signal, and output to the second amplifier circuit 202. Among them, the first load M7 and the second load M8 are mainly used to further convert the current signal converted by the first amplifier M1 and the second amplifier M2 into a voltage signal, thereby achieving the amplification effect.

[0040] In some embodiments, the first amplifier circuit 201 may not include the third amplifier M3, the fourth amplifier M4, the fifth amplifier M5, and the sixth amplifier M6. In some embodiments, the first amplifier circuit 201 may include the third amplifier M3, the fourth amplifier M4, the fifth amplifier M5, and the sixth amplifier M6 to increase the gain of the first amplifier circuit 201. Specifically, the third amplifier M3, the fourth amplifier M4, the fifth amplifier M5, and the sixth amplifier M6 can all be considered as loads, together with the first load M7 and the second load M8, forming the load of the first amplifier circuit 201. Due to the increase in load, i.e., the increase in output resistance, the voltage under the same current will also increase accordingly, thereby increasing the second voltage signal output by the first amplifier circuit 201.

[0041] like Figure 2 As shown, the drain of the first amplifier M1 is connected to the source of the third amplifier M3, the drain of the third amplifier M3 is connected to the drain of the fifth amplifier M5, the source of the fifth amplifier M5 is connected to the drain of the first load M7, the drain of the second amplifier M2 is connected to the source of the fourth amplifier M4, the drain of the fourth amplifier M4 is connected to the drain of the sixth amplifier M6, the source of the sixth amplifier M6 is connected to the drain of the second load M8, the gates of the first load M7 and the second load M8 are connected, the gates of the fifth amplifier M5 and the sixth amplifier M6 are connected, and the gates of the third amplifier M3 and the fourth amplifier M4 are connected.

[0042] In some embodiments, the second amplifier circuit 202 includes a second current source transistor M9 and a secondary amplifier M10, wherein the second current source transistor M9 provides a second current to the second amplifier circuit 202 so that the secondary amplifier M10 can amplify the second voltage signal transmitted from the first amplifier circuit 201 to obtain an output voltage signal.

[0043] In some embodiments, the secondary amplifier M10 is connected to the output terminal of the first amplifier circuit 201, and the second current source transistor M9 and the secondary amplifier M10 form a common source structure to increase the gain of the second amplifier circuit 202 in amplifying the second voltage signal.

[0044] In some embodiments, the second amplifier circuit 202 further includes a third current source transistor M11 and a third switch 12. The third current source transistor M11 can provide a third current to the second amplifier circuit 202, so that the sample-and-hold circuit 20 can obtain a sufficiently large current under heavy load conditions. In some embodiments, the third switch 12 controls the input of the third current. When the third switch 12 is closed, the third current source transistor M11 can provide a third current to the second amplifier circuit 202. At this time, the current of the second amplifier circuit 202 includes both the second current and the third current. When the third switch 12 is open, the third current source transistor M11 cannot provide a third current to the second amplifier circuit 202. At this time, the current of the second amplifier circuit 202 only includes the second current. It should be understood that the third current is a bias current. Because this bias current is present when the third switch 12 is on compared to when it is off, the current in the sample-and-hold circuit 20 when the third switch 12 is on is greater than the current when the third switch 12 is off. This allows the sample-and-hold circuit 20 to reach the current required to drive the analog-to-digital converter 110 under heavy load conditions, while reducing the current under no-load conditions, thereby reducing system power consumption. In this way, the switching between high and low power consumption of the system can be achieved by turning the third switch 12 on and off.

[0045] like Figure 2 As shown, the output of the sample-and-hold circuit 20 is the drain of the secondary amplifier M10 and also the output of the second amplifier circuit 202. The input of the second amplifier circuit 202 is the gate of the secondary amplifier M10. The gate of the secondary amplifier M10 is directly connected to the drains of the fourth amplifier M4 and the sixth amplifier M6 to receive the second voltage signal output by the first amplifier circuit 201. In some embodiments, the secondary amplifier M10 can convert the second voltage signal input to the gate into a current signal, and further convert it into a voltage signal through the second current source transistor M9. The second current source transistor M9, in addition to providing DC current, can also be considered a load to further convert the current signal converted by the secondary amplifier M10 into an output voltage signal.

[0046] In some embodiments, the gate of the second amplifier M2 and the drain of the second amplifier M10 can be connected to form a unity-gain buffer.

[0047] In some embodiments, the first current source transistor M0, the second current source transistor M9, and the third current source transistor M11 can be one or more combinations of adjustable current sources, pulsed current sources, and high-precision current sources. In some embodiments, the gates of the first current source transistor M0, the second current source transistor M9, and the third current source transistor M11 are all connected to a bias voltage to provide DC current.

[0048] In some embodiments, the sources of the first current source transistor M0, the second current source transistor M9, and the third current source transistor M11 can all be connected to ground, and the sources of the first load M7, the second load M8, and the secondary amplifier M10 can all be connected to an external power supply.

[0049] In some embodiments, the sample-and-hold circuit 20 may further include a first resistor R, a second capacitor C0, and a third capacitor C1. The first resistor R and the second capacitor C0 are connected in series to the drain of the secondary amplifier M10 and the output terminal of the first amplifier circuit 201. The third capacitor C1 is connected in parallel across the second capacitor C0 via a fourth switch 11. In some embodiments, when the third switch 12 is open, the fourth switch 11 is closed; when the third switch 12 is closed, the fourth switch 11 is open. In some embodiments, the state of the fourth switch 11 may change simultaneously with that of the third switch 12, or it may change immediately after the state of the third switch 12 changes. In some embodiments, the control circuit controlling the fourth switch 11 may be a circuit or processor (the processor may include an internal processor or an external processor) that includes a timing control module. In some embodiments, the opening and closing of the fourth switch 11 may be controlled by a control circuit. The control circuit controlling the fourth switch 11 may be the same control circuit as the control circuit controlling the third switch 12, or it may be another control circuit controlled by the control circuit controlling the third switch 12.

[0050] In some embodiments, the fourth switch 11 may be turned on or off according to a control signal, including but not limited to one or more combinations of diodes, transistors, field-effect transistors, IGBTs, and MOSFETs. In some embodiments, the first resistor R includes, but is not limited to, one or more combinations of wire-wound resistors, carbon composite resistors, carbon film resistors, metal film resistors, and metal oxide film resistors.

[0051] It should be understood that when the third switch 12 is open, the system power consumption is low. To ensure the stability of the system in the low power consumption state, the capacitance can be increased. At this time, the fourth switch 11 is closed, so that the third capacitor C1 is connected in parallel across the two ends of the second capacitor C0, thereby increasing the capacitance of the second amplifier circuit 202 and achieving the effect of ensuring the stability of the system in the low power consumption state.

[0052] It should be understood that, in the embodiments of this application, the sample-and-hold circuit 20 adopts a two-stage amplification process, which enables the voltage input to the sample-and-hold circuit 20 to obtain a greater gain, thereby enabling the voltage input to the analog-to-digital converter 110 to meet sufficient gain accuracy.

[0053] In some embodiments, when the sample-and-hold circuit 20 and the analog-to-digital converter 110 are electrically connected via the second switch 50, the third switch 12 can be simultaneously turned on and off with the second switch 50. In some embodiments, after the second switch 50 is turned on, the third switch 12 may turn on after a fixed period of time. The value of this fixed period of time may be preset or reset according to the operating conditions. In some embodiments, after the second switch 50 is turned off, the third switch 12 may turn off after a fixed period of time. The value of this fixed period of time may be preset or reset according to the operating conditions. In some embodiments, the turning on and off of the third switch 12 may be controlled by a control circuit, which may be a circuit or processor including a timing control module (the processor may include an internal processor or an external processor). In some embodiments, the control circuit controlling the third switch 12 may be the same control circuit as the control circuit controlling the second switch 50. In some embodiments, the control circuit controlling the third switch 12 may be another control circuit controlled by the control circuit controlling the second switch 50.

[0054] It is understood that, using the structure of this application embodiment, the current of the sample-and-hold circuit 20 can be different in different states by turning the third switch 12 on and off, thereby achieving the switching between high and low power consumption of the system. In some embodiments, for the case where the analog-to-digital converter circuit 1000 includes N input circuits 100 and an analog-to-digital converter 110, by turning the second switch 50 and the third switch 12 on and off in tandem, only one input circuit is connected to the analog-to-digital converter 110 at any given time, and only the sample-and-hold circuit of that input circuit is in a heavy-load state, while the sample-and-hold circuits of the other input circuits are in a light-load state, thereby significantly reducing the power consumption of the system while reducing the overall system cost.

[0055] It should be noted that the above description of the analog-to-digital conversion circuit 1000 and the sample-and-hold circuit 20 and their structures is for convenience only and should not limit this application to the scope of the embodiments described.

[0056] The beneficial effects that the embodiments of this application may bring include, but are not limited to: (1) reading out the voltage signals output by multiple input circuits in sequence through an analog-to-digital converter, thereby greatly reducing the cost and power consumption of the entire system; (2) improving the voltage amplification effect through the two-stage amplifier circuit structure of the sample-and-hold circuit, thereby enhancing the ability to drive the analog-to-digital converter; (3) introducing bias current through the closing of the third switch when the analog-to-digital converter needs to be driven, thereby further increasing the current input to the analog-to-digital converter and achieving a better driving effect; (4) opening the third switch when the analog-to-digital converter does not need to be driven, thereby reducing the power consumption of the sample-and-hold circuit and achieving the purpose of saving power consumption.

[0057] It should be noted that different embodiments may produce different beneficial effects. In different embodiments, the beneficial effects may be any one or a combination of the above, or any other possible beneficial effects.

[0058] The basic concepts have been described above. Obviously, for those skilled in the art, the detailed disclosure above is merely illustrative and does not constitute a limitation of this application. Although not explicitly stated herein, those skilled in the art may make various modifications, improvements, and corrections to this application. Such modifications, improvements, and corrections are suggested in this application, and therefore remain within the spirit and scope of the exemplary embodiments of this application.

[0059] Furthermore, this application uses specific terms to describe embodiments of the application. For example, "an embodiment," "one embodiment," and / or "some embodiments" refer to a particular feature, structure, or characteristic associated with at least one embodiment of the application. Therefore, it should be emphasized and noted that "an embodiment," "one embodiment," or "an alternative embodiment" mentioned twice or more in different locations in this specification do not necessarily refer to the same embodiment. In addition, certain features, structures, or characteristics in one or more embodiments of the application can be appropriately combined.

[0060] Furthermore, those skilled in the art will understand that aspects of this application can be described and illustrated through several patentable types or situations, including any new and useful combination of processes, machines, products, or substances, or any new and useful improvements thereof. Accordingly, aspects of this application can be implemented entirely by hardware, entirely by software (including firmware, resident software, microcode, etc.), or by a combination of hardware and software. All of the above hardware or software may be referred to as a “data block,” “module,” “engine,” “unit,” “component,” or “system.” Furthermore, aspects of this application may manifest as a computer product located on one or more computer-readable media, the product including computer-readable program code.

[0061] Computer storage media may contain a propagated data signal containing computer program code, for example, on baseband or as part of a carrier wave. This propagated signal may take various forms, including electromagnetic, optical, and suitable combinations thereof. Computer storage media can be any computer-readable medium other than a computer-readable storage medium, which can be connected to an instruction execution system, apparatus, or device to enable communication, propagation, or transmission of a program for use. The program code located on the computer storage medium can be propagated through any suitable medium, including radio, cable, fiber optic cable, RF, or similar media, or any combination of the above media.

[0062] The computer program code required for the operation of each part of this application can be written in any one or more programming languages, including object-oriented programming languages ​​such as Java, Scala, Smalltalk, Eiffel, JADE, Emerald, C++, C#, VB.NET, Python, etc., conventional procedural programming languages ​​such as C, Visual Basic, Fortran 2003, Perl, COBOL 2002, PHP, ABAP, dynamic programming languages ​​such as Python, Ruby, and Groovy, or other programming languages. This program code can run entirely on the user's computer, or as a standalone software package on the user's computer, or partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer can be connected to the user's computer through any network, such as a local area network (LAN) or wide area network (WAN), or connected to an external computer (e.g., via the Internet), or in a cloud computing environment, or used as a service such as Software as a Service (SaaS).

[0063] Furthermore, unless expressly stated in the claims, the order of processing elements and sequences, the use of numbers and letters, or other names described in this application are not intended to limit the order of the processes and methods of this application. Although the foregoing disclosure has discussed some currently considered useful embodiments of the invention through various examples, it should be understood that such details are for illustrative purposes only, and the appended claims are not limited to the disclosed embodiments; rather, the claims are intended to cover all modifications and equivalent combinations that conform to the substance and scope of the embodiments of this application. For example, while the system components described above can be implemented using hardware devices, they can also be implemented solely through software solutions, such as installing the described system on existing servers or mobile devices.

[0064] Similarly, it should be noted that, in order to simplify the description of the present application and thus aid in the understanding of one or more embodiments of the invention, the foregoing description of the embodiments of the present application sometimes combines multiple features into a single embodiment, drawing, or description thereof. However, this disclosure method does not imply that the subject matter of the application requires more features than those mentioned in the claims. In fact, the embodiments contain fewer features than all the features of the single embodiments disclosed above.

[0065] In some embodiments, numbers describing the quantity of components and attributes are used. It should be understood that such numbers used in the description of embodiments are modified in some examples with the terms "approximately," "approximately," or "generally." Unless otherwise stated, "approximately," "approximately," or "generally" indicates that the numbers are allowed to vary by ±20%. Accordingly, in some embodiments, the numerical parameters used in the specification and claims are approximate values, which may be changed depending on the characteristics required by individual embodiments. In some embodiments, numerical parameters should take into account specified significant digits and employ a general method of digit reservation. Although the numerical ranges and parameters used to confirm their breadth of scope in some embodiments of this application are approximate values, in specific embodiments, such values ​​are set as precisely as feasible.

[0066] For each patent, patent application, patent application publication, and other material such as articles, books, specifications, publications, and documents referenced in this application, the entire contents of that patent are incorporated herein by reference. This excludes historical application documents that are inconsistent with or conflict with the content of this application, as well as documents that limit the broadest scope of the claims in this application (currently or subsequently appended to this application). It should be noted that if there are any inconsistencies or conflicts between the descriptions, definitions, and / or terminology used in the supplementary materials of this application and the content of this application, the descriptions, definitions, and / or terminology used in this application shall prevail.

[0067] Finally, it should be understood that the embodiments described in this application are merely illustrative of the principles of the embodiments of this application. Other modifications may also fall within the scope of this application. Therefore, alternative configurations of the embodiments of this application are considered as examples and not limitations, and are regarded as consistent with the teachings of this application. Accordingly, the embodiments of this application are not limited to the embodiments explicitly described and illustrated in this application.

Claims

1. An analog-to-digital conversion circuit, characterized in that, include: There are N input circuits and an analog-to-digital converter, where N is a natural number greater than 1. For each of the N input circuits: The input circuit includes a signal acquisition circuit and a sample-and-hold circuit; The signal acquisition circuit is used to convert other signals into voltage signals; The sample-and-hold circuit is connected to the signal acquisition circuit and is used to amplify the voltage signal to obtain an output voltage signal. The sample-and-hold circuit includes a first amplification circuit and a second amplification circuit. The second amplification circuit includes a second current source transistor, a third current source transistor, and a third switch. The conduction of the third switch is related to the load state of the sample-and-hold circuit. The second current source transistor provides a second current to the second amplification circuit, the third current source transistor provides a third current to the second amplification circuit, and the third switch controls the input of the third current. When the output terminal of the sample-and-hold circuit is connected to the analog-to-digital converter, the sample-and-hold circuit is in a heavy-load state, the third switch is closed, and the current of the second amplification circuit includes both the second current and the third current. When the output terminal of the sample-and-hold circuit is disconnected from the analog-to-digital converter, the sample-and-hold circuit is in an unloaded state, the third switch is open, and the current of the second amplification circuit includes only the second current. The analog-to-digital converter is connected sequentially to the output terminals of the N input circuits in the time domain, and is used to convert the output voltage signals output by the N input circuits into digital signals respectively.

2. The circuit according to claim 1, characterized in that, Each of the N input circuits also includes a first switch. In each input circuit: The output terminal of the signal acquisition circuit is connected to the first terminal of the first switch, and the second terminal of the first switch is connected to the input terminal of the sample-and-hold circuit. The first switch controls the conduction between the signal acquisition circuit and the sample-and-hold circuit according to the first control signal.

3. The circuit according to claim 2, characterized in that, Each of the N input circuits also includes a first capacitor. In each input circuit: The first capacitor is used to sample the voltage signal transmitted from the signal acquisition circuit to the sample-and-hold circuit, and the first capacitor is connected to the second terminal of the first switch.

4. The circuit according to claim 2, characterized in that, Each of the N input circuits also includes a second switch. In each input circuit: The output terminal of the sample-and-hold circuit is connected to the first terminal of the second switch, and the second terminal of the second switch is connected to the input terminal of the analog-to-digital converter. The second switch controls the conduction of the input circuit and the analog-to-digital converter according to the second control signal.

5. The circuit according to claim 4, characterized in that, The N first switches of the N input circuits are simultaneously turned on or off according to the first control signal, and the N second switches of the N input circuits are turned on sequentially according to the second control signal.

6. The circuit according to claim 1, characterized in that, The second amplifier circuit includes a two-stage amplifier, which performs a second amplification process on the voltage signal to obtain the output voltage signal.

7. The circuit according to claim 4, characterized in that, In each input circuit: When the second switch is turned on, the sample-and-hold circuit is in a heavy-load state, and the third switch is turned on; When the second switch is open, the sample-and-hold circuit is in an unloaded state, and the third switch is open; The current in the sample-and-hold circuit when the third switch is on is greater than the current in the sample-and-hold circuit when the third switch is off.

8. The circuit according to claim 1, characterized in that, The signal acquisition circuit is a photoelectric converter, used to convert the optical signal into the voltage signal.

9. The circuit according to claim 1, characterized in that, The signal acquisition circuit is a pixel array.

10. The circuit according to claim 1, characterized in that, The sample-and-hold circuit is a unity-gain buffer or a sample-and-hold amplifier.

11. The circuit according to claim 1, characterized in that, The analog-to-digital conversion circuit is used in one of the following systems: CT imaging system, CMOS image sensing system, and CCD image sensing system.

12. An analog-to-digital conversion circuit, characterized in that, include: An input circuit and an analog-to-digital converter, wherein the input circuit includes a signal acquisition circuit and a sample-and-hold circuit; The signal acquisition circuit is used to convert other signals into voltage signals; The sample-and-hold circuit is connected to the signal acquisition circuit and is used to amplify the voltage signal to obtain an output voltage signal. The sample-and-hold circuit includes a first amplifier circuit and a second amplifier circuit. The second amplifier circuit includes a second current source transistor, a third current source transistor, and a third switch. The conduction of the third switch is related to the load state of the sample-and-hold circuit. The second current source transistor provides a second current to the second amplifier circuit, the third current source transistor provides a third current to the second amplifier circuit, and the third switch controls the input of the third current. When the output terminal of the sample-and-hold circuit is connected to the analog-to-digital converter, the sample-and-hold circuit is in a heavy-load state, the third switch is closed, and the current of the second amplifier circuit includes both the second current and the third current. When the output terminal of the sample-and-hold circuit is disconnected from the analog-to-digital converter, the sample-and-hold circuit is in an unloaded state, the third switch is open, and the current of the second amplifier circuit includes only the second current. The analog-to-digital converter is connected to the output terminal of the input circuit and is used to convert the output voltage signal output by the input circuit into a digital signal.

13. The circuit according to claim 12, characterized in that, The circuit includes N input circuits, where N is a natural number greater than 1; The analog-to-digital converter is connected sequentially to the output terminals of the N input circuits in the time domain, and is used to convert the output voltage signals output by the N input circuits into digital signals respectively.

14. The circuit according to claim 12, characterized in that, In the input circuit, the output terminal of the input circuit is the output terminal of the sample-and-hold circuit: The current in the sample-and-hold circuit when the third switch is on is greater than the current in the sample-and-hold circuit when the third switch is off.

15. The circuit according to claim 14, characterized in that, The first amplifier circuit includes a first current source transistor and a plurality of first-stage amplifiers, wherein the first current source transistor provides a first current to the first amplifier circuit, and the plurality of first-stage amplifiers amplify the voltage signal to obtain a second voltage signal.

16. The circuit according to claim 15, characterized in that, The plurality of first-stage amplifiers includes a first amplifier, a second amplifier, a third amplifier, a fourth amplifier, a fifth amplifier, and a sixth amplifier, wherein, The first amplifier and the second amplifier amplify the voltage signal to obtain a second voltage signal. The third amplifier, the fourth amplifier, the fifth amplifier, and the sixth amplifier are of common source and common gate structure, used to increase the gain of the first amplifier circuit.

17. The circuit according to claim 15, characterized in that, The first amplifier circuit also includes a first load and a second load.

18. The circuit according to claim 15, characterized in that, The second amplifier circuit includes a two-stage amplifier, which performs a second amplification process on the second voltage signal to obtain the output voltage signal.

19. The circuit according to claim 18, characterized in that, The sample-and-hold circuit further includes a first resistor, a second capacitor, and a third capacitor. The first resistor and the second capacitor are connected in series between the drain of the secondary amplifier and the output terminal of the first amplifier circuit. The third capacitor is connected in parallel across the second capacitor via a fourth switch. When the third switch is open, the fourth switch is closed, and the third capacitor is connected in parallel with the second capacitor; When the third switch is closed, the fourth switch is open, and the third capacitor is disconnected.

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