A method and apparatus for implementing physical memory protection

Abstract

The application discloses a method and device for realizing physical memory protection. In the embodiment of the application, the PMP, which is a basic component of the RISC-V CPU for memory isolation, is a protection method for a physical space based on page storage management, effectively supports paging protection of the physical memory, and realizes more effective and flexible permission management of the physical memory in units of pages for an operating system based on page storage management.

Description

Technical Field

[0001] This application relates to, but is not limited to, computer technology, and in particular to a method and apparatus for implementing physical memory protection. Background Technology

[0002] The Reduced Instruction Set Computing-five (RISC-V) is currently one of the most widely used reduced instruction sets. To support secure processing, RISC-V provides a mechanism to restrict the physical addresses that software can access. This mechanism, called Physical Memory Protection (PMP), provides memory protection in various modes.

[0003] PMP (Memory Management Platform) is a fundamental component of RISC-V CPUs for memory isolation, providing the most basic capability for securing a Trusted Execution Environment (TEE). However, because PMP only supports a fixed number of memory regions, it cannot be scaled to accommodate complex memory protection. Furthermore, since these memory regions must be contiguous in physical storage, this can lead to storage fragmentation issues. Summary of the Invention

[0004] This application provides a method and apparatus for implementing physical memory protection, which can protect physical space based on page-based memory management to adapt to complex memory protection.

[0005] This invention provides a method for implementing physical memory protection, comprising:

[0006] The entry for the address to be accessed is retrieved from the page table stored in memory;

[0007] Based on the access attribute information in the found table entries, manage access permissions for the corresponding spaces according to the addresses that need to be accessed.

[0008] In one exemplary instance, the method further includes specifying the starting address of the page table in memory via a register.

[0009] In one exemplary instance, retrieving the entry from a page table stored in memory for the address to be accessed includes:

[0010] In the case where the page table includes a single page table, the entry is found based on the address to be accessed and the starting address of the page table in memory.

[0011] or,

[0012] The page table includes both a first page table and a second page table. Based on the address to be accessed and the starting address of the first page table in memory, a first entry is found. If the first entry stores pre-configured access attribute information corresponding to the memory address, the entry is determined to be the first entry. If the first entry stores the base address of the second page table, a second entry is found based on the base address of the second page table and the address to be accessed, and the second entry is the first entry.

[0013] In one exemplary instance, the page table includes multiple entries, each entry storing access attribute information for multiple pre-configured corresponding memory addresses.

[0014] In one exemplary instance, the page table includes 1024 entries.

[0015] In one exemplary instance, the step of managing access permissions for the corresponding space based on the access attribute information in the found table entries, according to the address to be accessed, includes:

[0016] In the case where the page table includes a single page table, access control for the 4MB space is performed according to the access attribute information in the table entries.

[0017] The page table includes a first page table and a second page table. When the page table is a first entry, access control is performed on the 4MB space according to the access attribute information in the first entry based on the address to be accessed. When the page table is a second entry, access control is performed on the 4KB space according to the access attribute information in the second entry based on the address to be accessed.

[0018] This application also provides a computer-readable storage medium storing computer-executable instructions, which are used to execute the method for implementing physical memory protection described in any of the above embodiments.

[0019] This application embodiment provides an apparatus for implementing physical memory protection, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for performing the method for implementing physical memory protection described in any of the above claims.

[0020] In one exemplary instance, the processor is a fifth-generation Reduced Instruction Set Computing (RISC-V) CPU.

[0021] This application embodiment further provides a device for implementing physical memory protection, including: a search module and a processing module; wherein,

[0022] The lookup module is used to find the entry in the page table stored in memory from the address that needs to be accessed;

[0023] The processing module is used to manage access permissions for the corresponding space based on the access attribute information in the found table entries and the address to be accessed.

[0024] In one exemplary instance, the lookup module is specifically used for:

[0025] In the case where the page table includes a single page table, the entry is found based on the address to be accessed and the starting address of the page table in memory.

[0026] or,

[0027] The page table includes both a first page table and a second page table. Based on the address to be accessed and the starting address of the first page table in memory, a first entry is found. If the first entry stores pre-configured access attribute information corresponding to the memory address, the entry is determined to be the first entry. If the first entry stores the base address of the second page table, a second entry is found based on the base address of the second page table and the address to be accessed, and the second entry is the first entry.

[0028] In one exemplary instance, the processing module is specifically used for:

[0029] In the case where the page table includes a single page table, access control for the 4MB space is performed according to the access attribute information in the table entries.

[0030] or,

[0031] The page table includes a first page table and a second page table. The first page table is a first table entry, and access control for 4MB space is performed according to the access attribute information in the first table entry based on the address to be accessed. The second page table is a second table entry, and access control for 4KB space is performed according to the access attribute information in the second table entry based on the address to be accessed.

[0032] One of the page tables includes 1024 entries.

[0033] The method for physical memory protection provided in this application is a page-based memory management method for protecting physical space, which can be referred to herein as Page-based Physical Memory Protection (PBPMP). PBPMP effectively supports page-based protection of physical memory. For operating systems that manage memory based on page-based memory management, the PBPMP provided in this application provides more effective and flexible permission management for physical memory at the page level. In this application, the page table is stored in memory, and the number of entries can be expanded to 1024×1024. Compared to the standard PMP with only 8 or 16 entries, the number of entries in PBPMP is significantly increased, resulting in a smaller granularity of the address space protected by each entry. Moreover, the PBPMP provided in this application manages access permissions at the page level, solving the problem that PMP requires contiguous physical memory for access management. Furthermore, the PBPMP provided in this application can dynamically manage access permissions for physical pages, allowing physical pages to be shared between different domains.

[0034] Other features and advantages of the invention will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practicing the invention. The objects and other advantages of the invention may be realized and obtained by means of the structures particularly pointed out in the description, claims, and drawings. Attached Figure Description

[0035] The accompanying drawings are used to provide a further understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0036] Figure 1 This is a flowchart illustrating the method for implementing physical memory protection in an embodiment of this application;

[0037] Figure 2 This is a schematic diagram illustrating the process of implementing physical memory protection based on a two-level page table in an embodiment of this application;

[0038] Figure 3(a) is a schematic diagram of an embodiment of the page mode descriptor in this application;

[0039] Figure 3(b) is a schematic diagram of an embodiment of the Block mode descriptor in this application;

[0040] Figure 4 This is a schematic diagram of the structure of the device for implementing physical memory protection in the embodiments of this application. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be noted that, unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

[0042] In a typical configuration of this application, the computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0043] Memory may include non-persistent storage in computer-readable media, such as random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media.

[0044] Computer-readable media include both permanent and non-permanent, removable and non-removable media that can store information using any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transferable medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include non-transitory computer-readable media, such as modulated data signals and carrier waves.

[0045] The steps illustrated in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases the steps shown or described may be performed in a different order than that presented here.

[0046] In related technologies, the PMP mechanism provides a set of configurable registers, including 16 PMP configuration registers (pmpcfg0~pmpcfg15) and 64 PMP address registers (pmpaddr0~pmpaddr63). Through the cooperation of these registers, protection of physical memory regions can be achieved. Each region can be configured with three memory access attributes: X (executable), R (readable), and W (writable). There are three methods for representing PMP protected regions: TOR, NA4, and NAPOT. TOR uses two pmpaddr registers to represent the start and end addresses of the protected address space, with the protected region located between these two addresses. NA4 indicates that the 4 bytes aligned to the beginning of the corresponding pmpaddr address are the protected space. NAPOT indicates that the region aligned to 2XLEN+3 bytes starting from the pmpaddr address is the protected space.

[0047] Currently, most mainstream CPUs provide security isolation technologies to implement TEE (Trusted Execution Environment), such as ARM's TrustZone and Intel's SGX. RISC-V processors can achieve isolation between different domains through PMP (Programmable Memory Manager). However, currently, the physical memory space of different domains on RISC-V is statically allocated. Therefore, once this physical memory is partitioned, it can only be used within that domain and cannot be shared between different domains. The main reasons are: the PMP mechanism in related technologies has a limited number of entries, usually 8 or 16, thus PMP can only control a limited number of address spaces; moreover, PMP entries are stored in registers, which is not conducive to the expansion of the number of PMP entries. In other words, the PMP function only supports a fixed number of memory regions, and therefore cannot be expanded to adapt to complex memory protection; furthermore, the address space granularity protected by PMP entries is relatively large, which is incompatible with the page-based memory management of modern operating systems. For operating systems that manage memory on a page basis, it is difficult to manage their physical memory using PMP.

[0048] Therefore, embodiments of this application provide a method for implementing physical memory protection, such as... Figure 1 As shown, it may include:

[0049] Step 100: Locate the entry in the page table stored in memory for the address to be accessed.

[0050] In one exemplary instance, the page table in this application embodiment is stored in memory, and this step may be preceded by specifying the starting address of the page table in memory through the PMP_BASE control and status register (CSR).

[0051] In one exemplary instance, the page table in step 100 may include a single page table comprising multiple entries, each entry storing access attribute information for multiple pre-configured corresponding memory addresses, such as X (indicating whether it is executable), R (indicating whether it is readable), and W (indicating whether it is writable). In one embodiment, a page table may include 1024 entries. In this case, step 100 may include: finding the entry required by the address to be accessed and the starting address of the page table in memory, and continuing with step 101.

[0052] In one exemplary instance, the page table in step 100 may include a first-level page table (referred to herein as the first page table) and a second-level page table (referred to herein as the second page table). The first page table includes multiple entries, each entry storing access attribute information for one or more pre-configured corresponding memory addresses, or the base address of one or more second-level page tables. The second page table includes multiple entries, each entry storing multiple pre-configured access attribute information for corresponding memory addresses. In this case, step 100 may include:

[0053] Find the first table entry based on the address to be accessed and the starting address of the first page table in memory. If the first table entry stores the access attribute information of the corresponding pre-configured memory address, then continue to step 101; if the first table entry stores the base address of the second page table, then find the second table entry based on the base address of the second page table and the address to be accessed, and continue to step 101.

[0054] In one exemplary instance, the page table in step 100 may include three or more levels of page tables. Each level of page table includes multiple entries, each entry being used to store access attribute information for multiple pre-configured corresponding memory addresses. Other levels of page tables include multiple entries, each entry being used to store access attribute information for one or more pre-configured corresponding memory addresses, or the base address of one or more next-level page tables of that level of page table.

[0055] Step 101: Based on the access attribute information in the found table entries, manage access permissions for the corresponding spaces according to the addresses that need to be accessed.

[0056] In one exemplary instance, the page table may include 1024 entries. In step 100, the page table may include a single page table. In step 101, the page table entry is found based on the address to be accessed and the starting address of the page table in memory. Access control for the 4MB space is then performed according to the access attribute information in the found page table entry.

[0057] In one exemplary instance, the page table may include 1024 entries. The page table in step 100 may include a first page table and a second page table. If the first entry found in the first page table in step 100 stores pre-configured access attribute information for the corresponding memory address, then in step 101, permission access management will be performed on the 4MB space according to the access attribute information in the first entry as needed for the address to be accessed. If the second entry found in the second page table in step 100 stores pre-configured access attribute information for the corresponding memory address, then in step 101, permission access management will be performed on the 4KB space according to the access attribute information in the second entry as needed for the address to be accessed.

[0058] The method for implementing physical memory protection provided in this application is a method for protecting physical space based on page-based memory management, which can be referred to herein as Page-based Physical Memory Protection (PBPMP). PBPMP effectively supports page-based protection of physical memory. For operating systems that manage memory based on page-based memory management, the PBPMP provided in this application provides a more effective and flexible permission management for physical memory in units of pages. In this embodiment, the page table is stored in memory, and the number of entries can be expanded to 1024×1024. Compared with the standard PMP, which has only 8 or 16 entries, the number of entries in PBPMP is greatly increased, resulting in a smaller granularity of the address space protected by each entry. Moreover, the PBPMP provided in this embodiment performs access control on a page-by-page basis, solving the problem that PMP must perform access control on contiguous physical memory. Furthermore, the PBPMP provided in this embodiment performs access control on a page-by-page basis, which has a small granularity and can dynamically manage the access permissions of physical pages. A page can be released after use and then used by other regions, that is, physical pages can be shared between different regions (domains).

[0059] Taking modern operating systems like Linux as an example, their memory management is page-based, with the smallest unit of a physical memory page being 4KB. The method for implementing physical memory protection provided in this application allows for access control of each page of physical memory (e.g., 4KB) by querying the page tables when the page table includes two levels. In other words, the PBPMP method in this application can flexibly manage the physical memory of modern operating systems like Linux.

[0060] The following describes in detail the method for implementing physical memory protection provided in this application embodiment, using a two-level page table as an example. In this embodiment, the page table of PBPMP is stored in memory, and its base address can be specified through the PMP_BASE CSR register. Taking RV32 as an example, PBPMP supports two-level table lookup, namely the first page table (L0 page table) and the second page table (L1 page table). The L0 page table includes 1024 entries, each supporting both block mode and page table mode. Each block manages 4MB of physical space, and the page table mode points to the next level page table, namely the L1 page table. The L1 page table also includes 1024 entries, each supporting page mode, with each page managing 4KB of physical space.

[0061] like Figure 2 As shown, firstly, PMP_BASE CSR gives the base address of the first-level page table, i.e., the first page table. Then, according to the first-level page number given by PA[31:22], the processor will read the first-level table entry, i.e. the first table entry, located at address (PMP_BASE+PA[31:22]×4).

[0062] If the first entry is in Block mode, the descriptor is shown in Figure 3(a). This entry will manage access permissions for the 4MB space starting with PPN[0]<<22;

[0063] If the first entry is in page table mode, as shown in Figure 3(b), then the first entry includes the base address of the second-level page table, i.e., the second page table. Based on the second-level page number given by PA[21:12], the processor will read the leaf node entry located at address (Next Page Table base address + PA[21:12] × 4), i.e., the second entry.

[0064] The second entry (Page Granule Descriptor) is always in page mode. The descriptor is shown in Figure 3(a). The second entry will manage access permissions for the 4KB space starting from PPN[0]<<22+PPN[1]<<12.

[0065] In Figure 3(b), the first 20 bits of the descriptor are the Physical Page Index (PPN), used to locate the physical address of the page table. The physical address can be found by using the physical address of the page table and the offset within the page. The lower 12 bits of the descriptor can be used for some identification and access control, such as: W indicates whether the physical page pointed to is writable, such as 1 for writable and 0 for non-writable; R indicates whether the physical page pointed to is readable, such as 1 for readable and 0 for non-readable; X indicates whether it is executable, such as 1 for executable and 0 for non-executable; A indicates the address control mode, used to indicate how to control the address range. A=0 indicates that it is not enabled and does not match any address. When A is not equal to zero, there are three cases: TOR, NA4, and NAPOT. Among them, NA4 can be regarded as a special case of NAPOT. In Figure 3(a), the first 22 bits of the descriptor are reserved bits.

[0066] The embodiments of this application can be applied to systems such as the Internet and the Internet of Things (IoT), such as 5G mobile Internet systems, autonomous driving systems, facial recognition, etc., and can be applied in any scenario that requires physical memory protection.

[0067] This application also provides a computer-readable storage medium storing computer-executable instructions for performing any of the above-described methods for implementing physical memory protection.

[0068] This application further provides an apparatus for implementing physical memory protection, including a memory and a processor, wherein the memory stores the following instructions executable by the processor: steps for performing the method for implementing physical memory protection as described in any of the preceding claims.

[0069] Figure 4 This is a schematic diagram of the structural composition of the device for implementing physical memory protection in the embodiments of this application, as shown below. Figure 4 As shown, it includes: a search module and a processing module; wherein,

[0070] The lookup module is used to find the entry in the page table stored in memory from the address that needs to be accessed;

[0071] The processing module is used to manage access permissions for the corresponding space based on the access attribute information in the found table entries and the address to be accessed.

[0072] In one exemplary instance, the lookup module is specifically used for:

[0073] The page table includes the case of a page table, and the table entry is found according to the address to be accessed and the starting address of the page table in memory;

[0074] Alternatively, if the page table includes a first page table and a second page table, the first entry is found based on the address to be accessed and the starting address of the first page table in memory. If the first entry stores the access attribute information for the corresponding pre-configured memory address, then the found entry is determined to be the first entry; if the first entry stores the base address of the second page table, then the second entry is found based on the base address of the second page table and the address to be accessed, and the second entry is the found entry.

[0075] In one exemplary instance, the page table includes multiple entries, each entry storing access attribute information for multiple pre-configured corresponding memory addresses, such as X (indicating whether it is executable), R (indicating whether it is readable), and W (indicating whether it is writable). In one embodiment, a page table may include 1024 entries.

[0076] In one exemplary instance, the processing module is specifically used for:

[0077] In the case of a page table containing a single page table, access control for the 4MB space is managed according to the access attribute information in the found table entries.

[0078] The page table includes a first page table and a second page table. The page table is the first table entry. Access control for 4MB of space is managed according to the access attribute information found in the first table entry based on the address to be accessed. The page table is the second table entry. Access control for 4KB of space is managed according to the access attribute information found in the second table entry based on the address to be accessed.

[0079] A single page table can contain 1024 entries.

[0080] The apparatus for physical memory protection provided in this application is a method for protecting physical space based on page-based memory management, which can be referred to herein as Page-based Physical Memory Protection (PBPMP). PBPMP effectively supports page-based protection of physical memory. For operating systems that manage memory based on page-based memory management, the PBPMP provided in this application provides more effective and flexible permission management for physical memory at the page level. In this application, the page table is stored in memory, and the number of entries can be expanded to 1024×1024. Compared to the standard PMP with only 8 or 16 entries, the number of entries in PBPMP is significantly increased, resulting in a smaller granularity of the address space protected by each entry. Moreover, the PBPMP provided in this application manages access permissions at the page level, solving the problem that PMP requires contiguous physical memory for access management. Furthermore, the PBPMP provided in this application can dynamically manage access permissions for physical pages, allowing physical pages to be shared between different domains.

[0081] Although the embodiments disclosed in this application are as described above, the content described is merely for the purpose of understanding this application and is not intended to limit this application. Any person skilled in the art to which this application pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed in this application; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A method for implementing physical memory protection, comprising: The process involves retrieving an entry from a page table stored in memory based on the address to be accessed. This includes: if the page table includes a first page table and a second page table, finding a first entry based on the address to be accessed and the starting address of the first page table in memory; if the first entry stores pre-configured access attribute information for the corresponding memory address, then the entry is identified as the first entry; if the first entry stores the base address of the second page table, finding a second entry based on the base address of the second page table and the address to be accessed, then the second entry is identified as the first entry. The page table contains 1024 entries, each storing access attribute information for multiple pre-configured corresponding memory addresses. Based on the access attribute information in the found table entries, manage access permissions for the corresponding spaces according to the addresses that need to be accessed.

2. The method according to claim 1, further comprising: The starting address of the page table in memory is specified by a register.

3. The method according to claim 1 or 2, wherein, The step of managing access permissions for the corresponding space based on the access attribute information in the found table entries, according to the required access address, includes: The page table includes a first page table and a second page table. When the page table is a first entry, access control is performed on the 4MB space according to the access attribute information in the first entry based on the address to be accessed. When the page table is a second entry, access control is performed on the 4KB space according to the access attribute information in the second entry based on the address to be accessed.

4. A computer-readable storage medium storing computer-executable instructions, said computer-executable instructions being used to perform the method for implementing physical memory protection as described in any one of claims 1 to 3.

5. A device for implementing physical memory protection, comprising a memory and a processor, wherein, The memory stores the following instructions that can be executed by a processor: steps for performing the method for implementing physical memory protection as described in any one of claims 1 to 3.

6. The device according to claim 5, wherein, The processor is a fifth-generation RISC-CV CPU.

7. A device for implementing physical memory protection, comprising: The search module and the processing module; among them, A lookup module is used to find an entry in a page table stored in memory from the address to be accessed. This includes: if the page table includes a first page table and a second page table, finding a first entry based on the address to be accessed and the starting address of the first page table in memory; if the first entry stores pre-configured access attribute information for the corresponding memory address, then the entry is identified as the first entry; if the first entry stores the base address of the second page table, finding a second entry based on the base address of the second page table and the address to be accessed, then the second entry is identified as the first entry. The page table includes 1024 entries, each storing multiple pre-configured access attribute information for corresponding memory addresses. The processing module is used to manage access permissions for the corresponding space based on the access attribute information in the found table entries and the address to be accessed.

8. The apparatus according to claim 7, wherein, The processing module is specifically used for: The page table includes a first page table and a second page table. The page table is the first entry. According to the address to be accessed, the 4MB space is managed for access permissions based on the access attribute information in the found first entry. The page table is the second entry. Based on the address to be accessed, the 4KB space is managed for access permissions according to the access attribute information in the found second entry.

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