Display device

Abstract

A display device is provided, including: a substrate, a transmissive region, a display region, a non-display region and a peripheral region being defined in the substrate; a plurality of pixels arranged in the display region; a plurality of initialization gate lines and a plurality of compensation gate lines respectively extending along the pixel columns; a plurality of gate driving circuits arranged in the peripheral region; and a plurality of gate connection lines arranged in the non-display region. The kth gate driving circuit among the plurality of gate driving circuits simultaneously drives the mth initialization gate line and the m+1th initialization gate line and the nth compensation gate line and the n+1th compensation gate line. The first part of the nth compensation gate line and the n+1th compensation gate line and the second part of the nth compensation gate line and the n+1th compensation gate line which are physically separated from each other by the transmissive region are electrically connected to each other by the first gate connection line among the plurality of gate connection lines.

Description

[0001] This application claims priority and all rights to Korean Patent Application No. 10-2020-0183612, filed on December 24, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0002] One or more embodiments relate to a display device. Background Technology

[0003] Display devices are configured to visually display data. They can be used as displays for small products such as mobile phones or large products such as televisions.

[0004] The display device may include a substrate divided into display and non-display areas, with gate lines and data lines insulated from each other in the display area. Multiple pixel areas are defined in the display area, and pixels in each of the multiple pixel areas receive electrical signals from intersecting gate and data lines and emit light to display an image externally. Thin-film transistors and pixel electrodes electrically connected to the thin-film transistors are disposed in each of the multiple pixel areas, and counter electrodes are commonly disposed in each of the multiple pixel areas. In such a display device, various lines configured to transmit electrical signals to the pixels in the display area may be provided in the non-display area; pads (or "soldering pads") may be connected to gate drivers, data drivers, and controllers.

[0005] Recently, the uses of display devices have diversified. Furthermore, display devices have become thinner and lighter, thus expanding their applications. As display devices are used more widely in various fields, research has been conducted to improve user visual satisfaction, such as expanding the display area. Various studies are being explored to expand the display area. Summary of the Invention

[0006] One or more embodiments include a display device in which the non-display area is reduced.

[0007] According to an embodiment, the display device includes: a substrate defining a transmissive region, a display region, a non-display region, and a peripheral region therein, the display region surrounding at least a portion of the transmissive region, the non-display region between the transmissive region and the display region, and the peripheral region outside the display region; a plurality of pixels arranged in pixel rows and pixel columns in the display region; a plurality of initialization gate lines and a plurality of compensation gate lines extending along the pixel columns, respectively; a plurality of gate driving circuits disposed in the peripheral region and arranged in the direction of the pixel columns; and a plurality of gate connection lines disposed in the non-display region, wherein the kth gate driving circuit among the plurality of gate driving circuits simultaneously drives... The m-th initialization gate line and the (m+1)-th initialization gate line among the plurality of initialization gate lines, and the n-th compensation gate line and the (n+1)-th compensation gate line among the plurality of compensation gate lines, each of the m-th initialization gate line, the (m+1)-th initialization gate line, and the n-th compensation gate line and the (n+1)-th compensation gate line includes a first portion and a second portion that are physically separated from each other by the transmission region, and the first portion and the second portion of each of the n-th compensation gate line and the (n+1)-th compensation gate line are electrically connected to each other through a first gate connection line among the plurality of gate connection lines, where k and n are positive integers, and m is a positive integer greater than n+1.

[0008] According to an embodiment, an even number of pixel rows can be located between the (n+1)th pixel row and the mth pixel row.

[0009] According to an embodiment, the first and second portions of each of the m-th initialization gate line and the (m+1)-th initialization gate line can be electrically connected to each other via the second gate connection line among the plurality of gate connection lines.

[0010] According to an embodiment, the first gate connection line can electrically connect the first and second portions of each of the m-th initialization gate line and the (m+1)-th initialization gate line to each other.

[0011] According to the embodiment, the two pixel rows can be between the (n+1)th pixel row and the mth pixel row. The nth initialization gate line and the (n+1)th initialization gate line among the plurality of initialization gate lines can be driven simultaneously by the (k-2)th gate driving circuit among the plurality of gate driving circuits. Furthermore, the mth compensation gate line and the (m+1)th compensation gate line among the plurality of compensation gate lines can be driven simultaneously by the (k+2)th gate driving circuit among the plurality of gate driving circuits.

[0012] According to an embodiment, the m-th pixel row can be the pixel row adjacent to the (n+1)-th pixel row.

[0013] According to an embodiment, the first gate connection line can electrically connect the first and second portions of each of the m-th initialization gate line and the (m+1)-th initialization gate line to each other.

[0014] According to an embodiment, the first and second portions of each of the m-th initialization gate line and the (m+1)-th initialization gate line can be electrically connected to each other via the second gate connection line among the plurality of gate connection lines.

[0015] According to an embodiment, the nth initialization gate line and the (n+1th initialization gate line) among the plurality of initialization gate lines can be driven simultaneously by the (k-1th)th gate driving circuit among the plurality of gate driving circuits, and the mth compensation gate line and the (m+1th)th compensation gate line among the plurality of compensation gate lines can be driven simultaneously by the (k+1th)th gate driving circuit among the plurality of gate driving circuits.

[0016] According to the embodiment, m+1 can be equal to 2k.

[0017] According to an embodiment, the k-th gate driving circuit may include: a side gate driving circuit disposed on one side of the peripheral region, wherein the side gate driving circuit can output a first gate signal to the first portion of each of the m-th initialization gate line and the (m+1)-th initialization gate line and the first portion of each of the n-th compensation gate line and the (n+1)-th compensation gate line; and a other side gate driving circuit disposed on the other side of the peripheral region, wherein the other side gate driving circuit can output a second gate signal to the second portion of each of the m-th initialization gate line and the (m+1)-th initialization gate line and the second portion of each of the n-th compensation gate line and the (n+1)-th compensation gate line.

[0018] According to an embodiment, the display device may further include: a plurality of scan lines extending along pixel rows; a plurality of scan driving circuits disposed in a peripheral region in a column direction, wherein the plurality of scan driving circuits can sequentially drive the plurality of scan lines; and a plurality of scan connecting lines disposed in a non-display region, wherein each of the nth scan line and the (n+1)th scan line may include a first portion and a second portion physically separated from each other by the transmissive region, the first portion and the second portion of the nth scan line are electrically connected to each other through a first scan connecting line among the plurality of scan connecting lines, and the first portion and the second portion of the (n+1)th scan line are electrically connected to each other through a second scan connecting line among the plurality of scan connecting lines.

[0019] According to an embodiment, the first scan connection line may include: a first scan connection electrode, which electrically connects a first portion of the nth scan line to a second portion of the nth scan line; and a second scan connection electrode, which electrically connects the first portion of the nth scan line to the second portion of the nth scan line.

[0020] According to an embodiment, the display device may further include: a first conductive layer including a first scan connection electrode; a semiconductor layer disposed on the first conductive layer; and a second conductive layer on the semiconductor layer, including a second scan connection electrode.

[0021] According to an embodiment, the display device may further include: a plurality of emission control lines extending along pixel rows respectively; and a plurality of emission control drive circuits disposed in the peripheral region and arranged in the direction of the pixel column, wherein each of the nth emission control line and the (n+1)th emission control line among the plurality of emission control lines includes a first portion and a second portion that are physically separated from and electrically insulated from each other by the transmissive regions, the first portion of the nth emission control line and the first portion of the (n+1)th emission control line can be simultaneously driven by a first emission control drive circuit on one side of the peripheral region among the plurality of emission control drive circuits, and the second portion of the nth emission control line and the second portion of the (n+1)th emission control line can be simultaneously driven by a second emission control drive circuit on the other side of the peripheral region among the plurality of emission control drive circuits.

[0022] According to an embodiment, the display device may further include: a plurality of emission control lines extending along pixel rows; a plurality of emission control drive circuits disposed in the peripheral region and arranged in the direction of the pixel column; and emission control connection lines disposed in the non-display region, wherein each of the nth emission control line and the (n+1)th emission control line may include a first portion and a second portion physically separated from each other by the transmissive region, and the first portion and the second portion of each of the nth emission control line and the (n+1)th emission control line may be electrically connected to each other through the emission control connection lines.

[0023] According to an embodiment, each of the pixels arranged in the nth pixel row among the plurality of pixels may include: a light-emitting element; a driving transistor that controls the current flowing to the light-emitting element based on a gate-source voltage; a scanning transistor that transmits a data voltage to the driving transistor in response to a scanning signal; a gate initialization transistor that applies an initialization voltage to the gate of the driving transistor in response to a signal transmitted through the nth initialization gate line among the plurality of initialization gate lines; and a compensation transistor that connects the drain of the driving transistor to the gate of the driving transistor in response to a signal transmitted through the nth compensation gate line.

[0024] According to an embodiment, the conductivity type of each of the gate initialization transistor and the compensation transistor may be the opposite of the conductivity type of the scan transistor.

[0025] According to an embodiment, the display device may further include: a first semiconductor layer including an active region of a scanning transistor; a second semiconductor layer including an active region of a gate initialization transistor and an active region of a compensation transistor; and a conductive layer between the first semiconductor layer and the second semiconductor layer.

[0026] According to an embodiment, the first semiconductor layer may include a silicon semiconductor material, and the second semiconductor layer may include an oxide semiconductor material.

[0027] According to an embodiment, the conduction duration of the signal transmitted through the nth compensation gate line can be equal to twice the conduction duration of the scan signal, or greater than twice the conduction duration of the scan signal.

[0028] According to an embodiment, the via can be defined to pass through the substrate to correspond to the transmission region.

[0029] According to an embodiment, the display device includes: a substrate defining a transmissive region, a display region, a non-display region, and a peripheral region therein, the display region surrounding at least a portion of the transmissive region, the non-display region being between the transmissive region and the display region, and the peripheral region being outside the display region; a plurality of pixels arranged in pixel columns and pixel rows in the display region; a plurality of gate lines extending along the pixel rows; and a plurality of gate connection lines disposed in the non-display region, wherein each of the m-th gate line and the (m+1)-th gate line and the n-th gate line and the (n+1)-th gate line includes a first portion and a second portion physically separated from each other by the transmissive region, the first portions of each of the m-th gate line, the (m+1)-th gate line, the n-th gate line, and the (n+1)-th gate line are connected to each other in the peripheral region, and the first portions and the second portions of each of the m-th gate line and the (m+1)-th gate line are electrically connected to each other through a first gate connection line among the plurality of gate connection lines, wherein n is a positive integer and m is a positive integer greater than n+1.

[0030] According to an embodiment, the first and second portions of each of the nth gate line and the (n+1)th gate line can be electrically connected to each other via a second gate connection line among the plurality of gate connection lines.

[0031] According to an embodiment, the first gate connection line can electrically connect the first portion and the second portion of each of the nth gate line and the (n+1)th gate line to each other.

[0032] According to an embodiment, the second portion of each of the m-th gate line, the (m+1)-th gate line, the n-th gate line, and the (n+1)-th gate line is connected to each other in the peripheral region.

[0033] Other features disclosed will be better understood through the accompanying drawings, claims, and detailed description. Attached Figure Description

[0034] The above and other features of the disclosed specific embodiments will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0035] Figure 1 This is a schematic perspective view of an electronic device according to an embodiment;

[0036] Figure 2 It is along Figure 1 A cross-sectional view of the electronic device taken by line I-I';

[0037] Figure 3 This is a schematic enlarged plan view of the display device according to an embodiment;

[0038] Figure 4 This is a schematic enlarged plan view of a display device according to an optional embodiment;

[0039] Figure 5 This is a schematic enlarged plan view of the display device according to an embodiment;

[0040] Figure 6 This is a schematic enlarged plan view of the display device according to an embodiment;

[0041] Figure 7 This is a schematic enlarged plan view of a display device according to an optional embodiment;

[0042] Figure 8 This is a schematic equivalent circuit diagram of the pixels of a display device according to an embodiment;

[0043] Figure 9 This is a schematic enlarged plan view of the display device according to an embodiment;

[0044] Figure 10 This is a signal timing diagram according to an embodiment for describing a method for driving multiple pixels;

[0045] Figure 11 This is a signal timing diagram according to an optional embodiment for describing a method of driving multiple pixels; and

[0046] Figure 12 and Figure 13 It is along Figure 9 The cross-sectional view of the display device taken by line II-II'. Detailed Implementation

[0047] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals throughout denote the same elements.

[0048] Because this description allows for various variations and numerous embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the written description. The effects and features of the disclosure, as well as methods of implementing them, will be illustrated with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the disclosure is not limited to the following embodiments and can be implemented in many different forms.

[0049] It will be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or there may be an intermediate element between the element and the other element. Conversely, when an element is referred to as being "directly on" another element, there is no intermediate element.

[0050] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teaching herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0051] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the,” as well as “at least one,” do not indicate a limitation of quantity and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprising” and / or “including” are used in this specification, it indicates the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0052] For ease of explanation, the dimensions of elements in the accompanying drawings may be exaggerated or reduced. For example, the disclosure is not limited thereto because the dimensions and thicknesses of components in the drawings are arbitrarily shown for ease of explanation.

[0053] When a particular embodiment can be implemented differently, the specific process sequence can be performed differently than the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in the reverse order of the described sequence.

[0054] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that relative terms are intended to include different orientations of the device other than those depicted in the drawings. For example, if the device in one of the drawings is flipped, an element described as being “below” the other element will subsequently be oriented to be “above” the other element. Thus, depending on the specific orientation of the drawing, the term “below” can include both “below” and “above” orientations. Similarly, if the device in one of the drawings is flipped, an element described as being “below” or “under” the other element will subsequently be oriented to be “above” the other element. Thus, the terms “below” or “under” can include both “above” and “below” orientations.

[0055] It will also be understood that when layers, regions, or components are referred to as being connected to each other, they can be directly connected to each other, or indirectly connected to each other with intermediate layers, intermediate regions, or intermediate components located between them. For example, when layers, regions, or components are referred to as being electrically connected to each other, they can be directly electrically connected to each other, or indirectly electrically connected to each other with intermediate layers, intermediate regions, or intermediate components located between them.

[0056] The x-axis, y-axis, and z-axis are not limited to the three axes of a Cartesian coordinate system and can be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis can be perpendicular to each other, or they can represent different directions that are not perpendicular to each other.

[0057] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless so explicitly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0058] Here, embodiments are described with reference to schematic cross-sectional views as idealized embodiments. Thus, variations in the shapes shown will be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but will include variations in shape due to, for example, manufacturing processes. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, acute angles shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0059] In the following description, embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0060] Figure 1 This is a schematic perspective view of an electronic device 1 according to an embodiment.

[0061] Reference Figure 1 Embodiments of electronic device 1 are configured to display dynamic or static images and can be limited to various product displays, including not only portable electronic devices such as mobile phones, smartphones, tablet PCs (“PCs”), mobile communication terminals, electronic notebooks, e-books, portable multimedia players (“PMPs”), navigation and ultra-mobile PCs (“UMPCs”), but also televisions (“TVs”), laptops, monitors, billboards and Internet of Things (“IoT”) devices.

[0062] Embodiments of electronic device 1 can also be used in wearable devices such as smartwatches, watch phones, glasses displays, or head-mounted displays (“HMDs”).

[0063] Optionally, the electronic device 1 can also be used as a dashboard of the vehicle, a central information display (“CID”) on the instrument cluster or central dashboard of the vehicle, an interior mirror display replacing the side mirrors of the vehicle, and a display arranged on the rear side of the front seats to serve as an entertainment device for rear-seat passengers of the vehicle. Figure 1 For ease of explanation and description, an embodiment of electronic device 1 as a smartphone is shown.

[0064] An embodiment of electronic device 1 may have a rectangular shape in a plan view. In one embodiment, for example, as... Figure 1 As shown, electronic device 1 can have a rectangular planar shape with a short side in the ±x direction and a long side in the ±y direction. The edges where the short side in the ±x direction and the long side in the ±y direction meet each other can be rounded to have a specific curvature, or can be formed to have right angles. The planar shape of electronic device 1 is not limited to a rectangle, but can have other polygonal shapes, elliptical shapes, or irregular shapes.

[0065] In one embodiment, the electronic device 1 may include a transmissive region TA and a display region DA surrounding at least a portion of the transmissive region TA. The electronic device 1 may also include a non-display region NDA between the transmissive region TA and the display region DA, and a peripheral region PA outside the display region DA. In one embodiment, for example, the peripheral region PA may surround the display region DA.

[0066] The transmissive region TA can be located within the display region DA. According to an embodiment, such as... Figure 1 As shown, the transmission region TA can be located on the upper left side of the display region DA. Alternatively, the transmission region TA can be arranged differently. In one embodiment, for example, the transmission region TA can be arranged at the center of the display region DA, or it can be arranged on the upper right side of the display region DA. In this document, "left," "right," "up," and "down" refer to the vertical or horizontal direction of the electronic device 1 when viewed in a plan view of the electronic device 1. In one embodiment, for example, "left" refers to the -x direction, "right" refers to the +x direction, "up" refers to the +y direction, and "down" refers to the -y direction. Figure 1 An embodiment of arranging a single transmission region TA is shown, but in an alternative embodiment, multiple transmission regions TA can be provided.

[0067] Electronic device 1 can provide an image by using a plurality of pixels PX in a display area DA. Each of the pixels PX may include a display element. Each of the pixels PX may include a display element such as an organic light-emitting diode (OLED). Each of the pixels PX may emit, for example, red, green, blue, or white light from the organic light-emitting diode. Hereinafter, pixel PX may refer to a sub-pixel that emits light of different colors from each other. Each of the pixels PX may be, for example, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0068] Figure 2 It is along Figure 1 A cross-sectional view of electronic device 1 taken by line I-I'.

[0069] Reference Figure 2 The electronic device 1 may include a display device 10 and a component 70 disposed below the display device 10 and superimposed with the transmissive region TA of the display device 10. The display device 10 and the component 70 may be housed in a housing HS.

[0070] The display device 10 may include a display element layer 20, an input sensing layer 40, a light function layer 50, and a cover window 60.

[0071] Display element layer 20 may include display elements (or light-emitting elements) that emit light to display images. The display elements may include light-emitting diodes, such as organic light-emitting diodes including an organic emitting layer.

[0072] According to an optional embodiment, the light-emitting diode (LED) may include an inorganic LED comprising inorganic materials. The inorganic LED may include a PN junction diode comprising inorganic semiconductor materials. In such an embodiment, when a voltage is applied to the PN junction diode in the forward direction, holes and electrons can be injected and recombine to generate energy. The PN junction diode can convert the generated energy into light energy to emit light of a specific color. The inorganic LED may have a width of several micrometers to several hundred micrometers. According to an embodiment, the inorganic LED may be referred to as a micro LED. According to an optional embodiment, the display element layer 20 may include a quantum dot LED.

[0073] In such an embodiment, the emitting layer of the display element layer 20 may include organic materials, inorganic materials, quantum dots, organic materials and quantum dots, or inorganic materials and quantum dots.

[0074] The input sensing layer 40 can obtain coordinate information corresponding to external inputs (e.g., touch events). The input sensing layer 40 may include sensing electrodes (or touch electrodes) and traces electrically connected to the sensing electrodes. The input sensing layer 40 may be located above the display element layer 20. The input sensing layer 40 can sense external inputs using mutual capacitance and / or self-capacitance methods.

[0075] The input sensing layer 40 may be formed directly on the display element layer 20, or it may be formed separately and then bonded to the display element layer 20 by an adhesive layer (such as an optically clear adhesive (“OCA”)). In one embodiment, for example, the input sensing layer 40 may be formed sequentially after the process of forming the display element layer 20. In such an embodiment, the adhesive layer may not be located between the input sensing layer 40 and the display element layer 20. Figure 2 An embodiment of the input sensing layer 40 is shown between the display element layer 20 and the light function layer 50, but in an alternative embodiment, the input sensing layer 40 may be above the light function layer 50.

[0076] The optical functional layer 50 may include an anti-reflective layer. The anti-reflective layer reduces the reflectivity of light (external light) incident from the outside toward the display device 10 through the cover window 60. The anti-reflective layer may include a retarder and a polarizer. The retarder may be a film-type retarder or a liquid crystal coating-type retarder. Furthermore, the polarizer may be a film-type polarizer or a liquid crystal coating-type polarizer. A film-type polarizer may include a stretched synthetic resin film, and a liquid crystal coating-type polarizer may include liquid crystals arranged in a specific array.

[0077] According to an optional embodiment, the antireflective layer may include a black matrix and color filters. The color filters may be arranged based on the arrangement of the colors of light emitted from each light-emitting diode of the display element layer 20. According to an optional embodiment, the antireflective layer may include a destructive interference structure. The destructive interference structure may include a first reflective layer and a second reflective layer on different layers from each other. The first reflected light and the second reflected light reflected from the first reflective layer and the second reflective layer, respectively, can destructively interfere with each other. Therefore, the reflectivity of external light is reduced.

[0078] The optical functional layer 50 may include a lens layer. The lens layer may improve the light emission efficiency of light emitted from the display element layer 20, or may reduce color deviation. The lens layer may include a layer having a concave lens shape or a convex lens shape, and / or may include multiple layers having different refractive indices. The optical functional layer 50 may include one or both of the aforementioned anti-reflective layer and lens layer.

[0079] In an embodiment, the display device 10 may include an opening 10H, that is, the opening 10H may be defined as a portion passing through the display device 10. In this document, when an element is described as including an opening, this description means that the opening is defined as passing through the element. In one embodiment, as... Figure 2 As shown, the display element layer 20, the input sensing layer 40 and the light function layer 50 each include a first opening 20H, a second opening 40H and a third opening 50H, and the first opening 20H, the second opening 40H and the third opening 50H are stacked on top of each other.

[0080] The first opening 20H can extend from the top surface of the display element layer 20 through the bottom surface of the display element layer 20, the second opening 40H can extend from the top surface of the input sensing layer 40 through the bottom surface of the input sensing layer 40, and the third opening 50H can extend from the top surface of the light function layer 50 through the bottom surface of the light function layer 50.

[0081] The openings 10H of the display device 10 (e.g., the first opening 20H, the second opening 40H, and the third opening 50H) can be arranged to overlap each other in the transmissive region TA. In an embodiment, the first opening 20H, the second opening 40H, and the third opening 50H may have the same size (or diameter) as each other. Alternatively, the first opening 20H, the second opening 40H, and the third opening 50H may have different sizes (or diameters) than each other.

[0082] According to an optional embodiment, at least one of the display element layer 20, the input sensing layer 40, and the light function layer 50 may not include an opening. In one embodiment, for example, one or both elements selected from the display element layer 20, the input sensing layer 40, and the light function layer 50 may not include an opening.

[0083] Cover window 60 may be on optical functional layer 50. Cover window 60 may be bonded to optical functional layer 50 via an adhesive layer such as OCA. Cover window 60 may comprise glass or plastic material. Plastic material may comprise polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0084] Cover window 60 may include a flexible window. In one embodiment, for example, cover window 60 may include a polyimide window or an ultra-thin glass window.

[0085] The transmissive region TA can be one type of component region (e.g., sensor region, camera region, speaker region, etc.) arranged for adding various functions to the electronic device 1. The component 70 can be arranged to overlap with the opening 10H of the display device 10.

[0086] Component 70 may include electronic components. In one embodiment, for example, component 70 may include electronic components that use light or sound. In one embodiment, for example, the electronic components may include a sensor that uses light (e.g., an infrared sensor), a camera configured to receive light to capture an image, a sensor configured to measure distance or identify fingerprints by outputting and sensing light or sound, a small lamp configured to output light, a speaker configured to output sound, etc.

[0087] Electronic components that use light can utilize light in various wavelengths, such as visible light, infrared light, and ultraviolet light. The transmission region TA can correspond to the area through which light and / or sound, output from component 70 to the outside or guided from the outside to the electronic component, can pass.

[0088] According to an alternative embodiment, when the electronic device 1 is used as a smartwatch or for a vehicle dashboard, component 70 may include a member containing a clock hand or a pointer indicating specific information (e.g., vehicle speed). In such an embodiment, the cover window 60 may include an opening in the transmission region TA, such that the component 70, like the pointer, is exposed to the outside. In an embodiment where the electronic device 1 includes a component 70 such as a speaker, the cover window 60 may also include an opening corresponding to the transmission region TA.

[0089] Figure 3 This is a schematic enlarged plan view of the display device 10 according to an embodiment.

[0090] Reference Figure 3Embodiments of the display device 10 may include a transmissive region TA, a display region DA, a non-display region NDA, and a peripheral region PA. The non-display region NDA may surround at least a portion of the transmissive region TA. The non-display region NDA is the area in which display elements such as organic light-emitting diodes are not disposed. As described later, signal lines configured to provide signals to pixels PX around the transmissive region TA may pass through or extend through the non-display region NDA. The display device 10 may include an opening 10H corresponding to the transmissive region TA.

[0091] In one embodiment, the display device 10 includes a substrate 100, such that the substrate can be described as including (or defining) a transmissive region TA, a display region DA, a non-display region NDA, and a peripheral region PA. In such an embodiment, the substrate 100 may include an opening corresponding to the transmissive region TA.

[0092] The display device 10 may include a plurality of pixels PX in the display area DA. The plurality of pixels PX may be arranged in pixel rows and pixel columns. Pixel rows may extend in the row direction (e.g., ±x direction), and pixel columns may extend in the column direction (e.g., ±y direction).

[0093] Display device 10 can display images using light emitted from the light-emitting diodes (LEDs) of pixel PX (e.g., red, green, and blue light). The LEDs of pixel PX may include organic light-emitting diodes (OLEDs), as will be referred to later. Figure 8 The description states that organic light-emitting diodes (OLEDs) can be electrically connected to pixel circuitry (PCs). Figure 8 An embodiment of the light-emitting diode is shown, including an organic light-emitting diode (OLED). However, in an alternative embodiment, as described above, the display device 10 may include an inorganic light-emitting diode instead of an organic light-emitting diode (OLED).

[0094] Pixel PX can be electrically connected to external circuitry in the peripheral region PA. Multiple gate drive circuits GDC can be located in the peripheral region PA. In an embodiment, as... Figure 3 As shown, multiple gate drive circuits (GDCs) can be arranged in the peripheral region PA in the column direction (e.g., ±x direction).

[0095] The gate drive circuit GDC can be connected to multiple compensation gate lines GC and multiple initialization gate lines GI arranged in a pixel row. The gate drive circuit GDC can be connected to the compensation gate lines GC and initialization gate lines GI extending in the row direction (e.g., ±x direction).

[0096] Each of the compensation gate lines GC can be connected to a pixel PX located in the same row. The compensation gate lines GC can be configured to sequentially transmit electrical signals to the pixels PX located in the same row. In one embodiment, for example, as... Figure 3 As shown, the nth compensation gate line GCn in the compensation gate line GC can be connected to the nth pixel PXn in the nth row, and can be configured to sequentially transmit electrical signals to the nth pixel PXn. In such an embodiment, the (n+1)th compensation gate line GCn+1 in the compensation gate line GC can be connected to the (n+1)th pixel PXn+1 in the (n+1)th row, and can be configured to sequentially transmit electrical signals to the (n+1)th pixel PXn+1. Here, n is a positive integer.

[0097] Each initialization gate line GI can be connected to a pixel PX located in the same row. The initialization gate line GI can be configured to sequentially transmit electrical signals to pixels PX located in the same row. In one embodiment, for example, as... Figure 3 As shown, the m-th initialization gate line GIM in the initialization gate line GI can be connected to the m-th pixel PXm in the m-th row, and can be configured to sequentially transmit electrical signals to the m-th pixel PXm. In such an embodiment, the (m+1)-th initialization gate line GIM+1 in the initialization gate line GI can be connected to the (m+1)-th pixel PXm+1 in the (m+1)-th row, and can be configured to sequentially transmit electrical signals to the (m+1)-th pixel PXm+1. Here, m is a positive integer greater than n+1.

[0098] Because m is greater than n+1, multiple pixel rows can exist between the (n+1)th pixel row and the mth pixel row. In one embodiment, for example, an even number of pixel rows can exist between the (n+1)th pixel row and the mth pixel row. In another embodiment, for example, two pixel rows can exist between the (n+1)th pixel row and the mth pixel row.

[0099] Optionally, the m-th pixel row can be a pixel row adjacent to the (n+1)-th pixel row or a pixel row immediately following the (n+1)-th pixel row. In such an embodiment, m can be n+2.

[0100] According to an embodiment, the gate drive circuit GDC can simultaneously drive the compensation gate line GC and the initialization gate line GI. The compensation gate line GC and the initialization gate line GI, driven by the same gate drive circuit GDC, can be connected to each other in the peripheral region PA.

[0101] In one embodiment, for example, such as Figure 3As shown, the k-th gate drive circuit GDCk in the gate drive circuit GDC can simultaneously drive the n-th compensation gate line GCn and the (n+1)-th compensation gate line GCn+1 in the compensation gate line GC, as well as the m-th initialization gate line Gim and the (m+1)-th initialization gate line Gim+1 in the initialization gate line GI. The n-th compensation gate line GCn, the (n+1)-th compensation gate line GCn+1, the m-th initialization gate line Gim, and the (m+1)-th initialization gate line Gim+1 can be connected to each other in the peripheral region PA. Here, k is a positive integer.

[0102] Figure 3 An embodiment is shown in which each of the gate drive circuits GDC simultaneously drives two compensation gate lines GC and two initialization gate lines GI, but the number of compensation gate lines GC and / or the number of initialization gate lines GI driven simultaneously by each of the gate drive circuits GDC can be varied.

[0103] According to an embodiment, each of the compensation gate lines GC adjacent to the transmission region TA in the row direction (e.g., ±x direction) may have a first portion and a second portion that are physically separated from each other by the transmission regions TA. In one embodiment, for example, as Figure 3 As shown, the nth compensation gate line GCn in the compensation gate line GC can have a first portion GCan and a second portion GCbn that are physically separated from each other by the transmission regions TA. The (n+1)th compensation gate line GCn+1 in the compensation gate line GC can have a first portion GCan+1 and a second portion GCbn+1 that are physically separated from each other by the transmission regions TA.

[0104] According to an embodiment, each of the initial gate lines GI adjacent to the transmission region TA in the row direction (e.g., ±x direction) may have a first portion and a second portion that are physically separated from each other by the transmission regions TA. In one embodiment, for example, as Figure 3 As shown, the m-th initialization gate line GIM in the initialization gate line GI can have a first portion GIam and a second portion GIbm that are physically separated from each other by the transmission regions TA. The (m+1)-th initialization gate line GIM+1 in the initialization gate line GI can have a first portion GIam+1 and a second portion GIbm+1 that are physically separated from each other by the transmission regions TA.

[0105] Multiple gate connection lines (GCLs) can be located in the non-display area NDA between the transmissive region TA and the display region DA. Each of the gate connection lines (GCLs) can bypass the non-display area NDA along the edge of the opening 10H formed or defined in the transmissive region TA of the display device 10.

[0106] In one embodiment, the gate connection line GCL can electrically connect the first and second portions of the compensation gate line GC, which are separate from each other. In such an embodiment, the gate connection line GCL can electrically connect the first and second portions of the initialization gate line GI, which are separate from each other.

[0107] In one embodiment, for example, such as Figure 3 As shown, the first portion GCan of the nth compensation gate line GCn and the first portion GCan+1 of the (n+1)th compensation gate line GCn+1, as well as the second portion GCbn of the nth compensation gate line GCn and the second portion GCbn+1 of the (n+1)th compensation gate line GCn+1, can be electrically connected to each other through the first gate connection line GCL1 in the gate connection line GCL. In such an embodiment, the first portion GIam of the mth initialization gate line GIM and the first portion GIam+1 of the (m+1)th initialization gate line GIM+1, as well as the second portion GIbm of the mth initialization gate line GIM and the second portion GIbm+1 of the (m+1)th initialization gate line GIM+1, can be electrically connected to each other through the second gate connection line GCL2 in the gate connection line GCL.

[0108] In this embodiment, as described above, the first and second portions of the compensation gate line GC, driven by the same gate drive circuit GDC, can be electrically connected to each other via a gate connection line GCL. Similarly, the first and second portions of the initialization gate line GI, also driven by the same gate drive circuit GDC, can be electrically connected to each other via a gate connection line GCL. In this embodiment, because the number of gate connection lines GCLs bypassing the transmission region TA is reduced, the non-display region NDA can be reduced. Therefore, the display region DA can be relatively increased.

[0109] In such an embodiment, because the first and second portions of the transmissive regions TA of the compensation gate line GC, which are separate from each other, are connected to each other via the gate connection line GCL, an electrical signal can be transmitted to the second portion of the compensation gate line GC. In such an embodiment, because the first and second portions of the transmissive regions TA of the initialization gate line GI, which are separate from each other, are connected to each other via the gate connection line GCL, an electrical signal can be transmitted to the second portion of the initialization gate line GI.

[0110] Figure 3 An embodiment is shown with the gate drive circuit GDC on one side of the peripheral region PA, but in an alternative embodiment, the gate drive circuit GDC may also be on the other side of the peripheral region PA (the side opposite to said side). In such an embodiment, the gate drive circuit GDC may be on one side and / or the other side of the peripheral region PA. Figure 9 An embodiment is shown in which the gate drive circuit GDC is located on one side and the other side of the peripheral region PA.

[0111] The gate drive circuit GDC on the other side of the peripheral region PA can be connected to the second part of the compensation gate line GC and the second part of the initialization gate line GI. The gate drive circuit GDC on the other side of the peripheral region PA can drive the second part of the compensation gate line GC and the second part of the initialization gate line GI.

[0112] In embodiments where the transmission region TA is on one side of the display region DA, the length of the first portion of the compensation gate line GC may differ from the length of the second portion of the compensation gate line GC. In one embodiment, for example, where the transmission region TA is located on the upper left side of the display region DA, the length of the second portion of the compensation gate line GC may be greater than the length of the first portion of the compensation gate line GC. This difference in length may result in a difference in the load of electrical signals (e.g., scan signals). Because the first portion and the second portion of the compensation gate line GC are connected to each other via the gate connection line GCL, the difference in load can be canceled out. This characteristic of the compensation gate line GC can be applied to the initialization gate line GI.

[0113] Figure 4 This is a schematic enlarged plan view of the display device 10 according to an optional embodiment. Figure 4 yes Figure 3 The modified embodiment, in Figure 4 The structure of the gate connection line (GCL) was modified.

[0114] Reference Figure 4 In an optional embodiment, each of the gate drive circuits GDC can simultaneously drive multiple compensation gate lines GC and multiple initialization gate lines GI. In one embodiment, for example, the k-th gate drive circuit GDCk can simultaneously drive the n-th compensation gate line GCn and the (n+1)-th compensation gate line GCn+1 among the compensation gate lines GC, and the m-th initialization gate line GIm and the (m+1)-th initialization gate line GIm+1 among the initialization gate lines GI. Here, k and n are positive integers, and m is a positive integer greater than n+1.

[0115] According to an embodiment, the first and second portions of the compensation gate line GC and the initialization gate line GI, driven by the same gate drive circuit GDC, can be electrically connected to each other via a single gate connection line GCL.

[0116] In one embodiment, for example as described above, the k-th gate drive circuit GDCk can simultaneously drive the n-th compensation gate line GCn, the (n+1)-th compensation gate line GCn+1, the m-th initialization gate line Gim, and the (m+1)-th initialization gate line Gim+1. In such an embodiment, the first portion GCan of the n-th compensation gate line GCn, the first portion GCan+1 of the (n+1)-th compensation gate line GCn+1, the first portion GIam of the m-th initialization gate line Gim, and the first portion GIam+1 of the (m+1)-th initialization gate line Gim+1 can be electrically connected via gate connection lines GCL to the second portions GCbn of the n-th compensation gate line GCn, GCbn+1 of the (n+1)-th compensation gate line GCn+1, GIbm of the m-th initialization gate line Gim, and GIbm+1 of the (m+1)-th initialization gate line Gim+1, respectively.

[0117] In such an embodiment, as described above, the first and second portions of the compensation gate line GC and the initialization gate line GI, driven by the same gate drive circuit GDC, are electrically connected to each other via a single gate connection line GCL. This reduces the number of gate connection lines GCL that bypass the transmission region TA, thereby reducing the non-display region NDA. Consequently, the display region DA can be relatively increased. In such an embodiment, the load difference caused by the length difference between the first and second portions of the compensation gate line GC and the initialization gate line GI can be reduced (or eliminated).

[0118] Figure 5 This is a schematic enlarged plan view of the display device 10 according to an embodiment.

[0119] Reference Figure 5 In this embodiment, multiple scan drive circuits SDC can be located in the peripheral region PA. For example... Figure 5 As shown, multiple scan drive circuits SDC can be arranged in the peripheral region PA in the column direction (e.g., ±x direction).

[0120] The scan drive circuit SDC can be connected to multiple scan lines GW arranged in a pixel row. The scan drive circuit SDC can be connected to scan lines GW extending in the row direction (e.g., ±x direction). The scan drive circuit SDC can be configured to sequentially drive the scan lines GW.

[0121] Each scan line GW can be connected to a pixel PX located in the same row. The scan line GW can be configured to sequentially transmit electrical signals to the pixels PX located in the same row. In one embodiment, for example, as... Figure 5As shown, the nth scan line GWn in the scan lines GW can be connected to the nth pixel PXn in the nth row, and can be configured to sequentially transmit electrical signals to the nth pixel PXn. In such an embodiment, the (n+1)th scan line GWn+1 in the scan lines GW can be connected to the (n+1)th pixel PXn+1 in the (n+1)th row, and can be configured to sequentially transmit electrical signals to the (n+1)th pixel PXn+1. n is a positive integer.

[0122] According to an embodiment, each scan line GW adjacent to the transmission region TA in the row direction (e.g., ±x direction) may have a first portion and a second portion physically separated from each other by the transmission regions TA. In one embodiment, for example, as Figure 5 As shown, the nth scan line GWn in the scan line GW may have a first portion GWan and a second portion GWbn that are physically separated from each other by the transmission regions TA. In such an embodiment, the (n+1)th scan line GWn+1 in the scan line GW may have a first portion GWan+1 and a second portion GWbn+1 that are physically separated from each other by the transmission regions TA.

[0123] Multiple scan connection lines SCL can be located in the non-display area NDA between the transmissive area TA and the display area DA. Each scan connection line SCL can bypass the non-display area NDA along the edge of the opening 10H defined in the display device 10 or formed in the transmissive area TA.

[0124] The scan connection line SCL can electrically connect the first and second parts of the scan line GW, which are separate from each other.

[0125] In one embodiment, for example, such as Figure 5 As shown, the first portion GWan and the second portion GWbn of the nth scan line GWn can be electrically connected to each other via the first scan connection line SCL1 in the scan connection line SCL. In such an embodiment, the first portion GWan+1 and the second portion GWbn+1 of the (n+1)th scan line GWn+1 can be electrically connected to each other via the second scan connection line SCL2 in the scan connection line SCL.

[0126] In such an embodiment, because the first and second portions of the transmissive regions TA of the scan line GW are separated from each other by the scan connection line SCL, electrical signals can be transmitted to the second portion of the scan line GW.

[0127] Figure 5An embodiment is shown with the scan drive circuit SDC on one side of the peripheral region PA, but in an alternative embodiment, the scan drive circuit SDC may also be on the other side of the peripheral region PA (e.g., the side opposite to said side). In such an embodiment, the scan drive circuit SDC may be on one side and / or the other side of the peripheral region PA. Figure 9 An embodiment is shown in which the scan drive circuit SDC is located on one side and the other side of the peripheral region PA.

[0128] The scan drive circuit SDC on the other side of the peripheral region PA can be connected to the second part of the scan line GW. The scan drive circuit SDC on the other side of the peripheral region PA can drive the second part of the scan line GW.

[0129] In an embodiment where the transmission region TA is located on one side of the display region DA, the length of the first portion of the scan line GW may differ from the length of the second portion of the scan line GW. In one embodiment, for example, when the transmission region TA is on the upper left side of the display region DA, the length of the second portion of the scan line GW may be greater than the length of the first portion of the scan line GW. This difference in length may result in a difference in the load of the electrical signal (e.g., the scan signal). In this embodiment, because the first portion and the second portion of the scan line GW are connected to each other via the scan connection line SCL, the difference in load can be reduced.

[0130] Figure 6 This is a schematic enlarged plan view of the display device 10 according to an embodiment.

[0131] Reference Figure 6 In this embodiment, multiple transmit control drive circuits (EDCs) can be located in the peripheral area (PA). For example... Figure 6 As shown, the transmit control drive circuit EDC can be arranged in the peripheral region PA in the column direction (e.g., ±x direction).

[0132] The emission control drive circuit EDC can be connected to multiple emission control lines EM arranged in a pixel row. The emission control drive circuit EDC can be connected to emission control lines EM extending in the row direction (e.g., ±x direction).

[0133] The transmit control drive circuit EDC can be located on one side and the other side (e.g., the side opposite to the one on the peripheral region PA). The transmit control drive circuit EDC on one side of the peripheral region PA can be referred to as the first transmit control drive circuit EDC1, and the transmit control drive circuit EDC on the other side of the peripheral region PA can be referred to as the second transmit control drive circuit EDC2.

[0134] Each of the transmit control lines EM can be connected to a pixel PX located in the same row. The transmit control lines EM can be configured to sequentially transmit electrical signals to the pixels PX located in the same row. In one embodiment, for example, as... Figure 6 As shown, the nth transmission control line EMn in the transmission control line EM can be connected to the nth pixel PXn in the nth row, and can be configured to sequentially transmit electrical signals to the nth pixel PXn. In such an embodiment, the (n+1)th transmission control line EMn+1 in the transmission control line EM can be connected to the (n+1)th pixel PXn+1 in the (n+1)th row, and can be configured to sequentially transmit electrical signals to the (n+1)th pixel PXn+1. Here, n is a positive integer.

[0135] According to an embodiment, each of the transmission control lines EM adjacent to the transmission region TA in the row direction (e.g., ±x direction) may have a first portion and a second portion that are physically separated from each other by the transmission regions TA. In one embodiment, for example, as Figure 6 As shown, the nth transmission control line EMn in the transmission control line EM can have a first portion EMan and a second portion EMbn that are physically separated from each other by the transmission regions TA. In such an embodiment, the (n+1)th transmission control line EMn+1 in the transmission control line EM can have a first portion EMan+1 and a second portion EMbn+1 that are physically separated from each other by the transmission regions TA.

[0136] The first part of the transmit control line EM can be driven by the first transmit control drive circuit EDC1 on one side of the peripheral region PA, and the second part of the transmit control line EM can be driven by the second transmit control drive circuit EDC2 on the other side of the peripheral region PA.

[0137] According to an embodiment, each of the transmit control drive circuits (EDC) can simultaneously drive the transmit control line (EM). The transmit control lines (EM) driven by the same transmit control drive circuit (EDC) can be connected to each other in the peripheral region (PA).

[0138] In one embodiment, for example, such as Figure 6 As shown, the first transmit control drive circuit EDC1, located on one side of the peripheral region PA within the transmit control drive circuit EDC, can simultaneously drive the first portion EMan of the nth transmit control line EMn and the first portion EMan+1 of the (n+1)th transmit control line EMn+1. In this embodiment, the second transmit control drive circuit EDC2, located on the other side of the peripheral region PA within the transmit control drive circuit EDC, can simultaneously drive the second portion EMbn of the nth transmit control line EMn and the second portion EMbn+1 of the (n+1)th transmit control line EMn+1.

[0139] although Figure 6 An embodiment is shown in which each of the transmit control drive circuits EDC simultaneously drives two transmit control lines EM, but the number of transmit control lines EM simultaneously driven by each of the transmit control drive circuits EDC can be varied.

[0140] Figure 7 This is a schematic enlarged plan view of the display device 10 according to an optional embodiment. Figure 7 yes Figure 6 The modified embodiment, in Figure 7 A transmit control connection line (ECL) has been added.

[0141] Reference Figure 7 In this embodiment, multiple emission control connection lines (ECLs) may be located in a non-display area NDA between the transmissive region TA and the display region DA. Each of the emission control connection lines (ECLs) may bypass the non-display area NDA along the edge of the opening 10H defined in or formed in the transmissive region TA of the display device 10.

[0142] The transmit control connection line ECL can electrically connect the first and second parts of the transmit control line EM, which are separate from each other.

[0143] In one embodiment, for example, such as Figure 7 As shown, the first part EMan of the nth transmit control line EMn and the first part EMan+1 of the (n+1)th transmit control line EMn+1, as well as the second part EMbn of the nth transmit control line EMn and the second part EMbn+1 of the (n+1)th transmit control line EMn+1, can be electrically connected to each other via the transmit control connection line ECL.

[0144] In such an embodiment, as described above, the first and second portions of the transmit control line EM, driven by the same transmit control drive circuit EDC, can be electrically connected to each other via a single transmit control connection line ECL.

[0145] Figure 7 An embodiment is shown with the transmit control drive circuit EDC on one side and the other side of the peripheral region PA. However, in an alternative embodiment, the transmit control drive circuit EDC may also be on one side or the other side of the peripheral region PA. In such an embodiment, the first transmit control drive circuit EDC1 or the second transmit control drive circuit EDC2 may be omitted.

[0146] Figure 8 This is a schematic equivalent circuit diagram of the pixel PX of the display device according to an embodiment.

[0147] Reference Figure 8In one embodiment, a pixel PX may include a pixel circuit PC and a light-emitting element electrically connected to the pixel circuit PC. In one embodiment, for example, the light-emitting element may include an organic light-emitting diode (OLED).

[0148] In an embodiment, such as Figure 8 As shown, the pixel circuit PC may include a plurality of thin-film transistors T1 to T7 and a storage capacitor Cst. The thin-film transistors T1 to T7 and the storage capacitor Cst may be connected to signal lines GW, GC, GI, GB, EM and DL, initialization voltage line VIL, and drive voltage line PL. According to an embodiment, at least one of the signal lines GW, GC, GI, GB, EM and DL, initialization voltage line VIL, and drive voltage line PL may be shared by adjacent pixels PX.

[0149] Thin-film transistors T1 to T7 may include a driving thin-film transistor T1, a scanning thin-film transistor T2, a compensation thin-film transistor T3, a gate initialization thin-film transistor T4, an operation control thin-film transistor T5, an emission control thin-film transistor T6, and an anode initialization thin-film transistor T7.

[0150] Some of the thin-film transistors T1 to T7 can be configured as n-channel metal-oxide-semiconductor field-effect transistors (“MOSFETs”) (hereinafter referred to as NMOS), and others of them can be configured as p-channel MOSFETs (hereinafter referred to as PMOS).

[0151] In one embodiment, for example, such as Figure 8 As shown, the compensation thin-film transistor T3 and the gate initialization thin-film transistor T4 among the thin-film transistors T1 to T7 can be configured as NMOS, and the other thin-film transistors among them can be configured as PMOS.

[0152] According to an optional embodiment, the compensation thin-film transistor T3, the gate initialization thin-film transistor T4, and the anode initialization thin-film transistor T7 among the thin-film transistors T1 to T7 can be configured as NMOS, and the other thin-film transistors among them can be configured as PMOS. Optionally, only one of the thin-film transistors T1 to T7 can be configured as NMOS, and the other transistors among them can be configured as PMOS. Optionally, all thin-film transistors T1 to T7 can be configured as NMOS.

[0153] The signal lines include a scan line GW configured to transmit a scan signal Sgw, a compensation gate line GC configured to transmit a compensation signal Sgc, an initialization gate line GI configured to transmit an initialization signal Sgi to a gate initialization thin-film transistor T4, an emitt control line EM configured to transmit an emitt control signal Sem to an operation control thin-film transistor T5 and an emitt control thin-film transistor T6, a next scan line GB configured to transmit a next scan signal Sgb to an anode initialization thin-film transistor T7, and a data line DL that intersects the scan line GW and is configured to transmit a data signal Dm.

[0154] The driving voltage line PL is configured to transmit the first driving voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VIL is configured to transmit the initialization voltage Vint for initializing the anode of the organic light-emitting diode OLED and the driving thin film transistor T1.

[0155] The gate of driving thin-film transistor T1 is connected to the storage capacitor Cst. The source of driving thin-film transistor T1 is connected to the driving voltage line PL via the operation control thin-film transistor T5. The drain of driving thin-film transistor T1 is electrically connected to the anode of the organic light-emitting diode (OLED) via the emitter control thin-film transistor T6. Driving thin-film transistor T1 is configured to receive the data signal Dm based on the switching operation of scanning thin-film transistor T2 and supply driving current I to the OLED. OLED .

[0156] The gate of scanning thin-film transistor T2 is connected to the scan line GW, the source of scanning thin-film transistor T2 is connected to the data line DL, and the drain of scanning thin-film transistor T2 is connected to the source of driving thin-film transistor T1 and to the drive voltage line PL via operation control thin-film transistor T5. Scanning thin-film transistor T2 is turned on in response to the scan signal Sgw received via scan line GW and performs a switching operation to transmit the data signal Dm received via data line DL to the source of driving thin-film transistor T1.

[0157] The gate of the compensation thin-film transistor T3 is connected to the compensation gate line GC. The drain of the compensation thin-film transistor T3 is connected to the drain of the driving thin-film transistor T1 and to the anode of the organic light-emitting diode (OLED) via the emission control thin-film transistor T6. The source of the compensation thin-film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst and the gate of the driving thin-film transistor T1. In such an embodiment, the source of the compensation thin-film transistor T3 is connected to the drain of the gate initialization thin-film transistor T4. The compensation thin-film transistor T3 is turned on in response to the compensation signal Sgc received via the compensation gate line GC and diode-connected to the driving thin-film transistor T1 by electrically connecting the gate and drain of the driving thin-film transistor T1 to each other.

[0158] The gate of gate-initialized thin-film transistor T4 is connected to the initialization gate line GI. The source of gate-initialized thin-film transistor T4 is connected to the initialization voltage line VIL and the source of anode-initialized thin-film transistor T7. The drain of gate-initialized thin-film transistor T4 is connected to the lower electrode CE1 of storage capacitor Cst, the source of compensation thin-film transistor T3, and the gate of driving thin-film transistor T1. Gate-initialized thin-film transistor T4 is turned on in response to the initialization signal Sgi received through the initialization gate line GI and performs an initialization operation to initialize the voltage of the gate of driving thin-film transistor T1 by transmitting an initialization voltage Vint to the gate of driving thin-film transistor T1.

[0159] The gate of the operation control thin film transistor T5 is connected to the emitter control line EM, the source of the operation control thin film transistor T5 is connected to the drive voltage line PL, and the drain of the operation control thin film transistor T5 is connected to the source of the drive thin film transistor T1 and the drain of the scan thin film transistor T2.

[0160] The gate of the emission control thin film transistor T6 is connected to the emission control line EM, the source of the emission control thin film transistor T6 is connected to the drain of the driving thin film transistor T1 and the drain of the compensation thin film transistor T3, and the drain of the emission control thin film transistor T6 is electrically connected to the drain of the anode initialization thin film transistor T7 and the anode of the organic light-emitting diode OLED.

[0161] The operation control thin-film transistor T5 and the emission control thin-film transistor T6 simultaneously turn on in response to the emission control signal Sem received through the emission control line EM and transmit the first driving voltage ELVDD to the organic light-emitting diode OLED, causing the driving current I... OLED It flows through an organic light-emitting diode (OLED).

[0162] The gate of the anode initialization thin-film transistor T7 is connected to the next scan line GB. The drain of the anode initialization thin-film transistor T7 is connected to the drain of the emission control thin-film transistor T6 and the anode of the organic light-emitting diode (OLED). The source of the anode initialization thin-film transistor T7 is connected to the source of the gate initialization thin-film transistor T4 and the initialization voltage line VIL. The anode initialization thin-film transistor T7 is turned on in response to the next scan signal Sgb received through the next scan line GB, thus initializing the anode of the OLED.

[0163] In one embodiment, the next scan signal Sgb may be substantially synchronized with the scan signal Sgw. Alternatively, the next scan signal Sgb may be substantially synchronized with the scan signal Sgw of the next row. In one embodiment, for example, the next scan line GB may be substantially the same as the scan line GW of the next row. Pixels PX that are adjacent to each other in the column direction may share the scan line GW.

[0164] In an embodiment, such as Figure 8 As shown, the anode-initialized thin-film transistor T7 can be connected to the next scan line GB. Optionally, the anode-initialized thin-film transistor T7 can be connected to the emitter control line EM and driven in response to the emitter control signal Sem. The positions of the source and drain of the thin-film transistor can be varied depending on the transistor type (p-type or n-type).

[0165] The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 of the storage capacitor Cst is connected to the gate of the driving thin-film transistor T1, and the upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst can store the charge corresponding to the difference between the gate voltage of the driving thin-film transistor T1 and the first driving voltage ELVDD.

[0166] In this embodiment, the organic light-emitting diode (OLED) is connected to the pixel circuit PC and the second driving voltage ELVSS.

[0167] Despite Figure 8 Not shown, but the pixel circuit PC may include a boost capacitor comprising a first electrode and a second electrode. The first electrode of the boost capacitor may be connected to the gate of the scanning thin-film transistor T2 and the scan line GW, and the second electrode of the boost capacitor may be connected to the source of the compensation thin-film transistor T3.

[0168] The operation of each pixel PX according to the embodiment will be described in detail below.

[0169] During the initialization period, when the initialization signal Sgi is supplied through the initialization gate line GI, the gate initialization thin film transistor T4 turns on in response to the initialization signal Sgi, and drives the thin film transistor T1 to be initialized by the initialization voltage Vint supplied from the initialization voltage line VIL.

[0170] During the data programming period, when the scan signal Sgw and the compensation signal Sgc are supplied through the scan line GW and the compensation gate line GC, the scan thin-film transistor T2 and the compensation thin-film transistor T3 are turned on in response to the scan signal Sgw and the compensation signal Sgc. At this time, the driving thin-film transistor T1 is connected to the diode of the turned-on compensation thin-film transistor T3 and is forward biased.

[0171] A compensation voltage (Dm-|Vth|) is applied to the gate of the driving thin film transistor T1 by reducing the absolute value of the data signal Dm supplied from the data line DL by the threshold voltage (Vth is negative).

[0172] The first driving voltage ELVDD and the compensation voltage (Dm+Vth) are applied to the two ends of the storage capacitor Cst, and the charge corresponding to the voltage difference between the two ends of the storage capacitor Cst is stored in the storage capacitor Cst.

[0173] During the emission period, the operation control thin-film transistor T5 and the emission control thin-film transistor T6 are turned on in response to the emission control signal Sem received from the emission control line EM. Drive current I OLED The current I is generated based on the voltage difference between the gate voltage of the driving thin-film transistor T1 and the first driving voltage ELVDD, and the driving current I OLED The emission control thin-film transistor T6 supplies power to the organic light-emitting diode (OLED).

[0174] In an embodiment, at least one of the thin-film transistors T1 to T7 may include a semiconductor layer comprising an oxide, and the other thin-film transistors therein may include a semiconductor layer comprising silicon.

[0175] In such an embodiment, the driving thin-film transistor T1, which directly affects the brightness of the display device, may include a semiconductor layer comprising highly reliable polycrystalline silicon. Therefore, a high-resolution display device can be realized.

[0176] Because oxide semiconductors have high carrier mobility and low leakage current, the voltage drop is not large even with long drive times. In other words, even during low-frequency drive, the color change in the voltage drop profile is minimal, thus enabling efficient low-frequency drive.

[0177] Therefore, oxide semiconductors have the desired characteristic of low leakage current. Thus, at least one of the compensation thin-film transistors T3, gate initialization thin-film transistors T4, and anode initialization thin-film transistors T7 connected to the gate of the driving thin-film transistor T1 may include oxide semiconductors to prevent leakage current from flowing to the gate of the driving thin-film transistor T1 and reduce power consumption.

[0178] Figure 9 This is a schematic enlarged plan view of the display device according to an embodiment. Specifically, Figure 9 It shows Figure 3 Compensation gate line GC and initialization gate line GI, Figure 5 GW and scan lines Figure 6 The transmit control line EM.

[0179] Reference Figure 9 In this embodiment, the gate drive circuit GDC ( Figure 3 The scan drive circuit SDC and the transmit control drive circuit EDC can be located in the peripheral area PA. In such an embodiment, as... Figure 9As shown, the gate drive circuit GDC, the scan drive circuit SDC, and the emit control drive circuit EDC can be located in the peripheral region PA in the row direction (e.g., the ±x direction).

[0180] In such an embodiment, the gate drive circuit GDC, the scan drive circuit SDC, and the emit control drive circuit EDC can be located on one side and the other side of the peripheral region PA. In an alternative embodiment, as referred to above... Figures 3 to 5 as well as Figure 7 As described, the gate drive circuit GDC, scan drive circuit SDC, and transmit control drive circuit EDC can be located on one side or the other side of the peripheral region PA. In such an embodiment, the gate drive circuit GDC, scan drive circuit SDC, and transmit control drive circuit EDC on said one side of the peripheral region PA can be omitted, or the gate drive circuit GDC, scan drive circuit SDC, and transmit control drive circuit EDC on said the other side of the peripheral region PA can be omitted.

[0181] In the embodiment, the nth pixel PXn arranged in the nth pixel row of pixel PX ( Figure 3 It can be connected to the nth compensation gate line GCn. Figure 3 ), nth scan line GWn ( Figure 5 ), the nth initialization gate line GIn and the nth emitter control line EMn ( Figure 6 In such an embodiment, the (n+1)th pixel PXn+1 arranged in the (n+1)th pixel row can be connected to the (n+1)th compensation gate line GCn+1. Figure 3 ), the (n+1)th scan line GWn+1 ( Figure 5 ), the (n+1)th initialization gate line GIn+1 and the (n+1)th emitter control line EMn+1 Figure 6 Here, n is a positive integer.

[0182] According to the embodiments, although Figure 9 Not shown in the diagram, but the (n+1)th scan line GWn+1 can be connected to the nth pixel PXn. The nth pixel PXn and the (n+1)th pixel PXn+1 can share the (n+1)th scan line GWn+1. In the embodiment, as referenced above... Figure 8 The described method includes an anode initialization thin-film transistor T7 in each pixel of the nth pixel PXn, which can be turned on by the (n+1)th scan line GWn+1 in the next row, and can enable the anode initialization of the organic light-emitting diode OLED.

[0183] In an embodiment, the m-th pixel PXm arranged in the m-th pixel row can be connected to the m-th compensation gate line GCm, the m-th scan line GWm, and the m-th initialization gate line GIm. Figure 3) and the m-th transmit control line EMm. In such an embodiment, the (m+1)-th pixel PXm+1 arranged in the (m+1)-th pixel row can be connected to the (m+1)-th compensation gate line GCm+1, the (m+1)-th scan line GWm+1, and the (m+1)-th initialization gate line GIm+1 ( Figure 3 ) and the (m+1)th transmit control line EMm+1. Here, m is a positive integer greater than n+1.

[0184] According to the embodiments, although in Figure 9 Not shown, but the (m+1)th scan line GWm+1 can be connected to the m-th pixel PXm. The m-th pixel PXm and the (m+1)th pixel PXm+1 can share the (m+1)th scan line GWm+1. In such an embodiment, as referred to above... Figure 8 The described method includes an anode initialization thin-film transistor T7 in each pixel of the m-th pixel PXm, which can be turned on by the (m+1)-th scan line GWm+1 in the next row, and can enable the anode initialization of the organic light-emitting diode OLED.

[0185] The nth compensated gate line GCn, the (n+1)th compensated gate line GCn+1, the mth initialization gate line Gim, and the (m+1)th initialization gate line Gim+1 can be connected to the kth gate drive circuit GDCk. The nth compensated gate line GCn, the (n+1)th compensated gate line GCn+1, the mth initialization gate line Gim, and the (m+1)th initialization gate line Gim+1 can all be driven simultaneously by the kth gate drive circuit GDCk. Here, k is a positive integer.

[0186] In an embodiment, such as Figure 9 As shown, the first portion GCarn of the nth compensation gate line GCn, the first portion GCarn+1 of the (n+1)th compensation gate line GCn+1, the first portion GIam of the mth initialization gate line Gim, and the first portion GIam+1 of the (m+1)th initialization gate line Gim+1 can be connected to the kth gate drive circuit GDCk on one side of the peripheral region PA and driven simultaneously. In such an embodiment, the second portion GCbn of the nth compensation gate line GCn, the second portion GCbn+1 of the (n+1)th compensation gate line GCn+1, the second portion GIbm of the mth initialization gate line Gim, and the second portion GIbm+1 of the (m+1)th initialization gate line Gim+1 can be connected to the kth gate drive circuit GDCk on the other side of the peripheral region PA and driven simultaneously.

[0187] In such an embodiment, the k-th gate drive circuit GDCk on one side of the peripheral region PA can be configured to output a first gate signal to the first part GCan of the n-th compensation gate line GCn, the first part GCan+1 of the (n+1)-th compensation gate line GCn+1, the first part GIam of the m-th initialization gate line Gim, and the first part GIam+1 of the (m+1)-th initialization gate line Gim+1. On the other side of the peripheral region PA, the k-th gate drive circuit GDCk can be configured to output a second gate signal, the same as the first gate signal, to the second part GCbn of the n-th compensation gate line GCn, the second part GCbn+1 of the (n+1)-th compensation gate line GCn+1, the second part GIbm of the m-th initialization gate line Gim, and the second part GIbm+1 of the (m+1)-th initialization gate line Gim+1.

[0188] The first portion GGaN of the nth compensation gate line GCn and the first portion GGaN+1 of the (n+1)th compensation gate line GCn+1, as well as the second portion GCbn of the nth compensation gate line GCn and the second portion GCbn+1 of the (n+1)th compensation gate line GCn+1, can be connected to each other via the first gate connection line GCL1. The first portion GIam of the mth initialization gate line GIM and the first portion GIam+1 of the (m+1)th initialization gate line GIM, as well as the second portion GIbm of the mth initialization gate line GIM and the second portion GIbm+1 of the (m+1)th initialization gate line GIM, can be connected to each other via the second gate connection line GCL2.

[0189] The nth scan line GWn, the (n+1)th scan line GWn+1, the mth scan line GWm, and the (m+1)th scan line GWm+1 can be connected to the scan drive circuit SDC. The scan drive circuit SDC can sequentially drive the nth scan line GWn, the (n+1)th scan line GWn+1, the mth scan line GWm, and the (m+1)th scan line GWm+1.

[0190] In an embodiment, such as Figure 9 As shown, the first portion GWan of the nth scan line GWn, the first portion GWan+1 of the (n+1)th scan line GWn+1, the first portion GWam of the mth scan line GWm, and the first portion GWam+1 of the (m+1)th scan line GWm+1 can be connected to the scan drive circuit SDC on one side of the peripheral region PA and can be driven sequentially. In such an embodiment, the second portion GWbn of the nth scan line GWn, the second portion GWbn+1 of the (n+1)th scan line GWn+1, the second portion GWbm of the mth scan line GWm, and the second portion GWbm+1 of the (m+1)th scan line GWm+1 can be connected to the scan drive circuit SDC on the other side of the peripheral region PA and can be driven sequentially.

[0191] The nth transmit control line EMn, the (n+1)th transmit control line EMn+1, the mth transmit control line EMm, and the (m+1)th transmit control line EMm+1 can be connected to the transmit control drive circuit EDC. The nth transmit control line EMn and the (n+1)th transmit control line EMn+1 can be connected to the same transmit control drive circuit EDC and can be driven simultaneously. The mth transmit control line EMm and the (m+1)th transmit control line EMm+1 can be connected to the same transmit control drive circuit EDC and can be driven simultaneously.

[0192] In an embodiment, such as Figure 9 As shown, the first portion EMan of the nth transmit control line EMn, the first portion EMan+1 of the (n+1)th transmit control line EMn+1, the first portion EMam of the mth transmit control line EMm, and the first portion EMam+1 of the (m+1)th transmit control line EMm+1 can be connected to the transmit control drive circuit EDC on one side of the peripheral region PA. In such an embodiment, the second portion EMbn of the nth transmit control line EMn, the second portion EMbn+1 of the (n+1)th transmit control line EMn+1, the second portion EMbm of the mth transmit control line EMm, and the second portion EMbm+1 of the (m+1)th transmit control line EMm+1 can be connected to the transmit control drive circuit EDC on the other side of the peripheral region PA. The first part EMan of the nth transmission control line EMn, the first part EMan+1 of the (n+1)th transmission control line EMn+1, the first part EMam of the mth transmission control line EMm, and the first part EMam+1 of the (m+1)th transmission control line EMm+1, along with the second part EMbn of the nth transmission control line EMn, the second part EMbn+1 of the (n+1)th transmission control line EMn+1, the second part EMbm of the mth transmission control line EMm, and the second part EMbm+1 of the (m+1)th transmission control line EMm+1, can be separated by the transmission region TA.

[0193] The nth initialization gate line GIn and the (n+1)th initialization gate line GIn+1 can be connected to the pth gate drive circuit GDCp. In an embodiment, as shown... Figure 9 As shown, in addition to the nth initialization gate line GIn and the (n+1)th initialization gate line GIn+1, the ith compensation gate line GCI and the (i+1)th compensation gate line GCI+1 can also be connected to the pth gate drive circuit GDCp. The nth initialization gate line GIn, the (n+1)th initialization gate line GIn+1, the ith compensation gate line GCI, and the (i+1)th compensation gate line GCI+1 can be driven simultaneously by the pth gate drive circuit GDCp. Here, p is a positive integer less than k, and i is a positive integer less than n-1.

[0194] In an embodiment, such as Figure 9As shown, the first part GIan of the nth initialization gate line GIn and the first part GIan+1 of the (n+1)th initialization gate line GIn+1 can be connected to the pth gate drive circuit GDCp on one side of the peripheral region PA and can be driven simultaneously. The second part GIbn of the nth initialization gate line GIn and the second part GIbn+1 of the (n+1)th initialization gate line GIn+1 can be connected to the pth gate drive circuit GDCp on the other side of the peripheral region PA and can be driven simultaneously.

[0195] The first part GIan of the nth initialization gate line GIn and the first part GIan+1 of the (n+1)th initialization gate line GIn+1, as well as the second part GIbn of the nth initialization gate line GIn and the second part GIbn+1 of the (n+1)th initialization gate line GIn+1, can be connected to each other through the third gate connection line GCL3.

[0196] The m-th compensation gate line GCm and the (m+1)-th compensation gate line GCm+1 can be connected to the q-th gate drive circuit GDCq. In an embodiment, as shown... Figure 9 As shown, in addition to the m-th compensation gate line GCm and the (m+1)-th compensation gate line GCm+1, the j-th initialization gate line GIj and the (j+1)-th initialization gate line GIj+1 can also be connected to the q-th gate drive circuit GDCq. The m-th compensation gate line GCm, the (m+1)-th compensation gate line GCm+1, the j-th initialization gate line GIj, and the (j+1)-th initialization gate line GIj+1 can be driven simultaneously by the q-th gate drive circuit GDCq. Here, q is a positive integer greater than k, and j is a positive integer greater than m+1.

[0197] In an embodiment, such as Figure 9 As shown, the first part GCam of the m-th compensation gate line GCm and the first part GCam+1 of the (m+1)-th compensation gate line GCm+1 can be connected to the q-th gate drive circuit GDCq on one side of the peripheral region PA and can be driven simultaneously. The second part GCbm of the m-th compensation gate line GCm and the second part GCbm+1 of the (m+1)-th compensation gate line GCm+1 can be connected to the q-th gate drive circuit GDCq on the other side of the peripheral region PA and can be driven simultaneously.

[0198] According to an embodiment, the (i+1)th pixel row can be a pixel row preceding the nth pixel row. That is, i can be n-2. In such an embodiment, the nth initialization gate line GIn, the (n+1)th initialization gate line GIn+1, the ith compensation gate line GCI, and the (i+1)th compensation gate line GCI+1 can be simultaneously driven by the (k-1)th gate drive circuit. That is, p can be k-1.

[0199] According to an embodiment, the m-th pixel row can be a pixel row adjacent to or immediately following the (n+1)-th pixel row. That is, m can be n+2. In such an embodiment, the j-th pixel row can be a pixel row adjacent to or immediately following the (m+1)-th pixel row. That is, j can be m+2. In such an embodiment, the m-th compensation gate line GCm, the (m+1)-th compensation gate line GCm+1, the j-th initialization gate line GIj, and the (j+1)-th initialization gate line GIj+1 can be simultaneously driven by the (k+1)-th gate driving circuit. That is, q can be k+1.

[0200] Please refer to later Figure 10 The driving timing of pixel PX is described in more detail when the (i+1)th pixel row is the pixel row preceding the nth pixel row and the mth pixel row is the pixel row adjacent to the (n+1)th pixel row.

[0201] According to an embodiment, an even number of pixel rows can be located between the (i+1)th pixel row and the nth pixel row. In one embodiment, for example, two pixel rows can be located between the (i+1)th pixel row and the nth pixel row. That is, i can be n-4. In such an embodiment, the nth initialization gate line GIn, the (n+1)th initialization gate line GIn+1, the ith compensation gate line GCI, and the (i+1)th compensation gate line GCI+1 can be simultaneously driven by the (k-2)th gate drive circuit. That is, p can be k-2.

[0202] According to an embodiment, an even number of pixel rows can be located between the m-th pixel row and the (n+1)-th pixel row. In one embodiment, for example, two pixel rows can be located between the m-th pixel row and the (n+1)-th pixel row. That is, m can be n+4. In such an embodiment, an even number of pixel rows can be located between the j-th pixel row and the (m+1)-th pixel row. In one embodiment, for example, two pixel rows can be located between the j-th pixel row and the (m+1)-th pixel row. That is, j can be m+4. In such an embodiment, the m-th compensation gate line GCm, the (m+1)-th compensation gate line GCm+1, the j-th initialization gate line GIj, and the (j+1)-th initialization gate line GIj+1 can be simultaneously driven by the (k+2)-th gate driving circuit. That is, q can be k+2.

[0203] Please refer to later Figure 11 The driving timing of pixel PX is described in more detail when the even-numbered pixel rows are between the (i+1)th and (n)th pixel rows and the even-numbered pixel rows are between the (m)th and (n+1)th pixel rows.

[0204] According to an embodiment, m+1 can be equal to 2k. One gate drive circuit GDC can drive a total of two initialization gate lines GI, as described later. Figure 10 and Figure 11 As shown, the on-time of the initial gate line GI can begin earlier than the on-time of the compensation gate line GC. Therefore, when referring to the order in which the gate drive circuit GDC is arranged based on the initial gate line GI, the two initial gate lines GI are connected to one gate drive circuit GDC. Therefore, m+1 can be equal to 2k.

[0205] Figure 10 and Figure 11 This is a signal timing diagram illustrating a method for driving multiple pixels according to an embodiment. Specifically, Figure 10 Is Figure 9 The signal timing diagram shows the case where the (i+1)th pixel row is the pixel row preceding the nth pixel row, and the mth pixel row is the pixel row adjacent to or immediately following the (n+1)th pixel row. Figure 11 Is Figure 9 The signal timing diagram for the case where an even number of pixel rows are between the (i+1)th and (n)th pixel rows and between the (m)th and (n+1)th pixel rows.

[0206] Reference Figure 10 and Figure 11 During the cutoff duration (or data programming period) of the transmit control signal EM[n / n+1] transmitted to the nth transmit control line EMn and the (n+1)th transmit control line EMn+1 respectively, the initialization signal GI[n / n+1] transmitted to the nth initialization gate line GIn and the (n+1)th initialization gate line GIn+1 respectively, the compensation signal GC[n / n+1] transmitted to the nth compensation gate line GCn and the (n+1)th compensation gate line GCn+1 respectively, and the scan signals GW[n] and GW[n+1] transmitted to the nth scan line GWn and the (n+1)th scan line GWn+1 respectively can continue.

[0207] The on-time duration of the initialization signals GI[n / n+1] transmitted to the nth initialization gate line GIn and the (n+1)th initialization gate line GIn+1, respectively, corresponds to the initialization signal being at a high level. Similarly, the on-time duration of the compensation signals GC[n / n+1] transmitted to the nth compensation gate line GCn and the (n+1)th compensation gate line GCn+1, respectively, corresponds to the compensation signal being at a high level. Likewise, the on-time duration of the scan signals GW[n] and GW[n+1] transmitted to the nth scan line GWn and the (n+1)th scan line GWn+1, respectively, corresponds to the scan signal being at a low level. (Refer to the above.) Figure 8As described, the initialization signal Sgi can be applied to the gate initialization thin-film transistor T4, the compensation signal Sgc can be applied to the compensation thin-film transistor T3, and the scan signal Sgw can be applied to the scan thin-film transistor T2. In such an embodiment, the compensation thin-film transistor T3 and the gate initialization thin-film transistor T4 can be NMOS, and the scan thin-film transistor T2 can be PMOS. Therefore, the conduction duration of the initialization signal can correspond to the initialization signal being at a high level, the conduction duration of the compensation signal can correspond to the compensation signal being at a high level, and the conduction duration of the scan signal can correspond to the scan signal being at a low level.

[0208] According to an embodiment, high levels of initialization signals GI[n / n+1] transmitted to the nth initialization gate line GIn and the (n+1)th initialization gate line GIn+1, respectively, and high levels of compensation signals GC[n / n+1] transmitted to the nth compensation gate line GCn and the (n+1)th compensation gate line GCn+1, respectively, can be provided sequentially.

[0209] In one embodiment, for example, when the (i+1)th pixel row is a pixel row preceding the nth pixel row and the mth pixel row is a pixel row adjacent to or immediately following the (n+1)th pixel row, such as Figure 10 As shown, a high-level initialization signal and a high-level compensation signal can be provided continuously. That is, the on-time of the compensation signal can continue (or begin) immediately after the on-time of the initialization signal. In other words, the falling edge of the initialization signal can correspond to the rising edge of the compensation signal.

[0210] In an optional embodiment, when an even number of pixel rows are between the (i+1)th and nth pixel rows and between the mth and (n+1)th pixel rows, as follows: Figure 11 As shown, the cutoff duration can be set between the high level of the initialization signal and the high level of the compensation signal. That is, the on-duration of the compensation signal can begin after the on-duration of the initialization signal and at least one ring duration of the initialization signal. In other words, the falling edge of the initialization signal may not correspond to the rising edge of the compensation signal.

[0211] When the compensation signals GC[n / n+1] transmitted to the nth compensation gate line GCn and the (n+1)th compensation gate line GCn+1 are in the on-duration, the signals GW[n] transmitted to the nth scan line GWn and GW[n+1] transmitted to the (n+1)th scan line GWn+1 can be in the on-duration.

[0212] According to the embodiments, such as Figure 10 and Figure 11As shown, the conduction duration t1 of the compensation signal can be equal to or greater than twice the conduction duration t2 of the signal transmitted to the nth scan line GWn. The conduction duration t1 of the compensation signal can be equal to or greater than twice the conduction duration t3 of the signal transmitted to the (n+1)th scan line GWn+1. The conduction duration t1 of the compensation signal can be equal to or greater than the sum of the conduction duration t2 of the signal transmitted to the nth scan line GWn and the conduction duration t3 of the signal transmitted to the (n+1)th scan line GWn+1.

[0213] The features described above for the nth emitter control line EMn and the (n+1)th emitter control line EMn+1, the nth initialization gate line GIn and the (n+1)th initialization gate line GIn+1, the nth compensation gate line GCn and the (n+1)th compensation gate line GCn+1, and the nth scan line GWn and the (n+1)th scan line GWn+1 can be applied to the mth emitter control line EMm and the (m+1)th emitter control line EMm+1, the mth initialization gate line Gim and the (m+1)th initialization gate line Gim+1, the mth compensation gate line GCm and the (m+1)th compensation gate line GCm+1, and the mth scan line GWm and the (m+1)th scan line GWm+1.

[0214] However, the cutoff duration of the transmit control signal EM[m / m+1] transmitted to the m-th transmit control line EMm and the (m+1)-th transmit control line EMm+1 can continue after the cutoff duration of the transmit control signal EM[n / n+1] transmitted to the n-th transmit control line EMn and the (n+1)-th transmit control line EMn+1. The on-time of the initialization signal GI[m / m+1] transmitted to the m-th initialization gate line Gim and the (m+1)-th initialization gate line Gim+1 can continue after the on-time of the initialization signal GI[n / n+1] transmitted to the n-th initialization gate line GIn and the (n+1)-th initialization gate line GIn+1. The on-time of the compensation signal GC[m / m+1] transmitted to the m-th compensation gate line GCm and the (m+1)-th compensation gate line GCm+1 can continue after the on-time of the compensation signal GC[n / n+1] transmitted to the n-th compensation gate line GCn and the (n+1)-th compensation gate line GCn+1. The conduction duration of the scan signals GW[m] and GW[m+1] transmitted to the m-th scan line GWm and the (m+1)-th scan line GWm+1 can continue after the conduction duration of the scan signals GW[n] and GW[n+1] transmitted to the n-th scan line GWn and the (n+1)-th scan line GWn+1.

[0215] According to the embodiments, such as Figure 10 and Figure 11As shown, the conduction duration of the compensation signal GC[n / n+1] transmitted to the nth compensation gate line GCn and the (n+1)th compensation gate line GCn+1 can be substantially the same as the conduction duration of the initialization signal GI[m / m+1] transmitted to the mth initialization gate line GIM and the (m+1)th initialization gate line GIM+1. In such an embodiment, as described above regarding... Figure 9 As described, since the nth compensation gate line GCn and the (n+1)th compensation gate line GCn+1, as well as the mth initialization gate line Gim and the (m+1)th initialization gate line Gim+1, are driven simultaneously by the kth gate drive circuit GDCk, the conduction duration of each signal can be substantially the same.

[0216] Figure 12 and Figure 13 It is along Figure 9 A cross-sectional view of the display device taken by line II-II'. Specifically, Figure 12 and Figure 13 It is a cross-sectional view of a portion of the display area DA and a portion of the non-display area NDA.

[0217] Reference Figure 12 and Figure 13 In an embodiment, the first scan connection line SCL1 may include a first scan connection electrode SCL1a and a second scan connection electrode SCL1b. The first scan connection electrode SCL1a can make the nth scan line GWn ( Figure 5 The first part of GWan () Figure 9 Electrically connected to the nth scan line GWn ( Figure 5 The second part of GWbn () Figure 9 The second scan connection electrode SCL1b can electrically connect the first part GWan of the nth scan line GWn to the second part GWbn of the nth scan line GWn. For example... Figure 12 and Figure 13 As shown, the first scan connection electrode SCL1a and the second scan connection electrode SCL1b can be stacked on top of each other. Here, when the two elements of the display device are stacked on top of each other, the two elements are stacked on top of each other in a direction parallel to the z-axis (hereinafter referred to as the z-axis direction) or thickness direction of the display device or its substrate 100.

[0218] The features of the first scan connection line SCL1 described above can be applied to the second scan connection line SCL2 and the third scan connection line SCL3. Figure 9 ) and the fourth scan connection line SCL4 ( Figure 9 In one embodiment, for example, the second scan connection line SCL2 may include a third scan connection electrode SCL2a and a fourth scan connection electrode SCL2b. The third scan connection electrode SCL2a can make the (n+1)th scan line GWn+1 ( Figure 5 The first part of GWan+1 () Figure 9 Electrically connected to the (n+1)th scan line GWn+1 ( Figure 5 The second part of GWbn+1 () Figure 9 The fourth scan connection electrode SCL2b can electrically connect the first part GWan+1 of the (n+1)th scan line GWn+1 to the second part GWbn+1 of the (n+1)th scan line GWn+1. For example... Figure 12 and Figure 13 As shown, the third scan connection electrode SCL2a and the fourth scan connection electrode SCL2b can be stacked on top of each other.

[0219] In the following text, reference will be made to Figure 12 and Figure 13 The construction of the stacked structure included in the display device will be described in more detail. The positional relationship between the first gate connection line GCL1, the first scan connection line SCL1, the third gate connection line GCL3, and the second scan connection line SCL2 will be described.

[0220] In embodiments, the display device may include a substrate 100 comprising a glass material, a ceramic material, a metallic material, or a flexible or bendable material. In embodiments where the substrate 100 is flexible or bendable, the substrate 100 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate.

[0221] The substrate 100 may have a single-layer or multi-layer structure comprising at least one material selected from the above-described materials. In embodiments where the substrate 100 has a multi-layer structure, the substrate 100 may further include an inorganic layer. According to embodiments, the substrate 100 may have an organic / inorganic / organic structure.

[0222] In one embodiment, a buffer layer 111 may be disposed on a substrate 100. In another embodiment, a barrier layer (not shown) may also be included between the substrate 100 and the buffer layer 111. The barrier layer prevents or minimizes the penetration of impurities from the substrate 100 into the first semiconductor layer Act1 and the second semiconductor layer Act2. The barrier layer may comprise inorganic materials such as oxides or nitrides, organic materials, or organic / inorganic composite materials, and may have a single-layer or multi-layer structure comprising both inorganic and organic materials.

[0223] In an embodiment, a channel bottom electrode (not shown) may be located between the barrier layer and the buffer layer 111. The channel bottom electrode may comprise a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may comprise a single layer or multiple layers containing at least one of the aforementioned materials. In one embodiment, for example, the channel bottom electrode may have a Ti / Al / Ti multilayer structure.

[0224] The bottom electrode of the channel can be stacked with the channel region C1 of the first semiconductor layer Act1. The bottom electrode of the channel can be connected to the reference above. Figure 8 The driving voltage line PL is described and configured such that a first driving voltage ELVDD is applied thereto. In an embodiment, pixel circuits including NMOS and PMOS are driven by the bottom electrode of the channel to which the first driving voltage ELVDD is applied, thereby preventing the accumulation of unwanted charges in the first semiconductor layer Act1. As a result, the characteristics of the first thin-film transistor TFT1, which includes the first semiconductor layer Act1, can be stably maintained.

[0225] The first semiconductor layer Act1 may be on the buffer layer 111. The first semiconductor layer Act1 may include amorphous silicon or polycrystalline silicon. The first semiconductor layer Act1 may include a channel region C1 and a source region S1 and a drain region D1 on the opposite side of the channel region C1. The first semiconductor layer Act1 may include a single layer or multiple layers.

[0226] In an embodiment, the first gate insulating layer 113 and the second gate insulating layer 115 may be disposed or stacked on the substrate 100 to cover the first semiconductor layer Act1. The first gate insulating layer 113 and the second gate insulating layer 115 may comprise materials selected from silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO) x At least one of ZnO. x It can be ZnO or ZnO2.

[0227] In an embodiment, the first conductive layer CL1 may be on the first gate insulating layer 113. The first conductive layer CL1 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers comprising at least one of the above materials. In one embodiment, for example, the first conductive layer CL1 may have a Ti / Al / Ti multilayer structure.

[0228] The first conductive layer CL1 may include a first gate electrode G1, a lower electrode CE1 of a storage capacitor Cst, a first scan connection electrode SCL1a, and a third scan connection electrode SCL2a, all superimposed on at least a portion of the first semiconductor layer Act1. The first gate electrode G1 may be superimposed on the channel region C1 of the first semiconductor layer Act1. The first gate electrode G1 and the lower electrode CE1 of the storage capacitor Cst may be located in the display area DA, while the first scan connection electrode SCL1a and the third scan connection electrode SCL2a may be located in the non-display area NDA.

[0229] In an embodiment, the second conductive layer CL2 may be on the second gate insulating layer 115. The second conductive layer CL2 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers comprising at least one of the above materials. In one embodiment, for example, the second conductive layer CL2 may have a Ti / Al / Ti multilayer structure.

[0230] The second conductive layer CL2 may include a lower gate electrode G2a of the second gate electrode G2, an upper electrode CE2 of the storage capacitor Cst, a first gate connection line GCL1, and a third gate connection line GCL3. The lower gate electrode G2a defined by the second gate electrode G2 and the upper electrode CE2 of the storage capacitor Cst may be in the display area DA, while the first gate connection line GCL1 and the third gate connection line GCL3 may be in the non-display area NDA. The upper electrode CE2 of the storage capacitor Cst may be superimposed on at least a portion of the first gate electrode G1.

[0231] The lower gate electrode G2a of the second gate electrode G2 can be arranged to be stacked with the second semiconductor layer Act2, which includes an oxide semiconductor material. In such an embodiment, because the second semiconductor layer Act2, which includes an oxide semiconductor material, is susceptible to light, the lower gate electrode G2a can prevent the device characteristics of the second thin-film transistor TFT2, which includes an oxide semiconductor material, from being altered by photocurrents induced in the second semiconductor layer Act2 by external light incident from the substrate 100.

[0232] Figure 12 An embodiment is shown where the first scan connection electrode SCL1a and the third scan connection electrode SCL2a are in the same layer or directly on the same layer as the first gate electrode G1, and the first gate connection line GCL1 and the third gate connection line GCL3 are in the same layer or directly on the same layer as the upper electrode CE2, but this is not limited to this and can be modified in different ways.

[0233] In an alternative embodiment, for example, such as Figure 13As shown, the first gate connection line GCL1 and the third gate connection line GCL3 can be in the same layer as the first gate electrode G1 or directly on the same layer, and the first scan connection electrode SCL1a and the third scan connection electrode SCL2a can be in the same layer as the upper electrode CE2 or directly on the same layer. In such an embodiment, the first conductive layer CL1 may include the first gate connection line GCL1 and the third gate connection line GCL3, and the second conductive layer CL2 may include the first scan connection electrode SCL1a and the third scan connection electrode SCL2a.

[0234] According to an embodiment, the storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2. In an embodiment, as... Figure 12 and Figure 13 As shown, the storage capacitor Cst may be stacked with the first thin-film transistor TFT1. In one embodiment, for example, the first gate electrode G1 of the first thin-film transistor TFT1 may define or serve as the lower electrode CE1 of the storage capacitor Cst. Alternatively, the storage capacitor Cst may not be stacked with the first thin-film transistor TFT1 and may exist independently.

[0235] The upper electrode CE2 and lower electrode CE1 of the storage capacitor Cst are stacked, with a second gate insulating layer 115 between them to form a capacitor. In such an embodiment, the second gate insulating layer 115 can serve as the dielectric layer of the storage capacitor Cst.

[0236] In one embodiment, the first interlayer insulating layer 117 may be on the second gate insulating layer 115 to cover the upper electrode CE2 of the storage capacitor Cst. The first interlayer insulating layer 117 may include materials selected from silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO) x At least one of ZnO. x It can be ZnO or ZnO2.

[0237] The second semiconductor layer Act2 may be located on the first interlayer insulating layer 117. The second semiconductor layer Act2 may include an oxide semiconductor material. The second semiconductor layer Act2 may include an oxide of at least one material selected from indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and zinc (Zn).

[0238] In one embodiment, for example, the second semiconductor layer Act2 may include an InSnZnO (“ITZO”) semiconductor layer, an InGaZnO (“IGZO”) semiconductor layer, etc. In such an embodiment, because oxide semiconductors have a wide bandgap (approximately 3.1 electron volts (eV)), high carrier mobility, and low leakage current, the voltage drop is not large even with long drive times. Therefore, even during low-frequency drive, the brightness variation based on voltage drop is not significant.

[0239] The second semiconductor layer Act2 may include a channel region C2 and a source region S2 and a drain region D2 on the opposite side of the channel region C2.

[0240] In this embodiment, the third gate insulating layer 119 may be located on the second semiconductor layer Act2. The third gate insulating layer 119 may include materials selected from silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO) x At least one of the following: ZnO x It can be ZnO or ZnO2.

[0241] Figure 12 and Figure 13 An embodiment is shown in which the third gate insulating layer 119 covers the entire surface of the substrate 100 to cover the second semiconductor layer Act2. However, in an alternative embodiment, the third gate insulating layer 119 may be patterned to overlap with a portion of the second semiconductor layer Act2. In one embodiment, for example, the third gate insulating layer 119 may be patterned to overlap with the channel region C2 of the second semiconductor layer Act2.

[0242] In an embodiment, the third conductive layer CL3 may be on the third gate insulating layer 119. The third conductive layer CL3 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers comprising at least one of the above materials. In one embodiment, for example, the third conductive layer CL3 may have a Ti / Al / Ti multilayer structure.

[0243] The third conductive layer CL3 may include an upper gate electrode G2b of the second gate electrode G2 that is superimposed on at least a portion of the second semiconductor layer Act2, a second scan connection electrode SCL1b, and a fourth scan connection electrode SCL2b. The upper gate electrode G2b of the second gate electrode G2 may be superimposed on the channel region C2 of the second semiconductor layer Act2.

[0244] According to an embodiment, the second gate electrode G2 may include a lower gate electrode G2a and an upper gate electrode G2b. The second gate electrode G2 may be multiple lines. Figure 12 and Figure 13 The second gate electrode G2 is shown to be multiple lines, but in an alternative embodiment, the second gate electrode G2 may be a single line. In one embodiment, for example, either the lower gate electrode G2a or the upper gate electrode G2b may be omitted.

[0245] According to an embodiment, the first scan connection line SCL1 may include a first scan connection electrode SCL1a and a second scan connection electrode SCL1b, and the second scan connection line SCL2 may include a third scan connection electrode SCL2a and a fourth scan connection electrode SCL2b. Each of the first scan connection line SCL1 and the second scan connection line SCL2 may be multiple lines. The load can be reduced by constructing each of the first scan connection line SCL1 and the second scan connection line SCL2 as multiple lines.

[0246] Figure 12 and Figure 13 An embodiment is shown where the first scan connection line SCL1 and the second scan connection line SCL2 are multiple lines and the first gate connection line GCL1 and the third gate connection line GCL3 are single lines. However, in an alternative embodiment, the first scan connection line SCL1 and the second scan connection line SCL2 may be single lines and the first gate connection line GCL1 and the third gate connection line GCL3 may be multiple lines. According to the alternative embodiment, the first scan connection line SCL1, the second scan connection line SCL2, the first gate connection line GCL1, and the third gate connection line GCL3 may be multiple lines or a single line.

[0247] According to the embodiments, such as Figure 12 and Figure 13 As shown, the first gate connection line GCL1 and the first scan connection line SCL1, which are adjacent to each other, can be in different layers or directly on different layers. In such an embodiment, the distance between the first gate connection line GCL1 and the first scan connection line SCL1 in a direction perpendicular to the z-axis (e.g., the horizontal direction of the substrate 100) can be smaller than the distance when the first gate connection line GCL1 and the first scan connection line SCL1 are in the same layer or directly on the same layer. Therefore, the area occupied by the first gate connection line GCL1 and the first scan connection line SCL1 can be reduced. The area of ​​the non-display region NDA in which the first gate connection line GCL1 and the first scan connection line SCL1 are arranged can be reduced. The features of the first gate connection line GCL1 and the first scan connection line SCL1 described above can be applied to the third gate connection line GCL3 and the second scan connection line SCL2.

[0248] According to an embodiment, the first thin-film transistor TFT1 can be compared with the above reference. Figure 8 The described driving thin-film transistor T1 corresponds to this. Besides the first thin-film transistor TFT1 being stacked with the upper electrode CE2, the first thin-film transistor TFT1 can correspond to the scanning thin-film transistor T2, the operation control thin-film transistor T5, the emission control thin-film transistor T6, or the anode initialization thin-film transistor T7. In such an embodiment, the first semiconductor layer Act1 may include the active region of the driving thin-film transistor T1, the active region of the scanning thin-film transistor T2, the active region of the operation control thin-film transistor T5, the active region of the emission control thin-film transistor T6, or the active region of the anode initialization thin-film transistor T7.

[0249] According to an embodiment, the second thin-film transistor TFT2 can be compared with the above-mentioned reference. Figure 8 The described compensation thin-film transistor T3 or gate initialization thin-film transistor T4 correspond to this. In such an embodiment, the second semiconductor layer Act2 may include the active region of the compensation thin-film transistor T3 or the active region of the gate initialization thin-film transistor T4.

[0250] In an embodiment, the second interlayer insulating layer 121 may be on the third gate insulating layer 119 to cover the third conductive layer CL3. The second interlayer insulating layer 121 may include materials selected from silicon oxide (SiO2) and silicon nitride (SiN). x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), and zinc oxide (ZnO) x At least one of the following: ZnO x It can be ZnO or ZnO2.

[0251] In an embodiment, the first connecting electrode layer CM1 may be on the second interlayer insulating layer 121. The first connecting electrode layer CM1 may include a conductive material such as molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., and may include a single layer or multiple layers comprising at least one of the above materials. In one embodiment, for example, the first connecting electrode layer CM1 may have a Ti / Al / Ti multilayer structure.

[0252] The first connection electrode layer CM1 can be connected to at least one of the source region S1 and the drain region D1 selected from the first semiconductor layer Act1. The first connection electrode layer CM1 can be connected to at least one of the source region S2 and the drain region D2 selected from the second semiconductor layer Act2.

[0253] The first connecting electrode layer CM1 may be covered with an inorganic protective layer (not shown). The inorganic protective layer may include materials selected from silicon nitride (SiN). x ) and silicon dioxide (SiO) xA single or multiple layers of at least one of the following: . The inorganic protective layer may cover and protect some of the wires on the second interlayer insulation layer 121.

[0254] In an embodiment, the planarization layer 123 may be on the second interlayer insulating layer 121, and the light-emitting element 200 may be on the planarization layer 123.

[0255] Planarization layer 123 may comprise a single layer or multiple layers containing organic material and may provide a flat upper surface. Planarization layer 123 may comprise, for example, at least one selected from general polymers (e.g., benzocyclobutene (“BCB”), polyimide, hexamethyldisiloxane (“HMDSO”), polymethyl methacrylate (“PMMA”), or polystyrene (“PS”)), polymer derivatives having phenolic groups, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorinated polymers, p-xylene polymers, and vinyl alcohol polymers).

[0256] In an embodiment, the planarization layer 123 may be provided in multiple layers and may include a first planarization layer 123a and a second planarization layer 123b. In such an embodiment, a second connection electrode layer CM2 may be located between the first planarization layer 123a and the second planarization layer 123b. The second connection electrode layer CM2 may be connected to the first connection electrode layer CM1 through a contact hole defined in the first planarization layer 123a, and may electrically connect the light-emitting element 200 to the first thin-film transistor TFT1.

[0257] The light-emitting element 200 can be on the planarization layer 123. The light-emitting element 200 may include a pixel electrode 210, an intermediate layer 220 and a counter electrode 230, wherein the intermediate layer 220 includes an organic emitting layer.

[0258] Pixel electrode 210 may include a (semi-)transmissive electrode or a reflective electrode. According to an embodiment, pixel electrode 210 may include a reflective layer and a transparent or semi-transparent electrode layer on the reflective layer. The reflective layer may include at least one selected from Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and their compounds or mixtures. The transparent or semi-transparent electrode layer may include at least one selected from indium tin oxide (“ITO”), indium zinc oxide (“IZO”), zinc oxide (ZnO), indium oxide (In₂O₃), indium gallium oxide (“IGO”), and zinc aluminum oxide (“AZO”). According to an embodiment, pixel electrode 210 may include, for example, ITO / Ag / ITO.

[0259] In one embodiment, the pixel defining layer 125 may be on the planarization layer 123. In such an embodiment, the pixel defining layer 125 may prevent arcing or the like from occurring at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the edge of the portion of the counter electrode 230 on the pixel electrode 210.

[0260] The pixel-defining layer 125 can be formed by spin coating or the like using at least one organic insulating material selected from polyimide, polyamide, acrylic resin, benzocyclobutene and phenolic resin.

[0261] Intermediate layer 220 may be located within an opening defined in pixel defining layer 125. Intermediate layer 220 may include an organic emitting layer. The organic emitting layer may include an organic material comprising a fluorescent or phosphorescent material emitting red, green, blue, or white light. The organic emitting layer may include a low molecular weight organic material or a high molecular weight organic material. In embodiments, hole transport layer (“HTL”), hole injection layer (“HIL”), electron transport layer (“ETL”), electron injection layer (“EIL”), etc., may optionally be arranged below and above the organic emitting layer.

[0262] The intermediate layer 220 may be arranged to correspond to each pixel electrode 210. However, this disclosure is not limited thereto. The intermediate layer 220 may be modified in different ways. In one embodiment, for example, the intermediate layer 220 may include a monolithic layer covering a plurality of pixel electrodes 210.

[0263] Counter electrode 230 may include a transmissive electrode or a reflective electrode. According to embodiments, counter electrode 230 may include a transparent electrode or a translucent electrode, and may include a metal thin film with low work function, such as Li, Ca, LiF, Al, Ag, Mg, and any compounds or mixtures thereof, and a multilayer structure material having a structure such as LiF / Ca or LiF / Al. In embodiments, a transparent conductive oxide (“TCO”) layer such as ITO, IZO, ZnO, or In2O3 may also be present on the metal thin film. Counter electrode 230 may extend throughout the display area DA and may extend throughout the intermediate layer 220 and the pixel defining layer 125. Counter electrode 230 may be integrally formed in a plurality of light-emitting elements 200 to correspond to a plurality of pixel electrodes 210.

[0264] The light-emitting element 200 may be covered by an encapsulation layer (not shown). The encapsulation layer may include at least one organic encapsulation layer and at least one inorganic encapsulation layer.

[0265] The inorganic encapsulation layer may include at least one inorganic material selected from alumina, titanium dioxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The first and second inorganic encapsulation layers may include a single layer or multiple layers comprising at least one of the materials selected above. The organic encapsulation layer may include polymeric materials. Polymeric materials may include acrylic resins (such as polymethyl methacrylate or polyacrylic acid), epoxy resins, polyimides, and polyethylene. According to an embodiment, the organic encapsulation layer may include an acrylate polymer.

[0266] The features of the first gate connection line GCL1, the first scan connection line SCL1, the third gate connection line GCL3, and the second scan connection line SCL2 described above can be applied to the second gate connection line GCL2. Figure 9 ), third scan connection line SCL3 ( Figure 9 ), fourth gate connection line GCL4 ( Figure 9 ) and the fourth scan connection line SCL4 ( Figure 9 ).

[0267] This disclosure primarily describes embodiments of the display device, but is not limited thereto. It will be understood that, for example, methods of manufacturing the display device also fall within the scope of this disclosure.

[0268] According to one or more embodiments, a display device in which the non-display area is reduced can be implemented.

[0269] The invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0270] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, the display device comprising: A substrate defining a transmissive region, a display region, a non-display region, and a peripheral region therein, the display region surrounding at least a portion of the transmissive region, the non-display region between the transmissive region and the display region, and the peripheral region outside the display region; Multiple pixels are arranged in pixel rows and pixel columns in the display area; Multiple initialization gate lines and multiple compensation gate lines extend along the pixel column, respectively; Multiple gate driving circuits are disposed in the peripheral region and arranged in the direction of the pixel column; as well as Multiple gate connection lines are disposed in the non-display area. Specifically, the k-th gate driving circuit among the plurality of gate driving circuits simultaneously drives the m-th initialization gate line and the (m+1)-th initialization gate line among the plurality of initialization gate lines, as well as the n-th compensation gate line and the (n+1)-th compensation gate line among the plurality of compensation gate lines, so that the signals transmitted through the m-th initialization gate line, the (m+1)-th initialization gate line, the n-th compensation gate line, and the (n+1)-th compensation gate line have the same timing. Each of the m-th initialization gate line and the (m+1)-th initialization gate line, and each of the n-th compensation gate line and the (n+1)-th compensation gate line, includes a first portion and a second portion physically separated from each other by the transmission region. The first portion and the second portion of each of the nth and (n+1)th compensation gate lines are electrically connected to each other via the first gate connection line among the plurality of gate connection lines. Where k and n are positive integers, and m is a positive integer greater than n+1.

2. The display device according to claim 1, wherein, An even number of pixel rows are between the (n+1)th pixel row and the mth pixel row.

3. The display device according to claim 2, wherein, The first portion and the second portion of each of the m-th initial gate line and the (m+1)-th initial gate line are electrically connected to each other via the second gate connection line among the plurality of gate connection lines.

4. The display device according to claim 2, wherein, The first gate connection line electrically connects the first portion and the second portion of each of the m-th initialization gate line and the (m+1)-th initialization gate line to each other.

5. The display device according to claim 1, wherein, The two pixel rows are between the (n+1)th pixel row and the mth pixel row. The nth and (n+1)th initialization gate lines among the plurality of initialization gate lines are simultaneously driven by the (k-2)th gate driving circuit among the plurality of gate driving circuits, and The m-th and m+1-th compensation gate lines among the plurality of compensation gate lines are simultaneously driven by the k+2-th gate driving circuit among the plurality of gate driving circuits.

6. The display device according to claim 1, wherein, The m-th pixel row is the pixel row adjacent to the (n+1)-th pixel row.

7. The display device according to claim 6, wherein, The first gate connection line electrically connects the first portion and the second portion of each of the m-th initialization gate line and the (m+1)-th initialization gate line to each other.

8. The display device according to claim 6, wherein, The first portion and the second portion of each of the m-th initial gate line and the (m+1)-th initial gate line are electrically connected to each other via the second gate connection line among the plurality of gate connection lines.

9. The display device according to claim 1, wherein, The nth and (n+1)th initialization gate lines among the plurality of initialization gate lines are simultaneously driven by the (k-1)th gate driving circuit among the plurality of gate driving circuits, and The m-th and m+1-th compensation gate lines among the plurality of compensation gate lines are simultaneously driven by the k+1-th gate driving circuit among the plurality of gate driving circuits.

10. The display device according to claim 1, wherein, The m+1 is equal to 2k.

11. The display device according to claim 1, wherein, The k-th gate driving circuit includes: A side-mounted gate driving circuit is disposed on one side of the peripheral region, wherein the side-mounted gate driving circuit outputs a first gate signal to the first portion of each of the m-th initialization gate line and the (m+1)-th initialization gate line, and to the first portion of each of the n-th compensation gate line and the (n+1)-th compensation gate line; and Another gate driving circuit is disposed on the other side of the peripheral region, wherein the other gate driving circuit outputs a second gate signal to the second portion of each of the m-th initialization gate line and the (m+1)-th initialization gate line and the second portion of each of the n-th compensation gate line and the (n+1)-th compensation gate line.

12. The display device according to claim 1, further comprising: Multiple scan lines extend along the pixel row, respectively; Multiple scan driving circuits are arranged in the column direction in the peripheral region, wherein the multiple scan driving circuits sequentially drive the multiple scan lines; and Multiple scan connection lines are located in the non-display area. Each of the nth and (n+1)th scan lines comprises a first portion and a second portion that are physically separated from each other by the transmission region. The first portion and the second portion of the nth scan line are electrically connected to each other through the first scan connection line among the plurality of scan connection lines, and The first portion and the second portion of the (n+1)th scan line are electrically connected to each other via the second scan connection line among the plurality of scan connection lines.

13. The display device according to claim 12, wherein, The first scan connection line includes: A first scan connection electrode is used to electrically connect the first portion of the nth scan line to the second portion of the nth scan line; and The second scan connection electrode electrically connects the first portion of the nth scan line to the second portion of the nth scan line.

14. The display device according to claim 13, further comprising: A first conductive layer, including the first scan connection electrode; A semiconductor layer is disposed on the first conductive layer; as well as A second conductive layer is disposed on the semiconductor layer and includes the second scan connection electrode.

15. The display device according to claim 1, further comprising: Multiple emission control lines extend along the pixel row, respectively; as well as Multiple emission control drive circuits are disposed in the peripheral region and arranged in the direction of the pixel column. Each of the nth and (n+1)th transmission control lines comprises a first portion and a second portion that are physically separated from and electrically insulated from each other by the transmission region. The first portion of the nth transmit control line and the first portion of the (n+1)th transmit control line are simultaneously driven by a first transmit control drive circuit on one side of the peripheral region among the plurality of transmit control drive circuits, and The second portion of the nth transmission control line and the second portion of the (n+1)th transmission control line are simultaneously driven by a second transmission control drive circuit on the other side of the peripheral region among the plurality of transmission control drive circuits.

16. The display device according to claim 1, further comprising: Multiple emission control lines extend along the pixel row, respectively; Multiple emission control drive circuits are disposed in the peripheral region and arranged in the direction of the pixel column; as well as The transmission control connection cable is located in the non-display area. Each of the nth and (n+1)th transmission control lines comprises a first portion and a second portion physically separated from each other by the transmission region. The first portion and the second portion of each of the nth and (n+1)th transmit control lines are electrically connected to each other via the transmit control connection line.

17. The display device according to claim 1, wherein, Each of the plurality of pixels arranged in the nth pixel row includes: Light-emitting elements; The driving transistor controls the current flowing to the light-emitting element based on the gate-source voltage; A scanning transistor transmits a data voltage to the driving transistor in response to a scanning signal; A gate initialization transistor, in response to a signal transmitted through the nth initialization gate line of the plurality of initialization gate lines, applies an initialization voltage to the gate of the driving transistor; and A compensation transistor, in response to a signal transmitted through the nth compensation gate line, connects the drain of the driving transistor to the gate of the driving transistor.

18. The display device according to claim 17, wherein, The conductivity type of each of the gate initialization transistor and the compensation transistor is opposite to that of the scan transistor.

19. The display device according to claim 17, further comprising: The first semiconductor layer includes the active region of the scanning transistor; The second semiconductor layer includes the active region of the gate initialization transistor or the active region of the compensation transistor. as well as A conductive layer is located between the first semiconductor layer and the second semiconductor layer.

20. The display device according to claim 19, wherein, The first semiconductor layer comprises a silicon semiconductor material, and The second semiconductor layer comprises an oxide semiconductor material.

21. The display device according to claim 17, wherein, The conduction duration of the signal transmitted through the nth compensation gate line is equal to twice the conduction duration of the scan signal, or greater than twice the conduction duration of the scan signal.

22. The display device according to claim 1, wherein, The via is defined to pass through the substrate to correspond to the transmission region.

23. A display device, the display device comprising: A substrate defining a transmissive region, a display region, a non-display region, and a peripheral region therein, the display region surrounding at least a portion of the transmissive region, the non-display region between the transmissive region and the display region, and the peripheral region outside the display region; Multiple pixels are arranged in pixel rows and pixel columns in the display area; Multiple gate lines extend along the pixel row, respectively; as well as Multiple gate connection lines are disposed in the non-display area. Each of the m-th and m+1-th gate lines, as well as the n-th and n+1-th gate lines, includes a first portion and a second portion that are physically separated from each other by the transmission region. The first portion of each of the m-th gate line, the (m+1)-th gate line, the n-th gate line, and the (n+1)-th gate line is connected to each other in the peripheral region so that the signals transmitted through the first portion of each of the m-th gate line, the (m+1)-th gate line, the n-th gate line, and the (n+1)-th gate line have the same timing. The first portion and the second portion of each of the m-th gate line and the (m+1)-th gate line are electrically connected to each other via the first gate connection line among the plurality of gate connection lines. Where n is a positive integer, and m is a positive integer greater than n+1.

24. The display device according to claim 23, wherein, The first portion and the second portion of each of the nth gate line and the (n+1)th gate line are electrically connected to each other via a second gate connection line among the plurality of gate connection lines.

25. The display device according to claim 23, wherein, The first gate connection line electrically connects the first portion and the second portion of each of the nth gate line and the (n+1)th gate line to each other.

26. The display device according to claim 23, wherein, The second portion of each of the m-th gate line, the (m+1)-th gate line, the n-th gate line, and the (n+1)-th gate line is connected to each other in the peripheral region.

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