A signal sampling circuit and a semiconductor memory
CN114678056BActive Publication Date: 2026-08-28CHANGXIN MEMORY TECH INC
Patent Information
- Application Number
- CN202210294845.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-03-23
- Publication Date
- 2026-08-28
- Estimated Expiration
- 2042-03-23
AI Technical Summary
Technical Problem
这样，在CA信号采样之后，由于指令还需要进行译码处理，使得指令路径比地址路径多了用于译码的逻辑电路，造成指令信号和地址信号在到达下一级功能模块时会存在较大的时序偏差，进而导致下一级功能模块因为时序偏差出现问题
Benefits of technology
[0059]本公开实施例提供了一种信号采样电路以及半导体存储器，该信号采样电路包括输入采样电路、逻辑运算电路、指令译码电路和合并输出电路；其中，输入采样电路，用于根据第一时钟信号分别对第一片选信号和第一命令地址信号进行采样处理，得到第二片选信号和第二命令地址信号，第二命令地址信号中包括初始指令信号；逻辑运算电路，用于对第一时钟信号和第二片选信号进行逻辑运算，得到片选时钟信号；指令译码电路，用于根据片选时钟信号和第二片选信号对初始指令信号进行译码和采样处理，得到目标指令信号；合并输出电路，用于根据片选时钟信号对第二命令地址信号进行采样及输出合并处理，得到目标地址信号；其中，目标地址信号和目标指令信号之间的时序对齐。这样，基于该信号采样电路，在同一时钟周期的采样下，能够实现目标指令信号和目标地址信号的时序对齐，使得译码之后的指令信号和地址信号之间没有跟随工艺、电压、温度等变化的偏差，从而可以避免下一级功能模块因时序偏差而出现问题。
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Abstract
The embodiment of the present disclosure provides a signal sampling circuit and a semiconductor memory, the signal sampling circuit comprises: an input sampling circuit, which is used for sampling and processing a first chip select signal and a first command address signal respectively according to a first clock signal to obtain a second chip select signal and a second command address signal, and the second command address signal comprises an initial instruction signal; a logic operation circuit, which is used for performing logic operation on the first clock signal and the second chip select signal to obtain a chip select clock signal; an instruction decoding circuit, which is used for decoding and sampling the initial instruction signal according to the chip select clock signal and the second chip select signal to obtain a target instruction signal; and a merging output circuit, which is used for sampling and outputting the second command address signal according to the chip select clock signal to obtain a target address signal. In this way, the timing alignment between the target address signal and the target instruction signal can be realized.
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Citation Information
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