Semiconductor epitaxial structure and method of making same, semiconductor structure

Abstract

The application relates to a semiconductor epitaxial structure, a preparation method thereof and a semiconductor structure, and the semiconductor epitaxial structure comprises a substrate and a first transition layer, and the first transition layer is formed on the substrate; wherein the concentration of a first component of the first transition layer changes in a gradient along a thickness increasing direction, and the first component is an element of the substrate. By forming the first transition layer with the concentration of the first component changing in a gradient along the thickness increasing direction on the substrate, the first component being an element of the substrate, dislocations, pits or grain boundaries and other defects caused by lattice and thermal expansion mismatch are avoided, the thermal resistance of the epitaxial layer is effectively reduced, and the performance, reliability and service life of the semiconductor device are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor epitaxial structure and its preparation method, as well as a semiconductor structure. Background Technology

[0002] Semi-insulating silicon carbide (SiC) possesses advantages such as high thermal conductivity and high resistivity, and has a high degree of maturity in mass production, making it widely used in the fabrication of high-frequency, high-power epitaxial structures. For example, SiC remains the optimal substrate choice for epitaxial structures of gallium nitride (GaN) electron mobility transistors (HEMTs).

[0003] However, in the traditional process of growing heteroepitaxial single crystal thin films on SiC substrates, unavoidable lattice and thermal expansion mismatches lead to defects such as dislocations, pits, or grain boundaries, which increase the interfacial thermal resistance and cause the temperature of the manufactured semiconductor device to rise too quickly, seriously affecting the performance, reliability, and lifespan of the semiconductor device. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor epitaxial structure and its preparation method, as well as a semiconductor structure, that effectively reduces the thermal resistance of the epitaxial layer, in order to improve the performance, reliability, and service life of the manufactured semiconductor devices, addressing the technical problems mentioned above.

[0005] To achieve the above and other objectives, a first aspect of this application provides a semiconductor epitaxial structure, comprising:

[0006] Substrate; and

[0007] A first transition layer is formed on the substrate;

[0008] The concentration of the first component of the first transition layer varies gradient along the direction of increasing thickness, and the first component is an element of the substrate.

[0009] In the semiconductor epitaxial structure described in the above embodiments, there is a region with high initial defect density and low thermal conductivity near the interface where the epitaxial layer, such as the nucleation layer, is formed on the substrate. The thermal conductivity of this region improves with increasing nucleation layer thickness. However, since the thermal conductivity of the epitaxial layer is lower than that of the substrate, increasing the thickness of the epitaxial layer will increase the effective thermal resistance of the overall epitaxial structure. To reduce the overall thermal resistance of the epitaxial structure and obtain a thin epitaxial layer with high crystal quality and low interface disorder, a first transition layer is formed on the substrate surface. The concentration of the first component varies gradient along the direction of thickness increase. The first component is an element of the substrate, which perfectly transforms the in-plane lattice atomic configuration on the substrate into the epitaxial layer lattice within the transition range of 1-5 unit cell thickness, thereby obtaining a high-quality epitaxial layer. This effectively reduces the thermal resistance of the epitaxial layer while effectively controlling its thickness. This avoids defects such as dislocations, pits, or grain boundaries caused by lattice and thermal expansion mismatch, reduces interface thermal resistance, and improves the performance, reliability, and lifespan of the fabricated semiconductor device.

[0010] In one embodiment, the concentration of the first component in the first transition layer decreases stepwise or gradually along the direction of thickness increase, so that within the transition range of 1 unit cell to 5 unit cell thickness, the in-plane lattice atomic configuration on the substrate is perfectly transformed into the epitaxial layer lattice.

[0011] In one embodiment, the first transition layer includes a first intermediate layer and a second intermediate layer stacked sequentially, the first intermediate layer being located between the substrate and the second intermediate layer, wherein the concentration of the first component in the first intermediate layer is greater than the concentration of the first component in the second intermediate layer.

[0012] In one embodiment, the semiconductor epitaxial structure further includes a nucleation layer, a second transition layer, and a channel layer stacked sequentially, wherein the nucleation layer is located between the first transition layer and the second transition layer; wherein the concentration of the second component of the second transition layer varies gradient along the direction of increasing thickness, and the second component of the second transition layer is an element of the channel layer.

[0013] In the semiconductor epitaxial structure of the above embodiments, a second transition layer is formed on the side of the nucleation layer away from the substrate, where the concentration of the second component varies gradient along the direction of thickness increase. The second component of the second transition layer is an element of the channel layer. This allows the in-plane lattice atomic configuration of the nucleation layer to be perfectly transformed into the channel layer lattice within the transition range of 1-5 unit cell thickness, for example, 0.5 nm-1.5 nm. This avoids the need to grow a buffer layer and directly grows a high-quality channel layer, achieving a buffer-free structure design. The heat generated in the thin channel is more effectively dissipated into the substrate, effectively reducing the overall thermal resistance of the epitaxial structure and alleviating the problem of self-heating in the fabricated semiconductor device. Due to the implementation of the buffer-free structure design, this application effectively reduces the thickness of the overall epitaxial structure, reduces raw material consumption while ensuring the performance of the fabricated semiconductor device, significantly shortens the deposition time, minimizes manufacturing costs, and increases the production capacity of metal-organic chemical vapor deposition (MOCVD).

[0014] In one embodiment, the concentration of the second component in the second transition layer increases stepwise or gradually along the direction of thickness increase.

[0015] In one embodiment, the first transition layer further includes a third component, which is an element of the nucleation layer, and the concentration of the third component of the first transition layer increases stepwise or gradually along the direction of thickness increase.

[0016] In one embodiment, the second transition layer further includes a fourth component, which is an element of the nucleation layer, and the concentration of the fourth component of the second transition layer decreases stepwise or gradually along the direction of increasing thickness.

[0017] In one embodiment, the second transition layer includes a third intermediate layer and a fourth intermediate layer stacked sequentially, the third intermediate layer being located between the nucleation layer and the fourth intermediate layer, and the concentration of the second component in the third intermediate layer being less than the concentration of the second component in the fourth intermediate layer.

[0018] The second aspect of this application provides a semiconductor structure fabricated using the semiconductor epitaxial structure described in any of the embodiments of this application. This structure effectively reduces the thermal resistance of the epitaxial layer while effectively controlling the thickness of the epitaxial layer, thereby improving the performance, reliability, and lifespan of the fabricated semiconductor device.

[0019] A third aspect of this application provides a method for fabricating a semiconductor epitaxial structure, comprising:

[0020] Provide substrate;

[0021] A first transition layer is formed on the substrate, wherein the concentration of a first component of the first transition layer varies gradient along the direction of increasing thickness, and the first component is an element of the substrate.

[0022] In the semiconductor epitaxial structure fabrication method described in the above embodiments, a first transition layer is formed on the upper surface of the substrate, wherein the concentration of a first component varies gradient along the direction of thickness increase. The first component is an element of the substrate. This allows the in-plane lattice atomic configuration on the substrate to be perfectly transformed into the epitaxial layer lattice within a transition range of 1-5 unit cell thickness, thereby obtaining a high-quality epitaxial layer. This effectively reduces the thermal resistance of the epitaxial layer while effectively controlling its thickness. Consequently, defects such as dislocations, pits, or grain boundaries caused by lattice and thermal expansion mismatch are avoided, reducing interface thermal resistance and improving the performance, reliability, and lifespan of the fabricated semiconductor device. Attached Figure Description

[0023] To better describe and illustrate embodiments and / or examples of the applications disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, the embodiments and / or examples currently described, or the best mode of conduct of these applications as currently understood.

[0024] Figure 1 The diagram shown is a cross-sectional view of the semiconductor epitaxial structure provided in the first embodiment of this application.

[0025] Figure 2 The diagram shown is a cross-sectional view of the semiconductor epitaxial structure provided in the second embodiment of this application.

[0026] Figure 3 The diagram shown is a cross-sectional view of the semiconductor epitaxial structure provided in the third embodiment of this application.

[0027] Figure 4 The diagram shown is a cross-sectional view of the semiconductor epitaxial structure provided in the fourth embodiment of this application.

[0028] Figure 5 The diagram shown is a cross-sectional view of the semiconductor epitaxial structure provided in the fifth embodiment of this application.

[0029] Figure 6 The diagram shown is a cross-sectional view of the semiconductor epitaxial structure provided in the sixth embodiment of this application.

[0030] Figure 7 The diagram shows a process flow chart of a semiconductor epitaxial structure fabrication method provided in one embodiment of this application.

[0031] Figure 8This is a schematic diagram of a method for fabricating a semiconductor epitaxial structure provided in another embodiment of this application;

[0032] Figure 9 The diagram shown is a schematic flowchart of a method for fabricating a semiconductor epitaxial structure provided in another embodiment of this application.

[0033] Explanation of reference numerals in the attached figures: 10-substrate, 20-nucleation layer, 12-first transition layer, 121-first intermediate layer, 122-second intermediate layer, 23-second transition layer, 231-third intermediate layer, 232-fourth intermediate layer, 30-channel layer, 40-barrier layer, 50-cap layer. Detailed Implementation

[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate preferred embodiments of the application. However, this application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0036] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0037] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0038] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0039] Embodiments of the application are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures). Thus, variations from the illustrated shape can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. Consequently, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of regions of the device and are not intended to limit the scope of the application.

[0040] The multi-layer structure described in this application can be formed layer by layer or integrally; wherein, two adjacent layers can be in contact or isolated from each other.

[0041] Please see Figures 1 to 9 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this application. Although the illustrations only show components related to this application and are not drawn according to the actual number, shape and size of the components, the form, quantity and proportion of each component in actual implementation can be arbitrarily changed, and the layout of the components may also be more complex.

[0042] Please refer to Figure 1In one embodiment of this application, a semiconductor epitaxial structure is provided, including a substrate 10 and a first transition layer 12. The first transition layer 12 is formed on the substrate 10, wherein the concentration of a first component of the first transition layer 12 varies gradient along the direction of increasing thickness, and the first component is an element of the substrate 10.

[0043] As an example, please continue to refer to Figure 1 Because there is a region with high initial defect density and low thermal conductivity near the interface where an epitaxial layer, such as a nucleation layer, is formed on substrate 10, and the thermal conductivity of this region improves with increasing epitaxial layer thickness, but the thermal conductivity of the epitaxial layer is lower than that of substrate 10, increasing the thickness of the epitaxial layer will increase the effective thermal resistance of the overall epitaxial structure. To reduce the overall thermal resistance of the epitaxial structure and obtain a thin epitaxial layer with high crystal quality and low interface disorder, a first transition layer 12 is formed on the upper surface of substrate 10. The concentration of the first component varies gradient along the thickness direction. The first component is an element of substrate 10, which perfectly transforms the in-plane lattice atomic configuration of substrate 10 into the epitaxial layer lattice within the transition range of 1-5 unit cell thickness, thereby obtaining a high-quality epitaxial layer. This effectively reduces the thermal resistance of the epitaxial layer while controlling its thickness. This avoids defects such as dislocations, pits, or grain boundaries caused by lattice and thermal expansion mismatch, reduces interface thermal resistance, and improves the performance, reliability, and lifespan of the fabricated semiconductor device.

[0044] For example, please refer to Figure 2 In one embodiment of this application, a nucleation layer 20 is formed on the surface of the first transition layer 12 away from the substrate 10, such as a SiC substrate. This embodiment uses the formation of the nucleation layer 20 on a SiC substrate as an example to illustrate one implementation principle of this application. For example, the nucleation layer 20 is an aluminum nitride (AlN) nucleation layer. By controlling the gradient change of silicon composition along the thickness direction during the growth of the first transition layer 12, within the transition range of 1-5 unit cell thickness, for example, 0.5nm-1.5nm, the in-plane lattice atomic configuration of the SiC substrate is perfectly transformed into an AlN lattice, obtaining a high-quality AlN nucleation layer. The thickness of the AlN nucleation layer is reduced from the traditional 50nm-500nm to 2nm-50nm. While avoiding defects such as dislocations, pits, or grain boundaries caused by lattice and thermal expansion mismatch, the interface thermal resistance is reduced, improving the performance, reliability, and lifespan of the fabricated semiconductor device.

[0045] As an example, please continue to refer to Figure 2In one embodiment of this application, the concentration of the first component in the first transition layer 12 can be set to decrease stepwise or gradually decrease along the direction of thickness increase, so that within the transition range of 1 unit cell to 5 unit cell thickness, for example 0.5 nm to 1.5 nm, the in-plane lattice atomic configuration on the substrate 10 can be perfectly transformed into the lattice of the adjacent epitaxial layer, such as the nucleation layer 20, to obtain a high-quality epitaxial layer, effectively reducing the thermal resistance of the epitaxial layer while effectively controlling the thickness of the epitaxial layer.

[0046] As an example, in one embodiment of this application, please continue to refer to... Figure 2 The first transition layer 12 can be set to include (A1) y Si 1-y A buffer transition layer of N, 0 < y < 1, is used to form a compositionally graded interface structure. Experiments show that this embodiment significantly reduces composition-induced lattice mismatch and the surface energy gradient difference between the epitaxial layer and the substrate, thereby forming a high-quality epitaxial layer.

[0047] As an example, in one embodiment of this application, please continue to refer to... Figure 2 The first transition layer 12 further includes a third component, which is an element of the nucleation layer 20. The concentration of the third component in the first transition layer 12 increases gradually or progressively along the direction of thickness increase. Preferably, the elements of the first transition layer 12, except for the first element, are the same as those of the nucleation layer 20. For example, the first transition layer can be configured to include (Al) y Si 1-y A buffer transition layer of N, 0 < y < 1, is used to form a compositionally gradient interface structure, wherein aluminum is the nucleation element. The concentration of aluminum in the first transition layer 12 increases stepwise or gradually along the direction of thickness increase, so that within the transition range of 1 unit cell to 5 unit cell thickness, for example, 0.5 nm to 1.5 nm, the in-plane lattice atomic configuration on the substrate 10 is perfectly transformed into the lattice of the nucleation layer 20 to obtain a high-quality epitaxial layer. This effectively reduces the thermal resistance of the epitaxial layer while effectively controlling the thickness of the epitaxial layer.

[0048] As an example, in one embodiment of this application, please continue to refer to... Figure 2 It can be set to include (Al) y Si 1-y The thickness of the buffer transition layer for N is 0.5 nm to 5 nm; for example, to obtain the optimal growth interface, a layer including (Al) can be set. y Si 1-yThe thickness of the buffer transition layer of AlN is 1 nm. The nucleation layer 20 can be set to an aluminum nitride (AlN) nucleation layer, and the thickness of the AlN nucleation layer can be set to 5 nm-50 nm. As an example, to obtain the optimal thermal resistance value, the thickness of the AlN nucleation layer can be set to 30 nm.

[0049] Further, please refer to Figure 3 In one embodiment of this application, the first transition layer 12 includes a first intermediate layer 121 and a second intermediate layer 122 stacked sequentially, wherein the first intermediate layer 121 is located between the substrate 10 and the second intermediate layer 122; wherein the concentration of the first component in the first intermediate layer 121 is greater than the concentration of the first component in the second intermediate layer 122.

[0050] As an example, please continue to refer to Figure 3 The first intermediate layer 121 can be configured as a silicon-doped aluminum nitride layer, with an atomic ratio of aluminum to silicon of 0.4-0.6. For example, the atomic ratio of silicon to aluminum in the first intermediate layer 121 can be set to 0.6. Alternatively, the first intermediate layer 121 can be configured as (Al... 1 / 3 Si 2 / 3 )N x If x > 0, the second intermediate layer 122 can be set to a silicon-doped aluminum nitride layer, and the atomic ratio of aluminum to silicon in the second intermediate layer 122 can be set to 0.6-0.4. For example, the atomic ratio of silicon to aluminum in the second intermediate layer 122 can be set to 0.4. For example, the second intermediate layer 122 can be set to (Al... 2 / 3 Si 1 / 3 )N x x>0. By setting the concentration of silicon component in the first intermediate layer 121 to be greater than that in the second intermediate layer 122, the in-plane lattice atomic configuration on the substrate 10 is perfectly transformed into the lattice of the adjacent epitaxial layer, such as the nucleation layer 20, through the transition between the first intermediate layer 121 and the second intermediate layer 122, so as to obtain a high-quality epitaxial layer. While effectively reducing the thermal resistance of the epitaxial layer, the thickness of the epitaxial layer is effectively controlled.

[0051] As an example, please continue to refer to Figure 3 In one embodiment of this application, the thickness of the first intermediate layer 121 is 0.3nm-3nm, and the thickness of the second intermediate layer 122 is 0.3nm-3nm. To obtain the optimal growth interface, the combined thickness of the first intermediate layer 121 and the second intermediate layer 122 can be set to 1nm-3nm. To obtain the optimal thermal resistance value, the thickness of the nucleation layer 20 can be set to 25nm-35nm, for example, the thickness of the nucleation layer 20 can be set to 30nm.

[0052] Further, please refer to Figure 4In one embodiment of this application, the semiconductor epitaxial structure further includes a nucleation layer 20, a second transition layer 23 and a channel layer 30 stacked sequentially, wherein the nucleation layer 20 is located between the first transition layer 12 and the second transition layer 23; wherein the concentration of the second component of the second transition layer 23 varies gradient along the direction of increasing thickness, and the second component of the second transition layer 23 is an element of the channel layer 30.

[0053] As an example, please continue to refer to Figure 4 By forming a second transition layer 23 between the nucleation layer 20 and the channel layer 30, where the concentration of the second component varies gradient along the thickness direction, and the second component of the second transition layer 23 is an element of the channel layer 30, the in-plane lattice atomic configuration of the nucleation layer 20 is perfectly transformed into the lattice of the channel layer 30 within the transition range of 1-5 unit cell thickness, for example, 0.5 nm-1.5 nm. This avoids the need to grow a buffer layer and directly grows a high-quality channel layer, achieving a buffer-free structure design. The heat generated in the thin channel is more effectively dissipated into the substrate 10, effectively reducing the overall thermal resistance of the epitaxial structure and alleviating the problem of self-heating in the fabricated semiconductor device. Due to the realization of the buffer-free structure design, this application effectively reduces the thickness of the overall epitaxial structure, reduces raw material consumption while ensuring the performance of the fabricated semiconductor device, significantly shortens the deposition time, minimizes manufacturing costs, and increases the production capacity of metal-organic chemical vapor deposition (MOCVD).

[0054] As an example, please continue to refer to Figure 4 In one embodiment of this application, the concentration of the second component in the second transition layer increases gradually or stepwise along the direction of thickness increase. Preferably, the elements of the second transition layer 12, except for the second element, are the same as those of the nucleation layer 20. For example, the second transition layer 23 can be configured to include Al. x Ga 1-x A transition channel layer of N, 0 < x < 1, is used to form a compositionally graded interface structure. Experiments show that this embodiment significantly reduces composition-induced lattice mismatch and the surface energy gradient difference between the channel layer 30 and the nucleation layer 20, thereby forming a high-quality channel layer 30.

[0055] As an example, please continue to refer to Figure 4 In one embodiment of this application, an A1 may be provided. x Ga 1-x The thickness of the transition channel layer for N is 0.5 nm–5 nm, where 0 < x < 1. To obtain the optimal growth interface, Al can be included. x Ga 1-xThe thickness of the transition channel layer of N is 2nm; the channel layer 30 can be set to a gallium nitride (GaN) channel layer, and the thickness of the GaN channel layer can be set to 5nm-500nm, for example, the thickness of the GaN channel layer can be set to 250nm.

[0056] As an example, in one embodiment of this application, please continue to refer to... Figure 4 The second transition layer 23 further includes a fourth component, which is an element of the nucleation layer 20. The concentration of the fourth component in the second transition layer 23 decreases stepwise or gradually along the direction of increasing thickness. For example, the second transition layer 23 can be configured to include Al. x Ga 1-x The transition channel layer of N, 0 < x < 1, forms a compositionally gradient interface structure. For example, aluminum in the second transition layer 23 is the nucleation element, and the concentration of aluminum in the second transition layer decreases stepwise or gradually along the direction of thickness increase, so that the in-plane lattice atomic configuration of the nucleation layer 20 is perfectly transformed into the lattice of the channel layer 30 within the transition range of 1 unit cell to 5 unit cell thickness, for example, 0.5 nm to 1.5 nm, in order to avoid the growth of a buffer layer and directly grow a high-quality channel layer, realizing a buffer-free structure design.

[0057] As an example, in one embodiment of this application, please refer to Figure 5 The nucleation layer 20 can be configured as an aluminum nitride nucleation layer, and the channel layer 30 can be configured as a gallium nitride channel layer. The second transition layer 23 includes a third intermediate layer 231 and a fourth intermediate layer 232 stacked sequentially. The third intermediate layer 231 is located between the aluminum nitride nucleation layer and the fourth intermediate layer 232. The third intermediate layer 231 can be configured as a gallium-doped aluminum nitride layer, and the atomic ratio of gallium to aluminum in the third intermediate layer 231 can be configured as 0.4-0.6. For example, the third intermediate layer 231 can be configured as (Al... 2 / 3 Ga 1 / 3 )N x If x > 0, the fourth intermediate layer 232 can be set to a gallium-doped aluminum nitride layer, and the atomic ratio of gallium to aluminum in the fourth intermediate layer 232 can be set to 0.6-0.4. For example, the fourth intermediate layer 232 can be set to (Al... 1 / 3 Ga 2 / 3 )N x , x>0.

[0058] In the above embodiments, by suppressing the formation of structural defects in the GaN-AlN interface, a high-quality GaN channel layer can be obtained, achieving a buffer-free structure. Heat generated in the thin GaN channel will be more effectively dissipated into the substrate, and the thermal resistance of the material is expected to be significantly reduced, alleviating the device's self-heating problem. By avoiding thick doped (e.g., carbon- or iron-doped) buffer layers, the trapping effect is reduced. The AlN nucleation layer can effectively act as a back barrier, improving carrier confinement in high-frequency applications. While the total thickness of the epitaxial layer in conventional GaN-on-SiC HEMTs is typically 1500nm-3000nm, this application achieves a reduction in the total epitaxial thickness to 300nm-1500nm, reducing raw material consumption and significantly shortening deposition time, thereby minimizing manufacturing costs and increasing the production capacity of metal-organic chemical vapor deposition (MOCVD). Compared to standard HEMT structures with intentionally doped (carbon or iron, etc.) buffer layers, this does not affect material quality or device performance; in fact, the material may even outperform conventional materials at the device level.

[0059] For example, please refer to Figure 6 In one embodiment of this application, a barrier layer 40 and a cap layer 50 are sequentially stacked on the side of the channel layer 30 away from the substrate 10. The barrier layer 40 is used to form a heterojunction structure with the channel layer 30. The cap layer 50 is located on the side of the barrier layer 40 away from the channel layer 30. The barrier layer 40 can be set as an aluminum gallium nitride (AlGaN) barrier layer, and the thickness of the barrier layer 40 can be set to 10nm-50nm. The cap layer 50 can be set as a gallium nitride cap layer, and the thickness of the cap layer 50 can be set to 1nm-10nm. The cap layer 50 can be a passivation layer used to passivate the surface of the barrier layer 40, reduce the gate current, and facilitate metal / semiconductor ohmic contact.

[0060] In one embodiment of this application, the substrate may be a silicon carbide substrate or a gallium nitride substrate, etc. For example, the substrate may include at least one of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium or silicon (Si).

[0061] In one embodiment of this application, the multilayer epitaxial structure formed on the substrate may include semiconductor materials based on group III-V compounds. These group III-V compounds are compounds formed from boron (B), aluminum (Al), gallium (Ga), and indium (In) of group III and nitrogen (N), phosphorus (P), arsenic (As), or antimony (Sb) of group V in the periodic table, primarily including arsenic gallium phosphate (GaAs), indium phosphide (InP), and gallium nitride.

[0062] In one embodiment of this application, a semiconductor structure is provided, which is made using the semiconductor epitaxial structure described in any embodiment of this application. This effectively reduces the thermal resistance of the epitaxial layer while effectively controlling the thickness of the epitaxial layer, thereby improving the performance, reliability and lifespan of the manufactured semiconductor device.

[0063] For example, please refer to Figure 7 In one embodiment of this application, a method for fabricating a semiconductor epitaxial structure is provided, comprising:

[0064] Step 202: Provide a silicon carbide substrate;

[0065] Step 204: A first transition layer is formed on the substrate, wherein the concentration of a first component of the first transition layer varies gradient along the direction of increasing thickness, and the first component is an element of the substrate.

[0066] As an example, please continue to refer to Figure 7 By forming a first transition layer on the upper surface of a substrate, where the concentration of a first component varies gradient along the thickness increasing direction, and the first component is an element of the substrate, the in-plane lattice atomic configuration on the substrate is perfectly transformed into the epitaxial layer lattice within the transition range of 1-unit-cell thickness. This results in a high-quality epitaxial layer, effectively reducing the thermal resistance of the epitaxial layer while effectively controlling its thickness. This avoids defects such as dislocations, pits, or grain boundaries caused by lattice and thermal expansion mismatch, reduces interfacial thermal resistance, and improves the performance, reliability, and lifespan of the fabricated semiconductor devices.

[0067] For example, please refer to Figure 8 In one embodiment of this application, the step of forming a first transition layer on the substrate includes:

[0068] Step 2042: A first transition layer is formed on one side of the substrate using a physical vapor deposition process, and during the growth of the first transition layer, the concentration of the first component of the first transition layer is controlled to change gradient along the direction of thickness increase, wherein the first component is an element of the substrate.

[0069] As an example, please continue to refer to Figure 8A first transition layer, where the concentration of a first component varies gradient along the thickness increasing direction, can be formed between the substrate and the nucleation layer. This first component is an element of the substrate, allowing the in-plane lattice atomic configuration on the substrate to be perfectly transformed into the nucleation layer lattice within a transition range of 1-5 unit cells in thickness. This results in a high-quality nucleation layer, effectively reducing the thermal resistance of the epitaxial layer while effectively controlling the thickness of the nucleation layer. This avoids defects such as dislocations, pits, or grain boundaries caused by lattice and thermal expansion mismatch, reducing interfacial thermal resistance and improving the performance, reliability, and lifespan of the fabricated semiconductor device. Using physical vapor deposition to form the nucleation layer and the first transition layer can significantly shorten deposition time, minimize manufacturing costs, and increase production capacity.

[0070] For example, please refer to Figure 9 In one embodiment of this application, after forming the first transition layer on the substrate, the method further includes:

[0071] Step 2043: A nucleation layer is formed on the side of the first transition layer away from the substrate using a physical vapor deposition process.

[0072] As an example, please continue to refer to Figure 8 By forming a first transition layer with a gradient concentration of the first component along the thickness direction between the substrate and the nucleation layer, the in-plane lattice atomic configuration on the substrate is perfectly transformed into the nucleation layer lattice within a transition range of 1-5 unit cells in thickness, resulting in a high-quality nucleation layer. This effectively reduces the thermal resistance of the epitaxial layer while effectively controlling the thickness of the nucleation layer. This avoids defects such as dislocations, pits, or grain boundaries caused by lattice and thermal expansion mismatch, reduces interfacial thermal resistance, and improves the performance, reliability, and lifespan of the fabricated semiconductor device. Using physical vapor deposition to form the nucleation layer and the first transition layer can significantly shorten deposition time, minimize manufacturing costs, and increase production capacity.

[0073] As an example, please continue to refer to Figure 9 In one embodiment of this application, after forming a nucleation layer on the side of the first transition layer away from the substrate, the method further includes:

[0074] Step 2044: A second transition layer is formed on the side of the nucleation layer away from the substrate using physical vapor deposition. A channel layer is formed on the side of the second transition layer away from the nucleation layer using organometallic chemical vapor deposition. During the growth of the second transition layer, the concentration of the second component of the second transition layer is controlled to change gradient along the direction of thickness increase. The second component is an element of the channel layer.

[0075] As an example, please continue to refer to Figure 9By forming a second transition layer on the side of the nucleation layer away from the substrate, where the concentration of the second component varies gradient along the direction of thickness increase, and the second component of the second transition layer is an element of the channel layer, the nucleation layer is in a transition range of 1-5 unit cell thickness, for example, 0.5 nm-1.5 nm. This perfectly transforms the in-plane lattice atomic configuration of the nucleation layer into the channel layer lattice, avoiding the growth of a buffer layer and directly growing a high-quality channel layer. This achieves a buffer-free structure design, and the heat generated in the thin channel is more effectively dissipated into the substrate, effectively reducing the overall thermal resistance of the epitaxial structure and alleviating the problem of self-heating in the fabricated semiconductor device. Due to the implementation of the buffer-free structure design, this application effectively reduces the thickness of the overall epitaxial structure, reduces raw material consumption while ensuring the performance of the fabricated semiconductor device, significantly shortens the deposition time, minimizes manufacturing costs, and increases MOCVD throughput.

[0076] As an example, in one embodiment of this application, a III-V compound epitaxial structure is formed on the substrate using a metal-organic chemical vapor deposition (MOCVD) process, which can effectively control production costs while ensuring production capacity and efficiency.

[0077] In one embodiment of this application, the III-V compound is a compound formed from boron (B), aluminum (Al), gallium (Ga), indium (In) of Group III and nitrogen (N), phosphorus (P), arsenic (As) or antimony (Sb) of Group V in the periodic table, mainly including arsenic gallium nitride (GaAs), indium phosphide (InP) and gallium nitride.

[0078] For specific limitations on the semiconductor epitaxial structure preparation method in the above embodiments, please refer to the limitations on semiconductor epitaxial structures above, which will not be repeated here.

[0079] Unless otherwise expressly stated herein, the execution order of these steps in the semiconductor epitaxial structure fabrication method in the above embodiments is not strictly limited, and these steps can be executed in other orders. Moreover, at least some steps in the method may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages in other steps.

[0080] The methods for fabricating semiconductor epitaxial structures in the above embodiments are intended to illustrate the formation principle of the semiconductor epitaxial structures in the embodiments of this application, and are not intended to limit the specific semiconductor epitaxial structures in the embodiments of this application. Other fabrication methods can also be used to fabricate the semiconductor epitaxial structures in the embodiments of this application.

[0081] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation on this application.

[0082] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0083] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0084] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A semiconductor epitaxial structure, characterized in that, include: Substrate containing Si; as well as A first transition layer is formed on the substrate; the thickness of the first transition layer is 0.5 nm to 5 nm. The first transition layer is (Al y Si 1-y )N layer, where 0<y<1, and the y value increases in the direction of increasing thickness; an aluminum nitride nucleation layer is directly formed on the first transition layer; within the transition range of 1 unit cell to 5 unit cells in thickness, the first transition layer converts the in-plane lattice atomic configuration of the substrate to the lattice of the aluminum nitride nucleation layer; the thickness of the aluminum nitride nucleation layer is 2nm-50nm; A second transition layer is located on the surface of the aluminum nitride nucleation layer opposite to the first transition layer, and the second transition layer includes Al. x Ga 1-x N, 0 < x < 1, and the value of x decreases along the direction of increasing thickness, so that the in-plane lattice atomic configuration of the nucleation layer is transformed into the lattice of the gallium nitride channel layer within the transition range of 1 unit cell to 5 unit cell thickness, and there is no buffer layer structure between the gallium nitride channel layer and the second transition layer.

2. The semiconductor epitaxial structure according to claim 1, characterized in that, The concentration of Si element in the first transition layer decreases stepwise or gradually along the direction of thickness increase.

3. The semiconductor epitaxial structure according to claim 2, characterized in that, The first transition layer includes a first intermediate layer and a second intermediate layer stacked sequentially, wherein the first intermediate layer is located between the substrate and the second intermediate layer. The concentration of Si element in the first intermediate layer is greater than the concentration of Si element in the second intermediate layer.

4. The semiconductor epitaxial structure according to claim 1, characterized in that, The concentration of Ga element in the second transition layer increases stepwise or gradually along the direction of thickness increase.

5. The semiconductor epitaxial structure according to claim 1, characterized in that, The first transition layer further includes a third component, which is an element of the nucleation layer.

6. The semiconductor epitaxial structure according to claim 4, characterized in that, The second transition layer further includes a fourth component, which is an element of the nucleation layer.

7. The semiconductor epitaxial structure according to claim 4, characterized in that, The second transition layer includes a third intermediate layer and a fourth intermediate layer stacked sequentially, wherein the third intermediate layer is located between the nucleation layer and the fourth intermediate layer. The concentration of Ga in the third intermediate layer is less than the concentration of Ga in the fourth intermediate layer.

8. A semiconductor structure, characterized in that, It is made using the semiconductor epitaxial structure described in any one of claims 1-7.

9. A method for fabricating a semiconductor epitaxial structure, characterized in that, include: Provide a substrate containing Si; forming a first transition layer on the substrate, wherein the concentration of the Si element in the first transition layer varies in a gradient along the direction of increasing thickness, and the Si element is an element of the substrate; the thickness of the first transition layer is 0.5 nm to 5 nm; the first transition layer is (Al y Si 1-y )N layer, where 0<y<1, and the y value increases along the direction of increasing thickness; An aluminum nitride nucleation layer is directly formed on the first transition layer. The first transition layer, within a transition range of 1-5 unit cells thick, transforms the in-plane lattice atomic configuration of the substrate into the lattice of the aluminum nitride nucleation layer. The thickness of the aluminum nitride nucleation layer is 2 nm-50 nm. A second transition layer is formed on the surface of the aluminum nitride nucleation layer opposite to the first transition layer, the second transition layer comprising Al x Ga 1-x N, 0 < x < 1, and the value of x decreases along the direction of increasing thickness, so that the in-plane lattice atomic configuration of the nucleation layer is transformed into the lattice of the gallium nitride channel layer within the transition range of 1 unit cell to 5 unit cell thickness, and there is no buffer layer structure between the gallium nitride channel layer and the second transition layer.

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