Three-dimensional memory and methods of making the same

Abstract

This application provides a three-dimensional memory and a method for fabricating the same. The method for fabricating the three-dimensional memory includes: sequentially stacking a dielectric layer and a sacrificial layer on a substrate to form a stacked structure, wherein the sacrificial layer includes a first sacrificial layer and a second sacrificial layer, the second sacrificial layer being located on the side of the first sacrificial layer away from the substrate; forming a plurality of gate line gaps penetrating the stacked structure and extending to the substrate; and removing the first sacrificial layer through the gate line gaps, and removing a portion of the second sacrificial layer, wherein the unremoved portion of the second sacrificial layer, together with a portion of the dielectric layer, forms a top select gate isolation structure.

Description

Technical Field

[0001] This application relates to the field of semiconductor design and manufacturing, and more specifically, to the structure of a three-dimensional memory (3D NAND) and its fabrication method. Background Technology

[0002] Currently, in 3D NAND 9-hole processes, top select gate notching and related steps are typically used to divide two slices of memory within the same finger memory. This process involves at least one photolithography step, one etching step, and two or more chemical vapor deposition processes, making it complex and costly. The top select gate photolithography process requires high overlay accuracy perpendicular to the stacked structure, making the fabrication process quite challenging. Furthermore, due to the complexity of the etched material, abnormal polymer deposition during the etching process can cause defects in the top select gate notch.

[0003] It should be understood that the content described in the background section is only for the purpose of helping to understand the technical solutions disclosed in this application, and is not necessarily prior art before the filing date of this application. Summary of the Invention

[0004] This application provides a method for fabricating a three-dimensional memory. The method includes: sequentially stacking a dielectric layer and a sacrificial layer on a substrate to form a stacked structure, wherein the sacrificial layer includes a first sacrificial layer and a second sacrificial layer, the second sacrificial layer being located on the side of the first sacrificial layer away from the substrate; forming a plurality of gate line gaps penetrating the stacked structure and extending to the substrate; and removing the first sacrificial layer through the gate line gaps, and removing a portion of the second sacrificial layer, wherein the unremoved portion of the second sacrificial layer, together with a portion of the dielectric layer, forms a top select gate isolation structure.

[0005] In one embodiment, a portion of the dielectric layer is stacked on the portion of the second sacrificial layer that has not been removed to form the top select gate isolation structure.

[0006] In one embodiment, removing the first sacrificial layer via the gate gap and removing a portion of the second sacrificial layer includes: etching the first sacrificial layer and the second sacrificial layer via the gate gap, wherein the rate at which the first sacrificial layer is etched is greater than the rate at which the second sacrificial layer is etched.

[0007] In one embodiment, prior to forming the gate gap, the method further includes: forming a channel structure that penetrates the stacked structure and extends to the substrate, the channel structures being arranged in rows along a first direction, a plurality of the rows forming an array structure, each of the channel structures in the array structure being staggered with the channel structures of the adjacent row.

[0008] In one embodiment, the gate gaps penetrate the stacked structure along the first direction and the second direction, respectively, wherein the first direction is perpendicular to the second direction, and the second direction includes the direction in which the dielectric layer and the sacrificial layer are stacked sequentially.

[0009] In one embodiment, the top selected gate isolation structure extends through the stacked structure along the first direction.

[0010] In one embodiment, the step of forming the multilayer structure includes: sequentially stacking the dielectric layer and the first sacrificial layer on the substrate to form a multilayer structure; and sequentially stacking the dielectric layer and the second sacrificial layer on the side of the multilayer structure away from the substrate.

[0011] In one embodiment, after the top select gate isolation structure is formed, at least one row of channel structures in the array of channel structures extends through the top select gate isolation structure.

[0012] In one embodiment, the first sacrificial layer includes a first silicon nitride layer, and the second sacrificial layer includes a second silicon nitride layer, wherein the density of the second silicon nitride layer is greater than the density of the first silicon nitride layer.

[0013] In one embodiment, the method further includes forming the gate layer in the space formed after removing the first sacrificial layer and a portion of the second sacrificial layer.

[0014] In one embodiment, the step of forming the gate layer includes: removing the first sacrificial layer via the gate gap to form a first sacrificial gap; removing a portion of the second sacrificial layer via the gate gap to form a second sacrificial gap; and filling the first sacrificial gap and the second sacrificial gap with a conductive material.

[0015] This application also provides a three-dimensional memory, comprising: a substrate; a stacked structure located on the substrate and including a dielectric layer and a gate layer, the dielectric layer and the gate layer being stacked sequentially; a plurality of gate line gap structures penetrating the stacked structure and extending to the substrate; and a top selected gate isolation structure located on the side of the stacked structure away from the substrate, including a second sacrificial layer and a portion of the dielectric layer.

[0016] In one embodiment, the dielectric layer includes a first portion of the dielectric layer, and the top selected gate isolation structure includes a second sacrificial layer and the first portion of the dielectric layer, wherein the first portion of the dielectric layer and the second sacrificial layer are stacked alternately.

[0017] In one embodiment, the memory further includes: a channel structure extending through the stacked structure and to the substrate, wherein the channel structures are arranged in rows along a first direction, and a plurality of the rows form an array structure, wherein each of the channel structures in the array structure is staggered with the channel structures of the adjacent row.

[0018] In one embodiment, the gate line gaps penetrate the stacked structure along the first direction and the second direction, respectively, wherein the first direction is perpendicular to the second direction, and the second direction includes the direction in which the dielectric layer and the gate layer are stacked.

[0019] In one embodiment, the top selected gate isolation structure extends through the stacked structure along the first direction.

[0020] In one embodiment, at least one row of channel structures in the array of channel structures extends through the top selected gate isolation structure.

[0021] In one embodiment, the memory includes a plurality of block memories, the plurality of gate gap structures being configured to divide the block memories into a plurality of finger memories, each of the finger memories including at least one of the top select gate isolation structures.

[0022] In one embodiment, the top-select gate isolation structure is configured to divide each of the finger memories into a plurality of slice memories, each of the slice memories including at least one row of the channel structure.

[0023] This application's solution replaces the sacrificial silicon nitride layer in related processes by depositing a dense silicon nitride material with a slower etching rate on the side of the stacked structure furthest from the substrate. By precisely controlling the etching time, a portion of the dense silicon nitride material is retained while the sacrificial silicon nitride layer is completely removed, thus forming a top select gate notch. Compared to existing top select gate notch processing technologies, this solution omits several steps, effectively saving costs and shortening the product development cycle. It also exhibits strong compatibility with existing processes, effectively avoiding the difficulties in existing top select gate notch processing technologies, and enabling self-alignment of the top select gate notch overlay accuracy. Attached Figure Description

[0024] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0025] Figure 1 A flowchart illustrating a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application is shown schematically;

[0026] Figures 2 to 8This is a process schematic diagram of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application; and

[0027] Figure 9 This is a cross-sectional schematic diagram of a finger memory structure in a three-dimensional memory according to an exemplary embodiment of this application. Detailed Implementation

[0028] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first sacrificial layer discussed herein may also be referred to as the second sacrificial layer, and the first part of the top selection gate isolation structure may also be referred to as the second part of the top selection gate isolation structure, and vice versa.

[0030] In the accompanying drawings, the thickness, dimensions, and shapes of the components have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. For example, the thickness of the laminated structure depicted in the drawings of this application is not proportional to actual production. Terms such as “approximately,” “about,” and similar expressions used herein are used as terms of approximation, not as terms of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by those skilled in the art.

[0031] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0032] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0033] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0034] The features, principles and other aspects of this application are described in detail below.

[0035] Figure 1 This is a flowchart of a method 1000 for fabricating a three-dimensional memory according to an exemplary embodiment of this application. For example... Figure 1 As shown, this application provides a method 1000 for fabricating a three-dimensional memory, including step S1100, where a dielectric layer and a sacrificial layer are sequentially stacked on a substrate to form a stacked structure, wherein the sacrificial layer includes a first sacrificial layer and a second sacrificial layer located on the side of the first sacrificial layer away from the substrate. In step S1200, a plurality of gate line gaps are formed that penetrate the stacked structure and extend to the substrate. And in step S1300, the first sacrificial layer is removed through the gate line gaps, and a portion of the second sacrificial layer is removed, wherein the portion of the second sacrificial layer that is not removed forms a top select gate isolation structure with a portion of the dielectric layer.

[0036] It should be understood that the steps shown in method 1000 are not exclusive, and other steps may be performed before, after, or between any of the steps shown. Furthermore, some of the steps shown may be performed simultaneously or in a sequence different from the steps described. Figure 1 The execution is performed in the order shown.

[0037] In this application example, a dielectric layer and a sacrificial layer are sequentially stacked on a substrate to form a stacked structure, wherein the sacrificial layer includes a first sacrificial layer and a second sacrificial layer located on the side of the first sacrificial layer away from the substrate.

[0038] like Figure 2As shown, in step S1100, a multilayer structure 120 including a dielectric layer 121 and a sacrificial layer is formed on the substrate 110. The sacrificial layer includes a first sacrificial layer 122 and a second sacrificial layer 123. Specifically, the step of forming the multilayer structure 120 includes sequentially forming a dielectric layer 121 and a first sacrificial layer 122 on the substrate 110 to form a multilayer structure 130, and sequentially stacking the dielectric layer 121 and the second sacrificial layer 123 on the side of the multilayer structure 130 away from the substrate 110. The material of the substrate 110 may include, for example, silicon (e.g., single-crystal silicon, polycrystalline silicon), silicon-germanium (SiGe), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof.

[0039] In some examples, substrate 110 may include a base 111 and a composite layer 112 located on the base 111, wherein the base 111 has a certain thickness and can serve as a structural support for a device structure (e.g., stacked structure 120) formed thereon, and alternatively, the base 111 may be removed in some subsequent process steps.

[0040] In some examples, depending on the structure of the final three-dimensional memory, a portion or all of the composite layer 112 may be removed; this application does not limit this.

[0041] In some examples, the stacked structure 120 may include a multilayer structure 130 formed by alternately stacking a plurality of dielectric layers 121 and a plurality of first sacrificial layers 122 in a direction perpendicular or substantially perpendicular to the substrate 110 (y-direction), and a plurality of dielectric layers 121 and a plurality of second sacrificial layers 123 alternately stacked on the side of the multilayer structure 130 away from the substrate 110. It is understood that the second sacrificial layer 123 is located on the side of the first sacrificial layer 122 away from the substrate 110. Under the same etching conditions, the first sacrificial layer 122 and the second sacrificial layer 123 may have a high etch selectivity with respect to the dielectric layer 121, so that when the first sacrificial layer 122 and the second sacrificial layer 123 are removed in subsequent processes, the dielectric layer 121 is hardly removed. In some examples, the first sacrificial layer 122 and the second sacrificial layer 123 may have a high etch selectivity, such that when the first sacrificial layer 122 is completely removed in subsequent processes, the second sacrificial layer 123 is at least partially retained. For example, the material used for the dielectric layer 121 includes silicon oxide, the material used for the first sacrificial layer 122 includes silicon nitride, and the material used for the second sacrificial layer 123 includes dense silicon nitride.

[0042] For example, a multilayer structure 120 can be formed on a substrate 110 by alternately stacking multiple dielectric layers 121 and multiple first sacrificial layers 122 and alternately stacking multiple dielectric layers 121 and multiple second sacrificial layers 123 on a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof.

[0043] It should be understood that the number of layers in the stacked structure 120 is not limited to... Figure 2 The number of layers shown is not the actual number of layers. The number of stacked layers and the stacking height of the stacked structure 120 can be designed according to actual needs. This application does not make specific limitations on this.

[0044] See in some examples Figure 3 The via 140 penetrates the stacked structure 120 and extends to the substrate 110. The via 140 may consist of N (N≥2) sub-channel holes. Exemplarily, a first sub-stacked structure 120-1 is formed on the substrate 110. A first sub-channel hole 140-1 penetrating the first sub-stacked structure 120-1 and extending to the substrate 110 may be formed in the first sub-stacked structure 120-1 using, for example, an etching process. Then, a via-filling sacrificial layer (not shown) is formed in the first sub-channel hole 140-1. Subsequent sub-stacked structures and sub-channel holes are formed on the side of the first sub-stacked structure 120-1 away from the substrate 110, until the Nth sub-stacked structure 120-N and the Nth sub-channel hole 140-N are formed. N-1 via-filling sacrificial layers are correspondingly filled in the N-1 sub-channel holes, excluding the Nth sub-channel hole. For example, an etching process can be used to remove the via-filling sacrificial layer in the N-1 sub-channel holes based on the Nth sub-channel hole 140-N, so that the upper and lower adjacent sub-channel holes in the N sub-channel holes are at least partially aligned with each other to form the channel hole 140.

[0045] In some examples, such as Figure 4 and Figure 5 As shown, a barrier layer 151, a charge trapping layer 152, a tunneling layer 153, and a channel layer 154 can be sequentially formed within a channel via 140 to form a channel structure 150. Exemplarily, the barrier layer 151, charge trapping layer 152, and tunneling layer 153 can be a silicon oxide-silicon nitride-silicon oxide (ONO) structure. In some examples, the channel layer 154 can be used to transport the desired charge (electrons or holes). The material of the channel layer 154 includes p-type doped polysilicon. The space defined by the channel layer 154 can be filled with a channel filler layer 155, the material of which includes, for example, silicon oxide or silicon oxynitride.

[0046] For example, a barrier layer 151, a charge trapping layer 152, and a tunneling layer 153 may be deposited sequentially using one or more thin film deposition processes (e.g., ALD, CVD, PVD, or combinations thereof), and then a channel layer 154 may be deposited on the side of the tunneling layer 153 away from the channel hole 140.

[0047] In some examples, the channel structure 150 also includes a channel plug 156 formed on top of the channel filling layer 155, the channel plug 156 contacting the channel layer 154 to achieve electrical connection. The channel plug 156 may be made of the same material as the channel layer 154, such as p-type doped polysilicon. In a specific example of this application, the portion of the channel filling layer 155 located on top of the channel via 140 may be processed by wet etching and / or dry etching to form a recess on top of the channel via 140, and then a semiconductor material such as polysilicon may be deposited into the recess by one or more thin film deposition processes (e.g., CVD, PVD, ALD, or any combination thereof) to form the channel plug 156.

[0048] In some examples, one side of the channel plug 156 can be electrically connected to the channel layer 154, and the other side of the channel plug 156 can be electrically connected to the back-end interconnect structure (Array BEOL), and based on the back-end interconnect structure, electrically connect to the peripheral circuit wafer.

[0049] In some examples, the channel structure 150 may also include a selective epitaxial layer (not shown) located at the bottom of the channel via 140 and in contact with the substrate 110, with one end of the channel layer 154 connected to the upper surface of the selective epitaxial layer.

[0050] In this application example, multiple gate gaps are formed that penetrate the stacked structure and extend to the substrate. Figure 6 This is a process diagram illustrating the formation of a gate line gap 160 extending through the stacked structure 120 and reaching the substrate 110 according to the fabrication method of this application. Figure 6 As shown, a gate gap 160 can be formed in the stacked structure 120 from the side of the dielectric layer 121 away from the substrate 110. The gate gap 160 can penetrate the stacked structure 120 and extend to the substrate 110 along a second direction (e.g., the opposite direction of y) and can also penetrate the stacked structure 120 along a first direction (e.g., the z direction). In some examples, the gate gap 160 can sequentially penetrate the dielectric layer 121, the second sacrificial layer 123, and the first sacrificial layer 122. Exemplarily, processes such as wet etching, dry etching, or a combination thereof can be used to remove portions of the dielectric layer 121, the second sacrificial layer 123, and the first sacrificial layer 122 to form the gate gap 160.

[0051] In some examples, the gate gap 160 extends vertically or approximately vertically through the stacked structure 120 and laterally (along the z-direction) in a direction parallel to the substrate 110.

[0052] In this application example, the first sacrificial layer is removed via the gate gap, and a portion of the second sacrificial layer is removed, wherein the portion of the second sacrificial layer that is not removed forms a top select gate isolation structure with a portion of the dielectric layer.

[0053] like Figure 7 As shown, the first sacrificial layer 122 can be completely removed via the gate gap 160 to form the first sacrificial gap 161, and a portion of the second sacrificial layer 123 can be removed to form the second sacrificial gap 162. The remaining portion of the second sacrificial layer 123 is the first portion 171 of the top select gate isolation structure. In some examples, the first portion 171 of the top select gate isolation structure is parallel to the gate gap 160 in the z-direction.

[0054] In some examples, the first sacrificial layer 122 and the second sacrificial layer 123 may have a high etch selectivity ratio, thereby ensuring that when the first sacrificial layer 122 is completely removed, the second sacrificial layer 123 is at least partially retained. Exemplarily, the material for the first sacrificial layer 122 includes, for example, silicon nitride, and the material for the second sacrificial layer 123 includes, for example, dense silicon nitride. In some examples, the second sacrificial layer 123 may include at least one layer. The first sacrificial layer 122 and a portion of the second sacrificial layer 123 may be completely removed by a process such as wet etching, through which an etchant flows through the gate line gap 160.

[0055] In some examples, the second portion 172 of the top selected gate isolation structure is formed by the first portion of the dielectric layer, the first portion of the dielectric layer ( Figure 7 (As shown within the dashed box) It is stacked on top of the first part 171 of the top selection gate isolation structure, and has the same length in the x-direction as the first part 171 of the top selection gate isolation structure. The first part 171 and the second part 172 of the top selection gate isolation structure together form the top selection gate isolation structure 170. The top selection gate isolation structure 170 penetrates the stacked structure 120 along the z-direction.

[0056] It should be noted that the first sacrificial layer 122 and the second sacrificial layer 123 can be formed by controlling process parameters. The density of the second sacrificial layer 123 is higher than that of the first sacrificial layer 122, so that under the same etching conditions, when the first sacrificial layer 122 is completely removed, at least a portion of the second sacrificial layer 123 is still retained. Exemplarily, the first sacrificial layer 122 may include a first silicon nitride layer, and the second sacrificial layer 123 may include a second silicon nitride layer, where the density of the first silicon nitride is lower than that of the second silicon nitride. Under the same etching conditions, the first sacrificial layer 122 and the second sacrificial layer 123 can have a high etch selectivity ratio with the dielectric layer 121, meaning that the dielectric layer 121 is hardly removed when the first sacrificial layer 122 and the second sacrificial layer 123 are removed. Exemplarily, the material used for the dielectric layer 121 includes, for example, silicon oxide.

[0057] like Figure 8 As shown, in some examples, a thin-film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof may be used to deposit the gate layer 180 inside the first sacrificial gap 161 and the second sacrificial gap 162. Exemplarily, the gate layer 180 may be made of a conductive material, such as any one or a combination of tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides.

[0058] In some examples, the gate gap 160 may be filled to form a gate gap structure 190. Specifically, a third insulating layer (not shown) is formed on the inner wall and bottom of the gate gap 160, and then a conductive material is filled into the space defined by the third insulating layer. Exemplarily, the third insulating layer may be selected from the same material as the dielectric layer 121, such as silicon oxide. The conductive material may be selected from any one or combination of, for example, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), doped crystalline silicon, or silicides. Further, the conductive material may be formed using a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. 。

[0059] Another aspect of this application provides a three-dimensional memory. This three-dimensional memory structure can be fabricated using any of the fabrication methods described in the above embodiments. (Continue to refer to...) Figure 8 As shown, the three-dimensional memory may include a substrate 110, a stacked structure 120' located on the substrate 110, a plurality of gate gap structures 190, and a top selected gate isolation structure 170. The top selected gate isolation structure 170 includes a first portion 171 of the top selected gate isolation structure (e.g., a second sacrificial layer) and a second portion 172 of the top selected gate isolation structure (e.g., a portion of a dielectric layer).

[0060] In some examples, the stacked structure 120' may be formed by stacking a dielectric layer 121 and a gate layer 180. A top selected gate isolation structure 170 is located within the stacked structure 120', with its upper surface flush with the upper surface of the stacked structure 120' and extending in a direction (z-direction) parallel to the plurality of gate gap structures 190. The plurality of gate gap structures 190 penetrate the stacked structure 120' vertically or approximately vertically (in the opposite y-direction) and extend laterally (in the z-direction) in a direction parallel to the substrate 110.

[0061] In some examples, the second portion 172 of the top selected gate isolation structure is formed by the first portion of the dielectric layer, the first portion of the dielectric layer ( Figure 8 (As shown within the dashed box) It is stacked on the first portion 171 (second sacrificial layer) of the top select gate isolation structure, and has the same length in the x-direction as the first portion 171 of the top select gate isolation structure. The stacked structure 120' is formed by sequentially stacking multiple dielectric layers 121 and multiple gate layers 180. The first portion of the dielectric layer includes a portion of one or more dielectric layers 121 located on the upper side of the stacked structure 120'. The first portion of the dielectric layer and the second sacrificial layer are also alternately stacked in sequence. The second sacrificial layer is connected to the gate layer 180 in the x-direction.

[0062] In some examples, the three-dimensional memory can be divided into multiple memory slices (not shown), where each memory slice may include multiple block memories (not shown). Multiple gate linegage structures 190 can divide the block memory into multiple pointer memories 200 (e.g., Figure 9 As shown), the first part 171 of the top selected gate isolation structure is configured within the pointer memory 200, such that the pointer memory 200 forms two slice memories 210.

[0063] exist Figure 9 In the example, due to size limitations, the top selected gate isolation structure 170 extends through the fifth row of the nine-row channel structure 150, and each slice memory 210 includes four rows of channel structure 150. It should be noted that the number of rows of channel structure 150 is not limited to nine rows in the example; those skilled in the art can set an appropriate number of rows according to the specific structural requirements of different memory devices, and this application does not impose any limitations in this regard. Figure 9For example, after the 3D memory is manufactured, each pointer memory 200 will have eight rows of channel structures 150 and one row of virtual channel structures 150', with one channel structure 150 (or one virtual channel structure 150') corresponding to one channel hole 140. The channel structures 150 are arranged in rows along a first direction (z-direction) parallel to the gate gap 160, and multiple rows form an array structure 157. Each channel structure 150 in the array structure 157 is staggered with the channel structures 150 of the adjacent rows, and each channel structure 150 is also staggered with the adjacent virtual channel structure 150'. At least one row of channel structures 150 in the array formed by the channel structures 150 penetrates the top select gate isolation structure 170.

[0064] In other examples, the top selection gate isolation structure 170 can be placed between the channel structures 150 and does not pass through the channel structures 150.

[0065] Since the content and structure described above regarding the fabrication method can be fully or partially applied to the memory package structure described here, related or similar content will not be repeated.

[0066] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method of making a three-dimensional memory, comprising: The method includes: Forming a multilayer structure on a substrate, the multilayer structure comprising sequentially stacking a dielectric layer and a first sacrificial layer on the substrate to form a multilayer structure, and sequentially stacking a dielectric layer and a second sacrificial layer on the side of the multilayer structure away from the substrate; Forming a plurality of gate line gaps that penetrate the stacked structure and extend to the substrate; and The first sacrificial layer is removed via the gate gap, and a portion of the second sacrificial layer is removed, wherein the unremoved portion of the second sacrificial layer, together with a portion of the dielectric layer, forms a top select gate isolation structure; The removal of the first sacrificial layer via the gate gap and the removal of a portion of the second sacrificial layer include: The first sacrificial layer and the second sacrificial layer are etched through the gate gap, wherein the rate at which the first sacrificial layer is etched is greater than the rate at which the second sacrificial layer is etched.

2. The method according to claim 1, wherein, A portion of the dielectric layer is stacked on the portion of the second sacrificial layer that has not been removed to form the top select gate isolation structure.

3. The method according to claim 1, wherein, Before forming the gate line gap, the method further includes: A channel structure is formed that penetrates the stacked structure and extends to the substrate. The channel structures are arranged in rows along a first direction, and multiple rows form an array structure, wherein each channel structure in the array structure is staggered with the channel structures in the adjacent row.

4. The method according to claim 3, wherein, The gate gaps penetrate the stacked structure along the first direction and the second direction, respectively, wherein the first direction is perpendicular to the second direction, and the second direction includes the direction in which the dielectric layer and the sacrificial layer are stacked sequentially.

5. The method according to claim 4, wherein, The top selected gate isolation structure extends through the stacked structure along the first direction.

6. The method according to claim 1, wherein, The steps for forming the stacked structure include: The dielectric layer and the first sacrificial layer are sequentially stacked on the substrate to form a multilayer structure; and The dielectric layer and the second sacrificial layer are stacked sequentially on the side of the multilayer structure away from the substrate.

7. The method according to claim 3, wherein, After the top selection gate isolation structure is formed, at least one row of channel structures in the array of channel structures extends through the top selection gate isolation structure.

8. The method according to claim 1, wherein, The first sacrificial layer includes a first silicon nitride layer, and the second sacrificial layer includes a second silicon nitride layer, wherein the density of the second silicon nitride layer is greater than the density of the first silicon nitride layer.

9. The method according to claim 1 or 5, wherein, Also includes: A gate layer is formed in the space created after the removal of the first sacrificial layer and a portion of the second sacrificial layer.

10. The method according to claim 9, wherein, The steps for forming the gate layer include: The first sacrificial layer is removed via the gate gap to form a first sacrificial gap; A second sacrificial gap is formed by removing a portion of the second sacrificial layer via the gate gap; and The first and second sacrificial gaps are filled with conductive material.

11. A three-dimensional memory, characterized in that, include: Substrate; A stacked structure is located on the substrate and includes a dielectric layer and a gate layer, wherein the dielectric layer and the gate layer are stacked sequentially. Multiple gate gap structures penetrate the stacked structure and extend to the substrate; as well as The top selected gate isolation structure is located on the side of the stacked structure away from the substrate, and includes a second sacrificial layer and a portion of the dielectric layer, which are alternately stacked in sequence, and the second sacrificial layer and the portion of the dielectric layer are made of different materials.

12. The memory according to claim 11, wherein, The dielectric layer includes a first portion of the dielectric layer, and the top selected gate isolation structure includes a second sacrificial layer and the first portion of the dielectric layer, wherein the first portion of the dielectric layer and the second sacrificial layer are stacked alternately.

13. The memory according to claim 11, further comprising: A channel structure that penetrates the stacked structure and extends to the substrate. The channel structures are arranged in rows along a first direction, and multiple rows form an array structure, wherein each channel structure in the array structure is staggered with the channel structures in the adjacent row.

14. The memory according to claim 13, wherein, The gate line gaps penetrate the stacked structure along the first direction and the second direction, respectively, wherein the first direction is perpendicular to the second direction, and the second direction includes the direction in which the dielectric layer and the gate layer are stacked.

15. The memory according to claim 14, wherein, The top selected gate isolation structure extends through the stacked structure along the first direction.

16. The memory according to claim 13, wherein, At least one row of channel structures in the array of channel structures extends through the top selected gate isolation structure.

17. The memory according to claim 13, wherein, The memory includes a plurality of block memories, the plurality of gate gap structures being configured to divide the block memories into a plurality of finger memories, each of the finger memories including at least one of the top select gate isolation structures.

18. The memory according to claim 17, wherein, The top-select gate isolation structure is configured to divide each of the pointer memories into multiple slice memories, each of the slice memories including at least one row of the channel structure.

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