Semiconductor device and data storage system including semiconductor device

Abstract

A semiconductor device includes a stack structure including interlayer insulating layers and gate layers alternately stacked on a lower structure, and a memory vertical structure, a separation structure, and a support vertical structure penetrating the stack structure, wherein the gate layers include a lower gate layer, an upper gate layer, and an intermediate gate layer, wherein the separation structure includes a first separation structure, wherein the support vertical structure includes a first inner support vertical structure penetrating the lower gate layer, the intermediate gate layer, and the upper gate layer and adjacent to the first separation structure, wherein a portion of the first inner support vertical structure is directly connected to the first separation structure at a same level as the upper gate layer, and wherein a portion of the first inner support vertical structure is spaced apart from the first separation structure at a same level as the lower gate layer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0183044, filed on December 24, 2020, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of this disclosure relate to a semiconductor device and a data storage system including the semiconductor device. Background Technology

[0004] Semiconductor devices for storing large amounts of data in electronic systems requiring data storage are already essential. Therefore, methods for increasing the data storage capacity of semiconductor devices have been investigated. For example, as one method for increasing the data storage capacity of semiconductor devices, semiconductor devices comprising three-dimensionally arranged memory cells instead of two-dimensionally arranged memory cells have been proposed. Summary of the Invention

[0005] The exemplary embodiments of this disclosure provide a semiconductor device that can improve integration density and reliability.

[0006] An example embodiment of this disclosure provides a data storage system including semiconductor devices.

[0007] According to an example embodiment of this disclosure, a semiconductor device includes: a stacked structure including an interlayer insulating layer and a gate layer alternately stacked on a lower structure in a vertical direction; a memory vertical structure penetrating the stacked structure; a plurality of separation structures penetrating the stacked structure; and a plurality of supporting vertical structures penetrating the stacked structure, wherein the gate layer includes: a lower gate layer; an upper gate layer on the lower gate layer; and a plurality of intermediate gate layers, the plurality of intermediate gate layers being vertically spaced apart from each other between the lower gate layer and the upper gate layer, wherein the plurality of separation structures includes a first separation structure, wherein the plurality of supporting vertical structures includes a first inner supporting vertical structure penetrating the lower gate layer, the plurality of intermediate gate layers, and the upper gate layer, the first inner supporting vertical structure being adjacent to the first separation structure, wherein a first portion of the first inner supporting vertical structure is directly connected to the first separation structure at the same level as the upper gate layer, and wherein a second portion of the first inner supporting vertical structure is spaced apart from the first separation structure at the same level as the lower gate layer.

[0008] According to an exemplary embodiment of this disclosure, a semiconductor device includes a stacked structure comprising an interlayer insulating layer and a gate layer alternately stacked vertically on a lower structure; a plurality of separation structures penetrating the stacked structure; a plurality of supporting vertical structures penetrating the stacked structure in a stepped region on the lower structure; and a memory vertical structure penetrating the stacked structure in a memory cell array region on the lower structure. The gate layer comprises: a lower gate layer; an upper gate layer on the lower gate layer; and a plurality of intermediate gate layers, the intermediate gate layers being vertically spaced apart from each other between the lower gate layer and the upper gate layer. The gate layers include a stepped arrangement. A gate pad is disposed in a stepped region, wherein a plurality of separation structures include a first separation structure, wherein a plurality of supporting vertical structures include an inner supporting vertical structure and an outer supporting vertical structure disposed in the stepped region, wherein the inner supporting vertical structure penetrates a lower gate layer, a plurality of intermediate gate layers and an upper gate layer, wherein at least one of the inner supporting vertical structures has a side surface including an upper portion that contacts the first separation structure at the same level as the gate layer, wherein the outer supporting vertical structure penetrates the lower gate layer and the plurality of intermediate gate layers at a position spaced apart from the upper gate layer, and wherein the entire side surface of one of the outer supporting vertical structures is spaced apart from the first separation structure.

[0009] According to an example embodiment of this disclosure, a data storage system includes a main substrate; a semiconductor device on the main substrate; and a controller electrically connected to the semiconductor device on the main substrate. The semiconductor device includes: a stacked structure comprising an interlayer insulating layer and a gate layer alternately stacked vertically on a lower structure; a memory vertical structure penetrating the stacked structure; a plurality of separation structures penetrating the stacked structure; and a plurality of support vertical structures penetrating the stacked structure. The gate layer includes: a lower gate layer; an upper gate layer on the lower gate layer; and a plurality of intermediate gate layers vertically spaced apart from each other between the lower gate layer and the upper gate layer. The plurality of separation structures includes a first separation structure. The plurality of support vertical structures includes a first inner support vertical structure passing through the lower gate layer, the plurality of intermediate gate layers, and the upper gate layer. The first inner support vertical structure is adjacent to the first separation structure. A first portion of the first inner support vertical structure is directly connected to the first separation structure at the same level as the upper gate layer, and a second portion of the first inner support vertical structure is spaced apart from the first separation structure at the same level as the lower gate layer. Attached Figure Description

[0010] The above and other aspects, features, and advantages of this disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein the same reference numerals always denote the same elements. In the drawings:

[0011] Figure 1AThis is a plan view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

[0012] Figure 1B It shows Figure 1A An enlarged plan view of a portion of the semiconductor device shown;

[0013] Figures 2A to 2E This is a cross-sectional view of a semiconductor device according to an example embodiment of the present disclosure;

[0014] Figures 3A to 3D This is a plan view showing a portion of the elements of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0015] Figure 4 It shows Figure 2A An enlarged cross-sectional view of part "B" in the diagram;

[0016] Figure 5 This is an enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0017] Figure 6 This is an enlarged cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0018] Figure 7A This is an enlarged plan view illustrating a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0019] Figure 7B This is a cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0020] Figure 8A This is an enlarged plan view illustrating a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0021] Figure 8B This is a cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0022] Figure 9A This is a plan view illustrating a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0023] Figure 9B This is a cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0024] Figure 10 This is a cross-sectional view showing a modified example of a semiconductor device according to an exemplary embodiment of the present disclosure;

[0025] Figure 11 This is a flowchart illustrating a process for manufacturing a semiconductor device according to an exemplary embodiment of the present disclosure;

[0026] Figure 12 This is a diagram illustrating a data storage system including a semiconductor device according to an example embodiment of the present disclosure;

[0027] Figure 13 This is a perspective view illustrating a data storage system including a semiconductor device according to an example embodiment of the present disclosure; and

[0028] Figure 14 This is a cross-sectional view showing a data storage system including a semiconductor device according to an example embodiment of the present disclosure. Detailed Implementation

[0029] In the following description, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0030] In the following text, unless otherwise stated, terms such as “upper,” “upper part,” “upper surface,” “lower,” “lower part,” and “lower surface” may be indicated by reference numerals based on the accompanying drawings. For example, terms such as “upper part,” “middle part,” and “lower part” may be replaced by other terms such as “first,” “second,” and “third,” and may be used to describe elements of the exemplary embodiments. Elements may be described using terms such as “first,” “second,” and “third,” but elements are not limited by these terms and may also be referred to as “first element,” “second element,” and “third element.” Unless the context otherwise indicates, these terms are used only to distinguish one element, component, region, layer, or portion from another element, component, region, layer, or portion, for example, as a naming convention. Furthermore, in some cases, even if terms such as “first,” “second,” and “third” are not used in the specification, the term may still be referred to as “first,” “second,” or “third” in the claims in order to distinguish the different claimed elements from each other.

[0031] Reference Figures 1A to 2E Example embodiments of semiconductor devices are described. Figures 1A to 2E middle, Figure 1A This is a plan view illustrating a semiconductor device according to an example embodiment, while Figure 1B It shows Figure 1A An enlarged plan view of part "A" in the diagram. Figure 2A It is along Figure 1A The cross-sectional view taken from line I-I' in the diagram. Figure 2B It is along Figure 1A The cross-sectional view taken from line II-II' in the diagram. Figure 2C It is along Figure 1BThe cross-sectional view taken from line IIIa-IIIa' in the diagram. Figure 2D It is along Figure 1B The cross-sectional view taken from line IV-IV' in the diagram. Figure 2E It is along Figure 1B The cross-sectional view taken from line V-V' in the diagram.

[0032] Reference Figures 1A to 2E The semiconductor device 1 according to the example embodiment may include a first structure 3 and a second structure 21 that overlaps with the first structure 3 in the vertical direction Z.

[0033] In the example, the first structure 3 may include a patterned structure 17. The patterned structure 17 may include at least one silicon layer.

[0034] In the example, pattern structure 17 may include a first pattern layer 17a, a second pattern layer 17b, a third pattern layer 17c, and a fourth pattern layer 17d. The second pattern layer 17b and the fourth pattern layer 17d may be spaced apart from each other on the first pattern layer 17a. For example, the second pattern layer 17b and the fourth pattern layer 17d may overlap each other in a first horizontal direction X and / or a second horizontal direction Y. The third pattern layer 17c may cover the second pattern layer 17b and the fourth pattern layer 17d on the first pattern layer 17a. The thickness of the first pattern layer 17a may be greater than the thickness of each of the second pattern layer 17b, the third pattern layer 17c, and the fourth pattern layer 17d. At least one of the first pattern layer 17a, the second pattern layer 17b, the third pattern layer 17c, and the fourth pattern layer 17d may include a silicon layer. For example, the first pattern layer 17a, the second pattern layer 17b, and the third pattern layer 17c may include a silicon layer, such as a silicon layer with N-type conductivity. The fourth pattern layer 17d may include a material different from the silicon layer. For example, the fourth patterning layer 17d may include multiple layers stacked in sequence, such as a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer stacked in sequence.

[0035] In the example, the first structure 3 may further include a semiconductor substrate 4, a device isolation layer 6s defining a peripheral active region 6a on the semiconductor substrate 4, peripheral circuitry 8 formed on the semiconductor substrate 4, and a lower insulating layer 13 covering the peripheral circuitry 8 on the semiconductor substrate 4. The peripheral circuitry 8 may include circuit devices 9 such as transistors and circuit interconnects 11 electrically connected to the circuit devices 9, the circuit devices 9 including peripheral gates 9a and peripheral source / drains 9b. A portion of the circuit interconnects 11 may be peripheral pads 11p. A pattern structure 17 may be disposed on the lower insulating layer 13.

[0036] In the example, the first structure 3 may also include an intermediate insulating layer 19 on the side surface of the patterned structure 17.

[0037] The second structure 21 may include: a stacked structure 24, which includes an interlayer insulating layer 27 and a gate layer 30 alternately stacked in the vertical direction Z; a plurality of memory vertical structures 39 penetrating the stacked structure 24; a plurality of separation structures 60 penetrating the stacked structure 24; and a plurality of support vertical structures 54 penetrating the stacked structure 24. The second structure 21 may also include an upper insulating layer 65 covering the stacked structure 24. The memory vertical structures 39, the plurality of separation structures 60, and the plurality of support vertical structures 54 may extend upward from the portions penetrating the stacked structure 24.

[0038] In the example, the second structure 21 may include a first region MCA and a second region SA. The first region MCA may be a memory cell array region. The second region SA may be a stepped region. The second region SA may be referred to as an extended region or a gate contact region.

[0039] In the following text, the first region MCA will be referred to as the storage cell array region, and the second region SA will be referred to as the ladder region.

[0040] In an example embodiment, the second pattern layer 17b may be disposed below the memory cell array region MCA, while the fourth pattern layer 17d may be disposed below the step region SA.

[0041] Gate layers 30 can be stacked vertically in the Z direction and spaced apart from each other in the memory cell array region MCA, and can extend from the memory cell array region MCA into the stepped region SA to have a stepped shape. Therefore, gate layer 30 may include gate pads 30Pa, 30Pb, and 30Pc arranged in a stepped shape in the stepped region SA. Each of the gate pads 30Pa, 30Pb, and 30Pc of gate layer 30 can refer to an area that is exposed and not covered by another gate layer to form a stepped shape.

[0042] The stepped region SA may include a first stepped region SA1, a buffer region BA, and a second stepped region SA2, which are sequentially arranged in the first horizontal direction X and spaced apart from the storage cell array region MCA.

[0043] The gate layer 30 may include one or more lower gate layers 30L1 and 30L2, one or more upper gate layers 30U1 and 30U2, a plurality of intermediate gate layers 30M disposed between the one or more lower gate layers 30L1 and 30L2 and the one or more upper gate layers 30U1 and 30U2, and a buffer gate layer 30B disposed between the plurality of intermediate gate layers 30M and the one or more upper gate layers 30U1 and 30U2.

[0044] In an example embodiment, one or more upper gate layers 30U1 and 30U2 may be configured as a plurality of upper gate layers 30U1 and 30U2 spaced apart from each other in the vertical direction Z. For example, the plurality of upper gate layers 30U1 and 30U2 may include a first upper gate layer 30U1 and a second upper gate layer 30U2 disposed below the first upper gate layer 30U1.

[0045] In an example embodiment, one or more lower gate layers 30L1 and 30L2 may be a plurality of lower gate layers 30L1 and 30L2 spaced apart from each other in the vertical direction Z. For example, the plurality of lower gate layers 30L1 and 30L2 may include a first lower gate layer 30L1 and a second lower gate layer 30L2 disposed on the first lower gate layer 30L1.

[0046] In the example embodiment, a portion of the plurality of intermediate gate layers 30M may be word lines.

[0047] In an example embodiment, the first lower gate layer 30L1 may be the ground select gate line of a ground select transistor, while the second lower gate layer 30L2 may be a dummy gate line. In another example, the first lower gate layer 30L1 may be the erase control gate line of an erase control transistor used in an erase operation to erase data stored in a memory cell using the gate-induced drain leakage (GIDL) phenomenon.

[0048] In an example embodiment, the plurality of upper gate layers 30U1 and 30U2 may be the string select gate lines of a string select transistor. In another example, among the plurality of upper gate layers 30U1 and 30U2, the first upper gate layer 30U1 may be the erase control gate line of an erase control transistor, while the second upper gate layer 30U2 may be the string select gate line of a string select transistor.

[0049] The gate pads 30Pa of multiple upper gate layers 30U1 and 30U2 can be disposed in the first step region SA1, the gate pads 30Pb of the buffer gate layer 30B can be disposed in the buffer step region BA, and the gate pads 30Pc of multiple intermediate gate layers 30M and multiple lower gate layers 30L1 and 30L2 can be disposed in the second step region SA2.

[0050] In the example, each gate layer 30 may include a first layer 30a (in... Figure 2C and Figure 2D (middle) and the second layer 30b (in Figure 2C and Figure 2D(In the middle). The first layer 30a may cover the upper and lower surfaces of the second layer 30b and may also cover a portion of the side surfaces of the second layer 30b. For example, the first layer 30a may include a portion between the second layer 30b and the memory vertical structure 39 and a portion between the second layer 30b and the plurality of support vertical structures 54. In an example embodiment, the portion of the first layer 30a between the second layer 30b and the memory vertical structure 39 may contact the memory vertical structure 39, while the portion of the first layer 30a between the second layer 30b and the plurality of support vertical structures 54 may contact the plurality of support vertical structures 54. The first layer 30a and the second layer 30b may contact the separation structure 60. As used herein, unless the context otherwise requires, the term “contact” means a direct connection (i.e., contact).

[0051] In the example, the first layer 30a may include a dielectric material, while the second layer 30b may include a conductive material. For example, the first layer 30a may include a high-k dielectric material such as AlO, while the second layer 30b may include a conductive material such as TiN, WN, Ti, or W.

[0052] In another example, the first layer 30a may include a first conductive material (e.g., TiN, WN, etc.), while the second layer 30b may include a second conductive material (e.g., Ti, W, etc.) that is different from the first conductive material.

[0053] In another example, each gate layer 30 may be formed of one or more of doped polysilicon, metal-semiconductor compounds (e.g., TiSi, TaSi, CoSi, NiSi or WSi), metal nitrides (e.g., TiN, TaN or WN), or metals (e.g., Ti or W).

[0054] Multiple memory vertical structures 39 can pass through the stacked structure 24 in the memory cell array region MCA. Multiple memory vertical structures 39 can contact the patterned structure 17.

[0055] The second structure 21 may further include a string separation pattern 51 extending longitudinally in the first horizontal direction X and passing through the plurality of upper gate layers 30U1 and 30U2. The string separation pattern 51 may penetrate the buffer gate layer 30B. The string separation pattern 51 may include an insulating material such as silicon oxide. The string separation pattern 51 may be disposed at a level higher than the plurality of intermediate gate layers 30M. For example, the lower surface of the string separation pattern 51 may be at a vertical level higher than the upper surface of the plurality of intermediate gate layers 30M.

[0056] The second structure 21 may also include a dummy vertical structure 39d with the same material and cross-sectional structure as the multiple memory vertical structures 39. The dummy vertical structure 39d penetrates the string separation pattern 51 and extends downward, penetrating multiple intermediate gate layers 30M and multiple lower gate layers 30L1 and 30L2.

[0057] The plurality of separation structures 60 may include a plurality of main separation structures 60M parallel to each other. The plurality of main separation structures 60M may include a first separation structure 60M1 and a second separation structure 60M2 adjacent to each other.

[0058] Multiple main separation structures 60M can penetrate the stacked structure 24, and the stacked structure 24 can be separated by multiple main separation structures 60M in the second horizontal direction Y. The second horizontal direction Y can be perpendicular to the first horizontal direction X.

[0059] The plurality of separation structures 60 may also include a plurality of sub-separation structures 60SI and 60SO. For example, between the first separation structure 60M1 and the second separation structure 60M2 that are adjacent to each other, the plurality of sub-separation structures 60SI and 60SO may include an inner separation structure 60SI and an outer separation structure 60SO.

[0060] The inner separation structure 60SI may include a first inner separation structure 60SIa and a second inner separation structure 60SIb. The first inner separation structure 60SIa may contact the string separation pattern 51 and may be disposed in the first stepped region SA1. The second inner separation structure 60SIb may be disposed in the memory cell array region MCA and the first stepped region SA1.

[0061] The outer separation structure 60SO can be disposed in the second step region SA2. The end of the outer separation structure 60SO can extend into the buffer region BA, and the end of the inner separation structure 60SI can extend into the buffer region BA.

[0062] The inner separation structure 60SI can be spaced apart from the outer separation structure 60SO.

[0063] The inner separation structure 60SI can penetrate and contact multiple lower gate layers 30L1 and 30L2, multiple intermediate gate layers 30M, buffer gate layer 30B, and multiple upper gate layers 30U1 and 30U2. The inner separation structure 60SI can contact the patterned structure 17.

[0064] The outer separation structure 60S0 can penetrate and contact multiple lower gate layers 30L1 and 30L2 and multiple intermediate gate layers 30M, can contact the buffer gate layer 30B, and can be spaced apart from multiple upper gate layers 30U1 and 30U2. The outer separation structure 60SO can contact the patterned structure 17.

[0065] Each of the multiple sub-separation structures 60S may have a strip shape or a line shape extending along the first horizontal direction X.

[0066] In the example, between the first separation structure 60M1 and the second separation structure 60M2 that are adjacent to each other, n inner separation structures 60SI can be arranged in parallel in the second horizontal direction Y, and m outer separation structures 60SO can be arranged in parallel in the second horizontal direction Y, where n and m can be natural numbers.

[0067] In the example, n can be greater than m.

[0068] In the example, n can be odd, while m can be even.

[0069] In the example, when n is 5, m can be 4; when n is 7, m can be 6; and when n is 9, m can be 8.

[0070] In the example, each of the plurality of separation structures 60 may include a portion contacting the gate layer 30 and the interlayer insulating layer 27. For example, each of the plurality of separation structures 60 may include a first separation portion 60g contacting the gate layer 30 and the interlayer insulating layer 27, and a second separation portion 60i contacting the first separation portion 60g and the interlayer insulating layer 27. The second separation portion 60i may be above and below the first separation portion 60g. The width of the first separation portion 60g may be greater than the width of the second separation portion 60i adjacent to the first separation portion 60g. For example, the width of one of the first separation portions 60g may be greater than the width of the second separation portion 60i adjacent to the upper and lower portions of the first separation portion 60g.

[0071] In the example, the multiple supporting vertical structures 54 may include an inner supporting vertical structure 54I that penetrates the stacked structure 24 in the first step region SA1, a buffer supporting vertical structure 54B that penetrates the stacked structure 24 in the buffer region BA, and an outer supporting vertical structure 54O that penetrates the stacked structure 24 in the second step region SA2.

[0072] Multiple supporting vertical structures 54 can prevent deformation of the stacked structure 24 in the stepped region SA. Therefore, multiple supporting vertical structures 54 can improve the reliability of the semiconductor device 1.

[0073] In the example, between the first separation structure 60M1 and the second separation structure 60M2 that are adjacent to each other, the inner support vertical structure 54I can be set around the center of each gate pad 30Pa of the upper gate layers 30U1 and 30U2.

[0074] In the example, the number of inner support vertical structures 54I arranged sequentially in the horizontal direction Y between the first separation structure 60M1 and the second separation structure 60M2 that are adjacent to each other can be greater than the number of outer support vertical structures 54O arranged sequentially in the second horizontal direction Y.

[0075] In the example, the number of buffer support vertical structures 54B arranged sequentially in the second horizontal direction Y between the first separation structure 60M1 and the second separation structure 60M2 that are adjacent to each other can be less than the number of inner support vertical structures 54I, but can be greater than the number of outer support vertical structures 54O arranged sequentially in the second horizontal direction Y.

[0076] In the example, each of the plurality of supporting vertical structures 54 may be formed of an insulating material, silicon oxide, or porous silicon oxide. The cross-sectional structure of each of the plurality of supporting vertical structures 54 may differ from the cross-sectional structure of each of the memory vertical structures 39. For example, the memory vertical structure 39 may include a channel material layer, while the plurality of supporting vertical structures 54 may not include a channel material layer. For example, the plurality of supporting vertical structures 54 may not include a channel material layer.

[0077] In one example, the plurality of separation structures 60 may be formed of an insulating material, silicon oxide, or silicon oxide with voids. In another example, each of the plurality of separation structures 60 may include a conductive pattern and insulating spacers covering the side surfaces of the conductive pattern.

[0078] In the example, the lower end of each of the plurality of supporting vertical structures 54 may be positioned at a different level than the lower ends of the plurality of separating structures 60 adjacent to the plurality of supporting vertical structures 54. For example, among the plurality of supporting vertical structures 54, the lower end of one of the first inner supporting vertical structures 54I may be positioned at a different level than the lower end of one of the separating structures 60 adjacent to the first inner supporting vertical structure 54I (e.g., the lower end of the main separating structure 60M). The lower end of the first inner supporting vertical structure 54I may be positioned at a higher level than the lower end of the main separating structure 60M adjacent to the first inner supporting vertical structure 54I.

[0079] The second structure 21 may further include a gate contact plug 70g, a source contact plug 70s, and a peripheral contact plug 70p. The gate contact plug 70g may be disposed on the gate pads 30Pc of the lower gate layers 30L1 and 30L2 and the intermediate gate layer 30M, and on the gate pads 30Pa of the upper gate layers 30U1 and 30U2. The source contact plug 70s may contact the first pattern layer 17a of the pattern structure 17 and may extend upwards. The peripheral contact plug 70p may extend downwards from the portion penetrating the second structure 21 and may contact the peripheral pads 11p of the circuit interconnect 11. The second structure 21 may also include a bit line contact plug 70b electrically connected to the memory vertical structure 39.

[0080] In the example, at the same level as the gate layer 30, at least one of the inner support vertical structures 54I may contact one of the main separation structure 60M and the inner separation structures 60SIa and 60SIb. For example, at at least one level of the same level as the gate layer 30, one of the inner support vertical structures 54I may contact one of the adjacent separation structures 60 of the main separation structure 60M and the inner separation structures 60SIa and 60SIb.

[0081] For example, such as Figure 2C As shown, the inner support vertical structure 54I may include one of the main separation structure 60M and inner separation structures 60SIa and 60SIb. For example, a pair of inner support vertical structures 54Ia and 54Ib may be disposed on both sides of the first inner separation structure 60SIa. At at least one level of the same level as the gate layer 30, at least one of the pair of inner support vertical structures 54Ia and 54Ib may be in contact with at least a portion of the side surface of the first inner separation structure 60SIa.

[0082] In the example, at least one of the inner supporting vertical structures 54Ia and 54Ib can be spaced apart from the side surface of the first inner separation structure 60SIa at a "gate level" that can range from the same level as the lower gate layers 30L1 and 30L2 to the level at which a portion of the intermediate gate layer 30M is disposed, and at least one of the inner supporting vertical structures 54Ia and 54Ib can contact the side surface of the first inner separation structure 60SIa at a "gate level" that can range from the level at which other portions of the intermediate gate layer 30M are disposed to the level at which the upper gate layers 30U1 and 30U2 are disposed. The term "gate level" can refer to the vertical level at which the gate layer 30 is disposed. For example, as Figure 2CAs shown, at least one of the pair of inner supporting vertical structures 54Ia and 54Ib can be spaced apart from the side surface of the first inner separation structure 60SIa at the level of the first intermediate gate layer 30M1 disposed at the first level in the intermediate gate layer 30M, and can be in contact with the side surface of the first inner separation structure 60SIa at the level of the second intermediate gate layer 30M2 disposed at the second level above the first level in the intermediate gate layer 30M.

[0083] Therefore, at the same level as the gate layer 30, the side surface of one of the inner support vertical structures 54I can be adjacent to one of the main separation structure 60M and the inner separation structures 60SIa and 60SIb. For example, the upper part can contact the first inner separation structure 60SIa, while the lower part can not contact the first inner separation structure 60SIa. Figure 2C The upper part may be a portion of the side surface of the inner support vertical structure 54I at the same level as the first upper gate layer 30U1 or the same level as the second intermediate gate layer 30M2. The lower part may be a portion of the side surface of the inner support vertical structure 54I at the same level as the first lower gate layer 30L1 or the same level as the first intermediate gate layer 30M1.

[0084] In the example, the external support vertical structure 54O can be spaced apart from the separate structure 60.

[0085] In the following description, reference will be made to Figures 3A to 3D Describes the horizontal planar shape of a portion of the gate layer 30.

[0086] Figure 3A It is a plan view showing the horizontal planar shape of the first upper gate layer 30U1. Figure 3B It is a horizontal plan view of the second intermediate gate layer 30M2.

[0087] Figure 3C It is a plan view showing the horizontal planar shape of the first intermediate gate layer 30M1. Figure 3D It is a plan view showing the horizontal planar shape of the first lower gate layer 30L1. Figure 1A and Figure 1B It could be a plan view showing each element as seen from above.

[0088] Reference Figure 3AAt the level where the first upper gate layer 30U1 is disposed, each of the portion 60ML1 of the main separation structure 60M and the isolation portions 60SIaL1 and 60SIbL1 of the inner separation structures 60SIa and 60SIb may include a first portion 60aL1 that contacts the first upper gate layer 30U1 and a second portion 60bL1 that does not contact the first upper gate layer 30U1. The width of the first portion 60aL1 in the second direction Y may be greater than the width of the second portion 60bL1 in the second direction Y.

[0089] At the level where the first upper gate layer 30U1 is disposed, at least one of the portions 54IL1 of the inner support vertical structure 54I may contact the adjacent first portion 60aL1. At least one of the portions 54IL1 of the inner support vertical structure 54I may have a shape that extends into the first portion 60aL1.

[0090] At the level where the first upper gate layer 30U1 is provided, the width of each of the portions 60SOL1 of the outer separation structure 60SO in the second direction Y can be equal to the width of the second portion 60bL1 in the second direction Y, and the width in the second direction Y can be less than the width of the first portion 60aL1 in the second direction Y.

[0091] Reference Figure 3B At the level where the second intermediate gate layer 30M2 is disposed, each of the portion 60ML2 of the main separation structure 60M and the portion 60SOL2 of the outer separation structure 60SO may include a third portion 60aL2 that contacts the second intermediate gate layer 30M2 and a fourth portion 60bL2 that does not contact the second intermediate gate layer 30M2. The width of the third portion 60aL2 in the second direction Y may be greater than the width of the fourth portion 60bL2 in the second direction Y.

[0092] At the level where the second intermediate gate layer 30M2 is provided, the width of each of the portions 60SIaL2 and 60SIbL2 of the inner separation structures 60SIa and 60SIb in the second direction Y can be substantially equal to the width of the third portion 60aL2 in the second direction Y.

[0093] In the example, at the level where the second intermediate gate layer 30M2 is disposed, at least one of the portions 54IL2 of the inner support vertical structure 54I can contact one of the portions 60SIaL2 and 60SIbL2 of the inner separation structures 60SIa and 60SIb.

[0094] In the example, at the level where the second intermediate gate layer 30M2 is disposed, at least one of the portions 54BL2 of the buffer support vertical structure 54B can contact the adjacent discrete structures 60M, 60SIa, 60SIb and 60SO.

[0095] In the example, on the horizontal plane where the second intermediate gate layer 30M2 is provided, a portion 54OL2 of the outer support vertical structure 54O can be spaced apart from the main separation structure 60M and the outer separation structure 60SO.

[0096] Reference Figure 3C At the level where the first intermediate gate layer 30M1 is disposed, each of the portion 60ML3 of the main separation structure 60M and the portion 60SOL3 of the outer separation structure 60SO may include a fifth portion 60aL3 that contacts the first intermediate gate layer 30M1 and a sixth portion 60bL3 that does not contact the first intermediate gate layer 30M1. The width of the fifth portion 60aL3 in the second direction Y may be greater than the width of the sixth portion 60bL3 in the second direction Y.

[0097] At the level where the first intermediate gate layer 30M1 is provided, the width of each of the portions 60SIaL3 and 60SIbL3 of the inner separation structures 60SIa and 60SIb in the second direction Y can be substantially the same as the width of the fifth portion 60aL3 in the second direction Y.

[0098] In the example, at the level where the intermediate gate layer 30M1 is disposed, at least one of the portions 54IL3 of the inner supporting vertical structure 54I can be spaced apart from portions 60SIaL3 and 60SIbL3 of the inner separation structures 60SIa and 60SIb. For example, at the level where the first intermediate gate layer 30M1 is disposed, the portion 54IL3 of the inner supporting vertical structure 54I can be spaced apart from the adjacent inner separation structures 60SIa and 60SIb by a first distance D1.

[0099] In the example, at least one of the portions 54BL3 of the buffer support vertical structure 54B can be spaced apart from the adjacent separation structures 60M, 60SIa, 60SIb and 60SO on the horizontal level where the first intermediate gate layer 30M1 is disposed.

[0100] In the example, on the horizontal plane where the first intermediate gate layer 30M1 is provided, a portion 54OL3 of the outer support vertical structure 54O can be spaced from the adjacent main separation structure 60M and the adjacent outer separation structure 60SO by a second distance D2 greater than the first distance D1.

[0101] Reference Figure 3DAt the level where the first lower gate layer 30L1 is disposed, a portion 60ML4 of the main separation structure 60M and a portion 60SOL4 of the outer separation structure 60SO may include a seventh portion 60aL4 layer 30L1 that contacts the first lower gate layer 30L1 and an eighth portion 60bL4 that does not contact the first lower gate layer 30L1. The width of the seventh portion 60aL4 in the second direction Y may be greater than the width of the eighth portion 60bL4 in the second direction Y.

[0102] At the level where the first lower gate layer 30L1 is provided, the width of each of the portions 60SIaL4 and 60SIbL4 of the inner separation structures 60SIa and 60SIb in the second direction Y can be substantially equal to the width of the seventh portion 60aL4 in the second direction Y.

[0103] In the example, at the level where the first lower gate layer 30L1 is disposed, at least one of the portions 54IL4 of the inner supporting vertical structure 54I can be spaced apart from portions 60SIaL4 and 60SIbL4 of the inner separation structures 60SIa and 60SIb. For example, at the level where the first lower gate layer 30L1 is disposed, a portion 54IL4 of the inner supporting vertical structure 54I can be spaced apart from portions of adjacent inner separation structures 60SIa and 60SIb by a third distance D3.

[0104] In the example, at the level where the first lower gate layer 30L1 is provided, at least one of the portions 54BL4 of the buffer support vertical structure 54B can be spaced apart from the adjacent separation structures 60M, 60SIa, 60SIb and 60SO.

[0105] In the example, on the horizontal plane where the first lower gate layer 30L1 is provided, a portion 54OSL4 of the outer support vertical structure 54O can be spaced from the main separation structure 60M and the outer separation structure 60SO by a fourth distance D4 greater than the third distance D3.

[0106] In the example embodiment, the third distance D3 can be greater than... Figure 3C The first distance D1 in the middle.

[0107] In the example embodiment, the fourth distance D4 can be greater than... Figure 3C The second distance D2 in the equation.

[0108] By setting up multiple separation structures 60 and multiple support structures 54 as described above, a greater number of memory vertical structures 39 can be set up, and deformation of the stacked structure 24 can be prevented, thereby improving the integration density and reliability of the semiconductor device 1.

[0109] In the following description, reference will be made to Figure 4 An example structure describing the vertical structure 39 of the memory described above. Figure 4 It shows Figure 2A The enlarged cross-sectional view of part "B" in the image is shown, and an example embodiment will be described based on the memory vertical structure 39.

[0110] Reference Figure 4 The vertical structure 39 of the memory may include an insulating gap filling layer 46, a channel material layer 44 covering the outer surface and bottom surface of the insulating gap filling layer 46, a data storage structure 42 covering the outer surface and bottom surface of the insulating gap filling layer 46, and a pad material layer 48 on the insulating gap filling layer 46.

[0111] The data storage structure 42 may include a first dielectric layer 42c covering the outer and bottom surfaces of the channel material layer 44, a data storage material layer 42b covering the outer and bottom surfaces of the first dielectric layer 42c, and a second dielectric layer 42a covering the outer and bottom surfaces of the data storage material layer 42b. The first dielectric layer 42c may be in contact with the channel material layer 44, while the data storage material layer 42b may be spaced apart from the channel material layer 44.

[0112] For example, the insulating gap filling layer 46 may include silicon oxide, silicon oxide that can be formed by an atomic layer deposition process, or silicon oxide in which voids are formed.

[0113] The second dielectric layer 42a may comprise silicon oxide or silicon oxide doped with impurities. The first dielectric layer 42c may comprise at least one of silicon oxide and a high-k dielectric. For example, the data storage material layer 42b may comprise a material for trapping charge, such as silicon nitride.

[0114] The data storage material layer 42b of the data storage structure 42 of the vertical memory structure 39 may include regions for storing data in a semiconductor device such as a flash memory device. The channel material layer 44 may include polysilicon. The pad material layer 48 may include at least one of doped polysilicon, metal nitride (e.g., TiN, etc.), metal (e.g., W, etc.), and metal-semiconductor compound (e.g., TiSi, etc.).

[0115] The memory vertical structure 39 can sequentially penetrate the third pattern layer 17c and the second pattern layer 17b of the pattern structure 17, and can extend into the first pattern layer 17a.

[0116] In the pattern structure 17, the second pattern layer 17b can penetrate the data storage structure 42, isolate the lower part 42L of the data storage structure 42 from the upper part 42U of the data storage structure 42, and can contact the channel material layer 44.

[0117] In the following description, reference will be made to Figure 5 describe Figure 4Modified examples of the memory vertical structure 39 and pattern structure 17 described herein. Figure 5 This illustrates the reference in the foregoing example embodiments. Figure 4 Enlarged view of the modified example of the described memory vertical structure 39 and stacked structure 24.

[0118] Reference Figure 5 The lower part of the vertical memory structure 39' may include: an epitaxial channel layer 40, which includes a portion disposed in the patterned structure 17' with its upper surface positioned at a level higher than the upper surface of the first lower gate layer 30L1 and lower than the lower surface of the second lower gate layer 30L2; an insulating gap filler layer 46 disposed on the epitaxial channel layer 40; a channel material layer 44 located between the insulating gap filler layer 46 and the epitaxial channel layer 40 and covering the side surface of the insulating gap filler layer 46; and a data storage structure 42' covering the outer surface of the channel material layer 44. The data storage structure 42' may include a first dielectric layer 42c, a second dielectric layer 42a, and a data storage material layer 42b between the first dielectric layer 42c and the second dielectric layer 42a.

[0119] The lower part of the vertical structure 39' of the memory may also include a dielectric layer 28 between the first lower gate layer 30L1 and the epitaxial channel layer 40.

[0120] In the following description, reference will be made to Figure 6 Describe a modified example of the vertical memory structure 39 and the stacked structure 24. Figure 6 It shows Figure 4 Enlarged cross-sectional view of the modified example of the memory vertical structure 39 and stacked structure 24 shown.

[0121] Reference Figure 6 The stacking structure 24' may include a lower stacking structure 24L and an upper stacking structure 24U on the lower stacking structure 24L.

[0122] Each of the lower stacked structure 24L and the upper stacked structure 24U may include alternately stacked interlayer insulating layers 27 and gate layers 30. The lower stacked structure 24L may include the lower gate layers 30L1 and 30L2 described above, while the upper stacked structure 24U may include the upper gate layers 30U1 and 30U2 described above.

[0123] The memory vertical structure 39' may include a lower vertical portion 39L that penetrates the lower stacked structure 24L and an upper vertical portion 39U that penetrates the upper stacked structure 24U.

[0124] In the example embodiment, the width of the upper region of the lower vertical portion 39L may be different from the width of the lower region of the upper vertical portion 39U. For example, the width of the upper region of the lower vertical portion 39L may be greater than the width of the lower region of the upper vertical portion 39U.

[0125] In an exemplary embodiment, the side surfaces of the lower vertical portion 39L and the upper vertical portion 39U, which are adjacent to each other, may not be aligned in the vertical direction Z.

[0126] In the example, the side surface of the memory vertical structure 39' may include a curved portion at the level between the uppermost gate layer in the gate layer 30 of the lower stacked structure 24L and the lowermost gate layer in the gate layer 30 of the upper stacked structure 24U.

[0127] As described above, the outer support vertical structure 54O may be spaced apart from the main separation structure 60M and the outer separation structure 60SO, but its exemplary embodiments are not limited thereto. For example, at least a portion of the outer support vertical structure 54O may contact one of the adjacent main separation structure 60M and the adjacent outer separation structure 60SO. (Refer to...) Figure 7A and Figure 7B An example embodiment is described above, in which at least a portion of the external support vertical structure 54O can contact one of the adjacent main separation structure 60M and the adjacent external separation structure 60SO. Figure 7A It is shown in relation to Figure 3B A plan view of the planar shape at the same level as the second intermediate gate layer 30M2 in the middle. Figure 7B It shows along Figure 2D A cross-sectional view of a modified example of the cross-sectional structure intercepted by line IV-IV' in the diagram. (Refer to...) Figure 7A and Figure 7B Main description Figure 3B and Figure 2D The example shown is a modified example, and the description of other elements will not be repeated.

[0128] In the modified example, refer to Figure 7A and Figure 7B At least a portion of the outer support vertical structure 54O' can contact one of the adjacent main separation structure 60M and the adjacent outer separation structure 60SO. For example, at the level where the second intermediate gate layer 30M2 is disposed, at least one of the portions 54OL2' of the outer support vertical structure 54O' can contact one of the portions 60ML2 of the adjacent main separation structure 60M and the portions 60SOL2 of the adjacent outer separation structure 60SO.

[0129] like Figure 7B As shown, on the horizontal plane where the first intermediate gate layer 30M1 and the first lower gate layer 30L1 are provided, a portion of the outer support vertical structure 54O' can be spaced apart from portions of the adjacent main separation structure 60M and the adjacent outer separation structure 60SO.

[0130] In the following description, reference will be made to Figure 8A and Figure 8B This describes a modified example of the aforementioned internal support vertical structure 54I. Figure 8A It is shown in relation to Figure 3A A plan view of the same horizontal planar shape as the first upper gate layer 30U1 in the middle. Figure 8B It shows along Figure 2C A cross-sectional view of a modified example of the cross-sectional structure intercepted by line IIIa-IIIa'. The following description will primarily focus on... Figure 3A and Figure 2C The example in the example is a modified example, or it will directly reference other components.

[0131] In the modified example, refer to Figure 8A and Figure 8B In the internal support vertical structure 54I, the center of one of the main separation structure 60M and the internal separation structures 60SIa and 60SIb, and the center of the internal support vertical structure 54Ia of the pair of internal support vertical structures 54Ia and 54Ib arranged on both sides of the internal separation structure 60SIa, can be closer to the center of the internal separation structure 60SIa than the center of the other internal support vertical structure 54Ib. For ease of explanation, in Figure 8B In this structure, the inner support vertical structure 54Ia located on the left side of the first inner separation structure 60SIa will be referred to as the first support vertical structure, while the inner support vertical structure 54Ib located on the right side of the first inner separation structure 60SIa will be referred to as the second support vertical structure.

[0132] The distance between the center of the first inner separation structure 60SIa and the center of the first supporting vertical structure 54Ia can be less than the distance between the center of the first inner separation structure 60SIa and the center of the second supporting vertical structure 54Ib.

[0133] The distance between the center of the first inner separation structure 60SIa and the center of the first supporting vertical structure 54Ia can be greater in the lower region (e.g., the region at a relatively low level in the vertical direction Z) than in the upper region (e.g., the region at a relatively high level in the vertical direction Z).

[0134] The distance between the center of the first inner separation structure 60SIa and the center of the second supporting vertical structure 54Ib can be greater in the lower region than in the upper region.

[0135] The first inner separation structure 60SIa and the second supporting vertical structure 54Ib can be in contact with each other at the upper vertical level, and can be spaced apart from each other at the middle vertical level or the lower vertical level. For example, at the same level as the first upper gate layer 30U1, the first inner separation structure 60SIa and the second supporting vertical structure 54Ib can be in contact with each other, while at the same level as the first middle gate layer 30M1 and the first lower gate layer 30L1, the first inner separation structure 60SIa and the second supporting vertical structure 54Ib can be spaced apart from each other.

[0136] In the first supporting vertical structure 54Ia, the first inner separation structure 60SIa can contact the first supporting vertical structure 54Ia at a level from the level where the first lower gate layer 30L1 is disposed to the level where the first upper gate layer 30U1 is disposed.

[0137] In the example embodiment, at the level where the gate layer 30 is provided, the first inner separation structure 60SIa and the first supporting vertical structure 54Ia can be in contact with each other, while at other levels, such as at the level where the interlayer insulating layer 27 is provided, the first inner separation structure 60SIa and the first supporting vertical structure 54Ia can be spaced apart from each other.

[0138] like Figure 8A As shown, on the horizontal plane where the first upper gate layer 30U1 is disposed, the first support portion 54IL1a and the second support portion 54IL1b of the inner support vertical structure 54I (e.g., the first support portion 54IL1a and the second support portion 54IL1b disposed on both sides of the isolation portion 60SIaL1) may include a portion 60ML1 of the main separation structure 60M and one of the isolation portions 60SIaL1 and 60SIbL1 of the inner separation structures 60SIa and 60SIb. The contact area between the first support portion 54IL1a and the isolation portion 60SIaL1 may be larger than the contact area between the second support portion 54IL1b and the isolation portion 60SIaL1.

[0139] In the following description, reference will be made to Figure 9A and Figure 9B This describes a modified example of the aforementioned internal support vertical structure 54I. Figure 9A It shows Figure 2B The diagram shows a modified example of the internal support vertical structure 54I in the enlarged plan view. Figure 9B It shows along Figure 9A A cross-sectional view of the region intercepted by line IIIb-IIIb' in the diagram. Figure 9B It can be shown in Figure 2C A cross-sectional view of an example in which the internally supported vertical structure 54I in the cross-sectional structure is modified to form an internally supported vertical structure 154I. In the following description, reference will be made to... Figure 9A and Figure 9B Main description Figure 1B and Figure 2C This is a modified example of the example in the document, and will not provide descriptions of other components or will directly reference other components.

[0140] In the modified example, refer to Figure 9A and Figure 9B At a level higher than the first upper gate layer 30U1, the inner support vertical structure 154I can contact the adjacent separation structure in the main separation structure 60M and the inner separation structures 60SIa and 60SIb.

[0141] In the example, at a level lower than the first upper gate layer 30U1, the inner support vertical structure 154I can contact the adjacent separation structure in the main separation structure 60M and the inner separation structures 60SIa and 60SIb.

[0142] In the example, such as Figure 9A In the plane, at a level higher than the first upper gate layer 30U1, for example, the main separation structure 60M and the inner separation structures 60SIa and 60SIb may have a shape that partially cuts off the adjacent inner support vertical structure 154I. Therefore, at least one of the inner support vertical structures 154I may have a linearly shaped side surface that contacts the adjacent separation structures in the main separation structure 60M and the inner separation structures 60SIa and 60SIb, and a side surface that does not contact the separation structures and forms a curved surface.

[0143] Based on the above references Figures 1A to 9B In the example embodiments described, reference is made to Figures 2A to 2E The semiconductor substrate 4 and peripheral circuitry 8 described may be disposed below the stacked structure 24. However, exemplary embodiments thereof are not limited thereto. For example, refer to... Figures 2A to 2E The semiconductor substrate 4 and peripheral circuitry 8 described herein can be disposed above the stacked structure 24. In the following description, reference will be made to... Figure 10 To describe reference Figures 2A to 2E An example of a semiconductor substrate 4 and peripheral circuitry 8 disposed above a stacked structure 24 is described. Although no reference is provided. Figures 1A to 9B The described elements include, for example, the separation structure 60 that penetrates the stacked structure 24 and the supporting vertical structure 54, but refer to... Figure 10 Examples of modifications described may include references Figures 1A to 9B Elements such as the separation structure 60 and the supporting vertical structure 54 described in the foregoing example embodiments.

[0144] In the modified example, refer to Figure 10 The semiconductor device 1' according to the example embodiment may include a lower structure 121 and an upper structure 103 stacked in the vertical direction Z.

[0145] The lower structure 121 can be called the second structure, while the upper structure 103 can be called the first structure.

[0146] The lower structure 121 may include references Figures 1A to 2E The stacked structure 24, memory vertical structure 39, bit line contact plug 70b, gate contact plug 70g, and source contact plug 70s described in the foregoing example embodiments.

[0147] The lower structure 121 may further include a pattern structure 117. The pattern structure 117 may be related to a reference. Figures 1A to 2E The pattern structure 17 described in the foregoing example embodiments is substantially the same. For example, the pattern structure 117 may include patterns respectively related to reference... Figures 1A to 2E The first pattern layers 117a to 117d correspond to the first pattern layers 117a to 117d described in the foregoing example embodiments. When referring to orientation, layout, position, shape, size, quantity, or other measures, terms such as “same,” “equal,” “planar,” or “coplanar” as used herein do not necessarily mean exactly the same orientation, layout, position, shape, size, quantity, or other measures, but are intended to include, for example, substantially the same orientation, layout, position, shape, size, quantity, or other measures, within acceptable variations that may occur due to manufacturing processes. Unless the context or other statements otherwise indicate, the term “substantially” may be used herein to emphasize this meaning.

[0148] The lower structure 121 may cover the stacked structure 24 on the patterned structure 117, and may also include an upper insulating layer 165. The upper insulating layer 165 may be referenced... Figures 2A to 2E The upper insulating layer 65 described in the foregoing example embodiments is substantially the same.

[0149] The lower structure 121 may also include a bit line 151b electrically connected to the bit line contact plug 70b on the bit line contact plug 70b, a gate interconnect 151g electrically connected to the gate contact plug 70g on the gate contact plug 70g, and a source contact wiring 151a electrically connected to the source contact plug 70s on the source contact plug 70s.

[0150] The lower structure 121 may include a cover insulating structure 160 on the upper insulating layer 165, and a lower bonding interconnect structure 155 electrically connected to the bit line 151b, the gate interconnect 151g, and the source contact wiring 151a. The lower bonding interconnect structure 155 may include a lower bonding pad 155p.

[0151] The upper structure 103 may include a semiconductor substrate 204, peripheral circuitry 209 disposed between the semiconductor substrate 204 and the lower structure 121, and an upper bonding interconnect structure 211 electrically connected to the peripheral circuitry 209 between the peripheral circuitry 209 and the lower structure 121. The upper bonding interconnect structure 211 may include an upper bonding pad 211p. The peripheral circuitry 209 may be a transistor including a peripheral gate 209a and a peripheral source / drain 209b. The lower bonding pad 155p of the lower bonding interconnect structure 155 may contact the upper bonding pad 211p of the upper bonding interconnect structure 211. The lower bonding pad 155p may bond to the upper bonding pad 211p of the upper bonding interconnect structure 211. The lower bonding pad 155p and the upper bonding pad 211p may include copper material.

[0152] In the following description, reference will be made to Figure 11 Example embodiments describing methods for manufacturing semiconductor devices in example embodiments. Figure 11 This is a flowchart illustrating a method for manufacturing a semiconductor device according to an example embodiment.

[0153] Reference Figure 11 This can form a lower structure (S10). For example, the lower structure can be a reference. Figures 2A to 2E The first structure 3 is described in the foregoing example embodiment.

[0154] A preliminary stacked structure including an insulating layer and a sacrificial gate layer can be formed (S15). For example, the insulating layer can be a reference layer. Figures 2A to 2E The interlayer insulating layer 27 described in the foregoing example embodiments, and the sacrificial gate layer may be used to form a reference. Figures 2A to 2E The gate layer 30 as described in the foregoing example embodiment is a molded layer. The initial stacked structure can be formed in the shape and reference. Figures 1A to 2E The stacked structure 24 described in the foregoing example embodiments has a substantially the same shape.

[0155] Multiple vertical memory structures that penetrate the initial stacked structure can be formed (S20). For example, the multiple vertical memory structures can be... Figures 1A to 2E The vertical structure of multiple memory cells in the memory is 39.

[0156] Multiple supporting vertical structures (S25) can be formed that penetrate the initial stacked structure. For example, the multiple supporting vertical structures can be referenced. Figures 1A to 2E The aforementioned example embodiments describe a plurality of supporting vertical structures 54.

[0157] A separation trench penetrating the initial stacked structure can be formed (S30). Empty spaces can be formed by etching the sacrificial gate layer exposed by the separation trench (S35). A gate layer can be formed in the empty spaces (S40). For example, the gate layer can be... Figures 1A to 2E The gate layer 30 described in the text.

[0158] A separation structure that fills the separation trench can be formed (S45). In the above process S40, the gate layer may not completely fill the empty space. Therefore, the separation structure can fill the separation trench and also fill other parts of the empty space. The separation structure can be a reference. Figures 1A to 2E The separation structure 60 described in the foregoing example embodiment.

[0159] A contact plug can be formed (S50). For example, the contact plug can be... Figures 1A to 2E The bit line contact plug 70b, gate contact plug 70g, source contact plug 70s, and peripheral contact plug 70p are described in the document.

[0160] Interconnects can be formed (S55). For example, the interconnect can be a bit line electrically connected to the bit line contact plug 70b (e.g., it can be...). Figure 10 Bit line 151b), and gate interconnect electrically connected to gate contact plug 70g (e.g., it could be...). Figure 10 The gate interconnect 151g and the source interconnect electrically connected to the source contact plug 70s (e.g., may be) Figure 10 (Source contact wiring 151a in the middle).

[0161] In the following description, reference will be made to Figure 12 , Figure 13 and Figure 14 The description includes a data storage system for a semiconductor device according to an example embodiment.

[0162] Figure 12 This is a diagram illustrating a data storage system including a semiconductor device according to an example embodiment.

[0163] Reference Figure 12 The data storage system 1000 according to an example embodiment may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be a storage device including the semiconductor device 1100, or an electronic device including a storage device. For example, the data storage system 1000 may be a solid-state drive (SSD) device including the semiconductor device 1100, a universal serial bus (USB), a computing system, a medical device, or a communication device.

[0164] In an example embodiment, the data storage system 1000 may be an electronic system for storing data.

[0165] Semiconductor device 1100 can be a reference Figures 1A to 10The semiconductor device described in one of the foregoing example embodiments. The semiconductor device 1100 may include a first structure 1100F and a second structure 1100S located on the first structure 1100F.

[0166] The first structure 1100F can be configured as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and a logic circuit 1130. For example, the first structure 1100F may include peripheral circuits ( Figure 2A The peripheral circuit 8 or Figure 10 (The upper bonding interconnect structure 211 in the middle).

[0167] The second structure 1100S can be configured as a memory cell structure, which includes a bit line BL, a common source line CSL, a word line WL, a first upper gate line UL1 and a second upper gate line UL2, a first lower gate line LL1 and a second lower gate line LL2, and a memory cell string CSTR between the bit line BL and the common source line CSL.

[0168] The above pattern structure 17 (in Figures 1A to 2E The middle part may include a silicon layer with N-type conductivity, and the silicon layer with N-type conductivity may be a common source line (CSL).

[0169] In the second structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In the example embodiment, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0170] In the example embodiment, upper transistors UT1 and UT2 may include string select transistors, while lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of memory cell transistor MCT, and gate upper lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0171] The aforementioned gate layer 115g can form gate lower lines LL1 and LL2, word lines WL, and gate upper lines UL1 and UL2.

[0172] In an example embodiment, lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series with each other. Upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series with each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT1 may be used in an erase operation, which is configured to erase data stored in memory cells by using a gate-induced drain leakage (GIDL) phenomenon.

[0173] A common source line CSL, first and second lower gate lines LL1 and LL2, a word line WL, and first and second upper gate lines UL1 and UL2 may be electrically connected to a decoder circuit 1110 through a first connection wiring 1115 extending from a first structure 1100F to a second structure 1100S.

[0174] In an example embodiment, the aforementioned lower gate layers 30L1 and 30L2 (in Figure 2A ) may be lower gate lines LL1 and LL2, while upper gate layers 30U1 and 30U2 (in Figure 2A ) may be upper gate lines UL1 and UL2. A plurality of intermediate gate layers 30M (in Figure 2A ) may be word lines WL.

[0175] A bit line BL may be electrically connected to a page buffer 1120 through a second connection wiring 1125 extending from the first structure 1100F to the second structure 1100S. The bit line BL may be electrically connected to the aforementioned bit line contact plug 70b (in Figure 2A ).

[0176] In the first structure 1100F, the decoder circuit 1110 and the page buffer 1120 may perform a control operation on at least one selected memory cell transistor among a plurality of memory cell transistors MCT. The decoder circuit 1110 and the page buffer 1120 may be controlled by a logic circuit 1130. The semiconductor device 1100 may communicate with a controller 1200 through an input / output pad 1101 electrically connected to the logic circuit 1130. The input / output pad 1101 may be electrically connected to the logic circuit 1130 through an input / output connection wiring 1135 extending from the first structure 1100F to the second structure 1100S.

[0177] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface 1230. In an example embodiment, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0178] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface 1221 for handling communication with semiconductor device 1100. Through NAND interface 1221, control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, data to be read from memory cell transistors (MCTs), etc., can be sent. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0179] Figure 13 This is a perspective view showing a data storage system including a semiconductor device according to an example embodiment.

[0180] Reference Figure 13 The data storage system 2000 according to an example embodiment may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003, and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 through wiring patterns 2005 formed on the main substrate 2001.

[0181] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In an example embodiment, the data storage system 2000 may communicate with the external host via one of the following: Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI-Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). In an example embodiment, the data storage system 2000 may operate using power supplied from the external host through the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0182] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0183] DRAM 2004 can be configured as a buffer memory to mitigate speed differences between semiconductor package 2003, data storage space, and external host. The DRAM 2004 included in the data storage system 2000 can also be used as a high-speed cache memory and can provide space for temporary data storage during control operations on semiconductor package 2003. When DRAM 2004 is included in the data storage system 2000, controller 2002 may include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0184] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each semiconductor chip 2200 may be included in a reference... Figures 1A to 10 The semiconductor device described in one of the foregoing example embodiments.

[0185] Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, a semiconductor chip 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each semiconductor chip 2200, a connection structure 2400 electrically connecting the semiconductor chip 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chip 2200 and the connection structure 2400 on the package substrate 2100.

[0186] The package substrate 2100 can be configured as a printed circuit board including on-package pads 2130. Each of the semiconductor chips 2200 may include input / output pads 2210.

[0187] In an example embodiment, the connection structure 2400 may be a bonding wire that electrically connects the input / output pads 2210 to the on-package pads 2130. Therefore, in each of the first and second semiconductor packages 2003a and 2003b, the semiconductor chips 2200 may be electrically connected to each other via a bonding wire method and may be electrically connected to the on-package pads 2130 of the package substrate 2100. In an example embodiment, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a connection structure (e.g., a through-silicon via (TSV)) rather than via the connection structure 2400 using a bonding wire method.

[0188] In an example embodiment, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate insertion substrate different from the main substrate 2001, and the controller 2002 may be connected to the semiconductor chip 2200 via wiring formed on the insertion substrate.

[0189] Figure 14 This is a cross-sectional view illustrating a data storage system including semiconductor devices according to an example embodiment. Figure 14 It shows Figure 13 Example embodiments of semiconductor packaging 2003 are shown, illustrating along... Figure 13 The cross-sectional area of ​​semiconductor package 2003 is taken by line VI-VI'.

[0190] Reference Figure 14 In semiconductor packaging 2003, packaging substrate 2100 can be configured as a printed circuit board. Packaging substrate 2100 may include a packaging substrate body portion 2120, an upper packaging pad disposed on the top surface of the packaging substrate body portion 2120, a lower packaging pad 2125 disposed on the lower surface of the packaging substrate body portion 2120 or exposed at the bottom, and internal wiring 2135 electrically connecting the upper pad 2130 and the lower pad 2125 in the packaging substrate body portion 2120. The upper pad 2130 can be electrically connected to a connection structure 2400. The lower pad 2125 can be connected to a wiring pattern 2005 of the main substrate 2010 of the data storage system 2000 via a conductive connection portion 2800.

[0191] Each semiconductor chip 2200 may include a semiconductor substrate 3010, a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region, which includes peripheral wiring 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 located on the common source line 3205, a memory channel structure 3220 penetrating the gate stack structure 3210 and a separation structure 3230, a bit line 3240 electrically connected to the memory channel structure 3220, and (in Figure 2A The gate interconnect 93b is electrically connected to the word line WL of the gate stack structure 3210. The first structure 3100 may include a gate interconnect 93b. Figure 12 The first structure 1100F and the second structure 3200 may include Figure 12 The second structure 1100S in it.

[0192] Each semiconductor chip 2200 may include a through-wire 3245 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200. The through-wire 3245 may penetrate the gate stack structure 3210 and may be further disposed on the outside of the gate stack structure 3210.

[0193] Each semiconductor chip 2200 may also include input / output connection wiring 3265 electrically connected to the peripheral wiring 3110 of the first structure 3100 and extending into the second structure 3200, and input / output pads 2210 electrically connected to the input / output connection wiring 3265.

[0194] exist Figure 14 In the figure, an enlarged portion, indicated by reference numeral 1, can be provided for description. Figure 14 The semiconductor chip 2200 in the middle can be modified to have, for example, Figure 2A Examples of cross-sectional structures are shown in Figure 1. Therefore, each semiconductor chip 2200 may include those shown in Figure 1 to... Figure 9B The semiconductor device 1 in one of the foregoing example embodiments or reference Figure 10 The semiconductor device 1' is described.

[0195] According to the foregoing example embodiments, a semiconductor device that can improve integration density and reliability, as well as a data storage system including the semiconductor device, can be provided.

[0196] While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and alterations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A semiconductor device, comprising: The stacked structure includes an interlayer insulating layer and a gate layer that are alternately stacked on the lower structure in a vertical direction; The memory has a vertical structure that passes through the stacked structure; Multiple separate structures pass through the stacked structure; as well as Multiple supporting vertical structures pass through the stacked structure. The gate layer includes: a lower gate layer; an upper gate layer on the lower gate layer; and a plurality of intermediate gate layers spaced apart from each other along the vertical direction between the lower gate layer and the upper gate layer. The plurality of separation structures include a first separation structure. The plurality of vertical support structures include a first inner vertical support structure that passes through the lower gate layer, the plurality of intermediate gate layers, and the upper gate layer. The first inner vertical support structure is adjacent to the first separation structure. Wherein, the first portion of the first internal support vertical structure is directly connected to the first discrete structure at the same level as the upper gate layer, and The second portion of the first inner support vertical structure is spaced apart from the first separation structure at the same level as the lower gate layer.

2. The semiconductor device according to claim 1, in, The plurality of intermediate gate layers includes a first intermediate gate layer. Wherein, the third portion of the first inner support vertical structure is spaced apart from the first separation structure by a first distance at the same level as the first intermediate gate layer, and Wherein, the second part of the first inner support vertical structure is spaced apart from the first separation structure by a second distance at the same level as the lower gate layer, and the second distance is greater than the first distance.

3. The semiconductor device according to claim 1, in, The plurality of supporting vertical structures also includes a first outer supporting vertical structure that is adjacent to and spaced apart from the first separating structure. Wherein, the distance between the vertical structure of the memory and the first external support vertical structure is greater than the distance between the vertical structure of the memory and the first internal support vertical structure, and The first external support vertical structure passes through at least one of the plurality of intermediate gate layers and the lower gate layer, and is spaced apart from the upper gate layer.

4. The semiconductor device according to claim 3, in, The plurality of intermediate gate layers includes a first intermediate gate layer. Wherein, the first external support vertical structure passes through the first intermediate gate layer and the lower gate layer, and Wherein, the distance between a portion of the first outer support vertical structure passing through the first intermediate gate layer and the first separation structure is greater than the distance between the fourth portion of the first inner support vertical structure passing through the first intermediate gate layer and the first separation structure.

5. The semiconductor device according to claim 1, wherein, The lower end of the first internal support vertical structure is at a different level from the lower end of the first separation structure adjacent to the first internal support vertical structure.

6. The semiconductor device according to claim 1, in, The lower structure includes a substrate, peripheral circuitry on the substrate, and a patterned structure on the peripheral circuitry. The stacked structure is disposed on the patterned structure, and The memory vertical structure and the first inner support vertical structure are in contact with the pattern structure.

7. The semiconductor device according to claim 6, in, The vertical structure of the memory includes: an insulating gap-filling layer; a channel material layer, at least covering the side surface of the insulating gap-filling layer; and a data storage structure on the outer surface of the channel material layer. The pattern structure includes a first pattern layer, a second pattern layer on the first pattern layer, and a third pattern layer on the second pattern layer. The second patterned layer penetrates the data storage structure and contacts the channel material layer. Wherein, the first pattern layer and the third pattern layer are spaced apart from the channel material layer, and The first patterned layer, the second patterned layer, and the third patterned layer all include silicon layers.

8. The semiconductor device according to claim 6, in, The stacking structure includes a lower stacking structure and an upper stacking structure on the lower stacking structure. The lower stacked structure includes alternating stacked first interlayer insulating layers and first gate layers. The upper stacked structure includes alternately stacked second interlayer insulating layers and second gate layers. Wherein, the first interlayer insulating layer and the second interlayer insulating layer are configured to form the interlayer insulating layer of the stacked structure. Wherein, the first gate layer and the second gate layer are configured to form the gate layers of the stacked structure, and The side surface of the vertical structure of the memory includes a curved portion located between the uppermost gate layer in the first gate layer and the lowermost gate layer in the second gate layer.

9. The semiconductor device according to claim 1, further comprising: Semiconductor substrate, on the stacked structure; Peripheral circuitry, including peripheral devices and upper bonding pads between the semiconductor substrate and the stacked structure; as well as The lower bonding interconnect structure includes a lower bonding pad between the stacked structure and the peripheral circuitry. The upper bonding pad and the lower bonding pad are in contact with each other and are bonded to each other.

10. The semiconductor device according to claim 1, in, The plurality of separation structures include: a second separation structure parallel to the first separation structure; and a plurality of secondary separation structures disposed between the first separation structure and the second separation structure. The plurality of sub-separation structures include inner separation structures and outer separation structures. The internal separation structure penetrates and contacts the lower gate layer, the plurality of intermediate gate layers, and the upper gate layer. The external separation structure is spaced apart from the upper gate layer and penetrates and contacts the plurality of intermediate gate layers and the upper gate layer. Each of the plurality of sub-separation structures has a strip shape or line shape extending along a first horizontal direction. Among them, n internal separation structures are sequentially arranged between the first separation structure and the second separation structure along a second horizontal direction perpendicular to the first horizontal direction. Among them, m external separation structures are sequentially arranged between the first separation structure and the second separation structure along the second horizontal direction, and Here, n and m are different natural numbers.

11. The semiconductor device according to claim 10, wherein, n is greater than m.

12. The semiconductor device according to claim 10, in, n is odd, and Where m is an even number.

13. The semiconductor device according to claim 10, in, The plurality of supporting vertical structures also include a plurality of second inner supporting vertical structures between the first separating structure and the second separating structure. The first internal support vertical structure and the plurality of second internal support vertical structures are arranged to be spaced apart from each other in the second horizontal direction. The plurality of supporting vertical structures further includes a plurality of external supporting vertical structures, which are arranged to be spaced apart from each other along the second horizontal direction between the first separating structure and the second separating structure. The number of the first inner support vertical structures and the second inner support vertical structures arranged at intervals along the second horizontal direction is greater than the number of the plurality of outer support vertical structures arranged at intervals along the second horizontal direction between the first separation structure and the second separation structure.

14. The semiconductor device according to claim 13, in, The first inner support vertical structure and the plurality of second inner support vertical structures are adjacent to the inner separation structure in the second horizontal direction, and The plurality of external support vertical structures are adjacent to the external separation structure in the second horizontal direction.

15. The semiconductor device according to claim 14, in, The plurality of supporting vertical structures further includes buffer supporting vertical structures, which are arranged to be spaced apart from each other along the second horizontal direction between the first separation structure and the second separation structure. Wherein, the buffer support vertical structure does not face the inner separation structure and the outer separation structure in the second horizontal direction, and The number of buffer support vertical structures spaced apart from each other along the second horizontal direction is less than the number of the first inner support vertical structures and the second inner support vertical structures spaced apart from each other along the second horizontal direction, and greater than the number of the plurality of outer support vertical structures spaced apart from each other along the second horizontal direction.

16. The semiconductor device according to claim 1, in, The vertical structure of the memory includes a channel material layer, and The material of the channel material layer is not included in the plurality of supporting vertical structures.

17. A semiconductor device, comprising: The stacked structure includes an interlayer insulating layer and a gate layer that are alternately stacked on the lower structure in a vertical direction; Multiple separate structures pass through the stacked structure; Multiple supporting vertical structures pass through the stacked structure in the stepped area on the lower structure; as well as The memory vertical structure extends through the stacked structure in the memory cell array region of the lower structure. The gate layer includes: a lower gate layer; an upper gate layer on the lower gate layer; and a plurality of intermediate gate layers spaced apart from each other along the vertical direction between the lower gate layer and the upper gate layer. The gate layer includes gate pads arranged in a stepped shape within the stepped region. The plurality of separation structures include a first separation structure. The plurality of vertical support structures include an inner vertical support structure and an outer vertical support structure disposed in the stepped area. The internal support vertical structure passes through the lower gate layer, the plurality of intermediate gate layers, and the upper gate layer. Wherein, at least one of the inner support vertical structures has a side surface including an upper portion that contacts the first separation structure at the same level as the gate layer. The external support vertical structure passes through the lower gate layer and the plurality of intermediate gate layers at a position spaced apart from the upper gate layer. The entire side surface of the external support vertical structure is spaced apart from the first separation structure.

18. The semiconductor device according to claim 17, in, The vertical structure of the memory includes a channel material layer. The plurality of supporting vertical structures do not include the material of the channel material layer. Wherein, the side surface of at least one of the internal support vertical structures further includes a lower portion that does not contact the first separation structure at the same level as the gate layer, and The upper part is positioned at a higher level than the lower part.

19. A data storage system, comprising: Main substrate; Semiconductor devices on the main substrate; as well as The controller is electrically connected to the semiconductor device on the main substrate. The semiconductor device includes: The stacked structure includes an interlayer insulating layer and a gate layer that are alternately stacked on the lower structure in a vertical direction; The memory has a vertical structure that passes through the stacked structure; Multiple separate structures pass through the stacked structure; and Multiple supporting vertical structures pass through the stacked structure. The gate layer includes: a lower gate layer; an upper gate layer on the lower gate layer; and a plurality of intermediate gate layers spaced apart from each other along the vertical direction between the lower gate layer and the upper gate layer. The plurality of separation structures include a first separation structure. The plurality of vertical support structures include a first inner vertical support structure that passes through the lower gate layer, the plurality of intermediate gate layers, and the upper gate layer. The first inner vertical support structure is adjacent to the first separation structure. Wherein, the first portion of the first internal support vertical structure is directly connected to the first discrete structure at the same level as the upper gate layer, and The second portion of the first inner support vertical structure is spaced apart from the first separation structure at the same level as the lower gate layer.

20. The data storage system according to claim 19, in, The plurality of supporting vertical structures also includes a first outer supporting vertical structure that is adjacent to and spaced apart from the first separating structure. Wherein, the distance between the memory vertical structure and the first outer support vertical structure is greater than the distance between the memory vertical structure and the first inner support vertical structure. The first external support vertical structure passes through at least one of the plurality of intermediate gate layers and the lower gate layer, and is spaced apart from the upper gate layer. The plurality of intermediate gate layers includes a first intermediate gate layer. Wherein, the first external support vertical structure penetrates the first intermediate gate layer and the lower gate layer, and Wherein, at the same level as the first intermediate gate layer, the distance between a portion of the first outer support vertical structure passing through the first intermediate gate layer and the first separation structure is greater than the distance between a third portion of the first inner support vertical structure passing through the first intermediate gate layer and the first separation structure.

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