Image sensor

Abstract

An image sensor includes an array of a plurality of image pixels and a plurality of black level correction pixels. Each black level correction pixel includes a black level correction pixel photodetector, a black level correction pixel sensing circuit, and a black level correction pixel optics assembly configured to block light from impinging on the black level correction pixel photodetector. Each black level correction pixel optics assembly can include a first portion of a layer stack that includes a vertically alternating sequence of a first material layer having a first index of refraction and a second material layer having a second index of refraction.

Description

Technical Field

[0001] This disclosure relates to an image sensor having an optical blocking structure for black level correction pixels. Background Technology

[0002] Semiconductor image sensors are used to sense electromagnetic radiation, such as visible light, infrared radiation, and / or ultraviolet light. Complementary metal-oxide-semiconductor (CMOS) image sensors (CIS) and charge-coupled device (CCD) sensors are used in a variety of applications, such as digital cameras or embedded cameras in mobile devices. These devices utilize an array of multiple pixels (which may include photodiodes and transistors) to detect radiation using the light-generating effect of electron-hole pairs. Black level correction pixels are used to measure the level of background current in the photodetector due to thermal noise in the absence of light. However, various light-blocking materials in the prior art exhibit significant light leakage and compromise the accuracy of the thermal background current. Summary of the Invention

[0003] Some embodiments of this disclosure provide an image sensor comprising: an array of a plurality of image pixels and a plurality of black level correction pixels. The plurality of image pixels are located on a semiconductor substrate, wherein each image pixel within the plurality of image pixels includes an image pixel photodetector, an image pixel sensing circuit, and an image pixel optics assembly configured to filter and guide incident light onto the image pixel photodetector. The plurality of black level correction pixels are located adjacent to the plurality of image pixels on the semiconductor substrate, wherein each of these black level correction pixels includes a black level correction pixel photodetector, a black level correction pixel sensing circuit, and a black level correction pixel optics assembly configured to block light incident on the black level correction pixel photodetector, wherein each of these black level correction pixel optics assemblies includes a first portion of a layer stack comprising a vertically alternating sequence of a plurality of first material layers having a first refractive index and a plurality of second material layers having a second refractive index, wherein the first portion of the layer stack does not include any openings therethrough.

[0004] Other embodiments of this disclosure provide an image sensor comprising: an array of a plurality of image pixels and a plurality of black level correction pixels. The plurality of image pixels are located on a semiconductor substrate, wherein each image pixel within the plurality of image pixels includes an image pixel photodetector, an image pixel sensing circuit, and an image pixel optics assembly configured to filter incident light and direct the incident light onto the image pixel photodetector. The plurality of black level correction pixels are located adjacent to the plurality of image pixels on the semiconductor substrate, wherein each of these black level correction pixels includes a black level correction pixel photodetector, a black level correction pixel sensing circuit, and a black level correction pixel optics assembly configured to block light incident on the black level correction pixel photodetector, wherein each of these black level correction pixel optics assemblies includes: a first portion of a layer stack comprising at least two metal layers, wherein each of the at least two metal layers includes a respective wavelength subrange having greater reflectivity than another metal layer selected from the at least two metal layers in a wavelength range from 200 nm to 1,600 nm, and wherein the first portion of the layer stack does not include any openings therethrough.

[0005] Further embodiments of this disclosure provide an image sensor comprising: an array of a plurality of image pixels and a plurality of black level correction pixels. The plurality of image pixels are located on a semiconductor substrate, wherein each image pixel within the array includes an image pixel photodetector, an image pixel sensing circuit, and an image pixel optics assembly configured to filter incident light and direct the incident light onto the image pixel photodetector. The plurality of black level correction pixels are located adjacent to the plurality of image pixels on the semiconductor substrate, wherein each of these black level correction pixels includes a black level correction pixel photodetector, a black level correction pixel sensing circuit, and a black level correction pixel optics assembly configured to block light incident on the black level correction pixel photodetector, wherein each of these black level correction pixel optics assemblies includes an infrared blocking material layer that provides a higher absorption coefficient in the wavelength range from 800 nm to 1600 nm than any color filter material within the image pixel optics assembly. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0007] Figure 1AThis is a plan view of a first configuration of a plurality of pixels in an array for an image sensor, according to one embodiment of the present disclosure.

[0008] Figure 1B This is a plan view of a second configuration of a plurality of pixels in an array for an image sensor, according to another embodiment of the present disclosure.

[0009] Figure 2A This is a plan view of a front-side sensor assembly within the area of ​​a sub-pixel in an exemplary structure, according to one embodiment of the present disclosure.

[0010] Figure 2B It is along Figure 2A A vertical cross-sectional view of an exemplary structure with hinged vertical plane B – B' – B” – B'” – B””;

[0011] Figure 3 This is a vertical cross-sectional view of an exemplary structure following the formation of a metal interconnect structure within an interconnect-level dielectric layer and the attachment of a carrier substrate, according to one embodiment of the present disclosure.

[0012] Figure 4 This is a vertical cross-sectional view of an exemplary structure after thinning a semiconductor substrate, according to one embodiment of the present disclosure.

[0013] Figure 5 This is a vertical cross-sectional view of an exemplary structure after the formation of a deep trench isolation structure, according to one embodiment of the present disclosure.

[0014] Figure 6A This is a vertical cross-sectional view of an image pixel region of an exemplary structure after the formation of an anti-reflective coating, a near-end dielectric layer, a light-blocking material layer, and a patterned photoresist layer, according to one embodiment of the present disclosure.

[0015] Figure 6B According to one embodiment of the present disclosure, in Figure 6A A vertical cross-sectional view of the black level correction (BLC) pixel region of an exemplary structure during a process step;

[0016] Figure 7A yes Figure 6A and Figure 6B A vertical cross-sectional view of the first configuration of the light-blocking material layer;

[0017] Figure 7B yes Figure 6A and Figure 6B A vertical cross-sectional view of the second configuration of the light-blocking material layer;

[0018] Figure 7C yes Figure 6A and Figure 6B A vertical cross-sectional view of the third configuration of the light-blocking material layer;

[0019] Figure 7D yes Figure 6A and Figure 6B A vertical cross-sectional view of the fourth configuration of the light-blocking material layer;

[0020] Figure 7E yes Figure 6A and Figure 6B A vertical cross-sectional view of the fifth configuration of the light-blocking material layer;

[0021] Figure 8A This is a vertical cross-sectional view of the image pixel region of an exemplary structure after the formation of the grid structure, according to one embodiment of the present disclosure.

[0022] Figure 8B yes Figure 8A A plan view of the image pixel region of an exemplary structure. The hinged vertical plane A-A' corresponds to... Figure 8A The plane of the vertical cross-sectional view;

[0023] Figure 8C According to one embodiment of the present disclosure, in Figure 8A and Figure 8B The process steps are shown in the vertical cross-sectional view of the black level correction (BLC) pixel region of the exemplary structure.

[0024] Figure 9A This is a vertical cross-sectional view of the image pixel region of an exemplary structure after the formation of the optically transparent layer, color filter, and lens, according to one embodiment of the present disclosure.

[0025] Figure 9B According to one embodiment of the present disclosure, in Figure 9A During the manufacturing process, a vertical cross-sectional view of the black level correction pixel region of the exemplary structure is shown.

[0026] Figure 10A This is a vertical cross-sectional view of the image pixel region of an exemplary structure after the removal of the carrier substrate, according to one embodiment of the present disclosure.

[0027] Figure 10B According to one embodiment of the present disclosure, in Figure 10A During the manufacturing process, a vertical cross-sectional view of the black level correction pixel region of the first configuration of the exemplary structure;

[0028] Figure 11AThis is a vertical cross-sectional view of the image pixel region of the second configuration of the exemplary structure after the removal of the carrier substrate, according to one embodiment of the present disclosure.

[0029] Figure 11B This is a vertical cross-sectional view of the black level correction pixel region of the second configuration of the exemplary structure after the removal of the carrier substrate, according to one embodiment of the present disclosure.

[0030] Figure 12A This is a vertical cross-sectional view of the image pixel region of the third configuration of the exemplary structure after the removal of the carrier substrate, according to one embodiment of the present disclosure.

[0031] Figure 12B This is a vertical cross-sectional view of the black level correction pixel region of the third configuration of the exemplary structure after the removal of the carrier substrate, according to one embodiment of the present disclosure.

[0032] Figure 13A This is a vertical cross-sectional view of the image pixel region of the fourth configuration of the exemplary structure after the removal of the carrier substrate, according to one embodiment of the present disclosure.

[0033] Figure 13B This is a vertical cross-sectional view of the black level correction pixel region of the fourth configuration of the exemplary structure after the removal of the carrier substrate, according to one embodiment of the present disclosure.

[0034] Figure 14 This is a schematic circuit diagram of a photodetector circuit according to one embodiment of the present disclosure;

[0035] Figure 15 This is a process flow diagram illustrating an exemplary process sequence for forming an image sensor according to one embodiment of the present disclosure.

[0036] [Symbol Explanation]

[0037] 1000: Array

[0038] 1510: Steps

[0039] 1520: Steps

[0040] 500: Semiconductor substrate

[0041] 510: Semiconductor substrate

[0042] 600: Front sensor assembly

[0043] 601: Substrate semiconductor layer

[0044] 602: Second conductivity type photodiode layer

[0045] 603: Pinning layer of the first conductivity type

[0046] 605: Transfer gate electrode

[0047] 605B: Transfer Gate Electrode

[0048] 606: Second conductivity type photodiode layer

[0049] 607: First type of conductivity trap

[0050] 608: Floating diffusion region

[0051] 609: Front surface

[0052] 611: Transmission transistor main body region

[0053] 612: Active Region

[0054] 614: Gate Dielectric

[0055] 614T: Transfer gate dielectric

[0056] 615: Gate electrode

[0057] 620: Shallow trench isolation structure

[0058] 630: Transmission transistor

[0059] 640: Reset transistor

[0060] 650: Source follower transistor

[0061] 660: Select Transistor

[0062] 670: Interconnect-level dielectric layer

[0063] 680: Metal interconnect structure

[0064] 682: Metal through-hole structure

[0065] 684: Metal Wire Structure

[0066] 689: Joint Buffer Layer

[0067] 690: Carrier substrate

[0068] 709: Backside surface

[0069] 720: Deep trench isolation structure

[0070] 732: Anti-reflective coating

[0071] 734: Near-end dielectric layer

[0072] 740: Grid Structure

[0073] 740L: Light-blocking material layer

[0074] 741A: Metal layer

[0075] 741B: Metallic layer

[0076] 741C: Metallic layer

[0077] 741D: Metallic layer

[0078] 742A: First material layer

[0079] 742B: Second material layer

[0080] 747: Photoresist layer

[0081] 770: Optical Transparent Layer

[0082] 780: Color Filter

[0083] 781: Type I Color Filter

[0084] 782: Type II Color Filter

[0085] 783: Type III Color Filter

[0086] 786: Infrared blocking material layer

[0087] 790: Optical Lens

[0088] 800: Subpixel

[0089] 801: First subpixel

[0090] 801D: First detector region

[0091] 801S: First sensing circuit area

[0092] 802: Second subpixel

[0093] 802D: Second detector region

[0094] 802S: Second sensing circuit area

[0095] 803: Third subpixel

[0096] 803D: Third Detector Region

[0097] 803S: Third sensing circuit area

[0098] 809: Black Level Correction Subpixel

[0099] 811: First black level correction subpixel

[0100] 812: Second black level correction sub-pixel

[0101] 813: Third black level correction subpixel

[0102] 900 pixels

[0103] A-A': The perpendicular plane of the hinge

[0104] B – B' – B” – B'” – B””: Vertical plane of the hinge

[0105] C1, C2, C3, Cj, C(N-1), CN: Columns

[0106] FD: Floating diffusion region

[0107] hd1: First horizontal direction

[0108] hd2: Second horizontal direction

[0109] P11, P12, P13, P1N, P21, P22, P23, P31, P32, P33, Pij, PM1, PMN: pixels

[0110] PPD: Photodiode

[0111] R1, R2, R3, Ri, R(M-1), RM: lines

[0112] RST: Reset transistor

[0113] SEL: Select Transistor

[0114] SF: Source follower transistor

[0115] TG: Transfer gate electrode

[0116] UC: Unit

[0117] V_out: Column output bus Detailed Implementation

[0118] The following disclosure provides many different implementations or embodiments to achieve different features of the provided subject matter. Specific embodiments of components and arrangements are described below to simplify this disclosure. These are, of course, merely embodiments and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include implementations where the first and second features are formed in direct contact, and may also include implementations where additional features may be formed between the first and second features, so that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various embodiments of this disclosure. This repetition is for the purpose of simplicity and clarity, and the repetition itself does not imply a relationship between the various implementations and / or configurations discussed.

[0119] Furthermore, to facilitate the description of the relationship between one element or feature and another, as illustrated in the accompanying drawings, spatially relative terms such as “below,” “lower,” “lower,” “higher,” “upper,” and similar terms may be used herein. In addition to the orientations illustrated in the accompanying drawings, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted in the same manner.

[0120] This disclosure relates to semiconductor devices, and more particularly to image sensors using optical blocking structures for black level correction pixels and methods of forming the same.

[0121] Generally, the structures and methods disclosed herein can be used to provide enhanced black level correction for complementary metal-oxide-semiconductor (CMOS) image sensors. Within a black level correction pixel optics assembly, at least one light-blocking structure is provided for each black level correction (BLC) pixel to suppress the transmission of light not blocked by a flat light-blocking layer. The at least one light-blocking structure may be a composite structure comprising at least two different material layers. This at least one light-blocking structure may include a layer stack comprising a vertically alternating sequence of a first material layer having a first refractive index and a second material layer having a second refractive index. The refractive index and thickness of the multiple materials in the vertically alternating sequence can be customized to block light in a specific wavelength range that is not blocked by a flat light-blocking layer. Additionally or alternatively, the at least one light-blocking structure may include at least two metal layers having a larger wavelength subrange of reflectivity than the other metal layer. Additionally or alternatively, the at least one light-blocking structure may include an infrared blocking material layer that provides a higher absorption coefficient than a color filter material within the image pixel optics assembly. The various features and forms of the methods and structures disclosed herein will now be described with reference to the illustrations in this application.

[0122] See Figure 1A and Figure 1B The diagrams, in their respective plan views, illustrate a first configuration of a plurality of pixels 900 of an array 1000 for an image sensor and a second configuration of a plurality of pixels 900 of an array 1000 for an image sensor. The image sensor may be a backside illuminated (BSI) image sensor device. However, it should be understood that various embodiments of this disclosure can be used in front-side illuminated (FSI) image sensors.

[0123] Each pixel 900 represents a minimum unit area used to generate an image from an image sensor. The region comprising the plurality of pixels 900 in this array 1000 is referred to herein as a pixel array region. The plurality of pixels 900 in this pixel array region can be arranged in multiple rows and multiple columns. For example, a pixel array region may include M rows and N columns, where M and N are numbers from 1 to 2. 16 Integers within a range, such as from 2 8 to 2 14 Multiple pixels 900 in multiple rows can be consecutively numbered using integers ranging from 1 to M, and multiple pixels 900 in multiple columns can be consecutively numbered using integers ranging from 1 to N. Pixel P ij This refers to pixel 900 in the i-th row and j-th column.

[0124] Each pixel 900 includes at least one photodetector configured to detect radiation within a given wavelength range. Each pixel 900 may include multiple photodetectors configured to detect radiation within their respective wavelength ranges, which may differ from each other. In one embodiment, each pixel 900 may include multiple sub-pixels, each sub-pixel including a photodetector and a corresponding combination of electronic circuitry configured to detect radiation incident on the photodetector. For example, pixel 900 may include sub-pixels configured to detect radiation in a red wavelength range (e.g., from 635 nm to 700 nm), sub-pixels configured to detect radiation in a green wavelength range (e.g., from 520 nm to 560 nm), and sub-pixels configured to detect radiation in a blue wavelength range (e.g., from 450 nm to 490 nm). These sub-pixels are respectively referred to as red sub-pixels, green sub-pixels, and blue sub-pixels.

[0125] Typically, pixel 900 generates information about incident radiation per unit detection area. Subpixels generate information about the intensity of incident radiation detected within a specific wavelength range within a region of the unit detection area. Monochrome pixel 900 may include only a single subpixel. Pixel 900 configured to detect the spectral distribution of incident radiation includes multiple subpixels having at least two different detection wavelength ranges. Photodetectors in the pixel array region may include photodiodes, complementary metal-oxide-semiconductor (CMOS) image sensors, charge-coupled device (CCD) sensors, active sensors, passive sensors, other applicable sensors, or combinations thereof.

[0126] Within a principal subset of pixels 900 in each array 1000 of an image sensor, a plurality of pixels 900 comprise a plurality of image pixels, which are pixels used to generate a two-dimensional image. Another subset of pixels 900 within the plurality of pixels 900 in each array 1000 of the image sensor may comprise a plurality of black level correction (BLC) pixels, which are pixels used to determine a black level correction signal. Generally, in the absence of incident light, each sub-pixel within a black level correction pixel measures the charge accumulated within a corresponding photodiode region. In one embodiment, a plurality of black level correction pixels may be arranged around a frame of pixels 900 in this array 1000 of the image sensor. In an illustrated embodiment, the black level correction pixels may comprise a plurality of first row pixels (e.g., a plurality of pixels P). 1j (where the exponent j varies from 1 to N), multiple last row pixels (e.g., multiple m-th row pixels P) mj(where the exponent j varies from 1 to N), multiple first column pixels (e.g., multiple pixels P) i1 (where the exponent i varies from 1 to M), and multiple last column pixels (e.g., multiple pixels P). iN (where the exponent i varies from 1 to M).

[0127] In practice, blocking all incident light across the entire effective wavelength range of a photodetector for a black level correction pixel is extremely difficult. Typically, a single light-blocking material layer provides reflectivity significantly less than 100% over a sub-wavelength range and / or has a peak wavelength near which significant light transmission occurs. As will be explained below, the light-blocking structure of this disclosure uses at least two light-blocking material layers configured to block light more effectively than any single light-blocking material layer.

[0128] Reference Figure 2A and Figure 2B The diagram illustrates a photodetector circuit in an exemplary structure, comprising a group of multiple front-side sensor components 600 within the area of ​​a sub-pixel. The front-side sensor components 600 refer to all components of an image sensor that may be formed on the front surface 609 of a semiconductor substrate 500 or within a substrate semiconductor layer 601. The photodetector circuit includes a photodetector (containing a transfer transistor 630) and sensing circuitry (640, 650, 660), the sensing circuitry including a reset transistor 640, a source follower transistor 650, and a select transistor 660.

[0129] Each subpixel includes its own photodetector circuitry, which includes a subset of a plurality of front-side sensor components 600 that may be located within the area of ​​the subpixel. At least one set of subpixels 800 may be used for a pixel 900. Each subpixel includes a unit cell (UC) that may be repeated along at least one horizontal direction to provide a front-side sensor component 600 for a single pixel, which may include a single subpixel, two subpixels, or three or more subpixels. In one embodiment, a plurality of instances of the unit cell UC may be repeated along at least one horizontal direction. For example, the unit cell UC may be a repetition of a plurality of unit cells UC in a two-dimensional array, the plurality of unit cells UC being replicated with a first periodicity along a first horizontal direction hd1 and a second periodicity along a second horizontal direction hd2. Referring above... Figure 1A and Figure 1B The two-dimensional array discussed may be a rectangular array or a hexagonal array. Thus, the second horizontal direction hd2 may or may not be perpendicular to the first horizontal direction hd1.

[0130] Return to reference Figure 2A and Figure 2BThe semiconductor substrate 500 includes a substrate semiconductor layer 601. Each sub-pixel may be formed on or within the substrate semiconductor layer 601, which has a front surface 609 and a back surface. The substrate semiconductor layer 601 includes a semiconductor material, such as silicon, germanium, a silicon-germanium alloy, a compound semiconductor material, or another semiconductor material having a band gap not exceeding the energy of the photon to be detected. The material within the substrate semiconductor layer 601 may be selected according to the energy range of the photons to be detected by the sub-pixel. In one embodiment, the substrate semiconductor layer 601 may include monocrystalline silicon. Commercially available monocrystalline semiconductor substrates may be used for the semiconductor substrate 500. The semiconductor substrate 500 provided at this process step has a sufficiently high thickness to withstand multiple standard complementary metal-oxide-semiconductor process steps. For example, the thickness of the semiconductor substrate 500 may range from 200 microns to 1 millimeter (mm), although smaller and larger thicknesses may also be used.

[0131] The top portion of the substrate semiconductor layer 601 may be suitably doped to have a first conductivity type, which may be p-type or n-type. For example, an epitaxial semiconductor deposition process may be performed to form a single-crystal epitaxial semiconductor material layer at the upper portion of the substrate semiconductor layer, such that the atomic concentration of the dopant of the first conductivity type is from 1.0 x 10⁻⁶. 13 / cm 3 Up to 1.0 x10 16 / cm 3 Within this range, although both smaller and larger atomic concentrations can be used. The thickness of the semiconductor material layer in single-crystal epitaxy can range from 1 micrometer to 10 micrometers.

[0132] A first conductivity type well 607 can be formed by ion implantation around multiple regions where multiple shallow trench isolation structures 620 can subsequently be formed. The atomic concentration of the first conductivity type dopant in the first conductivity type well 607 can range from 1.0 × 10⁻⁶. 15 / cm 3 Up to 1.0×10 18 / cm 3 Within this range, although both smaller and larger atomic concentrations can be used. Shallow trench isolation structures 620 can be formed to provide electrical isolation between the individual components within the sub-pixel.

[0133] The second conductivity type of dopant can be implanted via the front surface 609 of the semiconductor substrate 500 using at least one masked ion implantation process. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. Individual doped regions having the second conductivity type of dopant are formed via at least one masked ion implantation process. A second conductivity type photodiode layer 602 can be formed below the front surface 609 of the semiconductor substrate 500 in each unit cell UC, such that the periphery of the second conductivity type photodiode layer 602 overlaps with the edge of the transfer gate electrode 605 in a plan view. The lateral extent of the second conductivity type photodiode layer 602 can be defined on one side of the subsequently formed transfer gate electrode. Therefore, the edge of the second conductivity type photodiode layer 602 can be laterally spaced from the shallow trench isolation structure 620 by a region in which the transfer gate electrode and the floating diffusion region can subsequently be formed.

[0134] A second conductive type dopant with higher implantation energy in the implantation process of forming the second conductive type photodiode layer 602 via a implantation ratio can form a buried second conductive type photodiode layer 606 below the second conductive type photodiode layer 602 at the bottom depth of the first conductive type well 607. The buried second conductive type photodiode layer 606 may be adjacent to the first conductive type well 607. In one embodiment, each buried second conductive type photodiode layer 606 may have a periphery adjacent to the first conductive type well 607.

[0135] In one embodiment, the depth of the top surface of the embedded second conductivity type photodiode layer 606 can range from 400 nanometers (nm) to 1,500 nanometers, although smaller and larger depths can also be used. In one embodiment, the depth of the bottom surface of the embedded second conductivity type photodiode layer 606 can range from 800 nanometers to 2,500 nanometers, although smaller and larger depths can also be used.

[0136] The unplanted portion of the substrate semiconductor layer 601 covering the buried second conductivity type photodiode layer 606 may have doping of the first conductivity type and may subsequently be used as the body region of the transmission transistor. Thus, the unplanted portion of the substrate semiconductor layer 601 covering the buried second conductivity type photodiode layer 606 is referred to herein as the transmission transistor body region 611. In one embodiment, the buried second conductivity type photodiode layer 606 may have the same lateral extent as the subsequently formed transmission transistor 630 and may partially overlap with a shallow trench isolation structure 620 surrounding the combination of the second conductivity type photodiode layer 602 and the transmission transistor body region 611.

[0137] Gate stack structures (614, 605, 615) may be formed on the front surface 609 of a semiconductor substrate 500 by deposition and patterning of a stack comprising a gate dielectric layer and a gate electrode layer. Each patterned portion of this stack constitutes a gate stack structure (614, 605, 615), which may be a transport gate stack structure (614T, 605) and a control gate stack structure (614, 615). Each transport gate stack structure (614, 605) includes a gate dielectric and a gate electrode, the gate dielectric being referred to herein as transport gate dielectric 614T, and the gate electrode being referred to herein as transport gate electrode 605. Each transport gate stack structure (614, 605) is located between a second conductivity type photodiode layer 602 and a floating diffusion region 608. Each control gate stack structure (614, 615) includes a gate dielectric 614 and a gate electrode 615.

[0138] Each of the multiple control gate stack structures (614, 615) includes a corresponding layer stack of gate dielectric 614 and gate electrode 615 of other multiple transistors in the sensing circuit, which may include a reset transistor 640, a source follower transistor 650, a select transistor 660, and other suitable transistors that can be used to amplify the signal generated by the photodetector of the sub-pixel.

[0139] Various active regions (608, 612) with a second conductivity type can be formed. Each active region (608, 612) may include a floating diffusion region 608, which functions as the drain region of the transfer transistor 630. The current between the second conductivity type photodiode layer 602 and the floating diffusion region 608 can be controlled by the transfer gate electrode 605.

[0140] The second conductivity type photodiode layer 602 can accumulate charge (e.g., electrons in an embodiment where the second conductivity type is n-type) during sensing (i.e., when a sub-pixel actively detects photons incident on it, for example, to capture an image or photograph) and can function as the source region of the transmission transistor 630. The active region 612 includes the source and drain regions of various transistors (640, 650, 660) in the sensing circuit. A floating diffusion region 608 can be perpendicularly spaced from the embedded second conductivity type photodiode layer 606 via the transmission transistor body region 611.

[0141] The floating diffusion region 608 and active region 612 forming each unit cell UC can be formed via ion implantation of dopants of a second conductivity type using a masked ion implantation process. During the ion implantation process, a combination of corresponding patterned photoresist layers and gate stack structures (614, 605, 615) can be used as an ion implantation barrier structure (i.e., a mask structure). The depth of the bottom surface of the floating diffusion region 608 can range from 100 nanometers (nm) to 400 nanometers, for example from 150 nm to 250 nm, although smaller and larger depths can also be used. The depth of the bottom surface of the active region 612 can range from 100 nm to 600 nm, for example from 150 nm to 400 nm, although smaller and larger depths can also be used.

[0142] The first conductivity type pinning layer 603 can be formed directly on top of the second conductivity type photodiode layer 602 via ion implantation of the first conductivity type dopant. The first conductivity type pinning layer 603 suppresses depletion at the interface between the second conductivity type photodiode layer 602 and the first conductivity type pinning layer 603, and electrically stabilizes the second conductivity type photodiode layer 602. The first conductivity type pinning layer 603 is omitted in all top views of the various exemplary structures disclosed herein to clearly illustrate the lateral extent of the second conductivity type photodiode layer 602 located below the first conductivity type pinning layer 603. The depth of the pn junction between the first conductivity type pinning layer 603 and the second conductivity type photodiode layer 602 can range from 5 nanometers to 100 nanometers, although smaller and larger depths are also possible. In addition to the pn junction between the second conductivity type photodiode layer 602 and the substrate semiconductor layer 601, the first conductivity type pinning layer 603 forms an additional pn junction with the second conductivity type photodiode layer 602.

[0143] An interconnect-level dielectric layer 670 may be formed over the front surface 609 of the semiconductor substrate 500, and a metal interconnect structure 680 connecting the nodes of transistors (630, 640, 650, 660) may be formed within each sub-pixel. The interconnect-level dielectric layer 670 may include a suitable dielectric material, such as undoped silicate glass, doped silicate glass, organosilicon glass, porous dielectric material, or a combination thereof. A dielectric pad may optionally be used in the interconnect-level dielectric layer 670, comprising various dielectric materials (e.g., silicon nitride, silicon oxynitride, silicon oxycarbide, and / or dielectric metal oxide). The metal interconnect structure 680 may include various metal via structures 682 and various metal line structures 684. For example, each of a plurality of floating diffusion regions 608 may be connected to the gate electrode 615 of a corresponding source follower transistor 650 via a subset of the plurality of metal interconnect structures 680. The photodetector may include a transmission transistor 630 and may be connected to a sensing circuit that includes additional transistors (640, 650, 660).

[0144] The sensing circuitry (640, 650, 660) includes a set of reset transistors 640, source follower transistors 650, and select transistors 660. Typically, the sensing circuitry (640, 650, 660) for each sub-pixel is located within the area of ​​a unit cell UC. In one embodiment, multiple transistors (640, 650, 660) of each interconnected set of sensing circuitry may be arranged side-by-side within the area of ​​a corresponding strip, the area of ​​which is located near the edge of the unit cell UC and extends along the entire length of the edge of the unit cell UC or at least 30% of the length of the edge of the unit cell UC. In another embodiment, multiple transistors (640, 650, 660) of each interconnected set of sensing circuitry may be arranged around a floating diffusion region 608 of a transfer transistor 630 located near a corner of the unit cell UC.

[0145] This exemplary structure includes image pixels and black level correction (BLC) pixels. Each sub-pixel within the black level correction pixels may have the same structure as the sub-pixels within the image pixels to provide an accurate estimate of the black level correction charge, i.e., the amount of charge collected by the photodetector circuit in the absence of incident radiation (e.g., due to thermal noise).

[0146] Reference Figure 3Additional interconnect-level dielectric layers 670 and additional metal interconnect structures 680 may be formed on the front side of the semiconductor substrate 500. The front side of the assembly of the semiconductor substrate 500, the interconnect-level dielectric layer 670, and the plurality of structures formed therein may be bonded to a carrier substrate 690. The carrier substrate 690 may be temporarily attached to the assembly of the semiconductor substrate 500 and the interconnect-level dielectric layer 670 to provide for subsequent thinning of the semiconductor substrate 500 and to provide for subsequent processing of the thinned assembly of the semiconductor substrate 500 and the interconnect-level dielectric layer 670. The carrier substrate 690 may comprise semiconductor material, insulating material, or metallic material, and may have a thickness ranging from 300 micrometers to 1 millimeter, although smaller and larger thicknesses may also be used.

[0147] Any suitable bonding method can be used to bond the carrier substrate 690 to the front side of the interconnect-level dielectric layer 670. Exemplary bonding methods that can be used to bond the carrier substrate 690 to the interconnect-level dielectric layer 670 include, but are not limited to, oxide-to-oxide bonding, oxide-to-semiconductor bonding, fusion bonding, hybrid bonding, anodic bonding, direct bonding, other suitable bonding processes, and / or combinations thereof. Optionally, a bonding buffer layer 689 comprising an intermediate bonding material (e.g., silicon oxide, silicon nitride, or semiconductor material) can be used to provide bonding between the interconnect-level dielectric layer 670 and the carrier substrate 690.

[0148] See Figure 4 The back side of the semiconductor substrate 500 can be thinned, for example, via grinding, polishing, isotropic etching processes, and / or anisotropic etching processes. The carrier substrate 690 can provide mechanical support to the semiconductor substrate 500 during the thinning process. In one embodiment, the semiconductor substrate 500 can be thinned to a thickness ranging from 1 micrometer to 12 micrometers, for example from 1.5 micrometers to 8 micrometers. The semiconductor substrate 500 thinned after the thinning process is referred to herein as the thinned semiconductor substrate 510, or simply as semiconductor substrate 510. The thickness of the thinned semiconductor substrate 510 can be determined by the maximum depth of the deep trenches subsequently formed on the back side of the thinned semiconductor substrate 510. In one embodiment, the thickness of the thinned semiconductor substrate 510 can be selected such that the deep trenches subsequently formed on the back side of the semiconductor substrate 510 reach the proximal surface of the shallow trench isolation structure 620. The back surface 709 of the thinned semiconductor substrate 510 can be polished to provide a flat, horizontal surface parallel to the front surface 609 of the thinned semiconductor substrate 510. The exemplary structure can then be flipped upside down for further processing.

[0149] Reference Figure 5A photoresist layer (not shown) can be applied over the back surface 709 of the thinned semiconductor substrate 510, and the photoresist layer can be photolithographically patterned to form a plurality of openings, which generally replicate the pattern of the shallow trench isolation structure 620 located below. Multiple uncovered portions of the semiconductor substrate 510 can be etched by performing anisotropic etching, which transfers the pattern of the plurality of openings in the photoresist layer into the semiconductor substrate 510. The depth of the plurality of deep trenches can range from 1 micrometer to 10 micrometers, for example from 1.5 micrometers to 8 micrometers. The plurality of deep trenches can be formed in the semiconductor substrate 510. The photoresist layer can then be removed, for example, via ashing.

[0150] At least one dielectric material, such as silicon oxide, may be deposited in the deep trench. Excess portions of at least one dielectric material covering the back surface 709 of the thinned semiconductor substrate 510 may be removed via a planarization process. The planarization process may include a chemical mechanical planarization (CMP) process and / or a recessed etching process. The remaining portion of the at least one dielectric material filling the deep trench comprises a deep trench isolation structure 720.

[0151] Multiple deep trench isolation structures 720 can define multiple areas for multiple sub-pixels 800. Each sub-pixel 800 can be located within a corresponding sub-pixel region, which is located within a region of a pixel, i.e., within a pixel region. For example, an area of ​​an image pixel may include an area of ​​a first sub-pixel 801, an area of ​​a second sub-pixel 802, and an area of ​​a third sub-pixel 803. In an illustrative embodiment, the first sub-pixel 801 may be formed in a region including a photodetector configured to detect green light, the second sub-pixel 802 may be formed in a region including a photodetector configured to detect red light, and the third sub-pixel 803 may be formed in a region including a photodetector configured to detect blue light. Each sub-pixel 800 may include a volume containing a patterned columnar portion of a semiconductor substrate 510, which is laterally surrounded by a connected set of multiple deep trenches. A pixel region of a pixel includes all sub-pixel regions of a set of multiple sub-pixels 800 contained within that pixel. Each black level correction (BLC) pixel includes at least one sub-pixel. In one embodiment, each black level correction pixel may include the same number of sub-pixels as the image pixels. In an illustrative embodiment, if the image pixels include a first sub-pixel 801, a second sub-pixel 802, and a third sub-pixel 803, the black level correction pixel may include a first black level correction sub-pixel, a second black level correction sub-pixel, and a third black level correction sub-pixel.

[0152] Reference Figure 6A and Figure 6BOptional anti-reflective coating (ARC) 732, near-end dielectric layer 734, and light-blocking material layer 740L may subsequently be sequentially deposited over the back surface 709 of semiconductor substrate 510.

[0153] Optional antireflective coating 732 includes an antireflective coating material that reduces reflections between the semiconductor material of the semiconductor substrate 510 and the overlying material layer (i.e., the near-end dielectric layer 734). Optional antireflective coating 732 may comprise a single material layer or a stack of multiple layers having gradually varying refractive indices. In one embodiment, optional antireflective coating 732 includes a semiconductor material, such as polycrystalline silicon, polycrystalline germanium, a silicon-germanium alloy, or a III-V compound semiconductor material. Antireflective coating 732 may have a thickness ranging from 50 nanometers to 300 nanometers, although smaller and larger thicknesses are also possible.

[0154] The proximal dielectric layer 734 may include a dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, or a dielectric metal oxide (e.g., aluminum oxide). The thickness of the proximal dielectric layer 734 may range from 100 nanometers to 1,000 nanometers, although smaller and larger thicknesses may also be used.

[0155] The light-blocking material layer 740L disclosed herein may be a composite light-blocking material layer comprising at least two different material layers. The light-blocking material layer 740L disclosed herein may include various stacks of material layers, such as in… Figures 7A to 7E shown in. Figures 7A to 7E It is illustrated that can be Figure 6A and Figure 6B Various configurations of the light-blocking material layer 740L used in the exemplary structure.

[0156] Reference Figures 7A to 7C The light-blocking material layer 740L may include at least two metal layers (741A, 741B, 741C, 741D). Figure 7A The first configuration is illustrated, wherein the light-blocking material layer 740L consists of two metal layers (741A, 741B), including a first metal layer 741A and a second metal layer 741B. Figure 7B The second configuration is illustrated, wherein the light-blocking material layer 740L consists of three metal layers (741A, 741B, 741C), including a first metal layer 741A, a second metal layer 741B, and a third metal layer 741C. Figure 7CA third configuration is illustrated, wherein the light-blocking material layer 740L consists of four metal layers (741A, 741B, 741C, 741D), including a first metal layer 741A, a second metal layer 741B, a third metal layer 741C, and a fourth metal layer 741D. Each of at least two metal layers (741A, 741B, 741C, 741D) in the light-blocking material layer 740L includes a respective wavelength sub-range, which has greater reflectivity in the wavelength range of 200 nm to 1,600 nm than the other metal layer selected from the at least two metal layers (741A, 741B, 741C, 741D).

[0157] In some embodiments, one of at least two metal layers (741A, 741B, 741C, 741D) comprises and / or is composed of a refractory metal layer, and the other of at least two metal layers (741A, 741B, 741C, 741D) comprises a layer of gold, silver, copper, and aluminum, and / or is composed of a layer selected from gold, silver, copper, and aluminum. The refractory metal layer may be substantially composed of a single refractory metal, which may be any one of tungsten, niobium, molybdenum, tantalum, rhenium, titanium, vanadium, chromium, zirconium, hafnium, ruthenium, rhodium, and iridium. Alternatively, the refractory metal layer may be substantially composed of an intermetallic alloy of at least two refractory metals, i.e., any alloy of at least two metals selected from tungsten, niobium, molybdenum, tantalum, rhenium, titanium, vanadium, chromium, zirconium, hafnium, ruthenium, rhodium, osmium, and iridium. Other suitable materials are also within the scope envisioned in this disclosure.

[0158] Alternatively or additionally, at least two metal layers (741A, 741B, 741C, 741D) may comprise at least two layers selected from gold, silver, copper, and aluminum. In one embodiment, the refractory metal layer may be a tungsten layer composed essentially of tungsten. Other suitable materials are also within the scope contemplated in this disclosure.

[0159] In a first configuration for the light-blocking material layer 740L, the light-blocking material layer 740L may consist of two metal layers (741A, 741B), one of which may be a refractory metal layer, and the other of which may be a layer selected from gold, silver, copper, and aluminum. Alternatively, the first metal layer 741A and the second metal layer 741B may be two different layers selected from gold, silver, copper, and aluminum.

[0160] In a second configuration for the light-blocking material layer 740L, the light-blocking material layer 740L may consist of three metal layers (741A, 741B, 741C), and the three metal layers (741A, 741B, 741C) may include one or two refractory metal layers, and the remaining metal layer may be selected from gold, silver, copper, and aluminum. Alternatively, the three metal layers (741A, 741B, 741C) may be at least two different metal layers selected from gold, silver, copper, and aluminum. The three metal layers (741A, 741B, 741C) may or may not include two layers of the same metal.

[0161] In a third configuration of the light-blocking material layer 740L, the light-blocking material layer 740L may consist of four metal layers (741A, 741B, 741C, 741D), and the four metal layers (741A, 741B, 741C, 741D) may include one, two, or three refractory metal layers, and the remaining metal layer may be selected from gold, silver, copper, and aluminum. Alternatively, the four metal layers (741A, 741B, 741C, 741D) may be at least two different metal layers selected from gold, silver, copper, and aluminum. The four metal layers (741A, 741B, 741C) may or may not include two layers of the same metal.

[0162] Although this disclosure is described using embodiments in which the light-blocking material layer 740L includes two, three, or four metal layers (741A, 741B, 741C, 741D), embodiments in which the light-blocking material layer 740L may include five or more metal layers are expressly contemplated herein.

[0163] Each of the at least two metal layers (741A, 741B, 741C, 741D) in the light-blocking material layer 740L may include a corresponding wavelength sub-range, which has greater reflectivity in the wavelength range from 200 nm to 1,600 nm than the other metal layer selected from the at least two metal layers (741A, 741B, 741C, 741D). Therefore, a first configuration of the light-blocking material layer 740L provides a first wavelength sub-range and a second wavelength sub-range, within the first wavelength sub-range, where the first metal layer 741A provides higher reflectivity than the second metal layer 741B, and within the second wavelength sub-range, the second metal layer 741B provides higher reflectivity than the first metal layer 741A. A sub-range refers to a gap within a range having a width smaller than the width of the entire range. The first wavelength sub-range does not overlap with the second wavelength sub-range.

[0164] The second configuration of the light-blocking material layer 740L provides: a first wavelength sub-range in which the first metal layer 741A provides higher reflectivity than the second metal layer 741B and / or the third metal layer 741C; a second wavelength sub-range in which the second metal layer 741B provides higher reflectivity than the first metal layer 741A and / or the third metal layer 741C; and a third wavelength sub-range in which the third metal layer 741C provides higher reflectivity than the first metal layer 741A and / or the second metal layer 741B. When the material compositions of the three metal layers (741A, 741B, 741C) are different from each other, the first, second, and third wavelength sub-ranges may not overlap.

[0165] The third configuration of the light-blocking material layer 740L provides: a first wavelength sub-range in which the first metal layer 741A provides higher reflectivity than the second metal layer 741B, the third metal layer 741C, and / or the fourth metal layer 741D; a second wavelength sub-range in which the second metal layer 741B provides higher reflectivity than the first metal layer 741A, the third metal layer 741C, and / or the fourth metal layer 741D; a third wavelength sub-range in which the third metal layer 741C provides higher reflectivity than the first metal layer 741A, the second metal layer 741B, and / or the fourth metal layer 741D; and a fourth wavelength sub-range in which the fourth metal layer 741D provides higher reflectivity than the first metal layer 741A, the second metal layer 741B, and / or the third metal layer 741C. When the material compositions of the four metal layers (741A, 741B, 741C, 741D) are different from each other, the first wavelength subrange, the second wavelength subrange, the third wavelength subrange, and the fourth wavelength subrange do not have any overlap.

[0166] Each of the at least two metal layers (741A, 741B, 741C, 741D) of the light-blocking material layer 740L may have a corresponding thickness ranging from 30 nanometers to 600 nanometers, for example from 60 nanometers to 300 nanometers, although smaller and larger thicknesses may also be used.

[0167] Table 1 illustrates two different sub-ranges of embodiments where either the aluminum or gold layer provides higher reflectivity. In this embodiment, aluminum provides higher reflectivity in the wavelength sub-range from 200 nm to 550 nm, while gold provides higher reflectivity in the wavelength sub-range from 600 nm to 1,600 nm.

[0168] Table 1: Reflectivity of aluminum and gold as a function of wavelength

[0169]

[0170] Reference Figure 7D The diagram illustrates a fourth configuration of the light-blocking material layer 740L, which includes a vertically alternating sequence of a first material layer 742A having a first refractive index and a second material layer 742B having a second refractive index. The first material layer 742A and the second material layer 742B alternate vertically in a sequence (742A, 742B) along the vertical direction.

[0171] In the vertically alternating sequence (742A, 742B), the first material layer 742A may be repeated at least twice. In other words, at least two first material layers 742A may be present in the vertically alternating sequence (742A, 742B). Similarly, in the vertically alternating sequence (742A, 742B), the second material layer 742B may be repeated at least twice. In other words, at least two second material layers 742B may be present in the vertically alternating sequence (742A, 742B). Within the vertically alternating sequence (742A, 742B), the total number of adjacent pairs of repetitions of the first material layer 742A and the second material layer 742B may be in the range of 2 to 20, for example, from 3 to 10. The total number of repetitions of adjacent pairs of first material layers 742A and second material layers 742B within a vertically alternating sequence (742A, 742B) can be selected to produce a constructive interference pattern for a specific wavelength subrange, such that the reflectivity of light within this wavelength subrange is in the range of 0.8 to 1.0, for example, from 0.9 to 1.0 (e.g., from 0.95 to 1.0).

[0172] In one embodiment, the first material layer 742A and / or the second material layer 742B may comprise a dielectric metal oxide, and / or be substantially composed of their respective dielectric metal oxides. In one embodiment, each dielectric metal oxide in the first material layer 742A and / or the second material layer 742B may comprise a material of magnesium oxide, aluminum oxide, ytterbium oxide, zinc oxide, tantalum oxide, zirconium oxide, hafnium oxide, tellurium oxide, and titanium oxide, and / or may be substantially composed of a material selected from magnesium oxide, aluminum oxide, ytterbium oxide, zinc oxide, tantalum oxide, zirconium oxide, hafnium oxide, tellurium oxide, and titanium oxide. Other suitable materials are contemplated within the scope of the disclosure.

[0173] In one embodiment, the first material layer 742A and / or the second material layer 742B may comprise doped silicate glass, and / or may consist primarily of doped silicate glass comprising at least one dopant element in an atomic percentage ranging from 1% to 50%. In one embodiment, the at least one dopant element may comprise calcium and one or more combinations of fluorine, boron, barium, phosphorus, lanthanum, and lead, and / or may consist of calcium and one or more combinations of fluorine, boron, barium, phosphorus, lanthanum, and lead. When the combination of calcium and fluorine is used as the at least one dopant element, CaF2 may be added to the silicate glass (SiO2) to provide doped silicate glass. The doped silicate glass may comprise any one of fluorosilicate glass, borosilicate glass, barium-doped silicate glass, lanthanum-doped silicate glass, or lead-doped silicate glass. Optionally or additionally, titanium oxide and / or aluminum oxide may be added to the silicate glass to form the doped silicate glass material of the first material layer 742A and / or the second material layer 742B. In the case where the first material layer 742A comprises a first-doped silicate glass material and the second material layer 742B comprises a second-doped silicate glass material, the first-doped silicate glass material and the second-doped silicate glass material may have different compositions and different refractive indices. All refractive indices discussed herein were measured at a wavelength of 587.56 nm, which is the wavelength of the sodium D line used in this technique to measure the refractive index.

[0174] In one embodiment, the first material layer 742A and / or the second material layer 742B may comprise silicon, doped silicon (including dopants with an atomic concentration of less than 5%), silicon nitride, silicon oxide, and silicon-rich silicon oxide, and / or may be substantially composed of silicon, doped silicon (including dopants with an atomic concentration of less than 5%), silicon nitride, silicon oxide, and silicon-rich silicon oxide.

[0175] In one embodiment, the first material layer 742A has a first refractive index, and the second material layer 742B has a second refractive index different from the first refractive index. The first and second refractive indices are in the range of 1.0 to 4.0, and the difference between the first and second refractive indices is in the range of 0.1 to 3.0.

[0176] In one embodiment, each of the plurality of first material layers 742A has a first thickness, each of the plurality of second material layers 742B has a second thickness, and the first thickness and the second thickness are in the range of 0.5 nanometers to 500 nanometers, for example, from 5 nanometers to 50 nanometers.

[0177] Table 2 provides information that can be used Figure 7D or Figure 7EList of refractive indices of the materials of the first material layer 742A and / or the second material layer 742B within the illustrated light-blocking material layer 740L.

[0178] Table 2: Available Figure 7D or Figure 7E The refractive index of the material used in the light-blocking layer 740L is shown.

[0179]

[0180] Reference Figure 7E The fifth configuration of the light-blocking material layer 740L is illustrated, which includes... Figure 7A , Figure 7B ,or Figure 7C The light-blocking material layer 740L, and Figure 7D The light-blocking material layers are stacked in layers of 740L. Typically, Figure 7E The light-blocking material layer 740L may include at least one metal layer, and a vertically alternating sequence of a first material layer 742A having a first refractive index and a second material layer 742B having a second refractive index. In one embodiment, Figure 7E The light-blocking material layer 740L may include at least two metal layers (741A, 741B, 741C, 741D), and a vertically alternating sequence of a first material layer 742A having a first refractive index and a second material layer 742B having a second refractive index. The at least two metal layers (741A, 741B, 741C, 741D) may be located above or below the vertically alternating sequence of the first material layer 742A and the second material layer 742B. The at least two metal layers (741A, 741B, 741C, 741D) may be used in conjunction with... Figures 7A to 7C The structure is identical to any structure shown in the diagram. The vertically alternating sequence of the first material layer 742A and the second material layer 742B can be... Figure 7D The same as in the above. A combination of at least two metal layers (741A, 741B, 741C, 741D) and a first material layer 742A and a second material layer 742B in a vertically alternating sequence reflects light with minimal deviation from 100% reflectivity in a wavelength range from 200 nm to 1,600 nm.

[0181] Return to reference Figure 6A and Figure 6BA photoresist layer 747 can be applied over a light-blocking material layer 740L, and the photoresist layer 747 can be photolithographically patterned to form multiple openings within multiple areas of multiple image pixels, but not within multiple areas of multiple black level correction (BLC) pixels including multiple black level correction sub-pixels 809. Each image pixel is a pixel 900, which is used to generate an electronic signal proportional to the amount of incident light for a pixel in an image, and each black level correction pixel is a pixel used to generate an electronic signal that measures background noise in the absence of incident light, for black level correction of multiple electronic signals generated from multiple image pixels. Openings can be formed for each sub-pixel (801, 802, 803) in the image pixel. Specifically, multiple openings in the photoresist layer 747 can be formed within multiple areas of the second conductivity type photodiode layer 602, that is, within multiple areas of multiple photodetectors, the multiple areas of which include a corresponding pn junction between the second conductivity type photodiode layer 602 and the doped well structure 607. Multiple areas of multiple transistors in the sensing circuit (e.g., reset transistor 640, source follower transistor 650, and select transistor 660) may or may not be covered by the photoresist layer 747. After photolithography, the photoresist layer 747 can cover the entire area of ​​the black level correction pixel.

[0182] Reference Figures 8A to 8C Multiple portions of the light-blocking material layer 740L, not covered by the patterned portions of the photoresist layer 747, can be etched to form multiple openings through it in the image pixel region. For example, an anisotropic etching process, such as reactive ion etching, can be used to transfer patterns in the photoresist layer 747 through the light-blocking material layer 740L. The remaining portions of the light-blocking material layer 740L form a grid structure 740. The grid structure 740 may cover the periphery of the second conductivity type photodiode layer 602 and may define a light-collecting area for each photodetector located within a corresponding sub-pixel 800 in the image pixel region. Pixel 900 may include multiple sub-pixels configured to detect a set of light at different wavelengths.

[0183] In one implementation, each image pixel may include a set of multiple image sub-pixels. For example, each image pixel may include at least one instance of a first sub-pixel 801, at least one instance of a second sub-pixel 802, and at least one instance of a third sub-pixel 803. Figure 8A and Figure 8BIn the illustrated embodiment, an image pixel may include a first sub-pixel 801 (e.g., a green sub-pixel) located in a first sub-pixel region, two second sub-pixel 802 (e.g., two red sub-pixels) located in two second sub-pixel regions, and a third sub-pixel 803 (e.g., a blue sub-pixel) located in a third sub-pixel region. Typically, an image pixel may include various combinations of at least two types of sub-pixels 800 configured to detect light in different wavelength ranges. Alternatively, the image sensor may be a monochrome image sensor comprising a single type of sub-pixel 800. In this embodiment, each image pixel may include only a single sub-pixel 800.

[0184] Each black level correction pixel may be a copy of an image pixel. In one embodiment, each black level correction pixel may include a set of multiple image sub-pixels. For example, each image pixel may include at least one instance of a first black level correction sub-pixel 811, at least one instance of a second black level correction sub-pixel 812, and at least one instance of a third black level correction sub-pixel 813. Typically, a black level correction pixel may include various combinations of at least two types of black level correction sub-pixels configured to provide a background level electrical signal in the absence of incident light. Alternatively, the image sensor may be a monochrome image sensor comprising a single type of sub-pixel 800. In this embodiment, each black level correction pixel may include only a single black level correction sub-pixel.

[0185] A grid structure 740 may be formed above the distal surface of a proximal dielectric layer 734 in an image pixel region. The grid structure 740 includes a plurality of openings that cover a corresponding one of a plurality of photodetectors (including a transmission transistor 630). A plurality of portions of the distal surface of the proximal dielectric layer 734 in contact with the bottom surface of the grid structure are a plurality of flat distal surface portions of the distal surface of the proximal dielectric layer 734.

[0186] In some embodiments, the grid structure 740 may divide each sub-pixel 800 in the image pixel region into a detector region and a sensing circuit region. For example, a first sub-pixel 801 may include a first detector region 801D covering a second conductivity type photodiode layer 602 of the first sub-pixel 801, and a first sensing circuit region 801S covering the sensing circuit (640, 650, 660) of the first sub-pixel 801. A second sub-pixel 802 may include a second detector region 802D covering a second conductivity type photodiode layer 602 of the second sub-pixel 802, and a second sensing circuit region 802S covering the sensing circuit (640, 650, 660) of the second sub-pixel 802. A third sub-pixel 803 may include a third detector region 803D covering a second conductivity type photodiode layer 602 of the third sub-pixel 803, and a third sensing circuit region 803S covering the sensing circuit (640, 650, 660) of the third sub-pixel 803. Typically, all subpixels 800 of this group within pixel 900 can be arranged using any pattern that contributes to the periodic repetition of multiple pixels 900 within the array 1000 of pixels 900.

[0187] Usually, in Figures 8A to 8C During the manufacturing process steps, such as in Figure 6A and Figure 6B During the manufacturing process, the first unpatterned portion of the light-blocking material layer 740L continuously extends over the entire area of ​​the black level correction pixel region (i.e., over each black level correction pixel). The grid structure 740 includes, as in... Figure 6A and Figure 6B The second portion of the light-blocking material layer 740L provided during the manufacturing process is provided in the image pixel area, and... Figures 8A to 8C The light-blocking material layer 740L is patterned during the manufacturing process. As discussed above, the light-blocking material layer 740L may be a composite layer stack comprising multiple layers, and the grid structure 740 includes a second portion of the layer stack that laterally adjacent to the first portion of the layer stack. Therefore, the first portion of the layer stack (i.e., in...) Figures 8A to 8C The light-blocking material layer 740L in the black level correction pixel area during the manufacturing process and the second part of the layer stack (i.e., the grid structure 740) have the same vertical sequence of multiple constituent layers. Each constituent layer within the layer stack has a uniform thickness across the first part and the second part of the layer stack.

[0188] Reference Figure 9A and Figure 9BAn optically transparent layer 770 with a flat top surface may be formed above the lattice structure 740. The optically transparent layer 770 may be formed by depositing a self-planarizing dielectric material, such as a flowable oxide (FOX). Alternatively, the deposition and planarization of the transparent dielectric material may be performed, for example, via chemical mechanical planarization to provide the optically transparent layer 770.

[0189] An optically transparent layer 770 extends vertically through an opening in the lattice structure 740 and has a second refractive index different from the first refractive index. The optically transparent layer 770 is formed on the dielectric layer 734 at the near end.

[0190] Various color filter materials can be applied over the optically transparent layer 770, and these materials can be patterned to form various color filters 780. The color filters 780 may include: a first-type color filter 781 formed within the regions of the first sub-pixel 801 and the first black level correction sub-pixel 811; a second-type color filter 782 formed within the regions of the second sub-pixel 802 and the second black level correction sub-pixel 812; and a third-type color filter 783 formed within the regions of the third sub-pixel 803 and the third black level correction pixel 813. The composition of each color filter material can be selected such that light within the target wavelength range passes through the color filter material, while light outside the target wavelength range is absorbed by the color filter material.

[0191] An optical lens 790 may be formed above a color filter 780 by applying an optically transparent material above the color filter 780 and by patterning the optically transparent material into a plurality of material portions having a plurality of convex surfaces centered on a corresponding opening among a plurality of lower openings within a grid structure 740.

[0192] Each combination of an optional anti-reflective coating 732, a near-end dielectric layer 734, a grid structure 740, and multiple portions of an optically transparent layer 770, an overlying color filter 780, and an overlying optical lens 790, located within a sub-pixel 800 in an image pixel region, constitutes an image sub-pixel optical device assembly configured to filter and focus light onto a corresponding lower photodetector of the image sub-pixel. An image sub-pixel optical device assembly for a group of all image sub-pixels within an image pixel constitutes an image pixel optical device assembly. Each combination of an optional anti-reflective coating 732, a near-end dielectric layer 734, a light-blocking material layer 740L, and multiple portions of an optically transparent layer 770, an overlying color filter 780, and an overlying optical lens 790, located within a sub-pixel 800 in a black level correction pixel region, constitutes a black level correction sub-pixel optical device assembly configured to block light incident on a corresponding lower photodetector of the black level correction sub-pixel. An image pixel optics assembly comprises a group of multiple black level correction sub-pixel optics for all black level correction sub-pixels within an image pixel.

[0193] Reference Figure 10A and Figure 10B The carrier substrate 690 and the bonding buffer layer 689 (if present) can be separated from the interconnect-level dielectric layer 670. Before or after separating the carrier substrate 690 from the semiconductor substrate 510, the semiconductor substrate 510 and the plurality of device structures thereon can be divided into discrete image sensors.

[0194] Typically, a plurality of pixels in an array 1000 can be formed on a semiconductor substrate 510. Each pixel within the plurality of pixels in the array 1000 includes at least one sub-pixel, and each sub-pixel includes a corresponding photodetector (including a transmission transistor 630) and a corresponding sensing circuit (640, 650, 660) located on the front surface 609 of the semiconductor substrate 510. Black level correction pixels, including black level correction sub-pixels, can be provided around the plurality of image pixels in the array. Image sub-pixel optics assemblies cover the photodetector circuitry of each image sub-pixel. Image pixel optics assemblies cover the photodetector circuitry of each image pixel. Black level correction sub-pixel optics assemblies cover the photodetector circuitry of each black level correction sub-pixel. Black level correction pixel optics assemblies cover the photodetector circuitry of each black level correction pixel.

[0195] Figure 10A and Figure 10B A first configuration of an exemplary structure is illustrated, wherein, as in Figure 6A and Figure 6BThe light-blocking material layer 740L provided during the manufacturing process includes at least two metal layers (741A, 741B, 741C, 741D), such as in... Figures 7A to 7C and Figure 7E As shown in the illustration. Figure 10A and Figure 10B Each of the plurality of black level correction pixel optical device assemblies provided during the manufacturing process includes a first portion of a layer stack, the first portion of the layer stack including at least two metal layers (741A, 741B, 741C, 741D) extending continuously over the entire area of ​​a corresponding black level correction pixel. As in Figure 10A and Figure 10B Each of the multiple image pixel optical device assemblies provided during the manufacturing process includes a portion of a grid structure 740, which is a second portion of a layer stack including at least two metal layers (741A, 741B, 741C, 741D), and the second portion of the layer stack includes multiple discrete openings above multiple areas of multiple photodetectors.

[0196] Each of the at least two metal layers (741A, 741B, 741C, 741D) comprises a respective wavelength subrange that has greater reflectivity than another metal layer selected from the at least two metal layers in the wavelength range from 200 nm to 1,600 nm, and wherein a first portion of the layer stack does not include any openings therethrough. In some embodiments, one of the at least two metal layers (741A, 741B, 741C, 741D) comprises a refractory metal layer, and the other of the at least two metal layers (741A, 741B, 741C, 741D) comprises a layer selected from gold, silver, copper, and aluminum. Alternatively or additionally, the at least two metal layers (741A, 741B, 741C, 741D) may comprise at least two layers selected from gold, silver, copper, and aluminum. In one embodiment, the light-blocking material layer 740L and the grating structure 740 may further include a vertically alternating sequence of a first material layer 742A having a first refractive index and a second material layer 742B having a second refractive index, as shown in... Figure 7E shown in.

[0197] Reference Figure 11A and Figure 11B The diagram illustrates a second configuration of an exemplary structure, wherein, as in Figure 6A and Figure 6B The light-blocking material layer 740L provided during the manufacturing process includes a layer stack comprising a vertically alternating sequence of a first material layer 742A having a first refractive index and a second material layer 742B having a second refractive index, as shown in... Figure 7D and Figure 7EAs illustrated in the diagram. In this configuration, each of the plurality of black level correction pixel optics assemblies includes a first portion of a layer stack comprising a vertically alternating sequence of a first material layer 742A having a first refractive index and a second material layer 742B having a second refractive index. The first portion of the layer stack does not include any openings therethrough. Each of the plurality of image pixel optics assemblies includes a portion of a grid structure 740, which is a second portion of a layer stack comprising a vertically alternating sequence of the first material layer 742A and the second material layer 742B, the second portion of the layer stack including a plurality of discrete openings above a plurality of areas of a plurality of photodetectors. The first portion and the second portion of the layer stack have the same vertical sequence of a plurality of constituent layers. Each constituent layer within the layer stack has a uniform thickness in both the first and second portions of the layer stack.

[0198] In one embodiment, the first material layer 742A and / or the second material layer 742B comprises a dielectric metal oxide. In one embodiment, each dielectric metal oxide in the first material layer 742A and / or the second material layer 742B comprises a material of magnesium oxide, aluminum oxide, ytterbium oxide, zinc oxide, tantalum oxide, zirconium oxide, hafnium oxide, tellurium oxide, and titanium oxide, and / or is substantially composed of a material selected from magnesium oxide, aluminum oxide, ytterbium oxide, zinc oxide, tantalum oxide, zirconium oxide, hafnium oxide, tellurium oxide, and titanium oxide.

[0199] In one embodiment, the first or second material layer comprises a doped silicate glass comprising at least one dopant element in an atomic percentage range of 1% to 50%. In one embodiment, the at least one dopant element may comprise calcium and at least one of a combination of fluorine, boron, barium, phosphorus, lanthanum, and lead. In one embodiment, the first material layer 742A and / or the second material layer 742B may consist substantially of silicon, doped silicon comprising dopants with an atomic concentration of less than 50% (e.g., from 0.5% to 50%), silicon nitride, silicon oxide, and silicon-rich silicon oxide.

[0200] In one embodiment, a first material layer 742A has a first refractive index, and a second material layer 742B has a second refractive index different from the first refractive index. The first and second refractive indices are in the range of 1.0 to 4.0, and the difference between the first and second refractive indices is in the range of 0.1 to 3.0. In one embodiment, each of the plurality of first material layers 742A has a first thickness, and each of the plurality of second material layers 742B has a second thickness. The first and second thicknesses are in the range of 0.5 nanometers to 500 nanometers, for example, from 5 nanometers to 50 nanometers.

[0201] Reference Figure 12A and Figure 12B The diagram illustrates a third configuration of an exemplary structure according to embodiments of this disclosure. This third configuration of the exemplary structure can be derived from any of the above-described configurations of the exemplary structure by forming an infrared blocking material layer 786 only in the black level correction pixel region. The infrared blocking material may be deposited above or below a layer of the plurality of color filters 780, or may be formed above a plurality of optical lenses 790. The infrared blocking material layer 786 may be patterned such that the entire area of ​​the black level correction pixel region is covered by the infrared blocking material, while the area of ​​the image pixel region is not covered by the infrared blocking material. Therefore, the infrared blocking material layer 786 is not present in the image pixel region and covers the entire area of ​​the black level correction pixel region.

[0202] The infrared blocking material layer 786 comprises a material that absorbs infrared radiation in the wavelength range from 800 nanometers to 1,600 nanometers. In one embodiment, the infrared blocking material layer 786 may comprise a polymeric material, a semiconductor material, and / or a metallic material. For example, the infrared blocking material layer 786 may comprise a color resist with embedded metal particles, and / or a color resist mixed with or embedded in black resin. The metal particles may comprise particles of one or more refractory metals, such as tungsten, niobium, molybdenum, tantalum, rhenium, titanium, vanadium, chromium, zirconium, hafnium, ruthenium, rhodium, osmium, and iridium. The average size of the metal particles (e.g., providing an effective diameter for spheres of equal volume) may range from 1 nanometer to 100 nanometers, for example from 5 nanometers to 30 nanometers, although smaller and larger average sizes may also be used. The thickness of the infrared blocking material layer 786 may range from 100 nanometers to 1,000 nanometers, although smaller and larger thicknesses may also be used.

[0203] In one embodiment, each of the plurality of black level correction pixel optics assemblies includes an infrared blocking material layer 786, which provides a higher absorption coefficient than any color filter material of the color filter 780 within the image pixel optics assembly in a wavelength range from 800 nm to 1,600 nm. While this disclosure has been described using one embodiment, the light-blocking material layer 740L in the third exemplary structure is used in… Figure 7C The third configuration of the light-blocking material layer 740L shown is illustrated, but in the third configuration of the exemplary structure, the light-blocking material layer 740L may have... Figures 7A to 7E Any configuration shown.

[0204] Reference Figure 13A and Figure 13B The illustration depicts a fourth configuration of an exemplary structure according to embodiments of this disclosure. The fourth configuration of the exemplary structure includes... Figure 7EThe illustration shows a fifth configuration of the light-blocking material layer 740L. In this configuration, the layer stack of the light-blocking material layer 740L may include at least one metal layer that is in contact with a vertically alternating sequence of a first material layer 742A and a second material layer 742B. The at least one metal layer may include at least two metal layers (741A, 741B, 741C, 741D) as described above.

[0205] Reference Figure 14 A circuit diagram for a photodetector circuit is illustrated according to an embodiment of this disclosure. The photodetector circuit configuration includes a transfer transistor 630 and an interconnection of multiple field-effect transistors (640, 650, 660). The transfer transistor 630 may include a pn junction between a combination of a second conductivity type photodiode layer 602 and a buried second conductivity type photodiode layer 606 and a substrate semiconductor layer 601 having a first conductivity type doping. The substrate semiconductor layer 601, the buried second conductivity type photodiode layer 606, the second conductivity type photodiode layer 602, and the first conductivity type pinning layer 603 function as photodiodes (PPDs). The second conductivity type photodiode layer 602 functions as the source region of the transfer transistor 630.

[0206] The floating diffusion region 608 (labeled "FD") functions as the drain region of the transfer transistor 630. The transfer gate electrode 605 (labeled "TG") controls the transfer of charge accumulated in the second conductivity type photodiode layer 602 to the floating diffusion region 608 through a semiconductor channel below the transfer gate electrode 605. The transfer transistor 630 can function as a photodetector.

[0207] The sensing circuit includes an interconnect assembly of multiple field-effect transistors (640, 650, 660). This interconnect assembly of the multiple field-effect transistors (640, 650, 660) is connected to a floating diffusion region 608. This interconnect assembly of the multiple field-effect transistors (640, 650, 660) includes a reset transistor RST, a source follower transistor SF, and a select transistor SEL. The reset transistor 640 (i.e., RST) is configured to deplete the charge in the floating diffusion region 608 immediately before sensing, such that the charge accumulated in the floating diffusion region 608 during sensing is linearly proportional to the charge accumulated in the second conductivity type photodiode layer 602. The gate electrode of the source follower transistor 650 (i.e., SF) is electrically connected to the floating diffusion region 608 via a set of multiple metal interconnect structures. Therefore, the voltage at the gate electrode of the source follower transistor 650 is proportional to the charge in the floating diffusion region 608. Select transistor 660 (i.e., SEL) can be turned on during a read operation to output the voltage at the common node of the source follower transistor and select transistor 660 (adjusted by the voltage at the gate electrode of the source follower transistor 650) to a column output bus (labeled "V_out").

[0208] Common Reference Figures 1A to 14 According to various embodiments of this disclosure, an image sensor is provided, which includes an image pixel array (e.g., on a semiconductor substrate 510) located on a semiconductor substrate 510. Figure 1A and Figure 1B P in ij (2≤i≤(M-1), 2≤j≤(N-1)), wherein each image pixel within a plurality of image pixels in an array includes an image pixel photodetector (which is included in each photodetector within the image pixel, such as each transmission transistor 630), an image pixel sensing circuit (which is included in each sensing circuit within the image pixel), and an image pixel optical assembly configured to filter incident light and guide the incident light to the image pixel photodetector. The image sensor includes a plurality of black level correction (BLC) pixels (e.g., ...) adjacent to the plurality of image pixels in this array on the semiconductor substrate 510. Figure 1A and Figure 1B P in st , where s is 1 or M, or t is 1 or N), wherein each black level correction pixel includes a black level correction pixel photodetector (which is contained within each photodetector within the black level correction pixel, such as each transmission transistor 630), a black level correction pixel sensing circuit (which is contained within each sensing circuit within the black level correction pixel), and a black level correction pixel optical assembly configured to block light incident on the black level correction pixel photodetector.

[0209] In some embodiments, each of the plurality of black level correction pixel optics assemblies includes a first portion of a layer stack comprising a vertically alternating sequence of a first material layer 742A having a first refractive index and a second material layer 742B having a second refractive index. The first portion of the layer stack does not include any openings therethrough.

[0210] In some embodiments, each of the plurality of black level correction pixel optics assemblies includes a first portion of a layer stack comprising at least two metal layers (741A, 741B, 741C, 741D). Each of the at least two metal layers (741A, 741B, 741C, 741D) comprises a respective wavelength subrange that has greater reflectivity than another metal layer (741A, 741B, 741C, 741D) selected from the at least two metal layers in the wavelength range from 200 nm to 1,600 nm. The first portion of the layer stack does not include any openings therethrough. In one embodiment, each of the at least two metal layers (741A, 741B, 741C, 741D) comprises a respective wavelength subrange that has greater reflectivity in the wavelength range from 200 nm to 1,600 nm than any other metal layer (741A, 741B, 741C, 741D) selected from the at least two metal layers.

[0211] In some embodiments, each of the plurality of black level correction pixel optics assemblies includes an infrared blocking material layer 786 that provides a higher absorption coefficient in a wavelength range from 800 nm to 1,600 nm than any color filter material within the image pixel optics assembly.

[0212] Typically, an image pixel optics assembly includes a grid structure 740, which includes a plurality of openings through an array thereof. The grid structure 740 includes a second portion of a layer stack that laterally adjoins a first portion of the layer stack.

[0213] Reference Figure 15 The process flow diagram illustrates an exemplary process sequence for forming an image sensor according to an embodiment of this disclosure. Referring to step 1510, an image pixel photodetector, an image pixel sensing circuit, a black level correction pixel, and a black level correction pixel sensing circuit may be formed on one side of the semiconductor substrate 510. Referring to step 1520, an image pixel optics assembly and a black level correction pixel optics assembly may be formed on the other side of the semiconductor substrate 510. The image pixel optics assembly and the black level correction pixel optics assembly may have the structural features described above.

[0214] Various embodiments of this disclosure provide an image sensor including a black level correction (BLC) pixel, which comprises a corresponding black level correction pixel optics assembly. A composite material layer comprising a stack of at least two material layers can be formed as a light-blocking material layer 740L in each of the plurality of black level correction pixel optics assemblies to enhance light reflection in the plurality of black level correction pixels. Alternatively or additionally, an infrared blocking material layer 786 can be formed in the black level correction pixel to enhance the blocking of infrared radiation from the black level correction pixel. The enhanced light blocking in the black level correction pixel increases the accuracy of the measurement of the background electrical signal of the photodetector and can enhance the fidelity of the image captured by the image sensor.

[0215] Some embodiments of this disclosure provide an image sensor comprising: an array of a plurality of image pixels and a plurality of black level correction pixels. The plurality of image pixels are located on a semiconductor substrate, wherein each image pixel within the plurality of image pixels includes an image pixel photodetector, an image pixel sensing circuit, and an image pixel optics assembly configured to filter and guide incident light onto the image pixel photodetector. The plurality of black level correction pixels are located adjacent to the plurality of image pixels on the semiconductor substrate, wherein each of these black level correction pixels includes a black level correction pixel photodetector, a black level correction pixel sensing circuit, and a black level correction pixel optics assembly configured to block light incident on the black level correction pixel photodetector, wherein each of these black level correction pixel optics assemblies includes a first portion of a layer stack comprising a vertically alternating sequence of a plurality of first material layers having a first refractive index and a plurality of second material layers having a second refractive index, wherein the first portion of the layer stack does not include any openings therethrough. In some embodiments, in an image sensor, an image pixel optics assembly includes a grating structure comprising a plurality of openings through an array therethrough, and the grating structure includes a second portion of a stack laterally adjacent to a first portion of the stack. In some embodiments, in an image sensor, the first and second portions of the stack have the same vertical sequence of constituent layers; and each of these constituent layers within the stack has a uniform thickness spanning the first and second portions of the stack. In some embodiments, in an image sensor, the first or second material layers comprise a dielectric metal oxide. In some embodiments, in an image sensor, the first or second material layers comprise a doped silicate glass comprising at least one dopant element in the atomic percentage range of 1% to 50%. In some embodiments, in an image sensor, the first or second material layers are primarily composed of silicon, doped silicon comprising dopants with an atomic concentration of less than 50%, silicon nitride, silicon oxide, and silicon-rich silicon oxide. In some embodiments, in the image sensor, the first refractive index and the second refractive index are in the range of 1.0 to 4.0; and the first refractive index and the second refractive index are in the range of 1.0 to 4.0. In some embodiments, in the image sensor, each of the first material layers has a first thickness; each of the second material layers has a second thickness; and the first thickness and the second thickness are in the range of 0.5 nanometers to 500 nanometers. In some embodiments, in the image sensor, the layer stack further includes at least one metal layer in contact with the vertically alternating sequence of the first material layers.In some implementations, each of these black level correction pixel optics assemblies in the image sensor includes an infrared blocking material layer that provides a higher absorption coefficient than any color filter material within the image pixel optics assembly in a wavelength range from 800 nm to 1,600 nm.

[0216] Other embodiments of this disclosure provide an image sensor comprising: an array of a plurality of image pixels and a plurality of black level correction pixels. The plurality of image pixels are located on a semiconductor substrate, wherein each image pixel within the plurality of image pixels includes an image pixel photodetector, an image pixel sensing circuit, and an image pixel optics assembly configured to filter incident light and direct the incident light onto the image pixel photodetector. The plurality of black level correction pixels are located adjacent to the plurality of image pixels on the semiconductor substrate, wherein each of these black level correction pixels includes a black level correction pixel photodetector, a black level correction pixel sensing circuit, and a black level correction pixel optics assembly configured to block light incident on the black level correction pixel photodetector, wherein each of these black level correction pixel optics assemblies includes: a first portion of a layer stack comprising at least two metal layers, wherein each of the at least two metal layers includes a respective wavelength subrange having greater reflectivity than another metal layer selected from the at least two metal layers in a wavelength range from 200 nm to 1,600 nm, and wherein the first portion of the layer stack does not include any openings therethrough. In some embodiments, in an image sensor, the image pixel optics assembly includes a grid structure comprising a plurality of openings through an array thereof, and the grid structure includes a second portion of a layer stack laterally adjacent to a first portion of the layer stack. In some embodiments, in an image sensor, the first and second portions of the layer stack have the same vertical sequence of multiple constituent layers; and each constituent layer within the layer stack has a uniform thickness across the first and second portions of the layer stack. In some embodiments, in an image sensor, one of the at least two metal layers comprises a refractory metal layer; and the other of the at least two metal layers comprises a layer selected from gold, silver, copper, and aluminum. In some embodiments, in an image sensor, the at least two metal layers comprise at least two layers selected from gold, silver, copper, and aluminum. In some embodiments, in an image sensor, the layer stack further includes a vertically alternating sequence of multiple first material layers having a first refractive index and multiple second material layers having a second refractive index. In some implementations, each of these black level correction pixel optics assemblies in the image sensor includes an infrared blocking material layer that provides a higher absorption coefficient than any color filter material within the image pixel optics assembly in a wavelength range from 800 nm to 1,600 nm.

[0217] Further embodiments of this disclosure provide an image sensor comprising: an array of a plurality of image pixels and a plurality of black level correction pixels. The plurality of image pixels are located on a semiconductor substrate, wherein each image pixel within the array includes an image pixel photodetector, an image pixel sensing circuit, and an image pixel optics assembly configured to filter incident light and direct the incident light onto the image pixel photodetector. The plurality of black level correction pixels are located adjacent to the plurality of image pixels on the semiconductor substrate, wherein each of these black level correction pixels includes a black level correction pixel photodetector, a black level correction pixel sensing circuit, and a black level correction pixel optics assembly configured to block light incident on the black level correction pixel photodetector, wherein each of these black level correction pixel optics assemblies includes an infrared blocking material layer that provides a higher absorption coefficient in the wavelength range from 800 nm to 1600 nm than any color filter material within the image pixel optics assembly. In some embodiments, in the image sensor, each of these black level correction pixel optics assemblies includes a first portion of a layer stack comprising a vertically alternating sequence of a plurality of first material layers having a first refractive index and a plurality of second material layers having a second refractive index; the first portion of the layer stack does not include any openings therethrough; and the image pixel optics assemblies include a grid structure comprising a plurality of openings in an array therethrough, and the grid structure includes a second portion of the layer stack laterally adjacent to the first portion of the layer stack. In some embodiments, in an image sensor, each of these black level correction pixel optics assemblies includes: a first portion of a layer stack comprising at least two metal layers; each of the at least two metal layers comprising a respective wavelength subrange having greater reflectivity than another metal layer selected from the at least two metal layers in a wavelength range from 200 nanometers to 1,600 nanometers; the first portion of the layer stack not including any openings therethrough; and the image pixel optics assemblies including a grid structure comprising a plurality of openings in an array therethrough, and the grid structure including a second portion of the layer stack laterally adjacent to the first portion of the layer stack.

[0218] Several embodiments have been outlined above to enable those skilled in the art to better understand the various forms of this disclosure. Those skilled in the art should understand that they may readily use this disclosure as a basis for the design and modification of other processes and structures to achieve the same purpose or the same advantages as the embodiments described herein. Those skilled in the art should also understand that equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. An image sensor, characterized in that, Include: An array of multiple image pixels is located on a semiconductor substrate, wherein each image pixel within the array of multiple image pixels includes an image pixel photodetector, an image pixel sensing circuit, and an image pixel optical assembly configured to filter and guide incident light onto the image pixel photodetector. A plurality of black level correction pixels are located adjacent to a plurality of image pixels in the array on the semiconductor substrate, wherein each of the plurality of black level correction pixels includes a black level correction pixel photodetector, a black level correction pixel sensing circuit, and a black level correction pixel optical assembly configured to block light illuminating the black level correction pixel photodetector. An optically transparent layer comprising a self-planarizing dielectric material having a flat top surface; Multiple color filters, each containing a corresponding color-filtering material, are located above the optically transparent layer; as well as A patterned layer stack, within the optically transparent layer and below the color filters, wherein the patterned layer stack comprises a vertically alternating sequence comprising a first material layer and a second material layer, the total number of repetitions of the first material layer and the second material layer being in the range of 2 to 20, the first material layer having a first refractive index, and the second material layer having a second refractive index different from the first refractive index, the patterned layer stack comprising a first portion of a region of the black level correction pixels and a second portion of a region of a plurality of image pixels in the array, the first portion not including any openings therethrough, the second portion being a grid structure having a plurality of openings, the vertically alternating sequence being configured to produce a constructive interference pattern for a wavelength subrange such that the reflectivity of light within the wavelength subrange is in the range of 0.8 to 1.

0.

2. The image sensor according to claim 1, characterized in that, The second portion of the patterned layer stack is laterally adjacent to the first portion of the patterned layer stack.

3. The image sensor according to claim 2, characterized in that: The first part of the patterned layer stack and the second part of the patterned layer stack have the same vertical sequence of multiple constituent layers; and Each of the plurality of constituent layers within the patterned layer stack has a uniform thickness spanning the first portion and the second portion of the patterned layer stack.

4. The image sensor according to claim 1, characterized in that, The plurality of first material layers or the plurality of second material layers comprise a dielectric metal oxide.

5. The image sensor according to claim 1, characterized in that, The plurality of first material layers or the plurality of second material layers comprise a doped silicate glass comprising at least one dopant element in an atomic percentage range of 1% to 50%.

6. The image sensor according to claim 1, characterized in that, The plurality of first material layers or the plurality of second material layers are mainly composed of silicon, doped silicon including dopants with an atomic concentration of less than 50%, silicon nitrides, silicon oxides, and silicon-rich silicon oxides.

7. The image sensor according to claim 1, characterized in that: The first refractive index and the second refractive index are in the range of 1.0 to 4.0; and The difference between the first refractive index and the second refractive index is in the range of 0.1 to 3.

0.

8. The image sensor according to claim 1, characterized in that: Each of the plurality of first material layers has a first thickness; Each of the plurality of second material layers has a second thickness; and The first thickness and the second thickness are in the range of 0.5 nanometers to 500 nanometers.

9. The image sensor according to claim 1, characterized in that, The patterned layer stack also includes at least one metal layer that contacts the plurality of first material layers in the vertically alternating sequence.

10. The image sensor according to claim 1, characterized in that, Each of the plurality of black level correction pixel optics assemblies includes an infrared blocking material layer that provides a higher absorption coefficient than any color filter material within the image pixel optics assembly in a wavelength range from 800 nm to 1,600 nm.

11. An image sensor, characterized in that, Include: An array of multiple image pixels is located on a semiconductor substrate, wherein each image pixel within the array of multiple image pixels includes an image pixel photodetector, an image pixel sensing circuit, and an image pixel optical assembly configured to filter incident light and guide the incident light to the image pixel photodetector. A plurality of black level correction pixels are located adjacent to a plurality of image pixels in the array on the semiconductor substrate, wherein each of the plurality of black level correction pixels includes a black level correction pixel photodetector, a black level correction pixel sensing circuit, and a black level correction pixel optical assembly configured to block light illuminating the black level correction pixel photodetector. An optically transparent layer comprising a self-planarizing dielectric material having a flat top surface; Multiple color filters, each containing a corresponding color-filtering material, are located above the optically transparent layer; as well as A patterned layer stack, within the optically transparent layer and below the color filters, wherein the patterned layer stack comprises a vertically alternating sequence and at least two metal layers below the vertically alternating sequence, the vertically alternating sequence comprising a first material layer and a second material layer, the total number of repetitions of the first material layer and the second material layer being in the range of 2 to 20, the first material layer having a first refractive index, and the second material layer having a second refractive index different from the first refractive index, the patterned layer stack comprising a first portion of a region of the black level correction pixels and a second portion of a region of a plurality of image pixels in the array, the first portion not including any openings therethrough, the second portion being a grid structure having a plurality of openings, the vertically alternating sequence being configured to produce a constructive interference pattern for a wavelength range such that the reflectivity of light within the wavelength range is in the range of 0.8 to 1.0; Each of the at least two metal layers includes a respective wavelength subrange that has greater reflectivity than another metal layer selected from the at least two metal layers in the wavelength range from 200 nanometers to 1,600 nanometers.

12. The image sensor according to claim 11, characterized in that, The second portion of the patterned layer stack is laterally adjacent to the first portion of the patterned layer stack.

13. The image sensor according to claim 12, characterized in that: Each constituent layer within the patterned layer stack has a uniform thickness spanning the first portion and the second portion of the patterned layer stack.

14. The image sensor according to claim 11, characterized in that: One of the at least two metal layers comprises a refractory metal layer; and The other of the at least two metal layers comprises a layer selected from gold, silver, copper, and aluminum.

15. The image sensor according to claim 11, characterized in that, The at least two metal layers comprise at least two layers selected from gold, silver, copper, and aluminum.

16. The image sensor according to claim 11, characterized in that, The first material layer and the second material layer comprise dielectric metal oxides.

17. The image sensor according to claim 11, characterized in that, Each of the plurality of black level correction pixel optics assemblies includes an infrared blocking material layer that provides a higher absorption coefficient than any color filter material within the image pixel optics assembly in a wavelength range from 800 nm to 1,600 nm.

18. An image sensor, characterized in that, Include: An array of multiple image pixels is located on a semiconductor substrate, wherein each image pixel within the array of multiple image pixels includes an image pixel photodetector, an image pixel sensing circuit, and an image pixel optical assembly configured to filter incident light and guide the incident light to the image pixel photodetector. A plurality of black level correction pixels are located adjacent to a plurality of image pixels in the array on the semiconductor substrate, wherein each of the plurality of black level correction pixels includes a black level correction pixel photodetector, a black level correction pixel sensing circuit, and a black level correction pixel optical assembly configured to block light illuminating the black level correction pixel photodetector. An optically transparent layer comprising a self-planarizing dielectric material having a flat top surface; Multiple color filters, each containing a corresponding color-filtering material, are located above the optically transparent layer; A patterned layer stack, within the optically transparent layer and below the color filters, wherein the patterned layer stack comprises a first portion of a region of the black level correction pixels and a second portion of a region of a plurality of image pixels in the array, the first portion not including any openings therethrough, and the second portion being a grid structure having a plurality of openings; and Multiple optical lenses are positioned above these color filters; Each of the plurality of black level correction pixel optics assemblies includes an infrared blocking material layer that provides a higher absorption coefficient than any color filter material within the image pixel optics assembly in a wavelength range from 800 nm to 1,600 nm. The infrared blocking material layer is located in a vertical direction between the color filters and the optical lenses, and is not located in a region where the plurality of image pixels of the array are located.

19. The image sensor according to claim 18, characterized in that: The patterned layer stack comprises a vertically alternating sequence of multiple first material layers having a first refractive index and multiple second material layers having a second refractive index; and The second portion of the patterned layer stack is laterally adjacent to the first portion of the patterned layer stack.

20. The image sensor according to claim 18, characterized in that: The patterned layer stack includes at least two metal layers; Each of the at least two metal layers includes a respective wavelength subrange that has greater reflectivity than the other metal layer selected from the at least two metal layers in the wavelength range from 200 nanometers to 1,600 nanometers.

Images