Light-emitting display device and multi-screen display device including the light-emitting display device

Abstract

A light-emitting display device and a multi-screen display device including the light-emitting display device are disclosed. The light-emitting display device includes: a substrate, the substrate including a peripheral portion adjacent to a plurality of outer surfaces of the substrate, wherein at least one of the plurality of outer surfaces includes the outermost surface of the substrate; a plurality of pixels located on the substrate to define a display area; a plurality of signal lines connected to the plurality of pixels; a light-emitting device layer included in each of the plurality of pixels; an encapsulation layer on the light-emitting device layer; and a plurality of wirings extending to the peripheral portion and at least partially covering the outermost surface of the substrate.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2020-0177154, filed on December 17, 2020, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This invention relates to a light-emitting display device and a multi-screen light-emitting display device including the light-emitting display device. Background Technology

[0004] Unlike liquid crystal displays (LCDs), light-emitting displays, being self-emissive, do not require a separate light source, allowing them to be manufactured in a lightweight and thin form. Furthermore, they operate at low voltage, thus reducing power consumption. In addition, light-emitting displays excel in color reproduction, response time, viewing angle, and contrast, attracting considerable attention as a next-generation display technology.

[0005] Light-emitting display devices display images based on the emission of light from a light-emitting device layer, wherein the light-emitting device layer includes light-emitting devices inserted between two electrodes. In this case, the light emitted by the light-emitting devices is emitted to the outside via the electrodes and the substrate.

[0006] The light-emitting display device includes a display panel implemented for displaying an image. The display panel may include a display area having a plurality of pixels for displaying the image and a border area surrounding the display area.

[0007] Related light-emitting display devices require bezels or mechanisms to cover the bezel area located at the boundary (or peripheral portion) of the display panel. Furthermore, these devices have a relatively large bezel width (or a large bezel width) due to the presence of the bezel. Moreover, when the bezel width of the light-emitting display device is reduced below a certain limit, the light-emitting device can degrade due to the penetration of external impurities such as moisture or humidity, thereby reducing the reliability of the display panel.

[0008] Recently, multi-screen luminous display devices that achieve large screens by arranging multiple luminous display devices in a grid pattern have been commercialized. Summary of the Invention

[0009] The inventors of this invention recognized that in multi-screen luminescent display devices of the related art, the presence of bezel areas or borders on each of the multiple luminescent display devices creates boundary portions, such as seams, between adjacent luminescent display devices. The inventors also recognized that when a single image (or image stream) is displayed on the entire assembled screen of the multi-screen luminescent display device, these boundary portions can cause a sense of discontinuity (or anticlimacticity) in the image. Furthermore, for this reason, the viewer's immersion and user experience when viewing the image (or video) can be significantly degraded.

[0010] Therefore, the inventors of this invention provide one or more embodiments of a light-emitting display device and a multi-screen display device including the light-emitting display device, which substantially overcome one or more problems caused by the limitations and disadvantages of related technologies. The one or more embodiments provided by the inventors also solve other technical problems in related technologies not mentioned above.

[0011] One aspect of the present invention aims to provide a light-emitting display device and a multi-screen display device including the light-emitting display device, which prevents the reliability of the light-emitting device from being reduced due to the penetration of external impurities such as moisture or humidity.

[0012] Another aspect of the present invention aims to provide a light-emitting display device and a multi-screen display device including the light-emitting display device, which has a zero bezel and prevents the reliability of the light-emitting device from being degraded due to the penetration of moisture or humidity. The terms "zero bezel" or "air bezel" are used to refer to a display device with a relatively small bezel or no bezel at all. For example, in some embodiments, a display device with a zero bezel includes a display with a bezel of a selected width. However, the width of the bezel or the bezel width falls below a threshold width, so that when two or more displays are assembled together, the bezel width is imperceptible to the viewer, thus not affecting the viewer's immersion or user experience. The threshold width may vary, but is not limited to, various factors including the distance from the multi-screen display to one or more viewers, the viewer's perception, etc. In other embodiments, a display device with a zero bezel includes a display with no bezel at all or a display with a 0 (zero) bezel width.

[0013] Another aspect of the present invention aims to provide a light-emitting display device and a multi-screen display device including the light-emitting display device, which can display an image without interruption when displaying an image on the entire screen.

[0014] Additional advantages and features of the invention will be set forth in part in the description below, some of which will become apparent to those skilled in the art upon review of the following description or will be learned by practice of the invention. These technical advantages of the invention can be realized and obtained by means of the structures specifically pointed out in the specification, claims, and drawings.

[0015] To achieve these and other advantages, as embodied and generalized herein, a display device is provided comprising: a substrate including a peripheral portion adjacent to a plurality of outer surfaces of the substrate, wherein at least one of the plurality of outer surfaces includes the outermost surface of the substrate; a plurality of pixels located on the substrate to define a display area; a plurality of signal lines connected to the plurality of pixels; a light-emitting device layer included in each of the plurality of pixels; an encapsulation layer on the light-emitting device layer; and a plurality of wirings extending to the peripheral portion and at least partially covering the outermost surface of the substrate.

[0016] A display device according to some embodiments of the present invention includes: a first substrate having a first surface adjacent to an edge of the first substrate; a second substrate facing the first substrate having a second surface adjacent to an edge of the second substrate, the second surface and the first surface being adjacent to each other; a plurality of pixels on the first substrate; a plurality of signal lines connected to the plurality of pixels; a light-emitting device layer located on each of the plurality of pixels and on an edge of the first substrate; and a plurality of wirings extending from the first substrate, at least one of the plurality of wirings extending on a first surface of the first substrate and a second surface of the second substrate to form an electrical connection between the first substrate and the second substrate.

[0017] A light-emitting display device according to some embodiments of the present invention includes: a substrate; a display portion including a plurality of pixel regions disposed on the substrate; a circuit layer including a plurality of pixel driving lines disposed in the plurality of pixel regions; a light-emitting device layer including a light-emitting layer disposed on the circuit layer located in the plurality of pixel regions; an encapsulation layer disposed on the light-emitting device layer; and a wiring portion surrounding a front peripheral portion and an outer surface of the substrate, and including a plurality of wirings passing through the encapsulation layer disposed at the front peripheral portion of the substrate to connect to the plurality of pixel driving lines.

[0018] In another aspect, a multi-screen display device includes: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display devices includes a display device, the display device comprising: a substrate including a peripheral portion adjacent to a plurality of outer surfaces of the substrate, wherein at least one of the plurality of outer surfaces includes the outermost surface of the substrate; a plurality of pixels located on the substrate to define a display area; a plurality of signal lines connected to the plurality of pixels; a light-emitting device layer included in each of the plurality of pixels; an encapsulation layer on the light-emitting device layer; and a plurality of wirings extending to the peripheral portion and at least partially covering the outermost surface of the substrate.

[0019] A multi-screen display device according to some embodiments of the present invention includes: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display devices includes a light-emitting display device, the light-emitting display device including: a substrate; a display portion including a plurality of pixel regions disposed on the substrate; a circuit layer including a plurality of pixel driving lines disposed in the plurality of pixel regions; a light-emitting device layer including a light-emitting layer disposed on the circuit layer located in the plurality of pixel regions; an encapsulation layer disposed on the light-emitting device layer; and a wiring portion surrounding a front peripheral portion and an outer surface of the substrate, and including a plurality of wirings passing through the encapsulation layer disposed at the front peripheral portion of the substrate to connect to the plurality of pixel driving lines.

[0020] Embodiments of the present invention may provide a display device and a multi-screen display device including the display device, which prevents the reliability of light-emitting devices from being reduced due to the penetration of moisture or humidity.

[0021] Embodiments of the present invention may provide a display device and a multi-screen display device including the display device, which has a zero bezel and prevents the reliability of the light-emitting device from being reduced due to the penetration of moisture or humidity.

[0022] According to some embodiments of the present invention, a borderless display device and a multi-screen display device including the display device can be provided.

[0023] According to some embodiments of the present invention, a multi-screen display device can be provided that displays images without any sense of discontinuity.

[0024] It should be understood that the foregoing general description and the following detailed description of the invention are illustrative and explanatory, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0025] The accompanying drawings, which provide a further understanding of the invention and are incorporated in and form a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0026] Figure 1 This is a plan view illustrating a light-emitting display device according to an embodiment of the present invention.

[0027] Figure 2 This is a schematic side view illustrating a light-emitting display device according to an embodiment of the present invention.

[0028] Figure 3A It is a diagram Figure 1 The diagram shown illustrates a pixel according to an embodiment of the present invention.

[0029] Figure 3B It is a diagram Figure 1 The diagram shown is an illustration of a pixel according to another embodiment of the present invention.

[0030] Figure 4 yes Figure 1 An enlarged view of region B1 shown in the image.

[0031] Figure 5 It is a diagram Figure 1 and Figure 4 The equivalent circuit diagram of one pixel is shown.

[0032] Figure 6 It is a diagram Figure 4 A diagram showing the gate drive circuit implemented in the display area shown.

[0033] Figure 7 This is a rear perspective view illustrating a light-emitting display device according to an embodiment of the present invention.

[0034] Figure 8 This is a rear perspective view illustrating a light-emitting display device according to another embodiment of the present invention.

[0035] Figure 9 This is a diagram illustrating the connection structure of the pixel driving line and the wiring section according to an embodiment of the present invention.

[0036] Figure 10 It is along Figure 9 The cross-sectional view shown is taken by line I-I'.

[0037] Figure 11 yes Figure 10 An enlarged view of region B2 shown.

[0038] Figure 12 yes Figure 10 An enlarged view of region B3 shown.

[0039] Figure 13 This is a diagram illustrating the connection structure of the pixel driving line and the wiring section according to another embodiment of the present invention.

[0040] Figure 14 yes Figure 13 An enlarged view of region B4 shown.

[0041] Figure 15 It is along Figure 14 The cross-sectional view taken by line II-II' shown.

[0042] Figure 16A yes Figure 15 An enlarged view of area B5 shown.

[0043] Figure 16B According to another embodiment Figure 15 An enlarged view of area B5 shown.

[0044] Figure 16C According to another embodiment Figure 15 An enlarged view of area B5 shown.

[0045] Figure 17 It is along Figure 14 The cross-sectional view taken by line III-III' is shown.

[0046] Figure 18 This is a diagram illustrating the connection structure of the pixel driving line, wiring section, and auxiliary line section according to another embodiment of the present invention.

[0047] Figure 19 It is along Figure 18 The cross-sectional view shown is taken from line IV-IV'.

[0048] Figure 20 It is along Figure 18 The cross-sectional view shown is taken from line V-V'.

[0049] Figure 21 It is along Figure 18 The cross-sectional view taken by line VI-VI' is shown.

[0050] Figure 22 It is along Figure 18 The cross-sectional view taken by line VII-VII' shown.

[0051] Figure 23 This is a diagram illustrating the connection structure of the pixel driving line, wiring section, and auxiliary line section according to another embodiment of the present invention.

[0052] Figure 24 This is a diagram illustrating the connection structure of the pixel driving line, wiring section, and auxiliary line section according to another embodiment of the present invention.

[0053] Figure 25 yes Figure 24 An enlarged view of region B6 shown.

[0054] Figure 26 It is along Figure 25 The cross-sectional view taken by line VIII-VIII' is shown.

[0055] Figure 27 This is an illustration of a light-emitting display device according to another embodiment of the present invention.

[0056] Figure 28 It is along Figure 27 The cross-sectional view shown is taken from line IX-IX'.

[0057] Figure 29 yes Figure 28 An enlarged view of region B7 shown.

[0058] Figure 30 This is an illustration of a light-emitting display device according to another embodiment of the present invention.

[0059] Figure 31 It is along Figure 30 The cross-sectional view shown is taken by line X-X'.

[0060] Figure 32 yes Figure 31 An enlarged view of region B8 shown.

[0061] Figure 33 This is an illustration of a multi-screen light-emitting display device according to an embodiment of the present invention.

[0062] Figure 34 It is along Figure 33 The cross-sectional view taken by line XI-XI' is shown. Detailed Implementation

[0063] Reference will now be made in detail to embodiments of the invention, some examples of which are illustrated in the accompanying drawings. In the following description, detailed descriptions of well-known functions or constructions relevant to this document will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the gist of the inventive concept. The described processing steps and / or the sequence of operations are exemplary; however, the order of steps and / or operations is not limited to those set forth herein, but may vary according to those known in the art, except for steps and / or operations that must occur in a particular order. Similar reference numerals refer to similar elements throughout. The names of the various elements used in the following description are chosen solely for ease of writing and may therefore differ from those used in actual products.

[0064] The advantages and features of the invention, as well as its implementation, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments listed herein. Rather, these embodiments are provided to make the disclosure of the invention comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art.

[0065] The shapes, sizes, proportions, angles, and quantities disclosed in the accompanying drawings for the purpose of describing embodiments of the invention are merely examples, and therefore the invention is not limited to the details illustrated. The same reference numerals refer to the same elements throughout. In the following description, detailed descriptions of related known functions or constructions will be omitted where it is determined that such detailed descriptions would unnecessarily obscure the focus of the invention. Where the terms "comprising," "having," and "including" are used in the description herein, additional parts may be added unless "only" is used.

[0066] When interpreting a factor, even if not explicitly stated, the factor should be interpreted as including a range of error.

[0067] When describing positional relationships, for example, when the positional relationship between two parts is described as “on top of,” “above,” “below,” and “after,” one or more additional parts may be placed between the two parts, unless more restrictive terms such as “exactly” or “directly” are used.

[0068] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous situations may be included unless more restrictive terms such as “exactly,” “immediately after,” or “directly” are used.

[0069] It will be understood that although the terms "first," "second," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are merely used to distinguish one element from another. For example, without departing from the scope of the invention, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0070] In describing the elements of the present invention, terms such as first, second, A, B, (a), (b), etc., may be used. These terms are used only to distinguish the corresponding element from other elements, and they do not limit the nature, order, or priority of the corresponding elements. It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, the element may be directly on or directly connected to the other element or layer, or there may be an intermediate element or layer. Furthermore, it should be understood that when an element is disposed above or below another element, it may indicate that the elements are disposed in direct contact with each other, but it may also indicate that the elements are disposed without direct contact with each other.

[0071] The term "at least one" should be understood to include any one and all combinations of one or more of the relevant listed elements. For example, "at least one of the first element, the second element, and the third element" means a combination of all elements selected from two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element.

[0072] As used herein, the term "around" includes at least partially surrounding one or more of the relevant elements and completely enclosing one or more of the relevant elements. Similarly, the term "cover" as used herein includes at least partially covering one or more of the relevant elements and completely covering one or more of the relevant elements. For example, if an encapsulation layer surrounds a weir pattern, this can be interpreted as the encapsulation layer at least partially surrounding the pattern. However, in some embodiments, the encapsulation layer may completely surround the weir pattern. The meaning of the term "around" as used herein may be further specified based on the relevant figures and embodiments. In this invention, the terms "around," "at least partially surrounding," "completely enclosing," etc., are used. According to the definition of "around" as set forth above, when the term "around" is used only in embodiments, it can refer to either at least partially surrounding one or more of the relevant elements or completely enclosing one or more of the relevant elements. The same applies to the term "cover."

[0073] Those skilled in the art will fully understand that the features of the various embodiments of the present invention can be combined or integrated with each other, either partially or entirely, and can be technically interoperable and driven in various ways. The embodiments of the present invention can be implemented independently of each other, or implemented together in an interdependent relationship.

[0074] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When adding reference numerals to elements in each drawing, similar reference numerals may refer to similar elements even if the same element is shown in other drawings. Furthermore, for ease of description, the scale of each element shown in the drawings differs from the actual scale; therefore, embodiments of the present invention are not limited to the scales shown in the drawings.

[0075] Figure 1 This is a plan view illustrating a light-emitting display device according to an embodiment of the present invention. Figure 2 This is a schematic side view illustrating a light-emitting display device according to an embodiment of the present invention.

[0076] Reference Figure 1 and Figure 2 According to an embodiment of the present invention, a light-emitting display device (or light-emitting display panel) 10 may include a substrate 100, the substrate 100 including a display area AA and a plurality of pixels P in the display area AA of the substrate 100.

[0077] The substrate 100 may be referred to as a first substrate, a base substrate, or a pixel array substrate. For example, the substrate 100 may comprise a glass material or a plastic material. The substrate 100 may be a glass substrate, or it may be a bendable or flexible thin glass substrate or plastic substrate.

[0078] The substrate 100 may include a first surface (adjacent to an edge) 100a, a second surface 100b, and an outer surface OS. The first surface 100a of the substrate 100 may be defined as a front surface, top surface, or upper surface facing the front surface direction (or forward direction) of the light-emitting display device. The second surface 100b of the substrate 100 may be defined as a back surface, rear surface, bottom surface, or lower surface facing the rear surface direction (or rearward direction) of the light-emitting display device. The outer surface OS of the substrate 100 may be defined as a side surface, side surface, or sidewall extending along the periphery between the first surface 100a and the second surface 100b, facing the lateral surface direction (or lateral direction) of the light-emitting display device, and exposed to the surrounding air.

[0079] The display area AA of the substrate 100 can be an area for displaying an image and can be referred to as an active portion, active region, display portion, or display section. The size of the display area AA can be the same as or substantially the same as that of the substrate 100 (or the light-emitting display device or the light-emitting display panel). For example, the size of the display area AA can be the same as the total size of the first surface 100a of the substrate 100. Therefore, the display area AA can be implemented (or disposed) on the entire front surface of the substrate 100, and thus the substrate 100 may not include an opaque non-display area disposed along the peripheral portion (or edge portion) of the first surface 100a to surround the entire display area AA, wherein the peripheral portion of the substrate 100 is adjacent to a plurality of outer surfaces of the substrate 100 and may be located inside the display area AA. Therefore, the entire front surface of the light-emitting display device can realize the display area AA.

[0080] The end (or outermost portion or lateral surface) AAa of the display area AA may overlap or be substantially aligned with the outer surface OS of the substrate 100. For example, the end AAa of the display area AA may be substantially coplanar with the outer surface OS of the substrate 100. For example, with respect to the thickness direction Z of the substrate 100, the end AAa of the display area AA and the vertical extension line VL extending perpendicularly from the outer surface OS of the substrate 100 may overlap each other or be substantially aligned on the same plane. That is, the end AAa of the display area AA may not be surrounded by a separate mechanism, but may only be adjacent to the surrounding air. For example, all lateral surfaces of the display area AA may be configured to be in direct contact with the air without being surrounded by a separate mechanism. Therefore, the outer surface OS of the substrate 100 corresponding to the end AAa of the display area AA may only be surrounded by air (or adjacent to the surrounding air), and thus, the light-emitting display device according to the present invention may have an air-frame structure or a frameless structure, wherein the end AAa (or the lateral surface of the display area AA) is surrounded by air rather than by an opaque non-display area.

[0081] Multiple pixels P can be arranged (or disposed) on the display area AA of the substrate 100 at a first interval D1. For example, multiple pixels P can be arranged (or disposed) on the display area AA of the substrate 100 along a first direction X and a second direction Y with a first interval D1. For example, the first direction X can intersect (or cross) the second direction Y. The first direction X can be the lateral direction, horizontal direction, or first length direction (e.g., lateral length direction) of the substrate 100 or the light-emitting display device. The second direction Y can be the longitudinal direction, vertical direction, or second length direction (e.g., longitudinal length direction) of the substrate 100 or the light-emitting display device.

[0082] Each of the plurality of pixels P can be implemented on a plurality of pixel regions defined on the display area AA of the substrate 100. Each of the plurality of pixels P can have a first length L1 parallel to a first direction X and a second length L2 parallel to a second direction Y. The first length L1 can be the same as the second length L2 or the first interval D1. The first length L1 and the second length L2 can be the same as the first interval D1. Therefore, the plurality of pixels (or pixel regions) P can all have the same size. For example, the first length L1 can be referred to as a first width, a lateral length, or a lateral width. The second length L2 can be referred to as a second width, a vertical length, or a vertical width.

[0083] Two adjacent pixels P along each of the first direction X and the second direction Y may have the same first interval D1 within the tolerance range of the manufacturing process. The first interval D1 may be the pitch (or pixel spacing) between two adjacent pixels P. For example, the first length L1 or the second length L2 of pixel P may be referred to as the pixel spacing. For example, the first interval (or pixel spacing) D1 may be the shortest distance (or shortest length) between the center portions of two adjacent pixels P.

[0084] Each of the plurality of pixels P may include: a circuit layer comprising pixel circuitry implemented in a pixel region on the substrate 100; and a light-emitting device layer disposed on the circuit layer and connected to the pixel circuitry. The pixel circuitry outputs a data current corresponding to a data signal in response to a data signal and a scan signal provided from a pixel driving line disposed in the pixel region. The light-emitting device layer may include a light-emitting layer that emits light using the data current provided from the pixel circuitry. The pixel driving line, the pixel circuitry, and the light-emitting device layer will be described below.

[0085] Multiple pixels P can be divided (or classified) into the outermost pixel Po and the innermost pixel (or internal pixel) Pi.

[0086] The outermost pixel Po can be the pixel closest to the outer surface OS of the substrate 100 among a plurality of pixels P. For example, the outermost pixel Po can be referred to as the first pixel P1.

[0087] The second interval D2 between the center portion of each outermost pixel Po and the outer surface OS of the substrate 100 can be half or less than half of the first interval D1. For example, the second interval D2 can be the outermost pixel region PAo (see...). Figure 4 The distance (or length) between the center portion of the outermost pixel region PAo and the outer surface OS of the substrate 100. For example, the second interval D2 can be the shortest distance (or shortest length) between the center portion of the outermost pixel region PAo and the outer surface OS of the substrate 100.

[0088] When the second interval D2 is greater than half of the first interval D1, the substrate 100 may have a size larger than the display area AA by the difference between half of the first interval D1 and the second interval D2. Therefore, the area between the end of the outermost pixel Po and the outer surface OS of the substrate 100 can constitute a non-display area surrounding the entire display area AA. For example, when the second interval D2 is greater than half of the first interval D1, the substrate 100 may necessarily include a border area based on the non-display area surrounding the entire display area AA. On the other hand, when the second interval D2 is half or less of the first interval D1, the end of each outermost pixel Po may be aligned with (or disposed on) the outer surface OS of the substrate 100, or the end AAa of the display area AA may be aligned with (or disposed on) the outer surface OS of the substrate 100. Thus, the display area AA can be implemented (or disposed) on the entire front surface of the substrate 100.

[0089] An inner pixel Pi can be a pixel other than the outermost pixel Po among a plurality of pixels P, or it can be a pixel surrounded by the outermost pixel Po among a plurality of pixels P. For example, an inner pixel Pi can be referred to as a second pixel P2. An inner pixel Pi (or a second pixel P2) can be implemented to have a different construction or structure than the outermost pixel Po (or a first pixel P1).

[0090] The light-emitting display device 10 according to an embodiment of the present invention may further include a discontinuity portion 115. The discontinuity portion 115 may also be referred to as a discontinuity wall 115.

[0091] The discontinuity 115 may be provided along the peripheral portion of the substrate 100. The discontinuity 115 may be implemented as a closed loop at the peripheral portion of the substrate 100. For example, Figure 9 A discontinuity 115 is shown continuously surrounding the outer periphery of the substrate 100 in a closed loop. The discontinuity 115 may be included in the outermost pixel Po, or may be disposed on the outer periphery of the outermost pixel Po. For example, the discontinuity 115 may be disposed between the center portion of the outermost pixel Po and the outer surface OS of the substrate 100, thus enabling it to have a different structure or configuration than the inner pixels Pi. The discontinuity 115 may be included in or disposed inside the outermost pixel Po, thus the light-emitting display device 10 according to an embodiment of the present invention may have a zero-bezel structure (or an air-bezel structure), whereby the entire front surface of the substrate 100 can be implemented as the display portion AA.

[0092] The discontinuity 115 can isolate the light-emitting layer formed at the peripheral portion of the substrate 100 at least once, thus blocking the penetration of moisture or humidity in the lateral direction of the substrate 100, thereby preventing degradation of the light-emitting layer or reduction in the reliability of the light-emitting layer due to the penetration of moisture or humidity. The discontinuity 115 according to embodiments of the present invention may include a plurality of discontinuities arranged in parallel. In some embodiments, the discontinuity 115 may also be referred to as a discontinuity wall. The discontinuity wall prevents any external impurities, such as moisture or humidity, from penetrating into the light-emitting layer. In one or more embodiments, a plurality of discontinuity walls are present to ensure that the light-emitting layer is protected from external impurities. In some cases, a dam or dam portion 117 having a different height than the discontinuity walls may be arranged inside the plurality of discontinuity walls. The dam may also serve as a barrier wall to prevent any penetration of external impurities. The dams may have different heights and may be of various numbers to protect the light-emitting layer. The dams may have a height higher than the discontinuity walls. The discontinuity 115 and the dam portion 117 will be described below.

[0093] The light-emitting display device 10 according to an embodiment of the present invention may further include a weir 117 and an encapsulation layer disposed on the light-emitting device layer and the weir 117.

[0094] The weir 117 may be provided along the peripheral portion of the substrate 100. The weir 117 may be implemented in a closed loop form at the peripheral portion of the substrate 100. The weir 117 may be included inside the outermost pixel Po, or may be provided at the peripheral portion of the outermost pixel Po. For example, the weir 117 may be provided between the central portion of the outermost pixel Po and the outer surface of the discontinuity 115. The weir 117 may be surrounded by the discontinuity 115. The outermost pixel Po may include the weir 117, and thus may be implemented with a different structure or configuration than the inner pixels Pi. The discontinuity 115 and the weir 117 may be included or provided inside the outermost pixel Po, so the light-emitting display device 10 according to the embodiment of the present invention may have a zero-bezel structure (or an air-bezel structure), whereby the entire front surface of the substrate 100 may be implemented as the display portion AA.

[0095] The encapsulation layer may be implemented around the light-emitting device layer and may be located on the discontinuity 115. According to embodiments of the present invention, the encapsulation layer may include a first inorganic encapsulation layer (or first encapsulation layer) disposed on the light-emitting device layer and the weir 117, a second inorganic encapsulation layer (or third encapsulation layer) disposed on the first inorganic encapsulation layer, and an organic encapsulation layer (or second encapsulation layer) disposed between the first and second encapsulation layers on the light-emitting device layer surrounded by the weir 117. The encapsulation layer will be described below.

[0096] The weir 117 may define or limit the arrangement area (or formation area) of the organic encapsulation layer covering the front surface (or top surface) of the light-emitting device layer. The weir 117 may block or prevent the overflow of the organic encapsulation layer.

[0097] The light-emitting display device 10 according to an embodiment of the present invention may further include a wiring section 400.

[0098] The wiring portion 400 can be implemented as a peripheral portion (also referred to as a first peripheral portion) surrounding or surrounding a peripheral portion of the substrate 100 and a surface of the substrate 100. The peripheral portion of the substrate may include a region adjacent to the outermost surface of the substrate. For example, a display device with a rectangular shape will have four peripheral portions because there will be four (or at least four) outermost surfaces in the substrate of the display device. The wiring portion 400 is located in Figure 1 One of the peripheral portions shown. In some embodiments, a side of the peripheral portion refers to one side of the peripheral portion. For example, one side of the peripheral portion may include the outer surface OS.

[0099] The wiring portion 400 may be included inside the outermost pixel Po located on one side of the peripheral portion of the substrate 100, or it may be disposed on the peripheral portion of the outermost pixel Po located on one side of the peripheral portion of the substrate 100. The outermost pixel Po located on one side of the peripheral portion of the substrate 100 may include the wiring portion 400, and therefore may be implemented to have a different structure or configuration than the inner pixel Pi. The wiring portion 400 may be referred to as a side wiring portion or a printed line portion.

[0100] The wiring portion 400 can pass through the circuit layer and the encapsulation layer located in the peripheral portion of the substrate 100 and can be electrically connected to multiple pixel driving lines. According to an embodiment of the present invention, the wiring portion 400 can sequentially pass through the encapsulation layer, the discontinuity portion 115, and the circuit layer, and can be electrically connected to multiple pixel driving lines. According to an embodiment of the present invention, the wiring portion 400 can sequentially pass through the encapsulation layer, the discontinuity portion 115, and the circuit layer, and can be electrically connected to multiple pixel driving lines; and it can also sequentially pass through the encapsulation layer, the weir portion 117, and the circuit layer, and can be electrically connected to multiple pixel driving lines. The wiring portion 400 will be described below.

[0101] The discontinuity portion 115, the weir portion 117, and the wiring portion 400 may be included or disposed within the outermost pixel Po. Therefore, the light-emitting display device 10 according to the embodiment of the present invention may have a zero-bezel structure (or an air bezel structure), thereby the entire front surface of the substrate 100 can be realized as the display portion AA.

[0102] Figure 3A It is a diagram Figure 1 The illustration shown is of a pixel according to an embodiment of the present invention. Figure 3B It is a diagram Figure 1 The diagram shown is an illustration of a pixel according to another embodiment of the present invention.

[0103] Reference Figure 1 and Figure 3A According to an embodiment of the present invention, a pixel (or a unit pixel) P may include first to fourth sub-pixels SP1 to SP4.

[0104] The first sub-pixel SP1 can be set in the first sub-pixel region of pixel region PA, the second sub-pixel SP2 can be set in the second sub-pixel region of pixel region PA, the third sub-pixel SP3 can be set in the third sub-pixel region of pixel region PA, and the fourth sub-pixel SP4 can be set in the fourth sub-pixel region of pixel region PA.

[0105] In an embodiment of the present invention, the first sub-pixel SP1 can be configured to emit light of a first color, the second sub-pixel SP2 can be configured to emit light of a second color, the third sub-pixel SP3 can be configured to emit light of a third color, and the fourth sub-pixel SP4 can be configured to emit light of a fourth color. Each of the first to fourth colors can be different. For example, the first color can be red, the second color can be blue, the third color can be white, and the fourth color can be green.

[0106] In another embodiment of the present invention, some of the colors in the first to fourth colors may be the same. For example, the first color may be red, the second color may be first green, the third color may be second green, and the fourth color may be blue.

[0107] The first to fourth sub-pixels SP1 to SP4 may each include multiple light-emitting areas EA1 to EA4 and multiple circuit areas CA1 to CA4.

[0108] The light-emitting areas EA1 to EA4 can be located at the center CP of pixel P, or they can be located near the center of pixel P. The first to fourth sub-pixels SP1 to SP4 can each be referred to as an opening area, an opening portion, a light-emitting portion, a light-generating area, or a light-generating portion.

[0109] According to the embodiment, the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 can be implemented to have the same size (or the same area). For example, the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 can have a uniform quad structure or a uniform stripe structure. For example, in the first to fourth sub-pixels SP1 to SP4 having a uniform quad structure (or a uniform stripe structure), each of the light-emitting regions EA1 to EA4 can be set close to the center portion of pixel P, thereby having a smaller size than each of the four equal regions of pixel P, or can be set to be concentrated on the center portion of pixel P.

[0110] Reference Figure 1 and Figure 3B According to another embodiment, each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform quaternary structure or a non-uniform stripe structure with different sizes. For example, each of the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 may have a non-uniform quaternary structure or a non-uniform stripe structure. For example, the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may be implemented to have different sizes around (or near) the central portion of pixel P.

[0111] The size of each of the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quaternary structure (or non-uniform stripe structure) can be set based on resolution, luminous efficiency, or image quality. When the light-emitting regions EA1 to EA4 have a non-uniform quaternary structure (or non-uniform stripe structure), among the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4, the light-emitting region EA4 of the fourth sub-pixel SP4 can have the smallest size, and the light-emitting region EA3 of the third sub-pixel SP3 can have the largest size. For example, each of the light-emitting regions EA1 to EA4 of each of the first to fourth sub-pixels SP1 to SP4 having a non-uniform quaternary structure (or non-uniform stripe structure) can be set to be concentrated around (or near) the central portion of pixel P.

[0112] The circuit regions CA1 to CA4 of each of the first to fourth sub-pixels SP1 to SP4 may be disposed around (or near) the corresponding light-emitting region in the light-emitting regions EA1 to EA4. Each of the circuit regions CA1 to CA4 may include circuitry and pixel driving lines for emitting light from the corresponding sub-pixel in the first to fourth sub-pixels SP1 to SP4. For example, the circuit regions CA1 to CA4 may be referred to as non-light-emitting regions, non-aperture regions, non-light-emitting portions, non-aperture portions, or peripheral portions.

[0113] Alternatively, in order to increase the aperture ratio of sub-pixels SP1 to SP4 corresponding to the dimensions of the light-emitting regions EA1 to EA4, or to reduce the pixel pitch D1 as the resolution of pixel P increases, the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may extend into the circuit regions CA1 to CA4 to overlap with some or all of the circuit regions CA1 to CA4. For example, each of the light-emitting regions EA1 to EA4 of the first to fourth sub-pixels SP1 to SP4 may be implemented on the substrate 100 to overlap with the corresponding circuit region in the circuit regions CA1 to CA4. In this case, each of the light-emitting regions EA1 to EA4 may have a size equal to or larger than the corresponding circuit regions CA1 to CA4.

[0114] Alternatively, each of the plurality of pixels P according to another embodiment of the present invention may include first to third sub-pixels SP1 to SP3.

[0115] The light-emitting areas EA1 to EA3 of the first to third sub-pixels SP1 to SP3 can each have a rectangular shape including a short side parallel to the first direction X and a long side parallel to the second direction Y, and can be configured, for example, in a 1×3 form or a 1×3 stripe form. For example, the first sub-pixel can be a red sub-pixel, the second sub-pixel can be a blue sub-pixel, and the third sub-pixel can be a green sub-pixel, but the embodiments of the present invention are not limited thereto.

[0116] Figure 4 yes Figure 1 An enlarged view of region B1 shown. Figure 5 yes Figure 1 and Figure 4 The equivalent circuit diagram of one pixel is shown.

[0117] Reference Figure 1 , Figure 4 and Figure 5 According to an embodiment of the present invention, the substrate 100 may include pixel driving lines DL, GL, PL, CVL, RL and GCL; a plurality of pixels P; a common electrode CE; a plurality of common electrode connection portions CECP; a contact pattern portion 110 and a discontinuity portion 115.

[0118] The pixel drive lines DL, GL, PL, CVL, RL, and GCL may include multiple data lines DL, multiple gate lines GL, multiple pixel drive power lines PL, multiple pixel common voltage lines CVL, multiple reference voltage lines RL, and multiple gate control lines GCL.

[0119] Each of the multiple data lines DL can extend along the second direction Y and can be arranged in the display area AA of the substrate 100 at predetermined (or selected) intervals separated from each other along the first direction X. For example, among the multiple data lines DL, odd-numbered data lines DLo can be arranged along the second direction Y at the first peripheral portion of each of the multiple pixel areas PA arranged on the substrate 100, and even-numbered data lines DLe can be arranged along the second direction Y at the second peripheral portion of each of the multiple pixel areas PA arranged on the substrate 100, but the embodiments of the present invention are not limited thereto.

[0120] Each of the plurality of gate lines GL can extend along a first direction X and can be disposed in the display area AA of the substrate 100 at predetermined (or selected) intervals separated from each other along a second direction Y. For example, among the plurality of gate lines GL, odd-numbered gate lines GLo can be disposed along the first direction X at the third peripheral portion of each of the plurality of pixel areas PA disposed on the substrate 100, and even-numbered gate lines GLe can be disposed along the first direction X at the fourth peripheral portion of each of the plurality of pixel areas PA disposed on the substrate 100, but the embodiments of the present invention are not limited thereto.

[0121] Each of the multiple pixel driving power lines PL can extend along the second direction Y and can be disposed in the display area AA of the substrate 100 at predetermined (or selected) intervals separated from each other along the first direction X. For example, among the multiple pixel driving power lines PL, the odd-numbered pixel driving power lines PL can be disposed at the first peripheral portion of the odd-numbered pixel area PA relative to the first direction X, and the even-numbered pixel driving power lines PL can be disposed at the second peripheral portion of the even-numbered pixel area PA relative to the first direction X, but the embodiments of the present invention are not limited thereto.

[0122] Two adjacent pixel driving power lines PL can be connected to multiple power sharing lines PSL disposed in each pixel region PA arranged along the second direction Y. For example, the multiple pixel driving power lines PL can be electrically connected to each other through multiple power sharing lines PSL, thus having a ladder structure or a mesh structure. The multiple pixel driving power lines PL can have a ladder structure or a mesh structure, thus preventing or minimizing the voltage drop (IR drop) of the pixel driving power supply caused by the line resistance of each of the multiple pixel driving power lines PL. Therefore, the light-emitting display device 10 according to the present invention can prevent or minimize the degradation of image quality caused by the deviation of the pixel driving power supply provided to each pixel P.

[0123] Each of the multiple power sharing lines PSL can branch from the adjacent pixel drive power line PL parallel to the first direction X and can be located in the middle region of each pixel region PA, but the embodiments of the present invention are not limited thereto.

[0124] Multiple pixel common voltage lines (CVLs) can extend along the second direction Y and can be disposed in the display area AA of the substrate 100 at predetermined (or selected) intervals separated from each other along the first direction X. For example, each of the multiple pixel common voltage lines (CVLs) can be disposed at the first peripheral portion of the even-numbered pixel area PA relative to the first direction X.

[0125] Multiple reference voltage lines RL can extend along a second direction Y and are arranged in the display area AA of the substrate 100 at predetermined (or selected) intervals separated from each other along a first direction X. Each of the multiple reference voltage lines RL can be arranged in the central region of each pixel area PA arranged along the second direction Y. For example, each of the multiple reference voltage lines RL can be arranged in each pixel area PA between odd data lines DLo and even data lines DLe.

[0126] Each of the multiple reference voltage lines RL can be shared by two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) along the first direction X in each pixel region PA. Therefore, in some embodiments, each of the multiple reference voltage lines RL may include a reference branch line RDL. The reference branch line RDL may branch (or protrude) in each pixel region PA toward two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)) along the first direction X and may be electrically connected to the two adjacent sub-pixels ((SP1, SP2)(SP3, SP4)).

[0127] Multiple gate control lines (GCLs) can extend along the second direction Y and are disposed in the display area AA of the substrate 100 at predetermined (or selected) intervals separated from each other along the first direction X. For example, the multiple gate control lines (GCLs) can be disposed in portions between multiple pixel areas PA relative to the first direction X or in the boundary region between two adjacent pixel areas PA.

[0128] Each of the plurality of pixels P may include at least three sub-pixels. For example, each of the plurality of pixels P may include first to fourth sub-pixels SP1 to SP4.

[0129] The first to fourth sub-pixels SP1 to SP4 may each include a pixel circuit PC and a light-emitting device layer.

[0130] According to an embodiment of the present invention, the pixel circuit PC can be disposed in the circuit region CA of the pixel region PA and can be connected to the adjacent gate line GLo or GLe, the adjacent data line DLo or GLe, and the pixel driving power line PL. For example, the pixel circuit PC disposed in the first sub-pixel SP1 can be connected to the odd-numbered data line DLo and the odd-numbered gate line GLo; the pixel circuit PC disposed in the second sub-pixel SP2 can be connected to the even-numbered data line GLe and the odd-numbered gate line GLo; the pixel circuit PC disposed in the third sub-pixel SP3 can be connected to the odd-numbered data line GLo and the even-numbered gate line GLe; and the pixel circuit PC disposed in the fourth sub-pixel SP4 can be connected to the even-numbered data line GLe and the even-numbered gate line GLe.

[0131] The pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can sample a data signal provided from the corresponding data line DLo or DLe in response to a scan signal provided from the corresponding gate line GLo or GLe, and can control the current flowing from the pixel drive power line PL to the light-emitting device layer based on the sampled data signal. For example, the pixel circuit PC can sample the data signal by using at least two thin-film transistors and at least one capacitor, and can control the current flowing into the light-emitting device layer based on the sampled data signal.

[0132] The pixel circuit PC according to an embodiment of the present invention may include a first switching thin-film transistor Tsw1, a second switching thin-film transistor Tsw2, a driving thin-film transistor Tdr, and a storage capacitor Cst. In the following description, the thin-film transistor may be referred to as a TFT.

[0133] The first switch TFT Tsw1 may include: a gate connected to adjacent gate lines GLo and GLe; a first electrode (source / drain) connected to adjacent data lines DLo and DLe; and a second electrode (drain / source) connected to a first node (or the gate node driving the TFT Tdr) n1. The first switch TFT Tsw1 can be turned on by a scan signal provided through the corresponding gate lines GLo and GLe and can transmit data signals provided through the corresponding data lines DLo and DLe to the first node n1 (e.g., the gate node n1 driving the TFT Tdr). According to an embodiment of the present invention, the gate of the first switch TFT Tsw1 in the pixel circuit PC of each of the first sub-pixel SP1 and the second sub-pixel SP2 may be connected to an odd-numbered gate line GLo, and the gate of the first switch TFT Tsw1 in the pixel circuit PC of each of the third sub-pixel SP3 and the fourth sub-pixel SP4 may be connected to an even-numbered gate line GLe. The first electrode (source / drain) of the first switch TFT Tsw1 in the pixel circuit PC of each of the first sub-pixel SP1 and the third sub-pixel SP3 can be connected to the odd-numbered data line DLo, and the first electrode (source / drain) of the first switch TFT Tsw1 in the pixel circuit PC of each of the second sub-pixel SP2 and the fourth sub-pixel SP4 can be connected to the even-numbered data line DLe.

[0134] The second switch TFT Tsw2 may include: a gate connected to adjacent gate lines GLo and GLe; a first electrode (source / drain) connected to an adjacent reference voltage line RL; and a second electrode (drain / source) connected to a second node (or the source node of the driving TFT Tdr) n2. The second switch TFT Tsw2 can be turned on by a scan signal provided through the corresponding gate lines GLo and GLe and can transmit a reference voltage provided through the corresponding reference branch line RDL and the reference voltage line RL to the source node n2 of the driving TFT Tdr. According to an embodiment of the present invention, the gate of the second switch TFT Tsw2 located in the pixel circuit PC of each of the first sub-pixel SP1 and the second sub-pixel SP2 may be connected to an odd number of gate lines GLo, and the gate of the second switch TFT Tsw2 located in the pixel circuit PC of each of the third sub-pixel SP3 and the fourth sub-pixel SP4 may be connected to an even number of gate lines GLe. The first electrode (source / drain) of the second switch TFT Tsw2 in the pixel circuit PC of each of the first sub-pixels SP1 to the fourth sub-pixels SP4 can be connected to the adjacent reference voltage line RL through the corresponding reference branch line RDL.

[0135] A storage capacitor Cst may be disposed in the overlapping region between the gate node n1 and the source node n2 of the driving TFT Tdr. The storage capacitor Cst may include a first capacitor electrode connected to the gate node of the driving TFT Tdr, a second capacitor electrode connected to the source node n2 of the driving TFT Tdr, and a dielectric layer formed in the overlapping region between the first and second capacitor electrodes. The storage capacitor Cst may be charged with the voltage difference between the gate node n1 and the source node n2 of the driving TFT Tdr, and the driving TFT Tdr may be turned on or off based on the charging voltage.

[0136] The driving TFT Tdr may include: a gate (or gate node n1) connected to the second electrode (drain / source) of the first switching TFT Tsw1 and the first capacitor electrode of the storage capacitor Cst; a source (or source node) connected to the second electrode (drain / source) of the second switching TFT Tsw2, the second capacitor electrode of the storage capacitor Cst, and the pixel electrode PE of the light-emitting device layer; and a drain (or drain node) connected to the adjacent pixel driving power line PL. The driving TFT Tdr can be turned on based on the voltage of the storage capacitor Cst and the amount of current flowing from the pixel driving power line PL to the light-emitting device layer can be controlled.

[0137] According to another embodiment, the pixel circuit PC of each of the first to fourth sub-pixels SP1 to SP4 can be implemented as a pixel driver chip using a semiconductor manufacturing process. It is disposed in the circuit region CA of the corresponding pixel region PA and connected to adjacent gate lines GLo and GLe, adjacent data lines DLo and DLe, and a pixel driver power line PL. For example, the pixel driver chip can be a minimum unit microchip or a chip assembly, and can be a semiconductor package device with a small size, including two or more transistors and one or more capacitors. Such a pixel driver chip can sample data signals provided from the corresponding data lines DLo and DLe in response to scan signals provided from the corresponding gate lines GLo and GLe, and can control the current flowing from the pixel driver power line PL to the light-emitting device layer based on the sampled data signals.

[0138] The light-emitting device layer can be disposed in the light-emitting region EA of the pixel region PA and electrically connected to the pixel circuit PC. According to an embodiment of the present invention, the light-emitting device layer may include a pixel electrode PE electrically connected to the pixel circuit PC, a common electrode CE electrically connected to the pixel common voltage line CVL, and a self-emissive device EL sandwiched between the pixel electrode PE and the common electrode CE.

[0139] According to another embodiment, the light-emitting layer EL may include at least one organic light-emitting layer. The light-emitting layer EL may further include a hole functional layer for providing holes to the organic light-emitting layer and an electron functional layer for providing electrons to the organic light-emitting layer. The light-emitting layer EL can emit light with a brightness corresponding to the data current based on the data current supplied from the pixel circuit PC.

[0140] A common electrode CE may be disposed in the display area AA of the substrate 100 and may be electrically connected to each of the plurality of pixels P. For example, the common electrode CE may be disposed in the display area AA of the substrate 100 other than the contact pattern portion 110 located in the substrate 100.

[0141] Each of the plurality of common electrode connection portions CECP can be disposed between a plurality of pixels P that overlap with a plurality of pixel common voltage lines CVL, and the common electrode CE can be electrically connected to each of the plurality of pixel common voltage lines CVL. Relative to the second direction Y, each of the plurality of common electrode connection portions CECP according to the embodiment of the present invention can be electrically connected to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL at a portion between the plurality of pixels P or at a boundary portion between the plurality of pixels P, and can be electrically connected to a portion of the common electrode CE, thus enabling the common electrode CE to be electrically connected to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL.

[0142] Each of the plurality of common electrode connection portions CECP can be disposed between at least two pixels among the plurality of pixels P, so as to electrically connect the common electrode CE to each of the plurality of pixel common voltage lines CVL, thereby preventing or minimizing the pixel common voltage drop (IR drop) caused by the surface resistance of the common electrode CE. Therefore, the light-emitting display device according to the embodiment of the present invention can prevent or minimize the image quality degradation caused by the deviation of the pixel common voltage provided to each pixel P arranged in the display area AA.

[0143] According to embodiments of the present invention, each of the plurality of common electrode connection portions (CECPs) may be formed together with a pixel electrode (PE) having at least a double-layer structure, thereby electrically connecting to each of the plurality of pixel common voltage lines (CVLs). Each of the plurality of common electrode connection portions (CECPs) may be connected to the common electrode (CE) via a side contact structure having a () shaped cross-section or a <) shaped cross-section. For example, when each of the plurality of common electrode connection portions (CECPs) is formed of a first metal layer and a second metal layer, each of the plurality of common electrode connection portions (CECPs) may include a side contact structure corresponding to an undercut structure or a conical structure formed on the lateral surface of the first metal layer due to the etching rate difference between the first metal layer and the second metal layer. For example, when each of the plurality of common electrode connection portions (CECPs) is formed of a first to a third metal layer, each of the plurality of common electrode connection portions (CECPs) may include a side contact structure corresponding to an undercut structure or a conical structure formed on the lateral surface of the first metal layer and the second metal layer due to the etching rate difference between the first metal layer and the third metal layer.

[0144] The contact pattern portion 110 may be disposed on a first peripheral portion (or one side peripheral portion) parallel to the first direction X in the first surface of the substrate 100. The contact pattern portion 110 may be adjacent to the outermost pixel and may be included (or disposed) inside the outermost pixel region PAo located in the first peripheral portion of the substrate 100, so that no non-display area (or border area) based on the contact pattern portion 110 is formed or exists in the substrate 100. For example, the contact pattern portion 110 may be disposed on a third peripheral portion of the outermost pixel region PAo located in the first peripheral portion of the substrate 100.

[0145] Contact pattern portion 110 may include multiple contact patterns PCP, DCP, RCP, GCP, and CCP, which are disposed on circuit layer 111 (see Figure 10 The contact pattern portion 110 may include a plurality of contact patterns PCP, DCP, RCP, GCP, and CCP disposed parallel to the circuit layer 111 along a first direction X on a first peripheral portion of the substrate 100. The contact pattern portion 110 according to an embodiment of the present invention may include five contact patterns: PCP, DCP, RCP, GCP, and CCP. The contact pattern portion 110 may include a plurality of data contact patterns DCP, a plurality of pixel drive power supply contact patterns PCP, a plurality of pixel common voltage contact patterns CCP, a plurality of reference voltage contact patterns RCP, and a plurality of gate contact patterns GCP, but is not limited thereto.

[0146] Data contact patterns (DCPs) can be used to receive data signals and can be the first contact pattern. According to an embodiment of the invention, each data contact pattern (DCP) can be disposed on the same layer as the data line (DL) and can extend (or be extended) from the end of each data line (DL) located at a peripheral portion on one side of the substrate 100 to the outer surface (OS) of the substrate 100, having a relatively wide width. According to another embodiment of the invention, each data contact pattern (DCP) can be disposed below the layer of the data line (DL) to have a relatively wide width, thereby overlapping with the end of each data line (DL) located at a peripheral portion on one side of the substrate 100, and each data contact pattern (DCP) can be electrically connected to the end of each data line (DL) through an internal contact hole.

[0147] The pixel driving power contact pattern PCP can be used to receive pixel driving power and can be a second contact pattern. According to an embodiment of the present invention, each pixel driving power contact pattern PCP can be disposed on the same layer as the pixel driving power line PL and can extend (or prolong) from the end of each pixel driving power line PL located at a peripheral portion on one side of the substrate 100 to the outer surface OS of the substrate 100, having a relatively wide width. According to another embodiment of the present invention, each pixel driving power contact pattern PCP can be disposed below the layer of the pixel driving power line PL, having a relatively wide width, thereby overlapping with the end of each pixel driving power line PL located at a peripheral portion on one side of the substrate 100, and each pixel driving power contact pattern PCP can be electrically connected to the end of each pixel driving power line PL through an internal contact hole.

[0148] A pixel common voltage contact pattern (CCP) can be used to receive a pixel common voltage and can be a third contact pattern. According to an embodiment of the invention, each pixel common voltage contact pattern (CCP) can be disposed on the same layer as the pixel common voltage line (CVL) and can extend (or prolong) from the end of each pixel common voltage line (CVL) located at a peripheral portion on one side of the substrate 100 to the outer surface OS of the substrate 100, having a relatively wide width. According to another embodiment of the invention, each pixel common voltage contact pattern (CCP) can be disposed below the layer of the pixel common voltage line (CVL) to have a relatively wide width, thereby overlapping with the end of each pixel common voltage line (CVL) located at a peripheral portion on one side of the substrate 100, and each pixel common voltage contact pattern (CCP) can be electrically connected to the end of each pixel common voltage line (CVL) through an internal contact hole.

[0149] A reference voltage contact pattern RCP can be used to receive a reference voltage and can be the fourth contact pattern. According to an embodiment of the invention, each reference voltage contact pattern RCP can be disposed on the same layer as the reference voltage line RL and can extend (or prolong) from the end of each reference voltage line RL located at a peripheral portion on one side of the substrate 100 to the outer surface OS of the substrate 100, having a relatively wide width. According to another embodiment of the invention, each reference voltage contact pattern RCP can be disposed below the layer of the reference voltage line RL, having a relatively wide width, thereby overlapping with the end of each reference voltage line RL located at a peripheral portion on one side of the substrate 100, and each reference voltage contact pattern RCP can be electrically connected to the end of each reference voltage line RL through an internal contact hole.

[0150] A gate contact pattern (GCP) can be used to receive a gate control signal and can be the fifth contact pattern. According to an embodiment of the invention, each gate contact pattern (GCP) can be disposed on the same layer as the gate control line (GCL) and can extend (or be extended) from the end of each gate control line (GCL) located at a peripheral portion on one side of the substrate 100 to the outer surface OS of the substrate 100, having a relatively wide width. According to another embodiment of the invention, each gate contact pattern (GCP) can be disposed below the layer of the gate control line (GCL) to have a relatively wide width, thereby overlapping with the end of each gate control line (GCL) located at a peripheral portion on one side of the substrate 100, and each gate contact pattern (GCP) can be electrically connected to the end of each gate control line (GCL) through an internal contact hole.

[0151] The contact pattern portion 110 according to an embodiment of the present invention may include a plurality of contact pattern groups (CPGs). At least two or more of the plurality of contact pattern groups (CPGs) may include at least one data contact pattern and at least one gate contact pattern.

[0152] According to an embodiment of the present invention, the contact pattern portion 110 may include a first contact pattern group CPG1 and a second contact pattern group CPG2.

[0153] The first contact pattern group CPG1 may be disposed in an odd-numbered outermost pixel Po among the outermost pixels Po disposed along the first direction X. For example, the first contact pattern group CPG1 may include a pixel driving power contact pattern PCP, two data contact patterns DCP, a reference voltage contact pattern RCP, and a gate contact pattern GCP. For example, the contact patterns PCP, DCP, RCP, and GCP included in the first contact pattern group CPG1 may be disposed (or arranged) (continuously) along the first direction X in the order of pixel driving power contact pattern PCP, data contact pattern DCP, reference voltage contact pattern RCP, data contact pattern DCP, and gate contact pattern GCP, but the embodiments of the present invention are not limited thereto.

[0154] The second contact pattern group CPG2 may be disposed in an even-numbered outermost pixel Po among the outermost pixels Po disposed along the first direction X. For example, the second contact pattern group CPG2 may include a pixel driving power contact pattern PCP, two data contact patterns DCP, a reference voltage contact pattern RCP, and a pixel common voltage contact pattern CCP. For example, the contact patterns PCP, DCP, RCP, and CCP included in the second contact pattern group CPG2 may be disposed (or arranged) (continuously) along the first direction X in the order of pixel driving power contact pattern PCP, data contact pattern DCP, reference voltage contact pattern RCP, data contact pattern DCP, and pixel common voltage contact pattern CCP, but the embodiments of the present invention are not limited thereto.

[0155] According to an embodiment of the present invention, the substrate 100 may further include multiple pixel common power auxiliary lines CSPL and multiple pixel common power auxiliary line connection portions SLCP.

[0156] Each of the plurality of pixel common power auxiliary lines CSPL can extend along the second direction Y and can be disposed adjacent to a corresponding pixel common voltage line CVL among the plurality of pixel common voltage lines CVL. Each of the plurality of pixel common power auxiliary lines CSPL can be electrically connected to the adjacent pixel common voltage line CVL but not electrically connected to the pixel common voltage contact pattern CCP, and can be provided with a pixel common voltage via the adjacent pixel common voltage line CVL. Therefore, in some embodiments, the substrate 100 according to the present invention may further include a plurality of line connection patterns LCP, which electrically connect adjacent pixel common voltage lines CVL and pixel common power auxiliary lines CSPL.

[0157] Each of the plurality of line connection patterns LCPs can be disposed on the substrate 100 such that the line connection pattern LCP overlaps with adjacent pixel common voltage lines (CVLs) and pixel common power auxiliary lines (CSPLs), and adjacent pixel common voltage lines (CVLs) and pixel common power auxiliary lines (CSPLs) can be connected by using a line jumping structure. For example, one side of each of the plurality of line connection patterns LCPs can be electrically connected to a portion of the pixel common power auxiliary line (CSPL) through a first line contact hole formed in an insulating layer on the pixel common power auxiliary line (CSPL), and the other side of each of the plurality of line connection patterns LCPs can be electrically connected to a portion of the pixel common voltage line (CVL) through a second line contact hole formed in an insulating layer on the pixel common voltage line (CVL).

[0158] Each of the multiple pixel common power supply auxiliary line connection portions SLCP can be disposed between multiple pixels P that overlap with multiple pixel common power supply auxiliary lines CSPL respectively, and can electrically connect the common electrode CE to each of the multiple pixel common power supply auxiliary lines CSPL. Relative to the second direction Y, each of the multiple pixel common power supply auxiliary line connection portions SLCP according to the embodiment of the present invention can be electrically connected to each of the multiple pixel common power supply auxiliary lines CSPL at a portion between multiple pixels P or at a boundary portion between multiple pixels P, and can be electrically connected to a portion of the common electrode CE, thereby electrically connecting the common electrode CE to each of the multiple pixel common power supply auxiliary lines CSPL. Therefore, the common electrode CE can be additionally connected to each of the multiple pixel common power supply auxiliary lines CSPL via the pixel common power supply auxiliary line connection portions SLCP. Therefore, the light-emitting display device according to the present invention can prevent or minimize image quality degradation caused by deviation of the pixel common power supply provided to each pixel P arranged in the display area AA. Furthermore, in the light-emitting display device according to the present invention, although a pixel common voltage contact pattern CCP is not additionally provided (or formed) to each of the plurality of pixel common power auxiliary lines CSPL, the pixel common voltage can be provided to each of the plurality of pixel common power auxiliary lines CSPL via the pixel common voltage line CVL and each of the plurality of line connection patterns LCP. For example, each of the plurality of pixel common power auxiliary line connection portions SLCP can electrically connect the corresponding pixel common power auxiliary line CSPL among the plurality of pixel common power auxiliary lines CSPL to the common electrode CE via a side contact structure having a "(" shaped cross-section structure or a "<" shaped cross-section structure (similar to each of the plurality of common electrode connection portions CECP).

[0159] The discontinuity 115 may be provided in a second region surrounding the first region of the substrate 100. For example, the second region of the substrate 100 may be a peripheral portion of the substrate 100 or a peripheral portion of each outermost pixel Po. The first region of the substrate 100 may be a region other than the second region. The discontinuity 115 may be implemented in a closed-loop form at the peripheral portion of the substrate 100. According to an embodiment of the present invention, the discontinuity 115 may be provided on the contact pattern portion 110. For example, the discontinuity 115 may be configured to intersect the contact patterns PCP, DCP, RCP, GCP, and CCP of the contact pattern portion 110 along the first direction X.

[0160] The discontinuity 115 can be implemented to disconnect (or isolate) the light-emitting layer EL inside the outermost pixel Po, which is disposed along the peripheral portion of the substrate 100, at least once. The discontinuity 115 can disconnect (or isolate) the light-emitting layer EL located at the peripheral portion of the substrate 100 at least once, and can block the side transmission of moisture or humidity penetrating in the lateral direction of the substrate 100, thereby preventing degradation of the light-emitting layer or reduction in the reliability of the light-emitting layer due to the side transmission of moisture or humidity. According to an embodiment of the present invention, the discontinuity 115 may include a plurality of discontinuous pattern portions arranged in parallel. For example, the discontinuity 115 may include at least three discontinuous pattern portions arranged in parallel.

[0161] The substrate 100 according to an embodiment of the present invention may further include a weir portion 117.

[0162] The weir 117 may be provided along the peripheral portion of the substrate 100. The weir 117 may be implemented in the peripheral portion of the substrate 100 with a closed-loop shape (or closed-loop line shape). The weir 117 may be included in the outermost pixel Po or provided at the peripheral portion of the outermost pixel Po. For example, the weir 117 may be provided between the center portion of the outermost pixel Po and the outer surface OS of the substrate 100. The weir 117 may be surrounded by discontinuities 115. For example, the weir 117 may be implemented as surrounding the isolation pattern portion closest to the innermost pixel Pi among a plurality of isolation pattern portions. According to an embodiment of the present invention, the weir 117 may be provided on the contact pattern portion 110. For example, the weir 117 may be configured to intersect (or intersect) the contact patterns PCP, DCP, RCP, GCP, and CCP of the contact pattern portion 110 along the first direction X.

[0163] Figure 6 It is a diagram Figure 4 A diagram showing the gate drive circuit implemented in the display area shown.

[0164] According to an embodiment of the present invention, the substrate 100 may further include a gate driving circuit 150 disposed in the display area AA of the substrate 100.

[0165] The gate drive circuit 150 can be implemented (or built into) within the display area AA of the substrate 100, generating a scan signal based on the gate control signal provided by the contact pattern portion 110 and the gate control line GCL, and sequentially providing the scan signal to multiple gate lines GL.

[0166] According to embodiments of the present invention, the gate control line GCL may include a start signal line, multiple shift clock lines, at least one gate drive voltage line, and at least one gate common voltage line. The gate control line GCL may extend along a second direction Y and may be disposed in the display area AA of the substrate 100 at predetermined (or selected) intervals separated from each other along a first direction X. For example, the gate control line GCL may be disposed between at least one or more pixels P along the first direction X.

[0167] According to an embodiment of the present invention, the gate drive circuit 150 can be implemented as a shift register, which includes multiple stages of circuitry 1501 to 150m, where m is an integer of 2 or greater.

[0168] Each of the plurality of stage circuit portions 1501 to 150m is disposed in each horizontal row of the first surface 100a of the substrate 100, spaced apart from each other along a first direction X, and is associatedly connected to each other along a second direction Y. Each of the plurality of stage circuit portions 1501 to 150m can generate a scan signal in a predetermined (or selected) sequence in response to a gate control signal provided by the contact pattern portion 110 and the gate control line GCL, and can provide the scan signal to the corresponding gate line GL.

[0169] Each of the multiple stage circuit sections 1501 to 150m according to the embodiment may include multiple branch circuits 1511 to 151n and a branch network 153.

[0170] Multiple branch circuits 1511 to 151n can be selectively connected to corresponding gate control lines in the gate control line GCL via branch network 153 and can be electrically connected to each other via branch network 153. Each of the multiple branch circuits 1511 to 151n can generate a scan signal based on the gate control signal provided through the gate control line GCL and the voltage of the branch network 153, and can provide the scan signal to the corresponding gate line GL.

[0171] Each of the plurality of branch circuits 1511 to 151n may include at least one of a plurality of TFTs constituting one of the stage circuit portions 1501 to 150m. Any one of the plurality of branch circuits 1511 to 151n may include a pull-up TFT connected to a gate line GL. Another branch circuit of the plurality of branch circuits 1511 to 151n may include a pull-down TFT connected to a gate line GL.

[0172] Each of the plurality of branch circuits 1511 to 151n according to embodiments of the present invention may be disposed in a circuit region between two adjacent pixels P or in a circuit region between at least two adjacent pixels P in each horizontal row of the substrate 100, but embodiments of the present invention are not limited thereto. For example, depending on the number of TFTs in each of the constituent stage circuit portions 1501 to 150m and the number of pixels P disposed in a horizontal row, each of the plurality of branch circuits 1511 to 151n may be disposed in a circuit region (or boundary region) between one or more adjacent pixels P.

[0173] Branch network 153 may be disposed in each horizontal row of substrate 100 and may electrically connect multiple branch circuits 1511 to 151n to each other. Branch network 153 according to an embodiment of the present invention may include multiple control nodes and multiple network lines.

[0174] Multiple control nodes may be disposed in each horizontal row of the substrate 100 and selectively connected to multiple branch circuits 1511 to 151n in a horizontal row. For example, multiple control nodes may be disposed in the upper edge region (or lower edge region) of the pixel region arranged in each horizontal row of the substrate 100.

[0175] Multiple network lines can be selectively connected to a gate control line GCL disposed in the substrate 100 and can be selectively connected to multiple branch circuits 1511 to 151n. For example, the multiple network lines can transmit gate control signals provided from the gate control line GCL to the corresponding branch circuits 1511 to 151n and can transmit signals between multiple branch circuits 1511 to 151n.

[0176] Each of the plurality of stage circuit portions 1501 to 150m according to embodiments of the present invention may include a first control node, a second control node, a node control circuit, an inverter circuit, and an output buffer circuit. The node control circuit may be configured to control the voltage of each of the first and second control nodes. The inverter circuit may be configured to control the voltage of the second control node based on the voltage of the first control node. The output buffer circuit may be configured to output a scan signal corresponding to a scan clock and a carry signal corresponding to a carry clock based on the voltage of the first control node, and to output a carry signal and a scan signal corresponding to a gate-off voltage level based on the voltage of the second control node. For example, the node control circuit, the inverter circuit, and the output buffer circuit may each include two or more of a plurality of branch circuits 1511 to 151n. For example, the plurality of branch circuits 1511 to 151n may be respectively divided (or classified) into a node control circuit, an inverter circuit, and an output buffer circuit.

[0177] As described above, according to an embodiment of the present invention, since the gate driving circuit 150 is disposed within the display area AA of the substrate 100, the second interval D2 between the center portion of the outermost pixel area PAo and the outer surface OS of the substrate 100 can be equal to or less than half of the first interval (or pixel pitch) D1 between adjacent pixel areas PA. For example, when the gate driving circuit 150 is not disposed within the display area AA of the substrate 100 but at the peripheral portion of the substrate 100, the second interval D2 will not be equal to or less than half of the first interval D1. Therefore, in the light-emitting display device according to an embodiment of the present invention, since the gate driving circuit 150 can be disposed within the display area AA of the substrate 100, the second interval D2 can be implemented to be equal to or less than half of the first interval D1.

[0178] Figure 7 This is a rear perspective view illustrating a light-emitting display device according to an embodiment of the present invention.

[0179] Reference Figure 1 , Figure 4 and Figure 7 According to an embodiment of the present invention, the light-emitting display device may further include a first pad portion 210 located in the rear surface 100b of the substrate 100.

[0180] The first pad portion 210 may be disposed in the first peripheral portion (or first rear peripheral portion) of the rear surface 100b of the substrate 100, which overlaps with the contact pattern portion 110 disposed on the front surface 100a of the substrate 100.

[0181] The first pad portion 210 may include a plurality of first pads (or wiring pads) arranged at defined intervals along a first direction X, thereby overlapping with the contact pattern of the contact pattern portion 110 respectively.

[0182] According to an embodiment of the present invention, the first pad portion 210 may include a plurality of first pixel driving power pads overlapping with each of a plurality of pixel driving power contact patterns PCP, a plurality of first data pads overlapping with each of a plurality of data contact patterns DCP, a plurality of first reference voltage contact pads overlapping with each of a plurality of reference voltage contact patterns RCP, a plurality of first gate pads overlapping with each of a plurality of gate contact patterns GCP, and a plurality of first pixel common voltage pads overlapping with each of a plurality of pixel common voltage contact patterns CCP.

[0183] The light-emitting display device according to an embodiment of the present invention may further include a second pad portion 230 and a link line portion 250 disposed in the rear surface 100b of the substrate 100.

[0184] The second pad portion (or input pad portion) 230 may be disposed in the rear surface 100b of the substrate 100. For example, the second pad portion 230 may be disposed in the middle portion of the rear surface 100b of the substrate 100 adjacent to the first peripheral portion. According to an embodiment of the present invention, the second pad portion 230 may include a plurality of second pads (or input pads) spaced apart from each other at a defined interval. For example, the second pad portion 230 may include a second pixel drive power pad, a second data pad, a second reference voltage pad, a second gate pad, and a second pixel common voltage pad.

[0185] The wiring portion 250 may include multiple wirings disposed between the first pad portion 210 and the second pad portion 230.

[0186] The interconnection section 250 according to an embodiment of the present invention may include: multiple pixel driving power lines that individually (or separately or in a one-to-one correspondence) connect multiple first pixel driving power pads to multiple second pixel driving power pads; multiple data lines that individually (or separately or in a one-to-one correspondence) connect multiple first data pads to multiple second data pads; multiple reference voltage lines that individually (or separately or in a one-to-one correspondence) connect multiple first reference voltage pads to multiple second reference voltage pads; multiple gate lines that individually (or separately or in a one-to-one correspondence) connect multiple first gate pads to multiple second gate pads; and multiple pixel common voltage lines that individually (or separately or in a one-to-one correspondence) connect multiple first pixel common voltage pads to multiple second pixel common voltage pads.

[0187] Each of the multiple pixel common voltage interconnects may include a first common interconnect 251 and a second common interconnect 253. The first common interconnect 251 may be disposed between the first pad portion 210 and the second pad portion 230 and commonly connected to multiple first pixel common voltage pads. The second common interconnect 253 may be commonly connected to multiple second pixel common voltage pads and electrically connected to the first common interconnect 251. The second common interconnect 253 may be disposed on a different layer than the first common interconnect 251 and electrically connected to the first common interconnect 251 via a via hole. The size of the second common interconnect 253 may gradually increase in the direction from the second pad portion 230 to the periphery of the substrate 100 in order to reduce (or minimize) the voltage drop of the pixel common voltage.

[0188] The wiring portion 400 may be configured to surround the contact pattern portion 110, the outer surface OS, and the first pad portion 210 of the substrate 100. According to an embodiment of the present invention, the wiring portion 400 may include a plurality of wirings 410 extending to the peripheral portion of the substrate 100 and at least partially covering the outermost surface of the substrate 100. At least one wiring 410 may be located on and in contact with the outer surface of the substrate 100. Each of the plurality of wirings 410 may be arranged at defined intervals along a first direction X to surround the contact pattern portion 110, the outer surface OS, and the first pad portion 210 of the substrate 100, and may be electrically connected to the contact pattern portion 110 and the first pad portion 210 in a one-to-one correspondence. According to an embodiment of the present invention, each of the plurality of wirings 410 may be formed by a printing process using conductive adhesive. According to another embodiment, each of the plurality of wirings 410 may be formed by a transfer process in which a conductive adhesive pattern is transferred to a transfer pad made of a flexible material and the conductive adhesive pattern transferred to the transfer pad is transferred to the wiring portion 400. For example, the conductive adhesive can be Ag adhesive, but the embodiments of the present invention are not limited thereto.

[0189] Each of the multiple wirings 410 can be electrically connected to the contact patterns PCP, DCP, RCP, GCP, and CCP of the contact pattern portion 110 via an encapsulation layer disposed in the peripheral portion of the substrate 100. In addition, each of the multiple wirings 410 can be electrically connected to a pad located in the first pad portion 210.

[0190] According to embodiments of the present invention, the multiple wirings 410 can be divided (or classified) into multiple pixel power supply wirings 411, multiple data wirings 413, multiple reference voltage wirings 415, multiple gate wirings 417, and multiple pixel common voltage wirings 419.

[0191] Multiple pixel power lines 411 can be formed around the contact pattern portion 110, the outer surface OS and the first pad portion 210 of the substrate 100, and can be electrically connected to multiple pixel driving power contact patterns PCP of the contact pattern portion 110 and multiple first pixel driving power pads of the first pad portion 210 in a one-to-one correspondence relationship.

[0192] Multiple data lines 413 can be formed around the contact pattern portion 110, the outer surface OS and the first pad portion 210 of the substrate 100, and can be electrically connected to multiple data contact patterns DCP of the contact pattern portion 110 and multiple first data pads of the first pad portion 210 in a one-to-one correspondence relationship.

[0193] Multiple reference voltage wirings 415 can be formed around the contact pattern portion 110, the outer surface OS, and the first pad portion 210 of the substrate, and can be electrically connected to multiple reference voltage contact patterns RCP of the contact pattern portion 110 and multiple first reference voltage pads of the first pad portion 210 in a one-to-one correspondence relationship.

[0194] Multiple gate wirings 417 can be formed around the contact pattern portion 110, the outer surface OS and the first pad portion 210 of the substrate 100, and can be electrically connected to multiple gate contact patterns GCP of the contact pattern portion 110 and multiple first gate pads of the first pad portion 210 in a one-to-one correspondence relationship.

[0195] Multiple pixel common voltage wirings 419 can be formed around the contact pattern portion 110, the outer surface OS and the first pad portion 210 of the substrate, and can be electrically connected to multiple pixel common voltage contact patterns CCP of the contact pattern portion 110 and multiple first pixel common voltage pads of the first pad portion 210 in a one-to-one correspondence relationship.

[0196] The light-emitting display device according to an embodiment of the present invention may further include a driving circuit unit 500 (or driving circuit 500).

[0197] The driving circuit unit 500 can drive (or illuminate) the pixels P disposed on the substrate 100 based on digital video data and timing synchronization signals provided from the display driving system, so that the display area AA displays an image corresponding to the image data. The driving circuit unit 500 can be connected to a second pad portion 230 disposed on the rear surface 100b of the substrate 100 and can output data signals, gate control signals, and driving power to the second pad portion 230 for driving (or illuminating) the pixels P disposed on the substrate 100.

[0198] The driving circuit unit 500 according to an embodiment of the present invention may include a flexible circuit film 510, a driving integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply circuit unit 590.

[0199] The flexible circuit film 510 can be connected to the second pad portion 230 disposed on the rear surface 100b of the substrate 100.

[0200] The driver IC 530 can be mounted on the flexible circuit film 510. The driver IC 530 can receive sub-pixel data and data control signals provided from the timing controller 570, and convert the sub-pixel data into analog data signals based on the data control signals, so as to provide the analog data signals to the corresponding data lines DL. The data signals can be provided to the corresponding third data pads located at the second pad portion 230 through the flexible circuit film 510.

[0201] The driver IC 530 can sense the feature values ​​of the driving TFTs disposed in the sub-pixel SP through multiple reference voltage lines RL disposed on the substrate 100, generate raw sensing data corresponding to the sensed values ​​for each sub-pixel, and provide the raw sensing data of each sub-pixel to the timing controller 570. For example, the light-emitting display device according to an embodiment of the present invention can sense the feature values ​​of the driving TFTs disposed in the sub-pixel SP through the sensing modes disclosed in Korean Patent Application Publications No. 10-2016-0093179, 10-2017-0054654, or 10-2018-0002099, but the embodiments of the present invention are not limited thereto.

[0202] PCB 550 can be connected to the other peripheral portion of flexible circuit film 510. PCB 550 can transmit signals and power between the components of drive circuit unit 500.

[0203] The timing controller 570 can be mounted on PCB 550 and can receive digital video data and timing synchronization signals from the display driver system via a user connector located on PCB 550. Alternatively, the timing controller 570 may not be mounted on PCB 550, but may be implemented in the display driver system or mounted on a separate control board connected between PCB 550 and the display driver system.

[0204] The timing controller 570 can arrange digital video data based on timing synchronization signals to generate pixel data that matches the pixel arrangement structure set in the display area AA and can provide the generated pixel data to the driver IC 530.

[0205] The timing controller 570 can generate each of a data control signal and a gate control signal based on the timing synchronization signal, control the driving timing of the driver IC 530 based on the data control signal, and control the driving timing of the gate drive circuit 150 based on the gate control signal.

[0206] The data control signal according to an embodiment of the present invention may include a source start pulse, a source shift clock, and a source output signal. The gate control signal according to an embodiment of the present invention may include a start signal (or a gate start pulse), multiple shift clocks, a forward driving signal, and a reverse driving signal. The gate control signal may be provided to a corresponding third gate pad located at the second pad portion 230 via a flexible circuit film 510.

[0207] Power supply circuit unit 590 can be mounted on PCB 550 and can generate various source voltages required for displaying an image on pixel P using an externally supplied input power supply, thereby providing the generated source voltages to the corresponding circuits. For example, power supply circuit unit 590 can generate and output the required logic source voltages for driving each of timing controller 570 and driver IC 530, multiple reference gamma voltages provided to driver IC 530, and at least one gate drive power supply (or voltage) and at least one gate common power supply (or voltage) for driving gate drive circuit 150. Furthermore, power supply circuit unit 590 can generate and output pixel drive power supplies and pixel common voltages, but embodiments of the invention are not limited thereto. For example, driver IC 530 can generate and output pixel drive power supplies and pixel common voltages based on multiple reference gamma voltages.

[0208] Figure 8 This is a rear perspective view illustrating a light-emitting display device according to another embodiment of the present invention, showing a wiring substrate additionally disposed thereon. Figure 1 and 7 An embodiment of the light-emitting display device is shown in the figure.

[0209] Reference Figure 8 According to another embodiment of the present invention, the light-emitting display device may include a first substrate 100, a second substrate 200, a bonding member 300, and a wiring portion 400.

[0210] The first substrate 100 may be referred to as a display substrate, pixel array substrate, upper substrate, front substrate, or base substrate. The substrate 100 may be a glass substrate, or a bendable or flexible thin glass substrate or plastic substrate. A plurality of pixels on the first substrate 100 may define a display area AA extending to the edge of the first substrate 100.

[0211] The first substrate 100 can be coupled with Figures 1 to 7The substrates 100 of the light-emitting display devices shown are substantially the same, therefore similar reference numerals refer to similar elements and their repeated descriptions can be omitted.

[0212] The second substrate 200 may be referred to as a wiring substrate, line substrate, link substrate, lower substrate, rear substrate, or link glass. The second substrate 200 may be a glass substrate, or a flexible or bendable thin glass substrate or plastic substrate. For example, the second substrate 200 may comprise the same material as the first substrate 100. The dimensions of the second substrate 200 may be the same as or substantially the same as the dimensions of the first substrate 100, but embodiments of the present invention are not limited thereto; the dimensions of the second substrate 200 may be smaller than the dimensions of the first substrate 100. For example, the second substrate 200 may be configured to have the same dimensions as the first substrate 100 in order to maintain or ensure the rigidity of the first substrate 100.

[0213] The second substrate 200 may include a first pad portion 210, a second pad portion 230, and an interconnect portion 250. Except that the first pad portion 210, the second pad portion 230, and the interconnect portion 250 are disposed on the rear surface 200b of the second substrate 200, each of the first pad portion 210, the second pad portion 230, and the interconnect portion 250 may be connected to… Figure 7 Each of the first pad portion 210, the second pad portion 230, and the interconnect portion 250 shown is substantially the same, so similar reference numerals refer to similar components and their repeated descriptions can be omitted.

[0214] The second substrate 200 can be joined (or connected) to the second surface 100b of the first substrate 100 using a joining member 300. The joining member 300 can be inserted between the first substrate 100 and the second substrate 200. Thus, the first substrate 100 and the second substrate 200 can be joined to each other relative to each other by the joining member 300.

[0215] The wiring portion 400 may be referred to as a side wiring portion, side wiring portion, printed wiring portion, or printed line portion. The wiring portion 400 may be configured to surround the outer surface OS of the first substrate 100 and the outer surface OS of the second substrate 200. According to an embodiment of the present invention, the wiring portion 400 may include multiple wirings disposed at each of a first outer surface (or a surface) OS1a of the outer surface OS of the first substrate 100 and a first outer surface (or a surface) OS1b of the outer surface OS of the second substrate 200. Each of the multiple wirings may be formed to surround each of the first outer surface OS1a of the first substrate 100 and the first outer surface OS1b of the second substrate 200. In addition to the multiple wirings 410 being configured to surround the first outer surface OS1a and contact pattern portion 110 of the first substrate 100 and the first outer surface OS1b and first pad portion 210 of the second substrate 200, the wiring portion 400 may be connected to... Figure 7 The wiring section 400 shown is basically the same, so similar reference numerals refer to similar components and their repeated descriptions can be omitted.

[0216] According to another embodiment of the present invention, the display device may further include a driving circuit unit 500.

[0217] The drive circuit unit 500 may include a flexible circuit film 510, a driver integrated circuit (IC) 530, a printed circuit board (PCB) 550, a timing controller 570, and a power supply circuit unit 590. Except that the flexible circuit film 510 is connected to the second pad portion 230 located on the rear surface of the second substrate 200, the drive circuit unit 500 with this configuration can be connected to… Figure 7 The drive circuit unit 500 shown is essentially the same, so similar reference numerals refer to similar elements and their repeated descriptions can be omitted.

[0218] Figure 9 This is a diagram illustrating the connection structure of the pixel driving line and the wiring section according to an embodiment of the present invention. Figure 10 It is along Figure 9 The cross-sectional view shown is taken by line I-I'. Figure 11 yes Figure 10 An enlarged view of region B2 shown. Figure 12 yes Figure 10 An enlarged view of region B3 is shown. Region B3 includes the peripheral portion of the substrate that is also adjacent to the outer surface (or outermost surface) of the substrate. Figure 10 The peripheral portion is shown to be adjacent to the first outer surface OS1a of the first substrate 100. In the description... Figures 9 to 12 At that time, and Figures 1 to 8 Elements that are identical or corresponding to each other are referred to by similar reference numerals, and their repeated descriptions are omitted or will be given.

[0219] Reference Figure 4 and Figures 9 to 11 The light-emitting display device according to an embodiment of the present invention may include a first substrate 100.

[0220] The first substrate 100 may include a display area AA having a first region and a second region surrounding the first region. The second region of the first substrate 100 may be a peripheral portion (or edge portion) of the first substrate 100 or a peripheral portion (or edge portion) of the outermost pixel. The first region of the first substrate 100 may be a portion other than the second region of the first substrate 100.

[0221] According to an embodiment of the present invention, the first substrate 100 may include a circuit layer 111, a planarization layer 112, a light-emitting device layer 113, a dam 114, a discontinuity 115, a weir 117, and an encapsulation layer 119.

[0222] The circuit layer 111 may be disposed on the first surface 100a of the first substrate 100. The circuit layer 111 may be referred to as a pixel array layer or a TFT array layer.

[0223] According to an embodiment of the present invention, the circuit layer 111 may include a buffer layer 111a and a circuit array layer 111b.

[0224] The buffer layer 111a prevents materials such as hydrogen included in the first substrate 100 from diffusing into the circuit array layer 111b during the high-temperature process of manufacturing TFTs. Furthermore, the buffer layer 111a prevents external moisture or humidity from penetrating into the light-emitting device layer 113. According to an embodiment of the present invention, the buffer layer 111a may include a first buffer layer BL1 having silicon nitride (SiNx) and disposed on the first substrate 100, and a second buffer layer BL2 having silicon oxide (SiOx) and disposed on the first buffer layer BL1. The buffer layer 111a may be covered by at least one insulating layer.

[0225] The circuit array layer 111b may include a pixel circuit PC, which includes a driving TFTTdr disposed in each of a plurality of pixel regions PA located on the buffer layer 111a.

[0226] The driving TFT Tdr disposed in each pixel region PA may include an active layer ACT, a gate insulating layer GI, a gate GE, an interlayer insulating layer 111c, a first electrode (source / drain) SD1, a second electrode (drain / source) SD2, and a passivation layer 111d.

[0227] An active layer ACT can be disposed on a buffer layer 111a in each pixel region PA. The active layer ACT may include a channel region overlapping with the gate GE, and a first electrode (source / drain) region and a second electrode (drain / source) region that are parallel to each other and sandwiched between the channel regions. The active layer ACT may be conductive in the conductivity process, and thus can be used as a bridge line for jumper structures that directly connect lines in the display region AA or electrically connect lines disposed on different layers.

[0228] The gate insulating layer GI can be disposed in the channel region of the active layer ACT. The gate insulating layer GI can isolate the active layer ACT from the gate GE.

[0229] The gate GE may be disposed on the gate insulating layer GI and connected to the gate line. The gate GE may overlap with the channel region of the active layer ACT, with the gate insulating layer GI between them.

[0230] An interlayer insulating layer 111c may be disposed on the first substrate 100 to cover the gate GE and the active layer ACT. The interlayer insulating layer 111c can electrically insulate (or isolate) the gate GE from the source / drain SD1 and SD2. For example, the interlayer insulating layer 111c may be referred to as an insulating layer or a first insulating layer, but embodiments of the present invention are not limited thereto.

[0231] The first electrode (source / drain) SD1 can be disposed on the interlayer insulating layer 111c overlapping the first electrode (source / drain) region of the active layer ACT, and can be electrically connected to the first electrode (source / drain) region of the active layer ACT through a first source / drain contact hole disposed in the interlayer insulating layer 111c. For example, the first electrode (source / drain) SD1 can be the source of the TFT Tdr, and the first electrode (source / drain) region of the active layer ACT can be the source region.

[0232] The second electrode (drain / source) SD2 can be disposed on the interlayer insulating layer 111c overlapping the second electrode (drain / source) region of the active layer ACT, and can be electrically connected to the second electrode (drain / source) region of the active layer ACT through a second source / drain contact hole disposed in the interlayer insulating layer 111c. For example, the second electrode (drain / source) SD2 can be the drain of the TFT Tdr, and the second electrode (drain / source) region of the active layer ACT can be the drain region.

[0233] The electrode materials of the source / drain electrodes SD1 and SD2 according to embodiments of the present invention can be used as signal lines extending along a first direction X on a first substrate 100. The source / drain electrodes SD1 and SD2 can be implemented together with the gate line GL.

[0234] A passivation layer 111d may be disposed on the first substrate 100 to cover the pixel circuit PC including the driving TFT Tdr. For example, when the interlayer insulating layer 111c is not disposed at the peripheral portion of the first substrate 100, the passivation layer 111d located at the peripheral portion of the first substrate 100 may directly contact the buffer layer 111a. The passivation layer 111d may be referred to as a protective layer or a second insulating layer, but embodiments of the present invention are not limited thereto.

[0235] Each of the first switch TFT Tsw1 and the second switch TFT Tsw2 constituting the pixel circuit PC can be formed together with the driving TFT Tdr, and therefore their repeated descriptions can be omitted or briefly given.

[0236] According to an embodiment of the present invention, the circuit layer 111 may further include a lower metal layer BML disposed between the first substrate 100 and the buffer layer 111a.

[0237] The lower metal layer BML may further include a light-shielding pattern (or light-shielding layer) LSP, which is disposed below (or beneath) the active layer ACT of each of the TFTs Tdr, Tsw1 and Tsw2 constituting the pixel circuit PC.

[0238] The light-shielding pattern LSP can be disposed in an island shape between the first substrate 100 and the active layer ACT. The light-shielding pattern LSP can block light incident on the active layer ACT through the first substrate 100, thereby preventing or minimizing threshold voltage variations of each TFT caused by external light. Optionally, the light-shielding pattern LSP can be electrically connected to the first electrode (source / drain) SD1 of the corresponding TFT, and thus can be used as the lower gate of the corresponding TFT. In this case, characteristic variations of each TFT caused by light and threshold voltage variations of each TFT caused by bias voltage can be minimized or prevented.

[0239] The lower metal layer BML can be used as a metal layer for implementing pixel driving lines PL, DL, RL, GCL, and CVL that are spaced apart from each other along a first direction X and extend along a second direction Y on the first substrate 100. Furthermore, the lower metal layer BML can be used as a metal layer for implementing multiple contact patterns PCP, DCP, RCP, GCP, and CCP of the contact pattern section 110.

[0240] According to an embodiment of the present invention, the lower metal layer BML can be deposited on the entire front surface 100a of the first substrate 100, and then can be patterned into light-shielding patterns LSP, pixel driving power lines PL, multiple data lines DL, pixel common voltage lines CVL, and contact patterns PCP, DCP, RCP, GCP and CCP using a patterning process.

[0241] A planarization layer 112 may be disposed on the first substrate 100 and may provide a planar surface on the circuit layer 111. The planarization layer 112 may cover the circuit layer 111 including the driving TFTs Tdr disposed in each of a plurality of pixel regions PA. The planarization layer 112 according to embodiments of the present invention may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but embodiments of the present invention are not limited thereto.

[0242] According to an embodiment of the present invention, the planarization layer 112 may be formed to cover the circuit layer 111 except for the peripheral portion of the first substrate 100. For example, the passivation layer 111d of the circuit layer 111 located at the peripheral portion of the first substrate 100 may be exposed and not covered by the planarization layer 112.

[0243] The light-emitting device layer 113 may be located on each of the plurality of pixels and on the edge of the first substrate 100, and may be disposed on the planarization layer 112. The light-emitting device layer 113 according to an embodiment of the present invention may include a pixel electrode PE, a light-emitting layer EL, and a common electrode CE.

[0244] The pixel electrode PE can be referred to as the anode, reflective electrode, lower electrode, or first electrode.

[0245] A pixel electrode PE can be disposed on a planarization layer 112 overlapping with the light-emitting region EA of each of the multiple pixel regions PA. The pixel electrode PE can be patterned and configured as an island in each pixel region PA, and can be electrically connected to the first electrode (source / drain) SD1 of the driving TFT Tdr of the corresponding pixel circuit PC. One side of the pixel electrode PE can be electrically connected to the first electrode (source / drain) SD1 of the driving TFT Tdr from the first electrode (source / drain) SD1 of the driving TFT Tdr, and through the electrode contact hole ECH located in the planarization layer 112.

[0246] The pixel electrode PE can be a metallic material with a low work function and excellent reflectivity.

[0247] According to an embodiment of the present invention, the pixel electrode PE may have a bilayer structure including a first pixel electrode layer (or a first metal layer) PEL1 and a second pixel electrode layer (or a second metal layer) PEL2. The first pixel electrode layer PEL1 and the second pixel electrode layer PEL2 may be sequentially deposited on the planarization layer 112 and then simultaneously patterned.

[0248] A first pixel electrode layer PEL1 may be disposed on a planarization layer 112. A second pixel electrode layer PEL2 may be disposed on (or stacked) on the first pixel electrode layer PEL1. For example, the first pixel electrode layer PEL1 may serve as an adhesive layer corresponding to the planarization layer 112 and may serve as an auxiliary electrode for the light-emitting layer EL; furthermore, the first pixel electrode layer PEL1 may include indium tin oxide (ITO) or indium zinc oxide (IZO), but embodiments of the present invention are not limited thereto. For example, the second pixel electrode layer PEL2 may serve as a reflector and may perform the function of reducing the resistance of the pixel electrode PE; furthermore, the second pixel electrode layer PEL2 may include one or more materials selected from aluminum (Al), silver (Ag), molybdenum (Mo), titanium (Ti), and Mo-Ti alloy (MoTi), but embodiments of the present invention are not limited thereto. For example, the pixel electrode PE according to an embodiment of the present invention may be formed as a bilayer structure of ITO / MoTi or IZO / MoTi.

[0249] According to another embodiment of the present invention, the pixel electrode PE may have a three-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, and a third pixel electrode layer (or a third metal layer). The third pixel electrode layer may be used as an electrode of the light-emitting layer EL and may include ITO or IZO. For example, according to another embodiment, the pixel electrode PE may be formed as a three-layer structure of IZO / MoTi / ITO or ITO / MoTi / ITO.

[0250] According to another embodiment, the pixel electrode PE may have a four-layer structure including a first pixel electrode layer PEL1, a second pixel electrode layer PEL2 on the first pixel electrode layer PEL1, a third pixel electrode layer (or a third metal layer) on the second pixel electrode layer PEL2, and a fourth pixel electrode layer (or a fourth metal layer) on the third pixel electrode layer.

[0251] In a four-layer pixel electrode PE, the first pixel electrode layer can serve as an adhesive layer corresponding to the planarization layer 112 and as an auxiliary electrode for the light-emitting layer EL. The first pixel electrode layer may include one or more materials selected from ITO, Mo, and MoTi. The second pixel electrode layer can reduce the resistance of the pixel electrode PE and may include Cu. The third pixel electrode layer can serve as a reflector and may include one or more materials selected from Al, Ag, Mo, Ti, and MoTi. The fourth pixel electrode layer can serve as an electrode for the light-emitting layer EL and may include ITO or IZO. For example, according to another embodiment, the pixel electrode PE can be formed as a four-layer structure of ITO / Cu / MoTi / ITO.

[0252] According to another embodiment, the pixel electrode PE may have a five-layer structure including a first pixel electrode layer made of ITO, a second pixel electrode layer made of MoTi, a third pixel electrode layer made of ITO, a fourth pixel electrode layer made of Ag, and a fifth electrode layer made of ITO.

[0253] The light-emitting layer EL can be disposed on a first region of the first substrate 100 and at least a portion of a second region of the first substrate 100. The light-emitting layer EL can be formed on the pixel electrode PE and can directly contact the pixel electrode PE. The pixel electrode PE can be disposed below (or beneath) the light-emitting layer EL. For example, the pixel electrode PE can be disposed between the planarization layer 112 and the light-emitting layer EL.

[0254] According to another embodiment, the light-emitting layer EL can be a common layer formed jointly in each of a plurality of sub-pixels SP without being distinguished by sub-pixels SP. The light-emitting layer EL can respond to the current flowing between the pixel electrode PE and the common electrode CE, thereby emitting white light (or blue light). For example, the light-emitting layer EL according to an embodiment of the present invention may include an organic light-emitting layer, or may include a stacked or combined structure of an organic light-emitting layer and a quantum dot light-emitting layer.

[0255] An organic light-emitting layer (EL) according to embodiments of the present invention may include two or more organic light-emitting layers for emitting white light. For example, the organic light-emitting layer EL may include a first organic light-emitting layer and a second organic light-emitting layer for emitting white light based on a combination of a first light and a second light. For example, the first organic light-emitting layer may include at least one of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer. The second organic light-emitting layer may include at least one of a blue light-emitting layer, a green light-emitting layer, a red light-emitting layer, a yellow light-emitting layer, and a yellow-green light-emitting layer for emitting a second light that, when combined with the first light, produces white light.

[0256] The organic light-emitting layer according to embodiments of the present invention may further include one or more functional layers for improving luminous efficiency and / or lifetime. For example, the functional layer may be interposed between a hole functional layer and an electron functional layer.

[0257] The common electrode CE can be referred to as a cathode, transparent electrode, upper electrode, or second electrode. The common electrode CE can be formed on the light-emitting layer EL and can be in direct contact with the light-emitting layer EL, or can be electrically in direct contact with the light-emitting layer EL. The common electrode CE may comprise a transparent conductive material that transmits light emitted from the light-emitting layer EL.

[0258] The common electrode CE according to embodiments of the present invention can be formed as a single-layer or multi-layer structure comprising at least one material selected from graphene and a transparent conductive material with relatively high work function. For example, the common electrode CE may comprise a metal oxide such as ITO or IZO, or may comprise a combination of oxide and metal, such as ZnO:Al or SnO2:Sb.

[0259] In addition, the light-emitting device layer 113 may further include a capping layer disposed on the common electrode CE. The capping layer can improve the light emission efficiency by adjusting the refractive index of the light emitted from the light-emitting layer EL.

[0260] A dam 114 may be disposed on the planarization layer 112 to define a pixel region PA on the first substrate 100. The dam 114 may be disposed on the planarization layer 112 to cover the peripheral portion of the pixel electrode PE. The dam 114 may define a light-emitting region EA (or opening portion) of each of the plurality of sub-pixels SP and may electrically isolate the pixel electrodes PE disposed in adjacent sub-pixels SP. The dam 114 may be formed to cover the electrode contact hole ECH disposed in each of the plurality of pixel regions PA. The dam 114 may be covered by a light-emitting layer EL. For example, the light-emitting layer EL may be disposed on the dam 114 and on the pixel electrode PE of each of the plurality of sub-pixels SP.

[0261] According to embodiments of the present invention, the dam 114 may be a transparent dam comprising a transparent material or a black dam comprising black pigment (or an opaque dam).

[0262] Reference Figure 4 , 9 According to embodiments of the present invention, the discontinuity 115 may be provided in a second region of the first substrate 100. The discontinuity 115 may be provided at a peripheral portion of the first substrate 100 or at a peripheral portion of each outermost pixel Po, forming a one-dimensional closed loop (or closed loop line) around the display portion AA. The discontinuity may be implemented on a buffer layer 111a or an interlayer insulating layer 111c located at a peripheral portion of the first substrate 100. For example, the interlayer insulating layer 111c may be provided at a portion other than the peripheral portion of the first substrate 100; in this case, the discontinuity 115 may be implemented on the buffer layer 111a.

[0263] According to an embodiment of the present invention, the discontinuity 115 can be implemented by disconnecting (or isolating) the light-emitting device layer 113 disposed in the second region of the first substrate 100 at least once. Therefore, the discontinuity 115 may be referred to as an isolation portion, isolation line portion, cutting portion, cutting line portion, severing portion, severing line portion, break portion, or break line portion, but the embodiments of the present invention are not limited thereto.

[0264] According to an embodiment of the present invention, the discontinuity 115 may include at least one discontinuous structure 115a to 115d having a closed-loop form. For example, when the discontinuity 115 includes multiple discontinuous structures 115a to 115d, the discontinuity 115 may include an external discontinuity located at the outer periphery of the weir 117 and an internal discontinuity located at the inner periphery of the weir 117. According to an embodiment of the present invention, the discontinuity 115 may include first to fourth discontinuous structures 115a to 115d. In this case, the external discontinuity may include first to third discontinuous structures 115a, 115b, and 115c, and the internal discontinuity may include the fourth discontinuous structure 115d. For example, the first to third discontinuous structures 115a, 115b, and 115c may be referred to as multiple external discontinuous structures, and the fourth discontinuous structure 115d may be referred to as at least one internal discontinuous structure, but the embodiments of the present invention are not limited thereto.

[0265] Each of the first to fourth discontinuous structures 115a to 115d according to embodiments of the present invention may include a first strip structure TS1 and a second strip structure TS2.

[0266] According to an embodiment of the present invention, the first strip structure TS1 can be implemented as a stacked structure of an interlayer insulating layer 111c and a passivation layer 111d. The first strip structure TS1 can be formed by a patterning and etching process performed on the interlayer insulating layer 111c and the passivation layer 111d in a second region of the first substrate 100. For example, in some embodiments, the first strip structure TS1 may also be referred to by terms such as a first structure, a first isolation structure, a first tapered structure, or a lower structure, but the embodiments of the present invention are not limited thereto.

[0267] According to an embodiment of the present invention, the side surface of the first strip structure TS1 can be implemented as an inclined structure or a conical structure. The bottom surface of the first strip structure TS1 can directly contact the top surface (or surface) of the buffer layer 111a. The top surface of the first strip structure TS1 can be disposed on the bottom surface of the first strip structure TS1 and can have a width narrower than the bottom surface of the first strip structure TS1. The side surface of the first strip structure TS1 can be formed to be inclined between the top surface and the bottom surface of the first strip structure TS1. In the first strip structure TS1, the included angle between the bottom surface and the side surface can be an acute angle, and the included angle between the top surface and the side surface can be an obtuse angle. For example, the cross-sectional structure of the cross-section of the first strip structure TS1 taken along the width direction can have a trapezoidal shape in which the top surface is narrower than the bottom surface.

[0268] According to another embodiment of the present invention, when the interlayer insulating layer 111c is not disposed at the peripheral portion of the first substrate 100, the first strip structure TS1 can be implemented using only the passivation layer 111d. The first strip structure TS1 can be formed by a patterning process performed on the passivation layer 111d located in the second region of the first substrate 100.

[0269] The second strip structure TS2 may be disposed on the first strip structure TS1. For example, in some embodiments, the second strip structure TS2 may also be referred to by terms such as second structure, second isolation structure, second conical structure or upper structure, but the embodiments of the present invention are not limited thereto.

[0270] The second strip structure TS2 may have a width wider than the top surface of the first strip structure TS1. The second strip structure TS2 may have a width greater than or equal to the bottom surface of the first strip structure TS1. For example, the side surface of the second strip structure TS2 may be an inclined structure or a conical structure. For example, the cross-sectional structure of the cross-section of the second strip structure TS2 taken along its width direction may have the same trapezoidal shape as the first strip structure TS1. Each of the outer peripheral portions on one side and the other side of the second strip structure TS2 may protrude beyond the outer surface of the side surface of the first strip structure TS1, relative to the width direction.

[0271] The second strip structure TS2 may include organic material. The second strip structure TS2 according to embodiments of the present invention may include the same material as the embankment 114, but embodiments of the present invention are not limited thereto. For example, the second strip structure TS2 may not be patterned (or removed) when a patterning process is performed on the embankment material, but may be implemented using the embankment material retained in the first strip structure TS1. The second strip structure TS2 may be implemented to have the same height (or thickness) as the embankment 114.

[0272] The side surface of the first strip structure TS1 may have an undercut structure relative to the second strip structure TS2. For example, the discontinuity 115 may include a boundary portion located between the first strip structure TS1 and the second strip structure TS2, or an undercut region located on the upper side surface of the first strip structure TS1. The second strip structure TS2 may protrude beyond the side surface of the first strip structure TS1 based on the undercut structure of the first strip structure TS1, thereby covering the side surface of the first strip structure TS1. Therefore, the second strip structure TS2 may have an eaves structure relative to the first strip structure TS1.

[0273] According to embodiments of the present invention, the discontinuity 115, comprising the first to fourth discontinuous structures 115a to 115d, can disconnect (or isolate) the light-emitting layer EL, or can disconnect (or isolate) the light-emitting layer EL and the common electrode CE. For example, the light-emitting layer EL formed (or deposited) on the discontinuity 115 can be automatically disconnected (or isolated) during the deposition process based on the undercut structure (or eaves structure) of each of the first to fourth discontinuous structures 115a to 115d, without the need for a separate isolation process. Therefore, the light-emitting layer EL disposed on the first substrate 100 can be disconnected (or isolated) four times in the second region of the first substrate 100, and can include four discontinuous regions (or isolation regions). For example, the deposition material of the light-emitting layer EL can be linear, so it will not be deposited on the side surface of the first strip structure TS1 covered by the second strip structure TS2 based on the undercut structure (or eaves structure) of each of the first to fourth discontinuous structures 115a to 115d. Therefore, the light-emitting layer EL formed (or deposited) on the first to fourth discontinuous structures 115a to 115d can be disconnected (or isolated) between the first strip structure TS1 and the second strip structure TS2. Thus, the light-emitting layer EL can be automatically disconnected (or isolated) through the first to fourth discontinuous structures 115a to 115d of the discontinuity 115 during the deposition process, which has the advantages and effects of preventing moisture and also serving as an auxiliary weir. Therefore, the separate patterning process for disconnecting (or isolating) the light-emitting layer EL located at the peripheral portion of the first substrate 100 to prevent lateral transport of moisture or humidity can be omitted. That is, the discontinuity 115 performs the function of disconnecting multiple portions of the common electrode CE from other portions, and based on its structure and location, it also performs the function of blocking moisture and other residues from reaching the main array, serving as an auxiliary weir for the function performed by the auxiliary weir 117. Since the discontinuous structure also serves to assist in performing this function, this allows the display panel to be constructed without the need for a dedicated weir separate from the weir 117.

[0274] Optionally, the common electrode CE disposed on the light-emitting layer EL can be automatically disconnected (or isolated) by the first to fourth discontinuous structures 115a to 115d of the discontinuity 115 during the deposition process, or it can be deposited on the side surface of the first strip structure TS1 covered by the second strip structure TS2, and can be formed continuously without discontinuous regions.

[0275] A weir 117 may be disposed on the circuit layer 111 in a second region of the first substrate 100 to have a closed-loop shape or a closed-loop line shape. For example, according to an embodiment of the present invention, the weir 117 may be disposed on the passivation layer 111d of the circuit layer 111. For example, the weir 117 may be surrounded by a discontinuity 115. For example, the weir 117 may be disposed between a third discontinuity structure 115c and a fourth discontinuity structure 115d. The weir 117 may be surrounded by the third discontinuity structure 115c and may surround the fourth discontinuity structure 115d. The weir 117 may prevent diffusion or overflow of the encapsulation layer 119.

[0276] The weir 117 according to an embodiment of the present invention may comprise the same material as the planarization layer 112 and be formed together with the planarization layer 112. The weir 117 may have the same height (or thickness) as the planarization layer 112, or it may have a higher height than the planarization layer 112. For example, the height (or thickness) of the weir 117 may be twice the height (or thickness) of the planarization layer 112.

[0277] According to another embodiment, the weir 117 may include a first weir (or lower weir) 117a formed together with the planarization layer 112 from the same material as the planarization layer 112, and a second weir (or upper weir) 117b stacked on the first weir 117a and comprising the same material as the dike 114. The first weir 117a may have the same height (or thickness) as the planarization layer 112, or it may have a height greater than the planarization layer 112. For example, the height (or thickness) of the first weir 117a may be twice the height (or thickness) of the planarization layer 112.

[0278] The encapsulation layer 119 may be disposed on the light-emitting device layer 113, and the encapsulation layer 119 and at least one wiring 410 may overlap each other at the peripheral portion of the first substrate 100. For example, the encapsulation layer 119 may be implemented to surround the entire front and side surfaces of the light-emitting device layer 113.

[0279] The encapsulation layer 119 according to an embodiment of the present invention may include first to third encapsulation layers 119a, 119b and 119c.

[0280] The first encapsulation layer 119a can be implemented to prevent oxygen or moisture from penetrating into the light-emitting device layer 113. The first encapsulation layer 119a can be disposed on the common electrode CE and surround the light-emitting device layer 113. For example, the first encapsulation layer 119a can be implemented as a conformal shape based on the surface shape of the common electrode CE, and thus can surround the common electrode CE. The ends of the first encapsulation layer 119a can directly contact the passivation layer 111d and can surround the ends of the common electrode CE. Therefore, the entire front and lateral surfaces of the light-emitting device layer 113 can be surrounded by the first encapsulation layer 119a. For example, the first encapsulation layer 119a can directly contact the top surface of the passivation layer 111d at each of the inner portion of the discontinuity 115, the weir 117, and the outer portion of the discontinuity 115, and can cover the boundary portion (or interface) located between the common electrode CE and the passivation layer 111d, thereby preventing or minimizing lateral moisture penetration. The first encapsulation layer 119a according to an embodiment of the present invention may include an inorganic material. For example, the first encapsulation layer 119a may be referred to as the first inorganic encapsulation layer.

[0281] The second encapsulation layer 119b may be implemented on the first encapsulation layer 119a with a thickness relatively thicker than that of the first encapsulation layer 119a. The second encapsulation layer 119b may have a thickness sufficient to cover particles (or undesirable materials or structures) located on or potentially located on the first encapsulation layer 119a. The second encapsulation layer 119b may diffuse to the peripheral portion of the first substrate 100 due to its relatively thick thickness, but the diffusion of the second encapsulation layer 119b may be blocked by the weir 117 (i.e., the second encapsulation layer 119b does not extend beyond the weir 117).

[0282] According to an embodiment of the present invention, a second encapsulation layer 119b may be disposed on a first encapsulation layer 119a and surrounded by a weir 117. The end of the second encapsulation layer 119b may directly contact the first encapsulation layer 119a on the weir 117. Therefore, the second encapsulation layer 119b may be disposed only on the first encapsulation layer 119a within the inner region (or inner area) surrounded by the weir 117. The second encapsulation layer 119b may be referred to as a particle cover layer. The second encapsulation layer 119b according to an embodiment of the present invention may comprise an organic material such as silicon carbide (SiOCz) acrylic acid or epoxy resin.

[0283] The third encapsulation layer 119c can be implemented to initially prevent oxygen or moisture from penetrating into the light-emitting device layer 113. The third encapsulation layer 119c can be disposed on the first encapsulation layer 119a and the second encapsulation layer 119b located on the weir 117. The third encapsulation layer 119c can be implemented to surround the second encapsulation layer 119b and the entire first encapsulation layer 119a not covered by the second encapsulation layer 119b. For example, the third encapsulation layer 119c can directly contact the top surface of the passivation layer 111d and can cover the boundary portion (or interface) between the first encapsulation layer 119a and the passivation layer 111d, thereby additionally preventing or minimizing lateral moisture penetration. The third encapsulation layer 119c according to an embodiment of the invention may contain inorganic material. For example, the third encapsulation layer 119c may be referred to as the second inorganic encapsulation layer. For example, the second encapsulation layer 119b can be inserted between the third encapsulation layer 119c and the first encapsulation layer 119a on the light-emitting device layer 113 surrounded by the weir 117.

[0284] According to an embodiment of the present invention, the first substrate 100 may further include a first margin area MA1, a second margin area MA2, and a weir area DA.

[0285] A first margin region MA1 may be disposed between the weir 117 and the light-emitting region EA of the outermost pixel Po. Based on the reliability margin of the light-emitting device layer 113 caused by lateral moisture penetration of water or moisture, the first margin region MA1 may be configured to have a first width between the end of the light-emitting region EA (or the embankment 114) of the outermost pixel Po and the weir 117. Therefore, the weir 117 may be implemented such that, relative to the first direction X, it separates the first margin region MA1 by a first width from the end of the light-emitting region EA.

[0286] A second margin region MA2 may be disposed between the outer surface OS of the first substrate 100 and the weir 117. Based on the reliability margin of the light-emitting device layer 113 caused by lateral moisture penetration of water or humidity, the second margin region MA2 may be configured to have a second width between the outer surface OS of the first substrate 100 and the weir 117. Therefore, the weir 117 may be configured to separate the second margin region MA2 from the outer surface OS of the first substrate 100 with a second width relative to the first direction X.

[0287] The weir region DA can be set between the first margin region MA1 and the second margin region MA2. The weir region DA can be configured to have a third width corresponding to the width of the lowest bottom surface (or bottom surface) of the weir section 117.

[0288] The width of each of the first margin region MA1, the second margin region MA2, and the weir region DA can be implemented such that, relative to the first direction X, the second interval D2 between the center portion of the outermost pixel and the outer surface OS of the first substrate 100 is half or less than the first interval (or pixel pitch) D1 between two adjacent pixel regions PA.

[0289] The light-emitting display device (or light-emitting display panel) according to the present invention may further include a wavelength conversion layer 121 disposed on the first substrate 100.

[0290] Wavelength conversion layer 121 can convert the wavelength of light incident from the light-emitting region EA of each pixel region PA. For example, wavelength conversion layer 121 can convert white light (or blue light) incident from the light-emitting region into colored light corresponding to the corresponding sub-pixel or can only transmit colored light corresponding to the corresponding sub-pixel. For example, wavelength conversion layer 121 may include at least one or more of wavelength conversion components and color filter layers.

[0291] The wavelength conversion layer 121 according to an embodiment of the present invention may include a coating layer 121b and a plurality of wavelength conversion components 121a.

[0292] Multiple wavelength conversion components 121a may be disposed on the encapsulation layer 119 located in the light-emitting region EA of each of the multiple sub-pixel regions. For example, each of the multiple wavelength conversion components 121a may be implemented to have the same size as the light-emitting region EA of each sub-pixel region, or to have a size wider than the size of the light-emitting region EA of each sub-pixel region.

[0293] The coating layer (or protective layer) 121b may be configured to cover the wavelength conversion member 121a and provide a flat surface on the wavelength conversion member 121a. For example, the coating layer 121b may be configured to cover the wavelength conversion member 121a and an encapsulation layer 119 in which the wavelength conversion member 121a is not disposed. The protective layer 121b according to embodiments of the invention may include organic materials. For example, the coating layer 121b may include acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin, but embodiments of the invention are not limited thereto. Alternatively, the coating layer 121b may further include a getter material for absorbing moisture and / or oxygen.

[0294] Alternatively, the wavelength conversion layer 121 according to an embodiment of the present invention may further include a quantum dot component inserted between the wavelength conversion component 121a and the encapsulation layer 119. The quantum dot component may be configured to re-emit colored light set in the sub-pixel by re-emitting white or blue light incident from the light-emitting device layer 113.

[0295] Alternatively, the wavelength conversion layer 121 may be a wavelength conversion sheet in sheet form and may be disposed on the encapsulation layer 119. For example, the wavelength conversion sheet (or quantum dot sheet) may include a wavelength conversion member 121a interposed between a pair of films. For example, the wavelength conversion member 121a of the wavelength conversion sheet may include a quantum dot member configured to re-emit colored light set in a sub-pixel by re-emitting white or blue light incident from the light-emitting layer 113.

[0296] The light-emitting display device or the first substrate 100 according to an embodiment of the present invention may further include a functional film 123.

[0297] The functional film 123 may be disposed on the wavelength conversion layer 121. For example, the functional film 123 may be connected to the wavelength conversion layer 121 via a transparent adhesive member 122.

[0298] The functional film 123 according to an embodiment of the present invention may include an anti-reflective layer (or anti-reflective film) for preventing the reflection of external light, thereby improving the outdoor visibility and contrast of the image displayed by the light-emitting display device 10. For example, the anti-reflective layer may include a circularly polarizing layer (or circularly polarizing film) that prevents external light reflected by the TFTs and / or pixel driving lines disposed on the first substrate 100 from propagating to the outside.

[0299] The functional membrane 123 according to an embodiment of the present invention may further include a barrier layer (or barrier membrane) for initially preventing the penetration of moisture or humidity or oxygen. The barrier layer may include a material with low water permeability (e.g., a polymer material).

[0300] The functional film 123 according to an embodiment of the present invention may further include an optical path control layer (or optical path control film) for controlling the path of light output from each pixel P to the outside. The optical path control layer may include a stacked structure of alternating high refractive index layers and low refractive index layers, and may change the path of light incident from each pixel P to reduce or minimize color shift based on viewing angle.

[0301] The light-emitting display device or the first substrate 100 according to an embodiment of the present invention may further include a side sealing member 125.

[0302] A side sealing member (or edge sealing member) 125 may be formed between the first substrate 100 and the functional film 123 and may cover all side (or lateral) surfaces of each of the circuit layer 111, the planarization layer 112, and the wavelength conversion layer 121. That is, the side sealing member 125 may cover all side surfaces of each of the circuit layer 111, the planarization layer 112, and the wavelength conversion layer 121 located between the functional film 123 and the first substrate 100 that are exposed to the outside of the light-emitting display device 10. For example, each of the outermost outer surface of the first substrate 100, the outer surface of the side sealing member 125, and the outer surface of the functional film 123 may be disposed (or aligned) on the same vertical extension line VL.

[0303] The side sealing member 125 according to embodiments of the present invention may include a silicone-based or ultraviolet (UV) curable sealant (or resin), but considering the tact time, the side sealing member 125 may include a UV curable sealant. Furthermore, the side sealing member 125 may be colored (e.g., blue, red, turquoise, or black), but embodiments of the present invention are not limited thereto; the side sealing member 125 may include a colored resin or light-blocking resin for preventing lateral light leakage. Alternatively, the side sealing member 125 may further include an absorbent material for absorbing moisture and / or oxygen.

[0304] The light-emitting display device according to an embodiment of the present invention may further include a second substrate 200.

[0305] The second substrate 200 may include a metal pattern layer and an insulating layer that insulates the metal pattern layer.

[0306] The metal patterned layer (or conductive patterned layer) may include multiple metal layers. According to embodiments of the present invention, the metal patterned layer may include a first metal layer 201, a second metal layer 203, and a third metal layer. The insulating layer may include multiple insulating layers. For example, the insulating layer may include a first insulating layer 202, a second insulating layer 204, and a third insulating layer 206. The insulating layer may be referred to as a back insulating layer or a patterned insulating layer.

[0307] The first metal layer 201, the second metal layer 203, and the third metal layer can be used as pads 211 of the first pad portion 210, pads of the second pad portion 230, and connections of the interconnect portion 250 located on the rear surface 200b of the second substrate 200. For example, the first metal layer 201 can be used as some of the connections among multiple connections, and the third metal layer can be used as pad 211 and other connections among multiple connections. The second metal layer 203 can be used as a jumper wire (or bridging wire) to electrically connect connections located on different layers.

[0308] A first insulating layer 202 may be implemented on the rear surface 200b of the second substrate 200 to cover the first metal layer 201. A second insulating layer 204 may be implemented on the rear surface 200b of the second substrate 200 to cover the second metal layer 203. A third insulating layer 206 may be implemented on the rear surface 200b of the second substrate 200 to cover the third metal layer.

[0309] The second substrate 200 can be joined to the rear surface of the first substrate 100 by the joining member 300.

[0310] A bonding member 300 may be disposed between the first substrate 100 and the second substrate 200. Therefore, the first substrate 100 and the second substrate 200 can be bonded to each other via the bonding member 300. According to an embodiment of the invention, the bonding member 300 may be a transparent adhesive member comprising optically clear adhesive (OCA) or optically clear resin (OCR) or a double-sided tape. According to another embodiment, the bonding member 300 may comprise glass fiber.

[0311] According to an embodiment of the present invention, the bonding member 300 may be disposed in the entire space between the first substrate 100 and the second substrate 200. For example, the entire second surface 100b of the first substrate 100 may be bonded to the entire surface of the bonding member 300, and the entire front surface 200a of the second substrate 200 may be bonded to the entire other surface of the bonding member 300.

[0312] According to another embodiment, the bonding member 300 may be disposed in a patterned structure between the first substrate 100 and the second substrate 200. For example, the bonding member 300 may have a line pattern structure or a mesh pattern structure. The mesh pattern structure may further include bent portions for discharging air bubbles that appear between the first substrate 100 and the second substrate 200 during the process of bonding the first substrate 100 to the second substrate 200 to the outside.

[0313] Alternatively, the bonding member 300 may further include a heat transfer element. In this case, the bonding member 300 can transfer heat generated in the first substrate 100 to the second substrate 200 via the heat transfer element to prevent or minimize temperature rise in the first substrate 100. The second substrate 200 can serve as a cooling member to prevent or minimize temperature rise in the first substrate 100. For example, the heat transfer element may include a heat transfer layer of a metallic material or a plurality of heat transfer particles. When the heat transfer element includes a heat transfer layer of a metallic material, the heat transfer layer may be electrically grounded or floating, and thus can serve as a noise blocking layer to prevent frequency noise or static electricity occurring in the drive circuit located on the rear surface 200b of the second substrate 200 from flowing into the pixels, pixel drive lines, and gate drive circuits 150 located on the first substrate 100.

[0314] The light-emitting display device according to an embodiment of the present invention may further include a wiring section 400.

[0315] The wiring section 400 can electrically connect the contact patterns PCP, DCP, RCP, GCP, and CCP of the contact pattern section 110 located on one side of the outer periphery of the first substrate 100 to the pads 211 of the first pad section 210 located on one side of the outer periphery of the second substrate 200. The wiring section 400 can be implemented around the outer surface OS1a of the first substrate 100 and the contact pattern section 110, and the outer surface OS1b of the second substrate 200 and the contact pattern section 110, so that the contact patterns PCP, DCP, RCP, GCP, and CCP of the contact pattern section 110 can be directly electrically connected to the pads 211 of the first pad section 210. The wiring section 400 can be provided on one side of the outer periphery of each of the first substrate 100 and the second substrate 200, and can be directly electrically connected to the contact pattern section 110 via the weir section 117 or the discontinuity section 115 and the entire weir section 117, so that it can replace the pad section located on the outermost outer periphery of the first substrate 100. Therefore, the light-emitting display device according to the embodiment of the present invention does not require a pad portion located at the outermost peripheral portion of the first substrate 100, and thus can have an air frame structure in which no frame area is provided.

[0316] According to an embodiment of the present invention, the wiring portion 400 may be electrically connected to the contact pattern portion 110 via a wiring contact hole CH passing through at least one of the discontinuities 115 and the weir portion 117 located on the contact pattern portion 110. The discontinuities 115 may be located on the contact pattern portion 110, wherein at least one of the plurality of wirings 410 may extend through the encapsulation layer and the discontinuities 115 to connect to the contact pattern portion 110.

[0317] According to a first embodiment of the present invention, the wiring portion 400 can pass through the third encapsulation layer 119c, the first encapsulation layer 119a, and the weir portion 117 located on the contact pattern portion 110, and can be electrically connected to the contact pattern portion 110. For example, according to the first embodiment of the present invention, the wiring portion 400 can be electrically connected to the contact pattern portion 110 via a wiring contact hole CH passing through the weir portion 117 located on the contact pattern portion 110. For example, according to the first embodiment of the present invention, the wiring portion 400 can be electrically connected to the contact pattern portion 110 via a wiring contact hole CH passing sequentially through the third encapsulation layer 119c, the first encapsulation layer 119a, the isolated light-emitting device layer 113, the weir portion 117, and the circuit layer 111 located on the contact pattern portion 110.

[0318] According to a second embodiment of the present invention, the wiring portion 400 can pass through the third encapsulation layer 119c, the first encapsulation layer 119a, and the discontinuity portion 115 located on the contact pattern portion 110, and can be electrically connected to the contact pattern portion 110. For example, according to the second embodiment of the present invention, the wiring portion 400 can be electrically connected to the contact pattern portion 110 via a wiring contact hole CH passing through the discontinuity portion 115 located on the contact pattern portion 110. For example, according to the second embodiment of the present invention, the wiring portion 400 can be electrically connected to the contact pattern portion 110 via a wiring contact hole CH passing sequentially through the third encapsulation layer 119c, the first encapsulation layer 119a, the isolated light-emitting device layer 113, the discontinuity portion 115, and the circuit layer 111 located on the contact pattern portion 110.

[0319] According to a third embodiment of the present invention, the wiring portion 400 may be electrically connected to the contact pattern portion 110 via wiring contact holes CH passing through each of the weir portion 117 and the discontinuity portion 115 located on the contact pattern portion 110.

[0320] The wiring contact hole CH can be implemented by at least one hole patterning process on the patterned layer on the contact pattern portion 110 of the first substrate 100 to expose at least a portion of each of the contact patterns PCP, DCP, RCP, GCP and CCP. The wiring contact hole CH according to an embodiment of the present invention may include at least one first to fifth wiring contact holes CH1 to CH5.

[0321] At least one first wiring contact hole CH1 can be implemented as passing through a first discontinuity structure 115a of the discontinuity 115. At least one second wiring contact hole CH2 can be implemented as passing through a second discontinuity structure 115b of the discontinuity 115. At least one third wiring contact hole CH3 can be implemented as passing through a third discontinuity structure 115c of the discontinuity 115. At least one fourth wiring contact hole CH4 can be implemented as passing through a fourth discontinuity structure 115d of the discontinuity 115. At least one fifth wiring contact hole CH5 can be implemented as passing through a weir section 117.

[0322] At least one of the first to fourth wiring contact holes CH1 to CH4 can be implemented to pass through each of the layers on the contact pattern portion 110, including the encapsulation layer 119 and each of the first to fourth discontinuity structures 115a to 115d of the discontinuity portion 115. Each of the at least one of the first to fourth wiring contact holes CH1 to CH4 according to an embodiment of the present invention can be implemented to pass sequentially through the coating layer 121b, the second inorganic encapsulation layer 119c and the first inorganic encapsulation layer 119a of the encapsulation layer 119, the isolated common electrode CEa and the isolated light-emitting layer ELa of the light-emitting device layer 113, the discontinuity structures 115a to 115d, and the buffer layer 111a located on the contact pattern portion 110, so as to expose at least a portion of each of the contact patterns PCP, DCP, RCP, GCP and CCP. For example, at least one second wiring contact hole CH2 may be implemented to pass sequentially through the coating layer 121b, the second inorganic encapsulation layer 119c and the first inorganic encapsulation layer 119a of the encapsulation layer 119, the isolated common electrode CEa and the isolated light-emitting layer ELa of the light-emitting device layer 113, the discontinuous structures 115a to 115d, and the buffer layer 111a on the contact pattern portion 110, so as to expose at least a portion of the data contact pattern DCP.

[0323] At least one fifth wiring contact hole CH5 may be implemented to pass through layers on the contact pattern portion 110, including a weir portion 117 and an encapsulation layer 119. Each of the at least one fifth wiring contact hole CH5 according to an embodiment of the present invention may be implemented to pass sequentially through a coating layer 121b, a second inorganic encapsulation layer 119c and a first inorganic encapsulation layer 119a on the contact pattern portion 110, an isolated common electrode CEa and an isolated light-emitting layer ELa of the light-emitting device layer 113, a weir portion 117, and a buffer layer 111a, so as to expose at least a portion of each of the contact patterns PCP, DCP, RCP, GCP and CCP.

[0324] The wiring portion 400 according to an embodiment of the present invention may include a plurality of wirings 410. The plurality of wirings 410 may be arranged at defined intervals along a first direction X, and may be implemented around the outer surface OS1a and contact pattern portion 110 of the first substrate 100 and the outer surface OS1b and contact pattern portion 110 of the second substrate 200. For example, each of the plurality of wirings 410 may be formed by a printing process using conductive adhesive. For example, the conductive adhesive may include silver (Ag) adhesive, but embodiments of the present invention are not limited thereto.

[0325] Each of the multiple wirings 410 may include a first portion (or front portion) 410a located on the contact pattern portion 110 of the first substrate 100, a second portion (or rear portion) 410b located on the first pad portion 210 of the second substrate 200, and a third portion (or side portion or center portion) 410c located between the first portion 410a and the second portion 410b on the outer surface OS1a of the first substrate 100 and the outer surface OS1b of the second substrate 200.

[0326] The first part 410a, the second part 410b, and the third part 410c of each of the multiple wirings 410 can be simultaneously achieved by a printing process using conductive adhesive.

[0327] The first part 410a of each of the multiple wirings 410 can be directly connected to the contact patterns PCP, DCP, RCP, GCP and CCP of the contact pattern section 110 via the wiring contact hole CH.

[0328] According to an embodiment of the present invention, the first portion 410a can be directly connected to the contact patterns PCP, DCP, RCP, GCP and CCP of the contact pattern portion 110 via wiring contact holes CH. For example, the first portion 410a may include at least five connecting portions (or contact portions) that fill at least one first to fifth wiring contact holes CH1 to CH5 to directly connect to one of the contact patterns PCP, DCP, RCP, GCP and CCP.

[0329] The second portion 410b of each of the multiple wirings 410 may be disposed on the first pad portion 210 located on the rear surface 200b of the second substrate 200, and may be directly connected to the pad 211 of the first pad portion 210. The third portion 410c of each of the multiple wirings 410 may be disposed between the first portion 410a and the second portion 410b, and may surround or encircle the outer surface OS1a of the first substrate 100 and the outer surface OS1b of the second substrate 200.

[0330] The contact patterns PCP, DCP, RCP, GCP and CCP of the contact pattern section 110 can be electrically connected to the pads 211 of the first pad section 210 via the first part 410a, the third part 410c and the second part 410b of each wiring 410.

[0331] According to the implementation, the multiple wirings 410 can be divided (or classified) into multiple pixel drive power supply wirings 411, multiple data wirings 413, multiple reference voltage wirings 415, multiple gate wirings 417, and multiple pixel common voltage wirings 419.

[0332] Each of the multiple pixel drive power lines 411 can be directly electrically connected to the pixel drive power contact pattern PCP of the contact pattern portion 110 via a wiring contact hole CH that passes sequentially through the encapsulation layer 119, the discontinuity portion 115, and the circuit layer 111, and can also be electrically connected to the first power contact pad of the first pad portion 210. Therefore, the pixel drive power output from the drive circuit unit can be provided to each pixel drive power line PL via the second pixel drive power pad, the pixel drive power interconnect, the first pixel drive power pad, the pixel drive power line 411, and the pixel drive power contact pattern PCL.

[0333] Each of the multiple data traces 413 can be directly electrically connected to the data contact pattern PCP of the contact pattern portion 110 via a wiring contact hole CH that passes sequentially through the encapsulation layer 119, the discontinuity portion 115, and the circuit layer 111, and can also be electrically connected to the first data pad of the first pad portion 210. Therefore, the data signal output from the drive circuit unit can be provided to each of the data lines DL via the second data pad, the data interconnect, the first data pad, the data trace 413, and the data contact pattern DCP.

[0334] Each of the multiple reference voltage wirings 415 can be directly electrically connected to the reference voltage contact pattern RCP of the contact pattern portion 110 via a wiring contact hole CH that passes sequentially through the package layer 119, the discontinuity portion 115, and the circuit layer 111, and can also be electrically connected to the first reference voltage pad of the first pad portion 210. Therefore, the reference voltage output from the drive circuit unit can be provided to each of the reference voltage lines RL via the second reference voltage pad, the reference voltage interconnect, the first reference voltage pad, the reference voltage wiring 415, and the reference voltage contact pattern RCP.

[0335] Each of the multiple gate wirings 417 can be directly electrically connected to the gate contact pattern GCP of the contact pattern portion 110 via a wiring contact hole CH that passes sequentially through the package layer 119, the discontinuity portion 115, and the circuit layer 111, and can also be electrically connected to the first gate pad of the first pad portion 210. Therefore, the gate control signal output from the drive circuit unit can be provided to each of the gate control lines GCL via the second gate pad, the gate interconnect, the first gate pad, the gate wiring 417, and the gate contact pattern GCP.

[0336] Each of the multiple pixel common voltage wirings 419 can be directly electrically connected to the pixel common voltage contact pattern CCP of the contact pattern portion 110 via wiring contact holes CH that pass sequentially through the encapsulation layer 119, the discontinuity portion 115, and the circuit layer 111, and can also be electrically connected to the first pixel common voltage pad of the first pad portion 210. Therefore, the pixel common voltage output from the driving circuit unit can be provided to each of the pixel common voltage lines CVL via the second pixel common voltage pad, the pixel common voltage interconnect, the first pixel common voltage pad, the pixel common voltage wiring 419, and the pixel common voltage contact pattern CCP.

[0337] exist Figures 10 to 12 The text describes how the wiring 410 of the wiring section 400 is directly electrically connected to contact patterns PCP, DCP, RCP, GCP, and CCP via at least one first to fourth wiring contact hole CH1 to CH4 formed in the first to fourth discontinuity structures 115a to 115d of the discontinuity section 115 and at least one fifth wiring contact hole CH5 formed in the weir section 117. However, embodiments of the present invention are not limited to this. For example, the wiring 410 of the wiring section 400 may be directly electrically connected to contact patterns PCP, DCP, RCP, GCP, and CCP via at least one first to fifth wiring contact hole CH1 to CH5.

[0338] Referenced above Figures 10 to 12 The second substrate 200, located on the rear surface of the first substrate 100, can be omitted. In this case, as... Figure 7 As shown, each of the first pad portion 210, the second pad portion 230, and the interconnect portion 250 located on the second substrate 200 can be disposed on the rear surface 100b of the substrate 100. Except that the wiring 410 of the wiring portion 400 is formed to surround one peripheral portion of the front surface of the substrate 100 and one peripheral portion of the rear surface of the substrate 100, and the contact patterns PCP, DCP, RCP, GCP, and CCP of the contact pattern portion 110 are electrically connected to the pads 211 of the first pad portion 210, the wiring 410 of the wiring portion 400 can be connected to... Figure 7 The basic structure is the same, so repeated descriptions are omitted.

[0339] The light-emitting display device (or wiring section) according to the present invention may further include an edge coating layer 450.

[0340] The edge coating layer 450 can be implemented to cover multiple wirings 410. According to an embodiment of the present invention, the edge coating layer 450 can be implemented to cover not only the multiple wirings 410 but also the entire first outer surface OS1a and first peripheral portion of the first substrate 100 and the first outer surface OS1b and first peripheral portion of the second substrate 200. The edge coating layer 450 can prevent corrosion of each of the multiple wirings 410, including metallic material, or electrical short circuits between the multiple wirings 410. Furthermore, the edge coating layer 450 can prevent or minimize the reflection of external light caused by the multiple wirings 410 and the pads of the first pad portion 210. According to an embodiment of the present invention, the edge coating layer 450 can include a light-shielding material having black ink.

[0341] The top surface of the edge coating layer 450 disposed on the first surface 100a of the first substrate 100 may be covered by the side sealing member 125.

[0342] The outer surface of the edge coating layer 450 can be the outermost outer surface of the first substrate 100. Therefore, each of the outermost outer surface of the first substrate, the outer surface of the side sealing member 125, and the outer surface of the functional film 123 can be disposed on the same vertical extension line VL.

[0343] As described above, the light-emitting display device according to an embodiment of the present invention may include a wiring portion 400 directly connected to a contact pattern located at the peripheral portion of the first substrate (or substrate) 100, thus eliminating the need for a pad portion located at the outermost peripheral portion of the first substrate 100, and thus enabling an air bezel structure in which no bezel area is provided.

[0344] Furthermore, the light-emitting display device according to the present invention can disconnect (or isolate) the light-emitting layer EL located at the peripheral portion of the first substrate (or substrate) 100 at least once by means of the discontinuity portion 115, thereby preventing or minimizing the deterioration of the light-emitting layer EL and / or the reduction in the reliability of the light-emitting layer EL due to the lateral transmission of moisture or humidity.

[0345] Figure 13 This is a diagram illustrating the connection structure of the pixel driving line and the wiring portion according to another embodiment of the present invention. Figure 14 yes Figure 13 An enlarged view of region B4 shown. Figure 15 It is along Figure 14 The cross-sectional view taken by line II-II' shown. Figure 16A yes Figure 15 The enlarged view of area B5 shown. Figure 16B According to another embodiment Figure 15 The enlarged view of area B5 shown. Figure 16C According to another embodiment Figure 15 The enlarged view of area B5 shown. Figure 17 It is along Figure 14 The cross-sectional view shown is taken along line III-III'. Region B5 includes the peripheral portion of the substrate that is also adjacent to the outer surface (or outermost surface) of the substrate. Figure 15 The peripheral portion adjacent to the first outer surface OS1a of the first substrate 100 is shown. Figures 9 to 12 It shows the addition of auxiliary lines. Figures 9 to 12 The embodiment of the light-emitting display device is shown. In the description... Figures 13 to 16C In this case, only the auxiliary lines and related components will be described below, while other components will be referred to by similar reference marks, and their repeated descriptions will be omitted.

[0346] Reference Figures 13 to 16C According to another embodiment of the present invention, the light-emitting display device may further include an auxiliary pattern section 116, which is located between the contact pattern section 110 connected to the plurality of pixel driving lines PL, DL, RL, GCL and CVL and the wiring section 400.

[0347] The auxiliary pattern portion 116 may be referred to as an intermediate metal portion or a signal transmission portion. In some embodiments, the auxiliary pattern portion 116 may refer to an auxiliary conductive structure. The auxiliary conductive structure may include a first auxiliary conductive structure located on the contact pattern portion 110, which may overlap with the location of the discontinuity portion 115 or the weir portion, wherein at least one wiring 410 may extend through the encapsulation layer to connect to the first auxiliary conductive structure. The auxiliary conductive pattern may also include a second auxiliary conductive structure located on the contact pattern portion 110, which may be located on the first auxiliary conductive structure and overlap with the location of the discontinuity portion 115 or the weir portion, wherein at least one wiring 410 may extend through the encapsulation layer to connect to the first auxiliary conductive structure and the second auxiliary conductive structure. The auxiliary pattern portion 116 according to an embodiment of the present invention may include first to fifth intermediate patterns 116a to 116e, which are electrically connected between the contact patterns PCP, DCP, RCP, GCP and CCP of the contact pattern portion 110 and the wiring 410 of the wiring portion 400. For example, each of the first to fifth intermediate patterns 116a to 116e may be referred to as an auxiliary pattern, a conductive auxiliary pattern, or a conductive intermediate pattern, but the embodiments of the present invention are not limited thereto.

[0348] Each of the first to fifth intermediate patterns 116a to 116e may be disposed at the discontinuity 115. For example, the first intermediate pattern 116a may be disposed in the first discontinuity structure 115a of the discontinuity 115. The second intermediate pattern 116a may be disposed in the second discontinuity structure 115b of the discontinuity 115. The third intermediate pattern 116c may be disposed in the third discontinuity structure 115c of the discontinuity 115. The fourth intermediate pattern 116d may be disposed in the fourth discontinuity structure 115d of the discontinuity 115.

[0349] The fifth intermediate pattern 116e may be disposed in the weir region DA. For example, the fifth intermediate pattern 116e may be disposed below the weir portion 117. For example, the fifth intermediate pattern 116e may be disposed between the weir portion 117 and the circuit layer 111.

[0350] Each of the first to fifth intermediate patterns 116a to 116e can be used as an intermediate center layer or signal transmission layer disposed between the contact patterns PCP, DCP, RCP, GCP, and CCP and the wiring portion 400. Each of the first to fifth intermediate patterns 116a to 116e can prevent electrical or physical contact defects between the contact patterns PCP, DCP, RCP, GCP, and CCP and the wiring 410 due to the distance between them. Furthermore, each of the first to fifth intermediate patterns 116a to 116e can be disposed between the first strip structure TS1 and the second strip structure TS2 of each of the first to fourth discontinuous structures 115a to 115d of the discontinuity portion 115, thereby improving the adhesion between the first strip structure TS1 and the second strip structure TS2.

[0351] The first to fourth intermediate patterns 116a to 116d can be respectively disposed in the first to fourth discontinuous structures 115a to 115d overlapping each of the contact patterns PCP, DCP, RCP, GCP, and CCP in the discontinuity portion 115, and can be electrically connected between the contact patterns PCP, DCP, RCP, GCP, and CCP and the wiring 410 of the wiring portion 400. For example, the first to fourth intermediate patterns 116a to 116d can be respectively disposed in the first to fourth discontinuous structures 115a to 115d overlapping the data contact pattern DCP, and can be electrically connected between the data contact pattern DCP and the data wiring 413. For example, each of the first to fourth intermediate patterns 116a to 116d can be commonly connected to the data contact pattern DCP and can be connected to the first portion 410a of the data wiring 413.

[0352] The fifth intermediate pattern 116e may be disposed in the weir portion 117 overlapping each of the contact patterns PCP, DCP, RCP, GCP, and CCP, and may be electrically connected between the contact patterns PCP, DCP, RCP, GCP, and CCP and the wiring 410 of the wiring section 400. For example, the fifth intermediate pattern 116e may be disposed in the weir portion 117 overlapping with the data contact pattern DCP, and may be electrically connected between the data contact pattern DCP and the data wiring 413.

[0353] exist Figures 13 to 16CThe description indicates that the auxiliary pattern section 116 includes first to fifth intermediate patterns 116a to 116e, but embodiments of the present invention are not limited thereto. For example, the auxiliary pattern section 116 may include at least one of the first to fifth intermediate patterns 116a to 116e. For example, the auxiliary pattern section 116 may include only one intermediate pattern 116e disposed in a weir portion 117 overlapping each of the contact patterns PCP, DCP, RCP, GCP, and CCP, and electrically connected between the contact patterns PCP, DCP, RCP, GCP, and CCP and the wiring 410 of the wiring section 400. For example, the auxiliary pattern section 116 may include at least one or more of the first to fourth intermediate patterns 116a to 116d disposed in a discontinuity portion 115 overlapping each of the contact patterns PCP, DCP, RCP, GCP, and CCP, and electrically connected between the contact patterns PCP, DCP, RCP, GCP, and CCP and the wiring 410 of the wiring section 400.

[0354] Each of the first to fifth intermediate patterns 116a to 116e according to embodiments of the present invention may include a first metal layer MLA and a second metal layer MLb.

[0355] The first metal layer MLA may be disposed in the circuit layer 111 that overlaps with the contact patterns PCP, DCP, RCP, GCP, and CCP. For example, the first metal layer MLA may be disposed between the contact patterns PCP, DCP, RCP, GCP, and CCP and each of the discontinuities 115 and the weirs 117. For example, the first metal layer MLA may be disposed between the contact patterns PCP, DCP, RCP, GCP, and CCP and the interlayer insulating layer 111c.

[0356] According to an embodiment of the present invention, a first metal layer MLA can be implemented on a buffer layer 111a to be electrically connected to contact patterns PCP, DCP, RCP, GCP, and CCP. For example, the first metal layer MLA can be disposed on the buffer layer 111a overlapping with the contact patterns PCP, DCP, RCP, GCP, and CCP, and can be electrically connected to the contact patterns PCP, DCP, RCP, GCP, and CCP via a first through-hole (or lower through-hole) VH1 passing through the buffer layer 111a. For example, the first metal layer MLA can be covered by at least one insulating layer located on the buffer layer 111a. For example, the first metal layer MLA can be covered by an interlayer insulating layer 111c.

[0357] According to an embodiment of the present invention, the first metal layer MLA of the first to fourth intermediate patterns 116a to 116d can be electrically connected to the contact patterns PCP, DCP, RCP, GCP and CCP via a first through hole VH1 passing through the buffer layer 111a located below the discontinuity 115.

[0358] According to an embodiment of the present invention, the first metal layer MLA of the fifth intermediate pattern 116e can be electrically connected to the contact patterns PCP, DCP, RCP, GCP and CCP via a first through hole VH1 passing through the buffer layer 111a located below the weir portion 117.

[0359] According to embodiments of the present invention, the first metal layer MLA can be implemented as a dot shape overlapping the contact patterns PCP, DCP, RCP, GCP, and CCP, or it can be implemented as a line shape overlapping the contact patterns PCP, DCP, RCP, GCP, and CCP in the first direction X. For example, the first metal layer MLA of the fifth intermediate pattern 116e can be provided in the weir portion 117, and therefore can have a relatively larger size than the first metal layer MLA of the first to fourth intermediate patterns 116a to 116d, but embodiments of the present invention are not limited thereto.

[0360] According to embodiments of the present invention, the first metal layer MLa can be implemented together with the gate of each thin-film transistor (TFT) Tdr located in the pixel region PA, or it can be implemented together with the source / drain of each TFT. For example, the first metal layer MLa can be implemented to have the same material and structure as the gate of each TFT Tdr, or it can be implemented to have the same material and structure as the source / drain of each TFT Tdr.

[0361] The second metal layer MLb can be electrically connected between the first metal layer MLA and the wiring 410. For example, the second metal layer MLb can be disposed on the passivation layer 111d overlapping the first metal layer MLA, and can be electrically connected to the first metal layer MLA via a second via (or upper via) VH2 that passes through the passivation layer 111d and the interlayer insulating layer 111c in sequence.

[0362] According to an embodiment of the present invention, the second metal layer MLb of the first to fourth intermediate patterns 116a to 116d can be disposed on the first strip structure TS1 of each of the first to fourth discontinuous structures 115a to 115d overlapping with the first metal layer MLA in the discontinuity 115, and can be electrically connected between the first metal layer MLA and the wiring 410. For example, the second metal layer MLb of the first to fourth intermediate patterns 116a to 116d can be disposed between the first strip structure TS1 and the second strip structure TS2 of each of the first to fourth discontinuous structures 115a to 115d in the discontinuity 115, and can be electrically connected to the first metal layer MLA via a second through-hole (or upper through-hole) VH2 passing sequentially through the passivation layer 111d and the interlayer insulating layer 111c. For example, the second metal layer MLb of the first to fourth intermediate patterns 116a to 116d can be disposed between the first strip structure TS1 and the second strip structure TS2, thereby enhancing the adhesion between the first strip structure TS1 and the second strip structure TS2.

[0363] According to an embodiment of the present invention, the second metal layer MLb of the fifth intermediate pattern 116e can be disposed between the first weir 117a and the first metal layer MLa in the weir portion 117, and can be electrically connected between the first metal layer MLa and the wiring 410. For example, the second metal layer MLb of the fifth intermediate pattern 116e can be disposed between the first weir 117a and the passivation layer 111d in the weir portion 117, and can be electrically connected to the first metal layer MLa via a second through-hole (or upper through-hole) VH2 passing sequentially through the passivation layer 111d and the interlayer insulating layer 111c located below the first weir 117a. For example, the second metal layer MLb of the fifth intermediate pattern 116e can be disposed between the first weir 117a and the passivation layer 111d, thereby enhancing the adhesion between the first weir 117a and the passivation layer 111d.

[0364] According to an embodiment of the present invention, the second metal layer MLb can be implemented as a dotted or linear shape similar to the first metal layer MLA. For example, the second metal layer MLb of the fifth intermediate pattern 116e can be provided in the weir portion 117, thereby having a size relatively larger than that of the second metal layer MLb of the first to fourth intermediate patterns 116a to 116d, but the embodiments of the present invention are not limited thereto.

[0365] According to embodiments of the present invention, the second metal layer MLb can be implemented together with the pixel electrode PE located in the pixel region PA. For example, the second metal layer MLb can be implemented to have the same material and structure as the pixel electrode PE.

[0366] Reference Figure 13 , 14 According to another embodiment of the present invention, the light-emitting display device may further include an auxiliary line portion 118, which is located in each of the weir portion 117 and the discontinuity portion 115 disposed at the peripheral portion of the first substrate 100 rather than at one peripheral portion.

[0367] The auxiliary line portion 118 may be referred to as a conductor portion. According to an embodiment of the present invention, the auxiliary line portion 118 may include first to fifth auxiliary lines 118a to 118e located in the weir portion 117. For example, each of the first to fifth auxiliary lines 118a to 118e may be referred to as a conductor, an electro-floating line, a conductive auxiliary line, or an electro-floating auxiliary line, but embodiments of the present invention are not limited thereto. An auxiliary line adjacent to the wiring 410 may include a first conductive structure overlapping with the discontinuity portion 115, the first conductive structure being electrically connected to multiple wirings 410. The auxiliary line may also include a second conductive structure on the first conductive structure, the second conductive structure overlapping with the discontinuity portion 115, the second conductive structure being electrically connected to multiple wirings 410.

[0368] Each of the first to fifth auxiliary lines 118a to 118e can be made to have the same material and structure as the pixel electrode PE located in the pixel region PA. For example, each of the first to fifth auxiliary lines 118a to 118e can be formed together with the second metal layer MLb of the auxiliary pattern portion 116.

[0369] Each of the first to fifth auxiliary lines 118a to 118e can be provided in each of the first to fourth discontinuous structures 115a to 115d of the discontinuity portion 115 to have a linear shape. For example, the first auxiliary line 118a can be provided in the first discontinuous structure 115a of the discontinuity portion 115. The second auxiliary line 118b can be provided in the second discontinuous structure 115b of the discontinuity portion 115. The third auxiliary line 118c can be provided in the third discontinuous structure 115c of the discontinuity portion 115. The fourth auxiliary line 118c can be provided in the fourth discontinuous structure 115d of the discontinuity portion 115.

[0370] According to an embodiment of the present invention, each of the first to fourth auxiliary lines 118a to 118d may be disposed on a passivation layer 111d that overlaps with each of the first to fourth discontinuous structures 115a to 115d of the discontinuity portion 115. For example, each of the first to fourth auxiliary lines 118a to 118d may be disposed between the first strip structure TS1 and the second strip structure TS2 of each of the first to fourth discontinuous structures 115a to 115d of the discontinuity portion 115, thereby enhancing the adhesion between the first strip structure TS1 and the second strip structure TS2.

[0371] Each of the first to fourth discontinuous structures 115a to 115d of the discontinuity portion 115 may include a first strip structure TS1 that overlaps with each of the first to fourth auxiliary lines 118a to 118d. For example, the third through-hole VH3 may sequentially pass through the passivation layer 111d and the interlayer insulating layer 111c used to implement the first strip structure TS1. For example, the third through-hole VH3 may be formed together with the first through-hole VH1 of the auxiliary pattern portion 116. Therefore, each of the first to fourth auxiliary lines 118a to 118d may be disposed on the passivation layer 111d of the first strip structure TS1 and may be inserted into the third through-hole VH3.

[0372] The fifth auxiliary line 118e can be provided in the weir region DA to have a linear shape. For example, the fifth auxiliary line 118e can be provided below the weir 117. For example, the fifth auxiliary line 118e can be provided between the weir 117 and the circuit layer 111.

[0373] According to an embodiment of the present invention, the fifth auxiliary line 118e may be provided on the passivation layer 111d that overlaps with the weir portion 117. For example, the fifth auxiliary line 118e may be provided between the passivation layer 111d and the first weir 117a of the weir portion 117, thereby enhancing the adhesion between the passivation layer 111d and the first weir 117a.

[0374] The weir region DA or weir portion 117 may include a fourth through-hole VH4 overlapping with the fifth auxiliary line 118e. For example, the fourth through-hole VH4 may sequentially pass through the passivation layer 111d and the interlayer insulation layer 111c located below the first weir 117a of the weir portion 117. For example, the fourth through-hole VH4 may be formed together with the second through-hole VH2 of the auxiliary pattern portion 116. Therefore, the fifth auxiliary line 118e may be provided on the passivation layer 111d located below the weir portion 117 and may be inserted into the fourth through-hole VH4.

[0375] As described above, similar to the light-emitting display device according to an embodiment of the present invention, the light-emitting display device according to another embodiment of the present invention may have an air-frame structure in which no frame area is provided, and may prevent or minimize the degradation of the light-emitting layer EL and / or the reduction in the reliability of the light-emitting layer EL due to the lateral transmission of moisture or humidity. Furthermore, the light-emitting display device according to another embodiment of the present invention may further include an auxiliary pattern portion 116 located between the contact patterns PCP, DCP, RCP, GCP and CCP and the wiring 410, thereby preventing electrical or physical contact defects between the contact patterns PCP, DCP, RCP, GCP and CCP and the wiring 410. Furthermore, the light-emitting display device according to another embodiment of the present invention may further include an auxiliary pattern portion 116 located between the first strip structure TS1 and the second strip structure TS2 of each of the first to fourth discontinuous structures 115a to 115d of the discontinuity portion 115, and disposed between the weir portion 117 and the circuit layer 111, thereby enhancing the adhesion between the first strip structure TS1 and the second strip structure TS2 and the adhesion between the weir portion 117 and the circuit layer 111.

[0376] Reference Figure 16B and 16C These pictures are Figure 16A Variations of the illustrated implementation. Figure 16A In some implementations, the wiring extends to contact holes CH (e.g., CH1, CH2, CH3, CH4, CH5). However, in some embodiments, the wiring may extend to only one of the contact holes CH. For example, Figure 16B This illustrates an embodiment of wiring extending to the first contact hole CH1. On the other hand, Figure 16CThis illustrates an implementation of wiring extending to the fifth contact hole CH5. Various combinations of wiring extending through the contact holes can be constructed based on circuit design and specific needs for a particular circuit arrangement. For example, in some circuit arrangements, the wiring may extend through two contact holes (e.g., CH2 and CH4). In other circuit arrangements, the wiring may extend through three contact holes (e.g., CH1, CH3, and CH4). For example, arranging the wiring to extend through all contact holes CH1-CH5 can have several technical advantages in ensuring the operation of the display device. For example, if some signal lines break due to various reasons (e.g., manufacturing errors, consumer errors, etc.), the display device can still maintain stable operation without experiencing an electrical break in the signal. Further advantages include a reduced contact resistance coefficient within the display.

[0377] Some via Figure 16C The advantage of the weir portion 117 in making contact is that the weir portion 117 is relatively larger and higher than the discontinuity portion 115 adjacent to it. Therefore, it is relatively easier to establish an electrical connection via the discontinuity portion 115 by extending the wiring to electrically connect to the contact pattern portion via the weir portion 117. Various wiring connections can be considered based on a trade-off of technical advantages. For example... Figure 16B As shown, extending the wiring through the contact hole furthest from the active area, such as the first contact hole CH1, has technical advantages from a resistance perspective and also reduces the amount of material used in the wiring. (Refer to...) Figure 14 , Figure 14 Some signal lines are shown to be electrically disconnected, as illustrated in internal area B4. Depending on the specific circuit layout required for connecting the specific lines (e.g., high-potential voltage EVDD line, reference voltage line, data line, low-potential voltage EVSS line, etc.), some signal lines may be disconnected, and electrical connections for other signal lines may be established using the required contact holes.

[0378] Those skilled in the art will recognize the expected technical advantages of these connections, arrangements, and quantities of wiring based on through-hole extensions.

[0379] Figure 18 This is a diagram illustrating the connection structure between the pixel driving line, the wiring portion, and the auxiliary line portion according to another embodiment of the present invention. Figure 19 It is along Figure 18 The cross-sectional view shown is taken from line IV-IV'. Figure 20 It is along Figure 18 The cross-sectional view shown is taken by line V-V'. Figure 21 It is along Figure 18 The cross-sectional view shown is taken from line VI-VI'. Figure 22 It is along Figure 18 The cross-sectional view taken by line VII-VII' shown. Figures 18 to 22It shows that Figures 13 to 17 The illustrated auxiliary line section is configured as a signal supply line in an embodiment. In the description... Figures 18 to 22 In this context, only the auxiliary lines and related components will be described below. Other components are derived from... Figures 13 to 17 The same reference markers refer to the same things, and repeated descriptions are omitted.

[0380] Reference Figure 18 According to another embodiment of the present invention, the auxiliary line portion 118 may include first to fifth auxiliary line portions 118a to 118e provided in the discontinuity portion 115 and the weir portion 117.

[0381] The first auxiliary line 118a may be formed on the first substrate 100 in the form of a closed loop line. For example, the first intermediate pattern of the auxiliary pattern portion 116 located on one side of the peripheral portion of the first substrate 100 and the first auxiliary line 118a located on the peripheral portion of the auxiliary line portion 118 other than one side of the peripheral portion of the first substrate 100 may be electrically connected to each other to form a closed loop line. For example, the first auxiliary line 118a may be referred to as a first closed loop auxiliary line or a first conductive closed loop line, but the embodiments of the present invention are not limited thereto.

[0382] The first auxiliary line 118a located on one side of the outer periphery of the first substrate 100 may be configured to intersect the contact pattern portion 110 in the first direction X. For example, the first auxiliary line 118a located on one side of the outer periphery of the first substrate 100 may be provided in the first discontinuity structure 115a located between the contact pattern portion 110 and the wiring portion 400.

[0383] The first auxiliary line 118a can be electrically connected to multiple pixel common voltage lines CVL located on one side of the outer periphery of the first substrate 100. Furthermore, the first auxiliary line 118a can be electrically (or collectively) connected to only a few pixel common voltage lines 419 among the multiple lines 411, 413, 415, 417, and 419 located in the wiring section 400. For example, the first auxiliary line 118a can be electrically (or collectively) connected to the first portion 410a of each pixel common voltage line 419 via at least one first wiring contact hole CH1.

[0384] Furthermore, the first auxiliary line 118a may be electrically connected to each of the multiple pixel common voltage lines CVL at the other peripheral portion of the first substrate 100, which is parallel to one peripheral portion of the first substrate 100. For example, the first auxiliary line 118a may be electrically (or jointly) connected to the other side of each pixel common voltage line CVL via a fifth via VH5 located at the other peripheral portion of the first substrate 100.

[0385] The first auxiliary line 118a can be disposed at the outermost peripheral portion of the first substrate 100 and can be maintained at the same potential as the pixel common voltage line CVL, thus cutting off static electricity flowing into the display portion AA from the outside for the first time, thereby preventing defects caused by static electricity. For example, the first auxiliary line 118a can discharge static electricity flowing in from the outside to the pixel common voltage wiring 419 and / or the pixel common voltage line CVL, thereby preventing defects caused by static electricity.

[0386] Each of the second auxiliary line 118b and the third auxiliary line 118c may be disposed on the outer peripheral portion of the first substrate 100, excluding the outer peripheral portion on one side. Each of the second auxiliary line 118b and the third auxiliary line 118c may be electrically connected to the first and last pixel driving power lines PL among the plurality of pixel driving power lines PL at one side (or one side corner) and the other side (or the other side corner) of the outer peripheral portion on one side of the first substrate 100. Furthermore, each of the second auxiliary line 118b and the third auxiliary line 118c may be electrically connected to the first portion 410a of each of the first and last pixel driving unit wirings 411 among the plurality of pixel driving power wirings 411 via at least one wiring contact hole CH2 and CH3.

[0387] Furthermore, each of the second auxiliary line 118b and the third auxiliary line 118c can be electrically connected to each of the plurality of pixel driving power lines PL at the peripheral portion on the other side of the first substrate 100. For example, each of the second auxiliary line 118b and the third auxiliary line 118c can be electrically (or jointly) connected to the other side of each of the pixel driving power lines PL via a fifth via VH5 located at the peripheral portion on the other side of the first substrate 100.

[0388] Each of the second auxiliary line 118b and the third auxiliary line 118c can maintain the same potential as the pixel drive power line PL. Each of the second auxiliary line 118b and the third auxiliary line 118c can be electrically connected to the pixel drive power line PL, thereby reducing the voltage drop (IR drop) of the pixel drive power supply caused by the line resistance of each pixel drive power line PL.

[0389] The fourth auxiliary line 118d can be formed on the first substrate 100 in the form of a closed loop line. For example, the first intermediate pattern of the auxiliary pattern portion 116 located on one side of the outer periphery of the first substrate 100 and the fourth auxiliary line 118d located on the outer periphery of the auxiliary line portion 118 other than one side of the outer periphery of the first substrate 100 can be electrically connected to each other to form a closed loop line. For example, the fourth auxiliary line 118d can be referred to as a second closed loop auxiliary line or a second conductive closed loop line, but the embodiments of the present invention are not limited thereto.

[0390] The fourth auxiliary line 118d located on one side of the outer periphery of the first substrate 100 can be configured to intersect the contact pattern portion 110 in the first direction X. For example, the fourth auxiliary line 118d located on one side of the outer periphery of the first substrate 100 can be provided in the fourth discontinuity structure 115d located between the contact pattern portion 110 and the wiring portion 400.

[0391] The fourth auxiliary line 118d can be electrically connected to multiple pixel common voltage lines CVL located on one side of the outer periphery of the first substrate 100. Furthermore, the fourth auxiliary line 118d can be electrically connected to the pixel-only common voltage line 419 among the multiple lines 411, 413, 415, 417, and 419 located in the wiring section 400. For example, the fourth auxiliary line 118d can be electrically (or collectively) connected to the first portion 410a of each pixel common voltage line 419 via at least one fourth wiring contact hole CH4.

[0392] Furthermore, the fourth auxiliary line 118d can be electrically connected to each of the multiple pixel common voltage lines CVL at the other peripheral portion of the first substrate 100, which is parallel to one peripheral portion of the first substrate 100. For example, the fourth auxiliary line 118d can be electrically (or jointly) connected to the other side of each pixel common voltage line CVL via a fifth via VH5 located at the other peripheral portion of the first substrate 100.

[0393] The fourth auxiliary line 118d can be disposed within the inner portion of the weir 117 and can maintain the same potential as the pixel common voltage line CVL, thus assisting in cutting off static electricity flowing into the display portion AA from the outside, thereby preventing defects caused by static electricity. For example, the fourth auxiliary line 118d can discharge static electricity flowing in from the outside to the pixel common voltage wiring 419 and / or the pixel common voltage line CVL, thereby preventing defects caused by static electricity.

[0394] The fifth auxiliary line 118e may be disposed on the outer peripheral portion of the first substrate 100, excluding the outer peripheral portion on one side. The fifth auxiliary line 118e may be electrically connected to the first and last pixel driving power lines PL among the plurality of pixel driving power lines PL at one side (or one side corner) and the other side (or the other side corner) of the outer peripheral portion on one side of the first substrate 100. In addition, the fifth auxiliary line 118e may be electrically connected to the first portion 410a of each of the first and last pixel driving power lines 411 among the plurality of pixel driving power lines 411 via at least one wiring contact hole CH5.

[0395] Furthermore, the fifth auxiliary line 118e may be electrically connected to each of the multiple pixel driving power lines PL at the peripheral portion on the other side of the first substrate 100. For example, the fifth auxiliary line 118e may be electrically (or collectively) connected to the other side of each pixel driving power line PL via a sixth via VH6 located at the peripheral portion on the other side of the first substrate 100.

[0396] The fifth auxiliary line 118e can maintain the same potential as the pixel drive power line PL. The fifth auxiliary line 118e can be electrically connected to the pixel drive power line PL, thereby reducing the voltage drop (IR drop) of the pixel drive power supply caused by the line resistance of each line of the pixel drive power line PL.

[0397] Reference Figure 18 and 19 In another embodiment of the present invention, the first auxiliary line 118a may be electrically connected to the first portion 410a of each pixel common voltage wiring 419 via at least one first wiring contact hole CH1 located on the pixel common voltage contact pattern CCP disposed in the contact pattern portion 110. Furthermore, the first auxiliary line 118a may be electrically connected to the pixel common voltage contact pattern CCP via a first through-hole VH1 formed in the buffer layer 111a on the pixel common voltage contact pattern CCP. Additionally, the first auxiliary line 118a may be electrically connected to the pixel common voltage contact pattern CCP via a metal layer MLA located in the first through-hole VH1 of the buffer layer 111a.

[0398] In another embodiment of the present invention, the fourth auxiliary line 118d may be electrically connected to the first portion 410a of each pixel common voltage wiring 419 of the wiring portion 400 via at least one fourth wiring contact hole CH4 located on the pixel common voltage contact pattern CCP in the contact pattern portion 110. Furthermore, the fourth auxiliary line 118d may be electrically connected to the pixel common voltage contact pattern CCP via a first through hole CH1 formed in the buffer layer 111a on the pixel common voltage contact pattern CCP. Additionally, the fourth auxiliary line 118d may be electrically connected to the pixel common voltage contact pattern CCP via a metal layer MLA located in the first through hole VH1 of the buffer layer 111a.

[0399] The first portion 410a of each pixel common voltage wiring 419 disposed in the wiring section 400 can be electrically (or jointly) connected to the first auxiliary line 118a via at least one first wiring contact hole CH1, and electrically (or jointly) connected to the fourth auxiliary line 118d via at least one fourth wiring contact hole CH4, and can be electrically (or jointly) connected to the pixel common voltage contact pattern CCP via the first auxiliary line 118a and the fourth auxiliary line 118d. Furthermore, the first portion 410a of each pixel common voltage wiring 419 in the wiring section 400 can be electrically (or jointly) connected to the second, third, and fifth intermediate patterns 116b, 116c, and 116e via all of the at least one second wiring contact hole CH2, at least one third wiring contact hole CH3, and at least one fourth wiring contact hole CH4, and can be electrically (or jointly) connected to the pixel common voltage contact pattern CCP via the second, third, and fifth intermediate patterns 116b, 116c, and 116e.

[0400] Therefore, in a light-emitting display device according to another embodiment of the present invention, a uniform pixel common voltage can be provided to the pixel common voltage line CVL located in the display portion AA of the first substrate 100, thereby improving the uniformity of the pixel common voltage. Furthermore, in a light-emitting display device according to another embodiment of the present invention, since the first and fourth auxiliary lines 118a and 118d, which have a closed-loop configuration on the first substrate 100, are electrically connected to the pixel common voltage line CVL, defects caused by static electricity flowing in from the outside can be prevented or minimized.

[0401] Reference Figure 18 and 20 In another embodiment of the invention, the first auxiliary line 118a may be electrically (or jointly) connected to the other side of each pixel common voltage line CVL via at least one fifth via VH5 located at the other peripheral portion of the first substrate 100. At least one fifth via VH5 may be formed in a buffer layer 111a in the overlapping region between the other side of each pixel common voltage line CVL and the first auxiliary line 118a. At least one fifth via VH5 may be formed together with at least one first via VH1. Furthermore, the first auxiliary line 118a may be electrically (or jointly) connected to the other side of each pixel common voltage line CVL via a metal layer MLA located in the fifth via VH5 of the buffer layer 111a.

[0402] The fourth auxiliary line 118d can be electrically (or collectively) connected to the other side of each pixel common voltage line CVL via at least one fifth via VH5 located on the other peripheral portion of the first substrate 100. At least one fifth via VH5 can be formed in a buffer layer 111a located in the overlapping region between the other side of each pixel common voltage line CVL and the fourth auxiliary line 118d. Furthermore, the fourth auxiliary line 118d can be electrically (or collectively) connected to the other side of each pixel common voltage line CVL via a metal layer MLA located in the fifth via VH5 of the buffer layer 111a.

[0403] A light-emitting display device according to another embodiment of the present invention may further include a plurality of first auxiliary contact patterns (SCCPs). For example, the first auxiliary contact pattern (SCCP) may be referred to as a pixel common voltage auxiliary contact pattern, but the embodiments of the present invention are not limited thereto.

[0404] According to an embodiment of the present invention, the first auxiliary contact pattern SCCP may be disposed on the same layer as the pixel common voltage line CVL, and may extend (or extend) from the end of each pixel common voltage line CVL located on the other peripheral portion of the substrate 100 to the outer surface OS of the substrate 100, so as to have a relatively wide width. According to another embodiment of the present invention, each first auxiliary contact pattern SCCP may be disposed below the pixel common voltage line CVL, overlapping with the end of each pixel common voltage line CVL located on the other peripheral portion of the substrate 100 and having a relatively wide width, and may be electrically connected to the end of each pixel common voltage line CVL via an internal contact hole.

[0405] The first auxiliary line 118a may be electrically (or jointly) connected to the first auxiliary contact pattern SCCP via at least one fifth via VH5 located on the other peripheral portion of the first substrate 100. Furthermore, the first auxiliary line 118a may be electrically (or jointly) connected to the first auxiliary contact pattern SCCP via a metal layer MLA located in the fifth via VH5 of the buffer layer 111a.

[0406] The fourth auxiliary line 118d can be electrically (or jointly) connected to the first auxiliary contact pattern SCCP via at least one fifth via VH5 located on the other peripheral portion of the first substrate 100. Furthermore, the fourth auxiliary line 118d can be electrically (or jointly) connected to the first auxiliary contact pattern SCCP via a metal layer MLA located in the fifth via VH5 of the buffer layer 111a.

[0407] Therefore, in a light-emitting display device according to another embodiment of the present invention, the pixel common voltage can be simultaneously provided to one side and the other side of each pixel common voltage line CVL via first and fourth auxiliary lines 118a and 118d having closed-loop line form, thereby further enhancing the uniformity of the pixel common voltage. Furthermore, in a light-emitting display device according to another embodiment of the present invention, since the first and fourth auxiliary lines 118a and 118d having closed-loop line form on the first substrate 100 are electrically connected to one side and the other side of the pixel common voltage line CVL, defects caused by static electricity flowing in from the outside can be prevented or minimized.

[0408] Reference Figure 18 and 21 In another embodiment of the present invention, the second auxiliary line 118b may be electrically connected to the first portion 410a of each of the first and last pixel driving power wirings 411 of the wiring portion 400 via at least one second wiring contact hole CH2 located on the first and last pixel driving power contact patterns PCP in the contact pattern portion 110. Furthermore, the second auxiliary line 118b may be electrically connected to the first and last pixel driving power contact patterns PCP via a first through-hole VH1 formed in the buffer layer 111a on the first and last pixel driving power contact patterns PCP. Additionally, the second auxiliary line 118b may be electrically connected to the first and last pixel driving power contact patterns PCP via a metal layer MLA disposed in the first through-hole VH1 of the buffer layer 111a.

[0409] The third auxiliary line 118c can be electrically connected to the first portion 410a of each of the first and last pixel driving power wirings 411 of the wiring section 400 via at least one third wiring contact hole CH3 located on the first and last pixel driving power contact patterns PCP in the contact pattern section 110. Furthermore, the third auxiliary line 118c can be electrically connected to the first and last pixel driving power contact patterns PCP via a first through-hole VH1 formed in the buffer layer 111a on the first and last pixel driving power contact patterns PCP. Additionally, the third auxiliary line 118c can be electrically connected to the first and last pixel driving power contact patterns PCP via a metal layer MLA disposed in the first through-hole VH1 of the buffer layer 111a.

[0410] The fifth auxiliary line 118e can be electrically connected to the first portion 410a of each of the first and last pixel driving power contact patterns 411 of the wiring section 400 via at least one fifth wiring contact hole CH5 located on the first and last pixel driving power contact patterns PCP in the contact pattern section 110. Furthermore, the fifth auxiliary line 118e can be electrically connected to the first and last pixel driving power contact patterns PCP via a first through-hole VH1 formed in the buffer layer 111a on the first and last pixel driving power contact patterns PCP. Additionally, the fifth auxiliary line 118e can be electrically connected to the first and last pixel driving power contact patterns PCP via a metal layer MLA disposed in the first through-hole VH1 of the buffer layer 111a.

[0411] Therefore, in a light-emitting display device according to another embodiment of the present invention, the first and last pixel driving voltage lines PL in the display portion AA of the first substrate 100 can be electrically connected to each of the second, third and fifth auxiliary lines 118b, 118c and 118e, thereby reducing the voltage drop (IR drop) of the pixel driving power supply due to the line resistance of each pixel driving power supply line PL.

[0412] Reference Figure 18 and 22 In another embodiment of the invention, the second auxiliary line 118b may be electrically (or collectively) connected to the other side of each pixel driving power line PL via at least one fifth via VH5 located at the other peripheral portion of the first substrate 100. At least one fifth via VH5 may be formed in a buffer layer 111a in the overlapping region between the other side of each pixel driving power line PL and the second auxiliary line 118b. Furthermore, the second auxiliary line 118b may be electrically (or collectively) connected to the other side of each pixel driving power line PL via a metal layer MLA located in the fifth via VH5 of the buffer layer 111a.

[0413] The third auxiliary line 118c can be electrically (or collectively) connected to the other side of each pixel driving power line PL via at least one fifth via VH5 located on the other peripheral portion of the first substrate 100. At least one fifth via VH5 can be formed in a buffer layer 111a in the overlapping region between the other side of each pixel driving power line PL and the fourth auxiliary line 118d. Furthermore, the third auxiliary line 118c can be electrically (or collectively) connected to the other side of each pixel driving power line PL via a metal layer MLA located in the fifth via VH5 of the buffer layer 111a.

[0414] The fifth auxiliary line 118e can be electrically (or collectively) connected to the other side of each pixel driving power line PL via at least one sixth via VH6 located on the other peripheral portion of the first substrate 100. At least one sixth via VH6 can be formed in a buffer layer 111a in the overlapping region between the other side of each pixel driving power line PL and the fourth auxiliary line 118d. At least one sixth via VH6 can be formed together with at least one fifth via VH5. Furthermore, the fifth auxiliary line 118e can be electrically (or collectively) connected to the other side of each pixel driving power line PL via a metal layer MLA located in the sixth via VH6 of the buffer layer 111a.

[0415] A light-emitting display device according to another embodiment of the present invention may further include a plurality of second auxiliary contact patterns SPCP. The second auxiliary contact patterns SPCP may be referred to as pixel driving power supply auxiliary contact patterns.

[0416] According to an embodiment of the present invention, the second auxiliary contact pattern SPCP can be disposed on the same layer as the pixel driving power line PL, and can extend (or extend) from the end of each pixel driving power line PL located on the other peripheral portion of the substrate 100 to the outer surface OS of the substrate 100, so as to have a relatively wide width. According to another embodiment of the present invention, each second auxiliary contact pattern SPCP can be disposed below the pixel driving power line PL, overlapping with the end of each pixel driving power line PL located on the other peripheral portion of the substrate 100 and having a relatively wide width, and can be electrically connected to the end of each pixel driving power line PL via an internal contact hole.

[0417] The second auxiliary line 118b can be electrically (or jointly) connected to the second auxiliary contact pattern SPCP via at least one fifth via VH5 located on the other peripheral portion of the first substrate 100. Furthermore, the second auxiliary line 118b can be electrically (or jointly) connected to the second auxiliary contact pattern SPCP via a metal layer MLA located in the fifth via VH5 of the buffer layer 111a.

[0418] The third auxiliary line 118c can be electrically (or jointly) connected to the second auxiliary contact pattern SPCP via at least one fifth via VH5 located on the other peripheral portion of the first substrate 100. Furthermore, the third auxiliary line 118c can be electrically (or jointly) connected to the second auxiliary contact pattern SPCP via a metal layer MLA located in the fifth via VH5 of the buffer layer 111a.

[0419] The fifth auxiliary line 118e can be electrically (or jointly) connected to the second auxiliary contact pattern SPCP via at least one sixth via VH6 located on the other peripheral portion of the first substrate 100. Furthermore, the fifth auxiliary line 118e can be electrically (or jointly) connected to the second auxiliary contact pattern SPCP via a metal layer MLA located in the sixth via VH6 of the buffer layer 111a.

[0420] Therefore, in a light-emitting display device according to another embodiment of the present invention, the pixel driving power supply can be provided to one side and the other side of each pixel driving power supply line PL simultaneously, thereby reducing the voltage drop (IR drop) of the pixel driving power supply caused by the line resistance of each pixel driving power supply line PL, and further enhancing the uniformity of the pixel driving power supply.

[0421] In addition, Figures 18 to 22 In this context, the third auxiliary line 118c can be implemented as not being electrically connected to the pixel drive power line PL and forming a closed loop like the first and fourth auxiliary lines 118a and 118d, but instead being electrically connected to the pixel common voltage line CVL.

[0422] Figure 23 This is a diagram illustrating the connection structure between a pixel driving line, a wiring portion, and an auxiliary line portion according to another embodiment of the present invention, showing how modifications can be made to achieve this connection. Figures 18 to 22 The implementation method is shown using the fifth auxiliary line. (In the description...) Figure 23 At that time, only the fifth auxiliary line and its related components will be described below; other components will be described by [other components]. Figures 18 to 22 The same reference marker is used for reference, and its repeated description is omitted.

[0423] Reference Figure 23 In another embodiment of the invention, the fifth auxiliary line 118e can be used as a reference voltage supply line to provide a reference voltage to a plurality of reference voltage lines RL.

[0424] According to an embodiment of the present invention, the fifth auxiliary line 118e may be formed as electrically connected to the first and last reference voltage contact pattern RCP among the plurality of reference contact patterns RCP located in the contact pattern portion 110.

[0425] The fifth auxiliary line 118e can be electrically connected via at least one fifth wiring contact hole CH5 to a first portion of each of the first and last reference voltage wirings 415. Furthermore, the fifth auxiliary line 118e can be electrically connected to the first and last reference voltage contact patterns RCP via a first via in a buffer layer 111a located on the first and last reference voltage contact patterns RCP. Additionally, the fifth auxiliary line 118e can be electrically connected to the first and last reference voltage contact patterns RCP via a metal layer located in the first via in the buffer layer 111a.

[0426] Furthermore, the fifth auxiliary line 118e may be electrically (or jointly) connected to the reference voltage line RL at the peripheral portion on the other side of the first substrate 100. For example, the fifth auxiliary line 118e may be electrically (or jointly) connected to the other side of each reference voltage line RL via a sixth via VH6 located at the peripheral portion on the other side of the first substrate 100.

[0427] The fifth auxiliary line 118e can maintain the same potential as each reference voltage line RL. The fifth auxiliary line 118e can be electrically connected to the reference voltage line RL, thus reducing the voltage drop (IR drop) of the reference voltage caused by the line resistance of each reference voltage line RL.

[0428] A light-emitting display device according to another embodiment of the present invention may further include a plurality of third auxiliary contact patterns SRCP. For example, the third auxiliary contact pattern SRCP may be referred to as a reference voltage auxiliary contact pattern, but the embodiments of the present invention are not limited thereto.

[0429] According to an embodiment of the present invention, the third auxiliary contact pattern SRCP may be disposed on the same layer as the reference voltage line RL, and may extend (or extend) from the end of each reference voltage line RL located on the other peripheral portion of the substrate 100 to the outer surface OS of the substrate 100, so as to have a relatively wide width. According to another embodiment of the present invention, each third auxiliary contact pattern SRCP may be disposed below the reference voltage line RL to overlap with the end of each reference voltage line RL located on the other peripheral portion of the substrate 100 and to have a relatively wide width, and may be electrically connected to the end of each reference voltage line RL via an internal contact hole.

[0430] The fifth auxiliary line 118e can be electrically (or jointly) connected to the third auxiliary contact pattern SRCP via at least one sixth via VH6 located on the other peripheral portion of the first substrate 100. Furthermore, the fifth auxiliary line 118e can be electrically (or jointly) connected to the third auxiliary contact pattern SRCP via a metal layer MLA located in the sixth via VH6 of the buffer layer 111a.

[0431] Therefore, in a light-emitting display device according to another embodiment of the present invention, the reference voltage can be provided to one side and the other side of each reference voltage line RL simultaneously, thereby reducing the voltage drop (IR drop) of the reference voltage caused by the line resistance of each reference voltage line RL, and further enhancing the uniformity of the reference voltage.

[0432] Figure 24 This is a diagram illustrating the connection structure between the pixel driving line, the wiring portion, and the auxiliary line portion according to another embodiment of the present invention. 25 is... Figure 24 An enlarged view of region B6 shown. Figure 26 It is along Figure 25 The cross-sectional view taken by line VIII-VIII' is shown. Figures 24 to 26 It shows Figures 13 to 17 The illustrated auxiliary line section is configured as a pixel common voltage supply line in an embodiment. In the description... Figures 24 to 26 In this case, only the auxiliary lines and related components will be described below; other components will be described by [other components]. Figures 13 to 17 The same reference marker is used for reference, and its repeated description is omitted.

[0433] Reference Figures 24 to 26 According to another embodiment of the present invention, the light-emitting display device may further include at least one auxiliary connection line SCL located on the first substrate 100.

[0434] At least one auxiliary connecting line SCL may be configured to be parallel to the second direction Y and may be configured to intersect with the auxiliary line portion 118. For example, at least one auxiliary connecting line SCL may be configured to be parallel to the second direction Y and may be configured to intersect with the first to fifth auxiliary lines 118a to 118e of the auxiliary line portion 118.

[0435] At least one auxiliary connection line SCL can be set on the same layer as the pixel common voltage line CVL.

[0436] At least one auxiliary connection line SCL may be electrically (or collectively) connected to each of the first to fifth auxiliary lines 118a to 118e of the auxiliary line section 118.

[0437] At least one auxiliary connection line SCL may be electrically (or collectively) connected to each of the first to fourth auxiliary lines 118a to 118d via at least one fifth via CH5. At least one fifth via VH5 may be formed in a buffer layer 111a located in the overlapping region between the at least one auxiliary connection line SCL and each of the first to fourth auxiliary lines 118a to 118d. At least one fifth via VH5 may be formed together with at least one first via VH1. Furthermore, at least one auxiliary connection line SCL may be electrically (or collectively) connected to each of the first to fourth auxiliary lines 118a to 118d via a metal layer MLA disposed in the fifth via VH5 of the buffer layer 111a.

[0438] At least one auxiliary connection line SCL may be electrically (or jointly) connected to the fifth auxiliary line 118e via at least one sixth via CH6. At least one sixth via VH6 may be formed together with at least one fifth via VH5. In addition, at least one auxiliary connection line SCL may be electrically (or jointly) connected to the fifth auxiliary line 118e via a metal layer MLA disposed in the sixth via VH6 of the buffer layer 111a.

[0439] In another embodiment of the present invention, the fourth auxiliary line 118d may be formed on the first substrate 100 in the form of a closed loop. For example, the fourth intermediate pattern of the auxiliary pattern portion 116 located on one side of the peripheral portion of the first substrate 100 and the fourth auxiliary line 118d located on the peripheral portion of the auxiliary line portion 118 other than one side of the peripheral portion of the first substrate 100 may be electrically connected to each other to form a closed loop. The fourth auxiliary line 118d may be as described above. Figure 18 and 19 The fourth auxiliary line 118d is described in essentially the same way, so its repeated description is omitted. For example, in this embodiment, the fourth auxiliary line 118d may be referred to as a closed-loop auxiliary line or a conductive closed-loop line, but the embodiments of the present invention are not limited thereto.

[0440] Each of the first to fifth auxiliary lines 118a to 118e of the auxiliary line section 118 can maintain the same potential as the pixel common voltage line CVL, thus cutting off static electricity flowing into the display section AA from the outside, thereby preventing defects caused by static electricity.

[0441] In another embodiment of the invention, each of the first to fifth auxiliary lines 118a to 118e of the auxiliary line portion 119 may be electrically (or collectively) connected to the other side of each pixel common voltage line CVL at the other peripheral portion of the first substrate 100.

[0442] Each of the first to fourth auxiliary lines 118a to 118d can be electrically (or collectively) connected to the other side of each pixel common voltage line CVL via at least one fifth via VH5 located at the peripheral portion on the other side of the first substrate 100. At least one fifth via VH5 can be formed in a buffer layer 111a located in the overlapping region between the other side of each pixel common voltage line CVL and each of the first to fourth auxiliary lines 118a to 118d. Furthermore, each of the first to fourth auxiliary lines 118a to 118d can be electrically (or collectively) connected to the other side of each pixel common voltage line CVL via a metal layer located in the fifth via VH5 of the buffer layer 111a.

[0443] The fifth auxiliary line 118e can be electrically (or collectively) connected to the other side of each pixel common voltage line CVL via at least one sixth via VH6 located on the other peripheral portion of the first substrate 100. At least one sixth via VH6 can be formed in a buffer layer 111a in the overlapping region between the other side of each pixel common voltage line CVL and the fifth auxiliary line 118e. Furthermore, the fifth auxiliary line 118e can be electrically (or collectively) connected to the other side of each pixel common voltage line CVL via a metal layer in the sixth via VH6 located in the buffer layer 111a.

[0444] Therefore, in a light-emitting display device according to another embodiment of the present invention, the pixel common voltage can be simultaneously provided to one side and the other side of each pixel common voltage line CVL via the auxiliary line portion 118, thereby further enhancing the uniformity of the pixel common voltage. Furthermore, a light-emitting display device according to another embodiment of the present invention may include a fifth auxiliary line 118e having a closed-loop line form on the first substrate 100, and first and fourth auxiliary lines 118a and 118d electrically connected to the fifth auxiliary line 118e, thereby better preventing or further minimizing defects caused by static electricity flowing in from the outside.

[0445] Figure 27 This is a diagram illustrating a light-emitting display device according to another embodiment of the present invention. Figure 28 It is along Figure 27 The cross-sectional view shown is taken from line IX-IX'. Figure 29 yes Figure 28 An enlarged view of region B7 is shown. Region B7 includes the peripheral portion of the substrate that is also adjacent to the outer surface (or outermost surface) of the substrate. Figure 28 The peripheral portion is shown to be adjacent to the first outer surface OS1a of the first substrate 100. Figures 27 to 29 It shows how to modify Figures 9 to 12 The embodiment shown is implemented using a weir portion in the light-emitting display device. In the description... Figures 27 to 29 At that time, only the weir and its related components will be described below; other components will be described by [other entities]. Figures 9 to 12 The same reference marker is used for reference, and its repeated description is omitted.

[0446] Reference Figures 27 to 29 In another embodiment of the light-emitting display device according to the present invention, the weir 117 may include a first weir 117-1 and a second weir 117-2 arranged in parallel.

[0447] The first dam 117-1 may be disposed on the circuit layer 111 to have a closed loop in the second region of the first substrate 100. According to an embodiment of the present invention, the first dam 117-1 may be disposed on the buffer layer 111a of the circuit layer 111. The first dam 117-1 can initially prevent the diffusion or overflow of the encapsulation layer 119. Furthermore, the first dam 117-1 can disconnect (or isolate) the light-emitting device layer 113.

[0448] The second weir 117-2 may be disposed on the circuit layer 111 to have a closed loop around the first weir 117-1 in a second region of the first substrate 100. According to an embodiment of the present invention, the second weir 117-2 may be disposed on the buffer layer 111a of the circuit layer 111. The second weir 117-2 may help prevent the diffusion or overflow of the encapsulation layer 119. Furthermore, the second weir 117-2 may additionally disconnect (or isolate) the light-emitting device layer 113.

[0449] Each of the first weir section 117-1 and the second weir section 117-2 according to embodiments of the present invention may include a weir strip structure DTS, a first weir 117a and a second weir 117b.

[0450] The weir-shaped strip structure DTS can be disposed in the circuit layer 111. According to an embodiment of the present invention, the weir-shaped strip structure DTS can be implemented as a stacked structure of an interlayer insulating layer 111c and a passivation layer 111d located in the weir region DA of the first substrate 100. The weir-shaped strip structure DTS can be formed by a patterning process performed on the interlayer insulating layer 111c and the passivation layer 111d.

[0451] The side surface of the weir strip structure DTS according to an embodiment of the present invention can be implemented as an inclined structure or a conical structure. The bottom surface of the weir strip structure DTS can directly contact the top surface (or surface) of the buffer layer 111a. The top surface of the weir strip structure DTS can be disposed on the bottom surface of the weir strip structure DTS and can have a width narrower than the bottom surface of the weir strip structure DTS. The side surface of the weir strip structure DTS can be formed to be inclined between the top surface and the bottom surface of the weir strip structure DTS. In the weir strip structure DTS, the included angle between the bottom surface and the side surface can be an acute angle, and the included angle between the top surface and the side surface can be an obtuse angle. For example, the cross-sectional structure of the cross-section of the weir strip structure DTS taken along the width direction can have a trapezoidal shape in which the top surface is narrower than the bottom surface.

[0452] According to another embodiment of the present invention, when the interlayer insulating layer 111c is not disposed at the peripheral portion of the first substrate 100, the weir-shaped structure DTS can be realized using only the passivation layer 111d. The weir-shaped structure DTS can be formed by a patterning process performed on the passivation layer 111d located in the second region of the first substrate 100.

[0453] A first weir (or lower weir portion) 117a may be provided on the weir strip structure DTS. The first weir 117a may have a width wider than the top surface of the weir strip structure DTS. The first weir 117a may have a width greater than or equal to the width of the bottom surface of the weir strip structure DTS. For example, the side surface of the first weir 117a may be an inclined structure or a conical structure. For example, the cross-sectional structure of the first weir 117a, taken along its width direction, may have the same trapezoidal shape as the weir strip structure DTS. Each of the outer periphery portions on one side and the other side of the first weir 117a may protrude beyond the outer surface of the side surface of the weir strip structure DTS, relative to the width direction.

[0454] According to an embodiment of the present invention, the side surface of the weir strip structure DTS may have an undercut structure relative to the first weir 117a. For example, each of the first weir portion 117-1 and the second weir portion 117-2 may include a boundary portion located between the weir strip structure DTS and the first weir 117a or an undercut region located on the upper side surface of the weir strip structure DTS. The first weir 117a may protrude beyond the side surface of the weir strip structure DTS based on the undercut structure of the weir strip structure DTS, thus covering the side surface of the weir strip structure DTS. Therefore, the first weir 117a may have an eaves structure relative to the weir strip structure DTS.

[0455] According to an embodiment of the present invention, the first weir 117a may have the same height (or thickness) as the planarization layer 112, or it may have a higher height than the planarization layer 112. For example, the height (or thickness) of the first weir 117a may be twice the height (or thickness) of the planarization layer 112.

[0456] A second weir (or upper weir) 117b may be disposed on the first weir 117a. According to embodiments of the present invention, the second weir 117b may comprise the same material as the dike portion 114 and may be stacked on the first weir 117a. For example, the side surface of the second weir 117b may be implemented as an inclined structure or a conical structure. For example, the cross-sectional structure of the cross-section of the second weir 117b taken along the width direction may have the same trapezoidal shape as the first weir 117a.

[0457] According to an embodiment of the present invention, each of the first weir 117-1 and the second weir 117-2 can disconnect (or isolate) the light-emitting layer EL of the light-emitting device layer 113, and can disconnect (or isolate) the light-emitting layer EL and the common electrode CE. For example, the light-emitting layer EL formed (or deposited) on the weir 117 can be automatically disconnected (or isolated) during the deposition process by the undercut structure (or eaves structure) of each of the first weir 117-1 and the second weir 117-2, without the need for a separate cutting process. Therefore, the light-emitting layer EL disposed on the first substrate 100 can be disconnected (or isolated) twice in the weir region DA of the first substrate 100, and may include two discontinuous regions (or isolated regions). For example, the deposition material of the light-emitting layer EL may be linear, so it will not be deposited on the side surface of the weir strip structure DTS covered by the first weir 117a based on the undercut structure (or eaves structure) of each of the first weir 117-1 and the second weir 117-2. Therefore, the light-emitting layer EL formed (or deposited) on the first weir 117-1 and the second weir 117-2 can be disconnected (or isolated) between the weir strip structure DTS and the first weir 117a. Thus, the light-emitting layer EL can be automatically disconnected (or isolated) through the first weir 117-1 and the second weir 117-2 during the deposition process, thereby eliminating the need for a separate patterning process to disconnect (or isolate) the light-emitting layer EL located at the peripheral portion of the first substrate 100 to prevent lateral transport of moisture or humidity.

[0458] Alternatively, the common electrode CE disposed on the light-emitting layer EL can be automatically disconnected (or isolated) through the first weir 117-1 and the second weir 117-2 of the weir 117 during the execution of a deposition-based deposition process, or it can be deposited on the side surface of the weir strip structure DTS covered by the first weir 117a and can be formed continuously without discontinuous areas.

[0459] In a light-emitting display device according to another embodiment of the present invention, the discontinuity 115 may be implemented to disconnect (or isolate) the light-emitting device layer 113 disposed in the second region of the first substrate 100 at least once.

[0460] According to an embodiment of the present invention, the discontinuity 115 may include: a first discontinuity 115a having a closed loop shape and surrounding the weir 117; and a second discontinuity 115b being surrounded by the weir 117 and having a closed loop shape.

[0461] The first discontinuity 115a may include a first strip structure TS1 and a second strip structure TS2. The first discontinuity 115a may be referenced above. Figures 9 to 12 The first discontinuity 115a described is substantially the same, therefore similar reference numerals refer to similar elements, and their repeated descriptions are omitted.

[0462] The second discontinuity 115b may include a first strip structure TS1 and a second strip structure TS2. The second discontinuity 115b may refer to the above. Figures 9 to 12 The fourth discontinuity 115d described is substantially the same, therefore similar reference numerals refer to similar elements, and their repeated descriptions are omitted.

[0463] In a light-emitting display device according to another embodiment of the present invention, the wiring portion 400 may be electrically connected to the contact pattern portion 110 via wiring contact holes CH passing through at least one of the weir portion 117 and the discontinuity portion 115 located on the contact pattern portion 110. In addition to the wiring portion 400 being electrically connected to the contact patterns PCP, DCP, RCP, GCP, and CCP of the contact pattern portion 110 via a plurality of wiring contact holes (e.g., first to fourth wiring contact holes) CH1 to CH4 passing through each of the first weir portion 117-1 and the second weir portion 117-2 of the weir portion 117 and the first and second discontinuities 115a and 115b of the discontinuity portion 115, the wiring portion 400 may be connected to the contact patterns PCP, DCP, RCP, GCP, and CCP of the contact pattern portion 110 as described above. Figures 9 to 12 The wiring sections described are basically the same, so their repeated descriptions are omitted.

[0464] Furthermore, the wiring section 400 can be electrically connected to the contact patterns PCP, DCP, RCP, GCP and CCP of the contact pattern section 110 via only the first wiring contact hole CH1 and the second wiring contact hole CH2 passing through each of the first weir 117-1 and the second weir 117-2 of the weir 117. In this case, the third wiring contact hole CH3 and the fourth wiring contact hole CH4 passing through each of the first and second discontinuities 115a and 115b of the discontinuity 115 can be omitted.

[0465] As described above, in a light-emitting display device according to another embodiment of the present invention, the overflow of the encapsulation layer 119 caused by the first weir 117-1 and the second weir 117-2 of the weir 117 can be prevented more definitively, and the light-emitting device layer 113 can be disconnected (or isolated) by the undercut structure of the first weir 117-1 and the second weir 117-2 of the weir 117, thereby reducing or minimizing the number of discontinuities 115.

[0466] Figure 30 This is a diagram illustrating a light-emitting display device according to another embodiment of the present invention. Figure 31 It is along Figure 30 The cross-sectional view shown is taken by line X-X'. Figure 32 yes Figure 31 An enlarged view of region B8 is shown. Region B8 includes the peripheral portion of the substrate that is also adjacent to the outer surface (or outermost surface) of the substrate. Figure 31 The peripheral portion is shown to be adjacent to the first outer surface OS1a of the first substrate 100. Figures 30 to 32 It shows the addition of auxiliary lines. Figures 27 to 29 The embodiment of the light-emitting display device is shown. In the description... Figures 30 to 32 At that time, only the weir and its related components will be described below; other components will be described by [other entities]. Figures 27 to 29 The same reference marker is used for reference, and its repeated description is omitted.

[0467] Reference Figures 30 to 32 According to another embodiment of the present invention, the light-emitting display device may further include an auxiliary pattern section 116, which is disposed between the contact pattern section 110 and the wiring section 400 connected to multiple pixel driving lines PL, DL, RL, GCL and CVL. The auxiliary pattern section 116 may have a... Figures 13 to 16C The auxiliary pattern section 116 shown has a basically the same structure, so its description will be omitted or will be briefly repeated below.

[0468] According to an embodiment of the present invention, the auxiliary pattern section 116 may include first to fourth intermediate patterns 116a to 116d, which are electrically connected between the contact patterns PCP, DCP, RCP, GCP and CCP of the contact pattern section 110 and the wiring 410 of the wiring section 400.

[0469] Each of the first and second intermediate patterns 116a and 116b may be disposed in the weir section 117.

[0470] The first intermediate pattern 116a may be disposed in the first weir portion 117-1 of the weir portion 117. For example, the first intermediate pattern 116a may be disposed between the weir strip structure DTS of the first weir 117a and the first weir portion 117-1, and may be electrically connected between the contact patterns PCP, DCP, RCP, GCP and CCP and the wiring 410.

[0471] The second intermediate pattern 116b may be disposed in the second weir portion 117-2 of the weir portion 117. For example, the second intermediate pattern 116b may be disposed between the weir strip structure DTS of the first weir 117a and the second weir portion 117-2, and may be electrically connected between the contact patterns PCP, DCP, RCP, GCP and CCP and the wiring 410.

[0472] Each of the third and fourth intermediate patterns 116c and 116d may be set in the discontinuity 115.

[0473] The third intermediate pattern 116c may be disposed in the first discontinuity structure 115a of the discontinuity portion 115. For example, the third intermediate pattern 116c may be disposed on the first strip structure TS1 of the first discontinuity structure 115a and may be electrically connected between the contact patterns PCP, DCP, RCP, GCP and CCP and the wiring 410.

[0474] The fourth intermediate pattern 116d may be disposed in the second discontinuity structure 115b of the discontinuity portion 115. For example, the fourth intermediate pattern 116d may be disposed on the first strip structure TS1 of the second discontinuity structure 115b and may be electrically connected between the contact patterns PCP, DCP, RCP, GCP and CCP and the wiring 410.

[0475] Each of the first to fourth intermediate patterns 116a to 116d can prevent electrical or physical contact defects between the contact patterns PCP, DCP, RCP, GCP and CCP and the wiring 410 due to the distance between the contact patterns PCP, DCP, RCP, GCP and CCP and the wiring 410.

[0476] Each of the first to fourth intermediate patterns 116a to 116d according to embodiments of the present invention may include a first metal layer MLA and a second metal layer MLb.

[0477] According to an embodiment of the present invention, the first metal layer MLA can be implemented on the buffer layer 111a to be electrically connected to the contact patterns PCP, DCP, RCP, GCP, and CCP. For example, the first metal layer MLA can be disposed on the buffer layer 111a overlapping the contact patterns PCP, DCP, RCP, GCP, and CCP, and can be electrically connected to the contact patterns PCP, DCP, RCP, GCP, and CCP via a first via VH1 through the buffer layer 111a. For example, according to an embodiment of the present invention, the first metal layer MLA can be implemented as a dot shape overlapping the contact patterns PCP, DCP, RCP, GCP, and CCP, or it can be implemented as a line shape overlapping the contact patterns PCP, DCP, RCP, GCP, and CCP in the first direction X. According to an embodiment of the present invention, the first metal layer MLA can be implemented to have the same material and structure as the gate of each TFT Tdr located in the pixel region PA, or it can be implemented to have the same material and structure as the source / drain of each TFT Tdr.

[0478] The second metal layer MLb can be electrically connected between the first metal layer MLA and the wiring 410. For example, the second metal layer MLb can be disposed on the passivation layer 111d overlapping the first metal layer MLA, and can be electrically connected to the first metal layer MLA via a second via VH2 passing sequentially through the passivation layer 111d and the interlayer insulating layer 111c. According to embodiments of the present invention, the second metal layer MLb can be implemented as a dot or line shape similar to the first metal layer MLA. According to embodiments of the present invention, the second metal layer MLb can be implemented as having the same material and structure as the pixel electrode PE disposed in the pixel region PA.

[0479] The second metal layer MLb of each of the first and second intermediate patterns 116a and 116b enhances the adhesion between the first weir and the weir strip structure DTS in the weir portion 117. The second metal layer MLb of each of the third and fourth intermediate patterns 116c and 116d enhances the adhesion between the first strip structure TS1 and the second strip structure TS2 in the discontinuity portion 115.

[0480] According to another embodiment of the present invention, the light-emitting display device may further include an auxiliary line portion 118, which is located in each of the weir portion 117 and the discontinuity portion 115 disposed on the portion of the first substrate 100 other than the peripheral portion. The auxiliary line portion 118 may have the same characteristics as the auxiliary line portion 118. Figure 13 , 14 The auxiliary line portion 118 shown in 17 has a basically the same structure, so it is omitted or will be briefly described again below.

[0481] According to an embodiment of the present invention, the auxiliary line portion 118 may include first to fourth auxiliary lines 118a to 118d located in the discontinuity portion 115 and the weir portion 117.

[0482] Each of the first to fourth auxiliary lines 118a to 118d can be electrically floated. According to an embodiment of the present invention, each of the first to fourth auxiliary lines 118a to 118d can be implemented to have the same material and structure as the pixel electrode PE disposed in the pixel region PA. For example, each of the first to fourth auxiliary lines 118a to 118d can be formed together with the second metal layer MLb of the auxiliary pattern portion 116.

[0483] Each of the first and second auxiliary lines 118a and 118b can be set in the weir section 117.

[0484] The first auxiliary line 118a may be set in the first weir section 117-1 of the weir section 117. For example, the first auxiliary line 118a may be set between the weir strip structure DTS of the first weir 117a and the first weir section 117-1.

[0485] The second auxiliary line 118b can be set in the second weir section 117-2 of the weir section 117. For example, the second auxiliary line 118b can be set between the weir strip structure DTS of the first weir 117a and the second weir section 117-2.

[0486] The first and second auxiliary lines 118a and 118b can enhance the adhesion between the weir strip structure DTS in the weir section 117 and the first weir 117a.

[0487] Each of the third and fourth auxiliary lines 118c and 118d can be set in the discontinuity 115.

[0488] The third auxiliary line 118c may be provided in the first discontinuity structure 115a of the discontinuity portion 115. For example, the third auxiliary line 118c may be provided on the first strip structure TS1 of the first discontinuity structure 115a.

[0489] The fourth auxiliary line 118d may be provided in the second discontinuity structure 115b of the discontinuity portion 115. For example, the fourth auxiliary line 118d may be provided on the first strip structure TS1 of the second discontinuity structure 115b.

[0490] The third and fourth auxiliary lines 118c and 118d can enhance the adhesion between the first strip structure TS1 and the second strip structure TS2 in the discontinuity 115.

[0491] As described above, the light-emitting display device according to another embodiment of the present invention may further include an auxiliary pattern portion 116 disposed between the contact patterns PCP, DCP, RCP, GCP and CCP and the wiring 410, thereby preventing electrical or physical contact defects between the contact patterns PCP, DCP, RCP, GCP and CCP and the wiring 410.

[0492] Furthermore, in a light-emitting display device according to another embodiment of the present invention, with Figures 18 to 26 Similar to the light-emitting display device shown, the auxiliary line section 118 can be used as a signal supply line.

[0493] According to embodiments of the present invention, such as Figures 18 to 22 As shown, each of the first and second auxiliary lines 118a and 118b is electrically connected to the first and last pixel driving power lines PL in a plurality of pixel driving power lines PL at one side (or one side corner portion) and the other side (or the other side corner portion) of the peripheral portion of one side of the first substrate 100, and is electrically connected to the first portion 410a of each of the first and last pixel driving power lines 411 in a plurality of pixel driving power lines 411 via at least one wiring contact hole CH2 and CH3. Furthermore, each of the first and second auxiliary lines 118a and 118b is electrically (or jointly) connected to the other side of each pixel driving power line PL at the peripheral portion of the other side of the first substrate 100. Therefore, since the pixel driving power lines PL are connected to the first and second auxiliary lines 118a and 118b, the voltage drop (IR drop) of the pixel driving power supply due to the line resistance of each pixel driving power line PL can be reduced, thereby enhancing the uniformity of the pixel driving power supply.

[0494] According to embodiments of the present invention, such as Figures 18 to 22As shown, each of the third and fourth auxiliary lines 118c and 118d can be formed on the first substrate 100 as a closed-loop line. Each of the third and fourth auxiliary lines 118c and 118d can be electrically connected to a plurality of pixel common voltage lines CVL at a peripheral portion on one side of the first substrate 100, and can be electrically connected only to the first portion 410a of each of the plurality of pixel common voltage wirings 419 via at least one wiring contact hole CH3 and CH4. Furthermore, each of the third and fourth auxiliary lines 118c and 118d can be electrically (or jointly) connected to the other side of each of the pixel common voltage lines CVL at a peripheral portion on the other side of the first substrate 100. Therefore, each of the third and fourth auxiliary lines 118c and 118d can maintain the same potential as the pixel common voltage lines CVL, thereby cutting off static electricity flowing into the display portion AA from the outside, thus preventing defects caused by static electricity.

[0495] According to embodiments of the present invention, such as Figure 23 As shown, one of the first and second auxiliary lines 118a and 118b, or the fourth auxiliary line 118d, can be formed to be electrically connected to the first and last reference voltage contact pattern RCP among the plurality of reference voltage contact patterns RCP located in the contact pattern portion 110. Furthermore, one of the first and second auxiliary lines 118a and 118b, or the fourth auxiliary line 118d, can be electrically (or jointly) connected to the other side of each reference voltage line RL at the peripheral portion on the other side of the first substrate 100. Therefore, since the reference voltage line RL is connected to one of the first and second auxiliary lines 118a and 118b, or the fourth auxiliary line 118d, the voltage drop (IR drop) of the reference voltage due to the line resistance of each reference voltage line RL can be reduced, thereby enhancing the uniformity of the reference voltage.

[0496] According to embodiments of the present invention, such as Figures 24 to 26 As shown, the first to fourth auxiliary lines 118a to 118d can be electrically (or jointly) connected to each other via auxiliary connection lines SCL. Furthermore, the fourth auxiliary line 118d can be formed as a closed loop on the first substrate 100 and can be formed to be electrically connected only to the pixel common voltage contact pattern CCP located in the contact pattern portion 110. Therefore, each of the first to fourth auxiliary lines 118a to 118d can maintain the same potential as the pixel common voltage line CVL, thus cutting off static electricity flowing into the display portion AA from the outside, thereby preventing defects caused by static electricity.

[0497] Figure 33 This is an illustration of a multi-screen display device according to an embodiment of the present invention. Figure 34 It is along Figure 33 The cross-sectional view taken by line XI-XI' is shown. Figure 33 and Figure 34 The diagram illustrates the process of laying... Figures 1 to 30 The multi-screen display device shown is implemented by a light-emitting display device according to an embodiment of the present invention.

[0498] Reference Figure 33 and Figure 34 According to embodiments of the present invention, a multi-screen display device (or a deployed display device) may include a plurality of display devices DM1 to DM4.

[0499] Multiple display devices DM1 to DM4 can each display a separate image or can display a single image in a segmented manner. Each of the multiple display devices DM1 to DM4 may include Figures 1 to 30 The light-emitting display device shown in this invention is therefore omitted or will be briefly described again. Figure 34 Each of the multiple display devices DM1 to DM4 shown is illustrated Figures 13 to 17 The light-emitting display device shown is not limited to this embodiment of the invention.

[0500] Multiple display devices DM1 to DM4 can be laid on a separate tiling frame so that they are in contact with each other at their side surfaces. For example, multiple display devices DM1 to DM4 can be laid in an N×M configuration to realize a multi-screen display device with a large screen. For example, N is a positive integer of 1 or greater, and M is a positive integer of 2 or greater, but the embodiments of the present invention are not limited to this. For example, N is a positive integer of 2 or greater, and M is a positive integer of 1 or greater.

[0501] Each of the plurality of display devices DM1 to DM4 may not include a border area (or non-display area) surrounding the entire display area AA of the displayed image, but may instead have an air border structure in which the display area AA is surrounded by air. For example, in each of the plurality of display devices DM1 to DM4, the entire first surface of the first substrate 100 may be implemented as the display area AA.

[0502] According to an embodiment of the present invention, in each of the plurality of display devices DM1 to DM4, the second interval D2 between the central portion CP of the outermost pixel Po and the outermost outer surface of the first substrate 100 (or the vertical extension line VL extending vertically from the outer surface of the first substrate 100) can be implemented as half or less of the first interval D1 (or pixel pitch) between adjacent pixels. Therefore, in two adjacent display devices that are connected (or in contact) with each other at the side surfaces along the first direction X and the second direction Y based on a lateral bonding method, the interval “D2+D2” between adjacent outermost pixel regions PAo can be equal to or less than the first interval D1 between two adjacent pixels.

[0503] Reference Figure 34In the first display device DM1 and the third display device DM3, which are connected (or in contact) to each other on their side surfaces along the second direction Y, the interval “D2+D2” between the center portion CP of the outermost pixel Po of the first display device DM1 and the center portion CP of the outermost pixel Po of the third display device DM3 can be equal to or less than the first interval D1 (or pixel pitch) between two adjacent pixels in each of the first display device DM1 and the third display device DM3.

[0504] Therefore, the interval "D2+D2" between the central portions CP of the outermost pixels Po of two adjacent display devices that are connected (or in contact) with each other on the side surfaces along the first direction X and the second direction Y can be equal to or less than the first interval D1 between two adjacent pixels in each of the display devices DM1 to DM4. Thus, there can be no seam or boundary portion between two adjacent display devices, thereby eliminating dark areas caused by boundary portions between display devices DM1 to DM4. As a result, images displayed on a multi-screen display device with multiple display devices DM1, DM2, DM3, and DM4 arranged in an N×M form can be displayed continuously without any sense of interruption (or discontinuity) at the boundaries between the multiple display devices DM1, DM2, DM3, and DM4.

[0505] exist Figure 33 and Figure 34 The diagram shows multiple display devices DM1 to DM4 arranged in a 2×2 configuration. However, embodiments of the present invention are not limited to this; the multiple display devices DM1 to DM4 can be arranged in an x×1 configuration, a 1×y configuration, or an x×y configuration. For example, x and y can be natural numbers 2 or greater that are equal to or different from each other.

[0506] As described above, in the case where the display area AA of each of the multiple display devices DM1 to DM4 is a screen and displays an image, the multi-screen display device according to the embodiment of the present invention can display an image continuously without interruption at the boundary portion between the multiple display devices DM1 to DM4, thereby enhancing the immersive experience of the viewer watching the image displayed by the multi-screen display device.

[0507] The present invention may also provide many additional features and implementations as described below and not mentioned herein.

[0508] In some embodiments, a light-emitting display device may include: a substrate having a front peripheral portion and an outer surface; a display portion including a plurality of pixel regions disposed on the substrate; a circuit layer including a plurality of pixel driving lines disposed in the plurality of pixel regions; a light-emitting device layer including a light-emitting layer disposed on the circuit layer located in the plurality of pixel regions; an encapsulation layer disposed on the light-emitting device layer; and a wiring portion surrounding the front peripheral portion and the outer surface of the substrate, and including a plurality of wirings passing through the encapsulation layer disposed at the front peripheral portion of the substrate to connect to the plurality of pixel driving lines.

[0509] The light-emitting display device may further include a contact pattern portion, the contact pattern portion including a plurality of contact patterns located on the circuit layer and connected to the plurality of pixel driving lines, wherein the plurality of wirings pass through an encapsulation layer located at the peripheral portion of the substrate and are electrically connected to the plurality of contact patterns.

[0510] Each contact pattern of the light-emitting display device can be disposed on the same layer as the plurality of pixel driving lines and extend from each pixel driving line.

[0511] The light-emitting display device may also include a plurality of auxiliary patterns electrically connected between the plurality of contact patterns and the plurality of wirings.

[0512] Each auxiliary pattern of the light-emitting display device may include: a first metal layer electrically connected to a corresponding contact pattern among the plurality of contact patterns; and a second metal layer disposed on the first metal layer and electrically connected to a corresponding wiring among the plurality of wirings.

[0513] The circuit layer of the light-emitting display device may include: a buffer layer disposed on the plurality of pixel driving lines and the plurality of contact patterns; and at least one insulating layer disposed on the buffer layer, wherein each auxiliary pattern includes: a first metal layer disposed on the buffer layer overlapping the plurality of contact patterns and electrically connected to the plurality of contact patterns via a first via formed in the buffer layer; and a second metal layer disposed on at least one insulating layer overlapping the first metal layer and electrically connected to the first metal layer via a second via formed in the at least one insulating layer, wherein the plurality of wirings are electrically connected to the second metal layer of each auxiliary pattern via wiring contact holes passing through the encapsulation layer.

[0514] The light-emitting display device may further include a weir disposed on the circuit layer along the periphery of the substrate, wherein the encapsulation layer includes: a first encapsulation layer disposed on the light-emitting device layer and the weir; a second encapsulation layer disposed on the first encapsulation layer and surrounded by the weir; and a third encapsulation layer disposed on the first encapsulation layer and the second encapsulation layer on the weir, wherein the plurality of wirings are electrically connected to the plurality of contact patterns via wiring contact holes passing through the third encapsulation layer, the first encapsulation layer and the weir.

[0515] The light-emitting display device may further include multiple auxiliary patterns, which are disposed in the weir and electrically connected between the multiple contact patterns and the multiple wirings.

[0516] The light-emitting display device includes a weir portion that may include: a first weir portion disposed on the circuit layer along a peripheral portion of the substrate; and a second weir portion disposed on the circuit layer to surround the first weir portion, wherein the plurality of wirings are electrically connected to the plurality of contact patterns via at least one first wiring contact hole passing through the third encapsulation layer, the first encapsulation layer, and the first weir portion, and are electrically connected to the plurality of contact patterns via at least one second wiring contact hole passing through the third encapsulation layer, the first encapsulation layer, and the second weir portion.

[0517] The light-emitting display device may further include a plurality of auxiliary patterns disposed in each of the first weir and the second weir and electrically connected between the plurality of contact patterns and the plurality of wirings.

[0518] Each of the first weir and the second weir in the light-emitting display device may include: a weir strip structure disposed at the circuit layer; a first weir disposed on the weir strip structure; a second weir disposed on the first weir; and an undercut region disposed at the boundary portion between the weir strip structure and the first weir.

[0519] The light-emitting display device may further include: a dam portion disposed on the circuit layer along the peripheral portion of the substrate; and a discontinuity portion disposed on the circuit layer along the peripheral portion of the substrate to isolate the light-emitting layer, wherein the encapsulation layer includes: a first encapsulation layer disposed on the light-emitting device layer, the dam portion, and the discontinuity portion; a second encapsulation layer disposed on the first encapsulation layer and surrounded by the dam portion; and a third encapsulation layer disposed on the first encapsulation layer and the second encapsulation layer on the dam portion, wherein the plurality of wirings are electrically connected to the plurality of contact patterns via wiring contact holes passing through the third encapsulation layer and the first encapsulation layer and additionally passing through one of the dam portion and the discontinuity portion.

[0520] The discontinuity of the light-emitting display device may include at least one discontinuous structure disposed on the circuit layer along the peripheral portion of the substrate, the at least one discontinuous structure including: a first strip structure disposed on the circuit layer; a second strip structure disposed on the first strip structure; and an undercut region at the boundary portion between the first strip structure and the second strip structure.

[0521] The light-emitting display device may further include a plurality of auxiliary patterns disposed at one or more of the weir portion and the discontinuity portion, and electrically connected between the plurality of contact patterns and the plurality of wirings.

[0522] Each auxiliary pattern included in the light-emitting display device may include: a first metal layer electrically connected to a corresponding contact pattern among the plurality of contact patterns; and a second metal layer disposed on the first metal layer, the second metal layer being electrically connected to a corresponding wiring among the plurality of wirings.

[0523] The light-emitting display device may further include an auxiliary line portion located on the outer periphery of the substrate, excluding the outer periphery of one side on which the plurality of contact patterns are disposed, wherein the auxiliary line portion includes auxiliary lines located at one or more of the weir portion and the discontinuity portion.

[0524] The light-emitting display device includes multiple pixel driving lines, which may include: data lines, pixel driving power lines, and pixel common voltage lines. The auxiliary lines are electrically connected to the pixel driving power lines or the pixel common voltage lines.

[0525] The light-emitting display device may further include an auxiliary line portion located at the peripheral portion of the substrate, wherein the auxiliary line portion includes: a plurality of auxiliary lines located at the peripheral portion of the substrate on another peripheral portion other than the peripheral portion on which the plurality of contact patterns are disposed; and at least one closed loop line configured as a closed loop line along the peripheral portion of the substrate.

[0526] The light-emitting display device includes multiple pixel driving lines, which may include: a data line, a pixel driving power line, and a pixel common voltage line, wherein at least one closed-loop line is electrically connected to the pixel common voltage line.

[0527] The light-emitting display device includes multiple auxiliary lines that can be electrically connected to the pixel driving power line.

[0528] The light-emitting display device may further include auxiliary connecting lines, which are connected together to the plurality of auxiliary lines and the at least one closed-loop line.

[0529] The size of the display portion of the light-emitting display device may be the same as the size of the substrate.

[0530] In some embodiments, a display device may include: a substrate including a peripheral portion adjacent to a plurality of outer surfaces of the substrate, wherein at least one of the plurality of outer surfaces includes the outermost surface of the substrate; a plurality of pixels located on the substrate to define a display area; a plurality of signal lines connected to the plurality of pixels; a light-emitting device layer included in each of the plurality of pixels; an encapsulation layer on the light-emitting device layer; and a plurality of wirings extending to the peripheral portion and at least partially covering the outermost surface of the substrate.

[0531] The peripheral portion of the display device may be located inside the display area.

[0532] The display device includes an encapsulation layer and at least one of the wirings, which may overlap each other at the peripheral portion.

[0533] The display device includes at least one of the wirings that may be located on and in contact with the outer surface of the substrate.

[0534] The display device includes at least one of the wirings that can extend through an encapsulation layer located at the periphery of the substrate.

[0535] The display device may further include a discontinuity wall located in a peripheral portion of the substrate to break the light-emitting device layer, wherein the encapsulation layer is located on the discontinuity wall, and at least one of the wirings extends into the encapsulation layer and the discontinuity wall.

[0536] The display device may further include: a discontinuity wall located in a peripheral portion of the substrate to break the light-emitting device layer; and a weir adjacent to the discontinuity wall in the peripheral portion of the substrate, wherein the weir has a different height than the discontinuity wall, and wherein at least one of the wirings extends into the encapsulation layer and the weir.

[0537] The display device may include an encapsulation layer comprising: a first encapsulation layer disposed on the light-emitting device layer and the weir; and a second encapsulation layer disposed on the first encapsulation layer and not extending beyond the weir, wherein the plurality of wirings overlap with the second encapsulation layer.

[0538] The display device may further include a plurality of auxiliary lines adjacent to the plurality of wirings, the plurality of auxiliary lines including: a first conductive structure overlapping the discontinuity wall, wherein the first conductive structure is electrically connected to the plurality of wirings.

[0539] The display device may further include a second conductive structure on the first conductive structure, the second conductive structure overlapping the discontinuity wall, wherein the second conductive structure is electrically connected to the multiple wirings.

[0540] In some embodiments, a display device may include: a first substrate having a first surface adjacent to an edge of the first substrate; a second substrate facing the first substrate having a second surface adjacent to an edge of the second substrate, the second surface and the first surface being adjacent to each other; a plurality of pixels on the first substrate; a plurality of signal lines connected to the plurality of pixels; a light-emitting device layer located on each of the plurality of pixels and on an edge of the first substrate; and a plurality of wirings extending from the first substrate, at least one of the plurality of wirings extending on a first surface of the first substrate and a second surface of the second substrate to form an electrical connection between the first substrate and the second substrate.

[0541] The plurality of pixels of the display device on the first substrate can define a display area extending to the edge of the first substrate.

[0542] The display device may further include an encapsulation layer located on the light-emitting device layer, wherein the plurality of wirings are adjacent to the edge of the first substrate and located on the encapsulation layer.

[0543] The display device may further include a contact pattern portion located on the first substrate, the contact pattern portion being adjacent to the outermost pixel among the plurality of pixels, the contact pattern portion being electrically connected to the plurality of signal lines, wherein at least one of the plurality of wirings extends through the encapsulation layer to connect to the contact pattern portion.

[0544] The display device may further include a discontinuity wall adjacent to the edge of the first substrate to break the light-emitting device layer, the discontinuity wall being located on the contact pattern portion, wherein at least one of the plurality of wirings extends through the encapsulation layer and the discontinuity wall to connect to the contact pattern portion.

[0545] The display device may further include a weir adjacent to the discontinuity wall, the weir having a height higher than the discontinuity wall, wherein at least one of the plurality of wirings extends through the encapsulation layer and the weir to connect to the contact pattern portion.

[0546] The display device may further include a first auxiliary conductive structure located on the contact pattern portion, the first auxiliary conductive structure overlapping the position of the discontinuity wall or the weir, wherein at least one of the plurality of wirings extends through the encapsulation layer to connect to the first auxiliary conductive structure.

[0547] The display device may further include a second auxiliary conductive structure located on the contact pattern portion, the second auxiliary conductive structure being located on the first auxiliary conductive structure and overlapping the position of the discontinuity wall or the weir, wherein at least one of the plurality of wirings extends through the encapsulation layer to connect to the first auxiliary conductive structure and the second auxiliary conductive structure.

[0548] Furthermore, the concepts provided herein can be part of a multi-screen display device comprising: a plurality of display devices disposed along at least one of a first direction and a second direction intersecting the first direction, wherein each of the plurality of display devices comprises a light-emitting display device or display device described herein.

[0549] The multi-screen display device includes a display portion that may have a plurality of pixels arranged at a pixel pitch in the first direction and the second direction, wherein the pixel pitch is the distance between the centers of pixels that are adjacent to each other in each of the first direction and the second direction, wherein in a first display device and a second display device that are adjacent to each other along each of the first direction and the second direction, the distance between the center portion of the outermost pixel of the first display device and the center portion of the outermost pixel of the second display device is less than or equal to the pixel pitch.

[0550] In each display device included in the multi-screen display device, a plurality of pixels may be arranged in the first direction and the second direction with a pixel pitch, wherein the pixel pitch is the distance between the centers of pixels that are adjacent to each other in each of the first direction and the second direction, wherein in the first display device and the second display device that are adjacent to each other along each of the first direction and the second direction, the distance between the center portion of the outermost pixel of the first display device and the center portion of the outermost pixel of the second display device is less than or equal to the pixel pitch.

[0551] The light-emitting display device according to the present invention can be applied to all electronic devices including light-emitting display panels. For example, the light-emitting display device according to the present invention can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, bending devices, electronic notebooks, e-books, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop personal computers (PCs), laptop PCs, notebook computers, workstations, navigation devices, car navigation devices, automotive light-emitting display devices, automotive equipment, theater equipment, theater light-emitting display devices, TVs, wallpaper display devices, signage devices, game consoles, laptops, monitors, cameras, portable video cameras, home appliances, etc.

[0552] The features, structures, and effects described above in this invention are included in at least one embodiment, but are not limited to only one embodiment. Furthermore, the features, structures, and effects described in at least one embodiment of this invention can be achieved by those skilled in the art through combinations or modifications of other embodiments. Therefore, anything related to combinations and modifications should be interpreted as falling within the scope of this invention.

[0553] Various modifications and variations may be made to this invention without departing from the spirit or scope thereof, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover any modifications and variations falling within the scope of the appended claims and their equivalents.

[0554] The above embodiments can be combined to provide further embodiments. The entire contents of all U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in and / or listed in the application data sheets are incorporated herein by reference. Various aspects of the embodiments may be modified as needed to provide further embodiments using the concepts of the various patents, applications, and publications.

[0555] These and other variations can be made to the embodiments based on the detailed description above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but rather should be interpreted to include all possible embodiments within the full scope of equivalence consistent with these claims. Therefore, the claims are not limited to the embodiments.

Claims

1. A display device, comprising: A substrate, the substrate including a peripheral portion adjacent to a plurality of outer surfaces of the substrate, wherein at least one of the plurality of outer surfaces includes the outermost surface of the substrate; Multiple pixels located on the substrate to define a display area; Multiple signal lines connected to the plurality of pixels; A light-emitting device layer is included in each of the plurality of pixels; An encapsulation layer on the light-emitting device layer; as well as Multiple wirings extend to the peripheral portion and at least partially cover the outermost surface of the substrate. At least one of the wirings extends through the encapsulation layer located at the periphery of the substrate.

2. The display device according to claim 1, wherein the peripheral portion is located inside the display area.

3. The display device of claim 1, wherein the encapsulation layer and at least one of the wirings overlap each other at the peripheral portion.

4. The display device according to claim 1, wherein at least one of the wirings is located on the outer surface of the substrate and is in contact with the outer surface.

5. The display device according to claim 1, further comprising a discontinuity wall located in the peripheral portion of the substrate to break the light-emitting device layer. The encapsulation layer is located on the discontinuity wall. At least one of the wirings extends into the encapsulation layer and the discontinuity wall.

6. The display device of claim 1, further comprising: Discontinuous walls, located in the peripheral portion of the substrate, to break the light-emitting device layer; And a weir portion, which is adjacent to the discontinuity wall in the peripheral portion of the substrate. The weir section has a different height than the discontinuous wall. At least one of the wirings extends into the encapsulation layer and the weir.

7. The display device according to claim 6, wherein the encapsulation layer comprises: A first encapsulation layer is disposed on the light-emitting device layer and the weir portion; as well as A second encapsulation layer is disposed on the first encapsulation layer and does not extend beyond the weir portion. The multiple wirings therein overlap with the second encapsulation layer.

8. The display device according to claim 5, further comprising a plurality of auxiliary lines adjacent to the plurality of wirings, the plurality of auxiliary lines comprising: The first conductive structure overlapping the discontinuous wall The first conductive structure is electrically connected to the plurality of wirings.

9. The display device according to claim 8, wherein the plurality of auxiliary lines further comprises: A second conductive structure on the first conductive structure, the second conductive structure overlapping the discontinuity wall. The second conductive structure is electrically connected to the plurality of wirings.

10. A display device, comprising: A first substrate, the first substrate having a first surface adjacent to an edge of the first substrate; A second substrate facing the first substrate has a second surface adjacent to the edge of the second substrate, and the second surface and the first surface are adjacent to each other. Multiple pixels on the first substrate; Multiple signal lines connected to the plurality of pixels; A light-emitting device layer is located on each of the plurality of pixels and on the edge of the first substrate; The encapsulation layer located on the light-emitting device layer; as well as Multiple wirings extending from the first substrate, at least one of which extends on a first surface of the first substrate and a second surface of the second substrate, to form an electrical connection between the first substrate and the second substrate. At least one of the wirings extends through the encapsulation layer located at the periphery of the substrate.

11. The display device of claim 10, wherein a plurality of pixels on the first substrate define a display area extending to the edge of the first substrate.

12. The display device of claim 11, wherein the plurality of wirings are adjacent to the edge of the first substrate and are located on the encapsulation layer.

13. The display device of claim 12, further comprising a contact pattern portion located on the first substrate, the contact pattern portion being adjacent to the outermost pixel of the plurality of pixels, the contact pattern portion being electrically connected to the plurality of signal lines, wherein at least one of the plurality of wirings extends through the encapsulation layer to connect to the contact pattern portion.

14. The display device of claim 13, further comprising a discontinuity wall adjacent to an edge of the first substrate to break the light-emitting device layer, the discontinuity wall being located on the contact pattern portion, wherein at least one of the plurality of wirings extends through the encapsulation layer and the discontinuity wall to connect to the contact pattern portion.

15. The display device of claim 14, further comprising a weir adjacent to the discontinuity wall, the weir having a height higher than the discontinuity wall, wherein at least one of the plurality of wirings extends through the encapsulation layer and the weir to connect to the contact pattern portion.

16. The display device of claim 15, further comprising a first auxiliary conductive structure located on the contact pattern portion, the first auxiliary conductive structure overlapping the position of the discontinuity wall or the weir, wherein at least one of the plurality of wirings extends through the encapsulation layer to connect to the first auxiliary conductive structure.

17. The display device of claim 16, further comprising a second auxiliary conductive structure located on the contact pattern portion, the second auxiliary conductive structure being located on the first auxiliary conductive structure and overlapping the position of the discontinuity wall or the weir, wherein at least one of the plurality of wirings extends through the encapsulation layer to connect to the first auxiliary conductive structure and the second auxiliary conductive structure.

18. A multi-screen display device, comprising: Multiple display devices are arranged along at least one of a first direction and a second direction intersecting the first direction. Each of the plurality of display devices includes the display device according to claim 1.

19. The multi-screen display device according to claim 18, wherein in the light-emitting display device of each of the plurality of display devices, the plurality of pixels are arranged at a pixel pitch in the first direction and the second direction. The pixel spacing is the distance between the centers of adjacent pixels in each of the first and second directions. In the first and second display devices adjacent to each other along the first and second directions, the distance between the center portion of the outermost pixel of the first display device and the center portion of the outermost pixel of the second display device is less than or equal to the pixel pitch.

Images