An FPGA-based semi-parallel SC decoder implementation method and system
The semi-parallel SC decoder was optimized by initialization and update modules, simplifying the decoder structure and achieving better decoding results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SUN YAT SEN UNIV
- Filing Date
- 2022-04-07
- Publication Date
- 2026-07-21
AI Technical Summary
Existing semi-parallel SC decoder architectures struggle to generate decoder parts and modules during the decoding process, increasing structural complexity.
By setting decoder parameters and initializing the partial and update modules and the reordering module, the processing unit group performs decoding operations, and performs bit decision, update and reordering processing based on the operation results, thereby optimizing the decoder structure.
The semi-parallel SC decoder structure was simplified, resulting in better decoding results.
Smart Images
Figure CN114679186B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of channel coding technology, and in particular to a method and system for implementing a semi-parallel SC decoder based on FPGA. Background Technology
[0002] Polar codes are a channel coding technique proposed by E. Arikan in 2007. This coding technique is currently the only proven channel coding technique with achievable channel capacity. Polar codes have several advantages, including a fine-grained rate adjustment mechanism and superior decoding performance. The serial cancellation decoding algorithm, due to its recursive nature, is well-suited for hardware programming and achieves parallel decoding. Later, a semi-parallel SC decoder structure was proposed, further reducing the number of instantiated processing units for longer code lengths. This sacrifices a small amount of decoding latency for less hardware resource consumption. However, their semi-parallel SC decoder structures struggle to generate decoder parts and modules during the decoding process, thus increasing the complexity of the semi-parallel SC decoder structure. Summary of the Invention
[0003] To address the aforementioned technical problems, the present invention aims to provide a method and system for implementing a semi-parallel SC decoder based on FPGA, which can achieve better decoding results while simplifying the structure of the semi-parallel SC decoder.
[0004] The first technical solution adopted in this invention is: a method for implementing a semi-parallel SC decoder based on FPGA, comprising the following steps:
[0005] Set the decoder parameters and initialize the partial and update modules and the reverse ordering module to obtain the initialized decoder;
[0006] Based on the initialized decoder, the processing unit group performs decoding operations on the processing unit and makes bit decisions based on the operation results to obtain the decision results;
[0007] Based on the judgment result, the decoder's parts and update modules are updated and reordered in sequence, and the decoding result is output.
[0008] Furthermore, the step of setting the decoder parameters and initializing the partial update module and the reverse ordering module to obtain the initialized decoder specifically includes:
[0009] Set the parameters of the decoder and set the fixed-point scheme of the system. The parameters of the decoder include the code length of the polar code to be decoded, the code rate of the polar code to be decoded, the system clock frequency corresponding to the decoder, the bit width of the channel input to the decoder in each clock cycle, and the number of processing units in the decoder processing unit group.
[0010] Based on the decoder parameters, initialize the decoder's partial sum update module and reverse ordering module to obtain the initialized partial sum update module and the initialized reverse ordering module;
[0011] Based on the decoder's parameters, the decoder's storage module is instantiated, and the decoder's log-likelihood ratio is written into the decoder's storage module.
[0012] Based on the log-likelihood ratio of the decoder, the processing unit group of the decoder is enabled to obtain the initialized decoder.
[0013] Furthermore, the step of initializing the partial sum update module and the reverse ordering module of the decoder according to the decoder parameters to obtain the initialized partial sum update module and the initialized reverse ordering module specifically includes:
[0014] Based on the decoder parameters, the decoded bit index is calculated using the jump column order calculation method to obtain the column number of the bit index;
[0015] Based on the decoder's parameters, the decoder's polar code is constructed to obtain the decoder's frozen bit index;
[0016] The decoder's partial sum update module and reverse ordering module are initialized based on the decoded bit index, resulting in the initialized partial sum update module and the initialized reverse ordering module.
[0017] Furthermore, the step of the processing unit group performing decoding operations on the processing unit based on the initialized decoder, and performing bit decision based on the operation results to obtain the decision result specifically includes:
[0018] Based on the initialized decoder, the processing unit group determines how many clock cycles to calculate and activates the processing unit according to the column number of the processing unit.
[0019] The value of the current execution indicator function is used to determine the execution function of the processing unit group in this clock cycle, and the corresponding execution function is selected.
[0020] The corresponding execution functions include the f function and the g function;
[0021] Based on the execution function, the log-likelihood ratio of the processing unit group under that clock cycle is calculated, and the value of the log-likelihood ratio is output.
[0022] Based on the frozen bit index, a decision is made on the current decoded bit index according to the value of the log-likelihood ratio, and the decision result is obtained.
[0023] Furthermore, the currently executing instruction function is specifically as follows:
[0024]
[0025] In the above formula, B(l,i) represents the current execution function of the processing unit group, l represents the current bit index column number of the processing unit, and i represents the decoding bit index.
[0026] Furthermore, the step of determining the current decoded bit index based on the value of the log-likelihood ratio, based on the frozen bit index, to obtain the decision result specifically includes:
[0027] Determine the current decoded bit index;
[0028] If the current decoded bit index is determined to be a frozen bit index, the output decision result is "0";
[0029] When it is determined that the current decoded bit index does not belong to the frozen bit index and the column number of the processing unit is "0", the highest bit of the log-likelihood ratio is judged.
[0030] If the highest bit of the log-likelihood ratio is determined to be "0", the output decision result is "0".
[0031] If the highest bit of the log-likelihood ratio is not "0", the output decision result is "1".
[0032] Furthermore, the g function of the execution function is as follows:
[0033]
[0034] In the above formula, express The corresponding part sum, LLR represents the log-likelihood ratio.
[0035] Furthermore, the step of sequentially updating and reordering the decoder's parts and update modules according to the decision result, and outputting the decoding result, specifically includes:
[0036] Based on the judgment, update the initialized parts and the updated module to obtain the enable value;
[0037] The initialization of the reverse ordering module is enabled based on the enable value;
[0038] Once the deordering module is detected as enabled, the initialized part and the output value of the update module are reordered to obtain the decoding result.
[0039] Furthermore, the specific update algorithm for the updated initial part and the update module is as follows:
[0040]
[0041]
[0042] In the above formula, in the above formula, This indicates the bit index i in the partial and update modules. N The corresponding register group has a bit width of N / 2 bits. This indicates the bit index i in the partial and update modules. N +1 corresponds to the register group, where i represents the index in registers G and r. This represents the "XOR" operation. Indicates bit index i N The corresponding bit decision result, This represents a register with a bit width of N / 2.
[0043] The second technical solution adopted in this invention is: a semi-parallel SC decoder implementation system based on FPGA, comprising:
[0044] The initialization module is used to set the decoder parameters and initialize the partial update module and the reverse ordering module to obtain the initialized decoder.
[0045] The decision module, based on the initialized decoder, has the processing unit group performing decoding operations on the processing unit and making bit decisions based on the operation results to obtain the decision result;
[0046] The update module is used to update and reorder the decoder components and update module in sequence according to the decision result, and output the decoding result.
[0047] The beneficial effects of the method and system of the present invention are as follows: The present invention addresses the existing semi-parallel SC decoder by updating the internal parts and modules of the semi-parallel SC decoder through the current execution instruction function of the processing unit group, thereby optimizing the structure of the existing semi-parallel SC decoder, performing bit decision on the decoding bit index, and outputting better decoding results. Attached Figure Description
[0048] Figure 1 This is a flowchart illustrating the steps of an FPGA-based semi-parallel SC decoder implementation method according to the present invention.
[0049] Figure 2 This is a block diagram of a semi-parallel SC decoder implementation system based on FPGA according to the present invention;
[0050] Figure 3 This is a schematic diagram of the optimized semi-parallel SC decoder structure of the present invention;
[0051] Figure 4 This is a schematic diagram of the updated part and the updated module structure of the present invention;
[0052] Figure 5 This is a schematic diagram of the result of the reverse ordering module of the present invention. Detailed Implementation
[0053] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art.
[0054] Reference Figure 1 This invention provides a method for implementing a semi-parallel SC decoder based on FPGA, the method comprising the following steps:
[0055] S1. Set the decoder parameters and initialize the partial and update modules and the reverse ordering module to obtain the initialized decoder;
[0056] S11. Set the parameters of the decoder and set the fixed-point scheme of the system. The parameters of the decoder include the code length of the polar code to be decoded, the code rate of the polar code to be decoded, the system clock frequency corresponding to the decoder, the bit width of the channel input to the decoder in each clock cycle, and the number of processing units in the decoder processing unit group.
[0057] Specifically, setting the fixed-point scheme of the system determines the number of bits in the log-likelihood ratio of the decoder, and sets the decoder parameters, including setting the code length of the polar code to be decoded to N = 1024, setting the code rate of the polar code to be decoded to 0.5, setting the system clock frequency corresponding to the decoder to 100MHz, and setting the bit width of the channel input to the decoder per clock cycle to w. in =128, setting the number of processing units in the decoder processing unit group to n. PEs =16; Further configure the fixed-point scheme of the system, and set the number of fixed-point values for the log-likelihood ratio of the system to w. LLR =8, where 1 bit is the sign bit, 5 bits are the integer bits, and 2 bits are the decimal bits. The bit width of each unit in the reversed address register group is set to w. re =9.
[0058] S12. Based on the decoder parameters, initialize the partial sum update module and the reverse ordering module of the decoder to obtain the initialized partial sum update module and the initialized reverse ordering module.
[0059] S121. Based on the decoder parameters, calculate the decoded bit index using the jump column order calculation method to obtain the column number of the bit index;
[0060] Specifically, for each decoded bit index, the jump column number corresponding to each index value is first calculated using a specific method, and the calculation result is stored in the FPGA's storage resources for subsequent table lookup; the specific calculation method is as follows: for 0≤i N ≤1023, For i N [9:0] with i N +1[9:0] the highest distinct bits, The range of values is in Represents each estimated bit The next column number of the post-judgment processing unit.
[0061] S122. Based on the decoder parameters, construct the polar code of the decoder to obtain the frozen bit index of the decoder.
[0062] Specifically, based on the decoder parameters, polar codes are constructed, frozen bit indices are obtained, and the frozen bit indices are stored in the FPGA's storage resources for subsequent table lookups.
[0063] S123. Initialize the partial sum update module and the reverse ordering module of the decoder according to the decode bit index to obtain the initialized partial sum update module and the initialized reverse ordering module.
[0064] Specifically, refer to Figure 4 and Figure 5 , in i N =0 or i N =512 initializes the register set of the part and updates the module. and in Where i N This represents the current decision bit index of the semi-parallel SC decoder, 0≤i N ≤N-1, further initialize the address register [8:0]addr_re[511:0] of the reordering module, write the reordering result corresponding to the value of "i" into each addr_re[i][511:0] for table lookup, for 0≤i≤511; at the same time, initialize the result register V[511:0]=512'd0 of the reordering module.
[0065] S13. Instantiate the decoder's storage module according to the decoder's parameters, and write the decoder's log-likelihood ratio into the decoder's storage module.
[0066] Specifically, instantiating the decoder's storage module is equivalent to packaging an "instantiated element," placing a program with specific functions into the "instantiated element," and setting the output and input pins. Later, to implement the program's function, it can be directly called. Nine dual-port RAMs are instantiated, serving as the memory for the channel log-likelihood ratio and the memory for the internal log-likelihood ratio of the decoding operation, respectively. The specific method for instantiating the nine RAMs as log-likelihood ratio data memory is as follows: Instantiate the log-likelihood ratio storage module RAM1. For l=9, RAM1 serves as the channel log-likelihood ratio storage RAM, with a write bit width of w. in =128, write depth is 64, read bit width is 256, read depth is 32, and the read depth can be calculated accordingly; for 1≤l≤8, RAM1 has a write bit width of 128 and a write depth of... The read bit width is 256, and the read depth is... The external log-likelihood ratio of the decoder is written into the internal storage module.
[0067] S14. Enable the processing unit group of the decoder according to the log-likelihood ratio of the decoder to obtain the initialized decoder.
[0068] Specifically, when there is a channel log-likelihood ratio input outside the decoder and the decoder is enabled, the decoder writes the channel log-likelihood ratio into the dual-port RAM9; after N channel log-likelihood ratio values are written, the decoder enables the processing unit and reads the channel log-likelihood ratio values from RAM9 as input to the processing unit group.
[0069] S2. Based on the initialized decoder, the processing unit group performs decoding operations on the processing unit and makes bit decisions based on the operation results to obtain the decision results;
[0070] S21. Based on the initialized decoder, the processing unit group determines how many clock cycles to calculate based on the column number of the processing unit and activates the processing unit.
[0071] Specifically, refer to Figure 3 When the processing unit group is enabled, the processing unit group determines the column number l that the processing unit is currently in to determine the input source and output destination. The input source of the processing unit group is RAM l, and the output destination is RAM (l-1).
[0072] The processing unit group determines the current column number l of the processing unit to decide how many clock cycles to perform calculations in that column number state and how many processing units to activate from the group. For 4 ≤ l ≤ 9, all processing units are activated each clock cycle, and calculations are performed in that column number state. For each clock cycle of calculation, for 0≤l<4, 16 processing units are activated. The calculation for one clock cycle is performed under the current column number. The column number of the processing unit can change in two ways: First, if the column number of the processing unit at this moment is not equal to 0, then after the completion of the multiple clock cycles corresponding to this column number, a -1 operation is performed. Second, if the column number of the processing unit at this moment is equal to 0, then in the next clock cycle, a lookup table is used to jump to the jump column number corresponding to the current bit index.
[0073] S22. Determine the execution function of the processing unit group in this clock cycle based on the value of the current execution indicator function, and select the corresponding execution function;
[0074] The processing unit group determines whether to execute the f function or the g function in the current clock cycle based on the value of the current execution indicator function. If the value of the current execution indicator function is 0, the processing unit group executes the f function in the current clock cycle; if the value of the current execution indicator function is 1, the processing unit group executes the g function in the current clock cycle. If the processing unit group executes the g function, it needs to read the required part from the output of the reordering module. The currently executing instruction function is as follows:
[0075]
[0076] In the above formula, B(l,i) represents the current execution function of the processing unit group, l represents the current bit index column number of the processing unit, and i represents the decoding bit index.
[0077] S23. The corresponding execution functions include the f function and the g function;
[0078] The execution function f is shown below:
[0079] f(LLR1,LLR2)=sign(LLR1,LLR2)·min(|LLR1|,|LLR2|)
[0080] In the above formula, LLR represents the log-likelihood ratio, sign(LLR1,LLR2) indicates the determination of the positive and negative signs of LLR1 and LLR2, and min(|LLR1|,|LLR2|) indicates taking the minimum value of the absolute values of LLR1 and LLR2.
[0081] During the evaluation process of the f function, if LLR1 and LLR2 have the same sign, it returns 1; if they have different signs, it returns -1.
[0082] The g function for execution is shown below:
[0083] g(LLR1,LLR2)=LLR2+(1-2Us )·LLR1
[0084] In the above formula, U s represents the partial sum.
[0085] S24. Calculate the log-likelihood ratio of the processing unit group in this clock cycle according to the execution function, and output the value of the log-likelihood ratio;
[0086] Specifically, the processing unit group calculates the value of the log-likelihood ratio input to RAMl within one clock cycle, and writes the result into RAM(l - 1); when the processing unit group completes the operations for the above number of clock cycles, for 0 < l ≤ 9, l = l - 1, output the value of the log-likelihood ratio.
[0087] S25. Based on the frozen bit index, make a decision on the current decoded bit index according to the value of the log-likelihood ratio, and obtain the decision result.
[0088] S251. Judge the current decoded bit index;
[0089] S252. When it is judged that the current decoded bit index belongs to the frozen bit index, output the decision result as "0";
[0090] S253. When it is judged that the current decoded bit index does not belong to the frozen bit index and the column number of the processing unit is "0", judge the highest bit of the value of the log-likelihood ratio;
[0091] S254. When it is judged that the highest bit of the value of the log-likelihood ratio is "0", output the decision result as "0";
[0092] S255. When it is judged that the highest bit of the value of the log-likelihood ratio is not "0", output the decision result as "1".
[0093] Specifically, if the current decoded bit index belongs to the frozen bit index, directly judge the current decoded bit as "0", and at the same time increment the look-up table address of the frozen bit index by 1; if the current decoded bit index does not belong to the frozen bit index, when l = 0, judge the highest bit of the operation result of the processing unit. If the highest bit is "1", then judge the current decoded bit as "1", otherwise judge the current decoded bit as "0".
[0094] S3. Update and reorder the partial sum update module of the decoder in sequence according to the decision result, and output the decoding result.
[0095] S31. Update the initialized partial sum update module according to the decision result to obtain the enable value;
[0096] S32. Perform an enabling process on the initialized reverse reordering module based on the enable value;
[0097] Specifically, when the decoder outputs a bit decision result, the partial sum update module is enabled. Within one clock cycle, it updates the partial sum using a specific algorithm and enables the reverse ordering module. The specific update algorithm for the partially sum update module after initialization is as follows:
[0098]
[0099]
[0100] In the above formula, This indicates the bit index i in the partial and update modules. N The corresponding register group has a bit width of N / 2 bits. This indicates the bit index i in the partial and update modules. N +1 corresponds to the register group, where i represents the index in registers G and r. This represents the "XOR" operation. Indicates bit index i N The corresponding bit decision result, This represents a register with a bit width of N / 2.
[0101] S33. If the deordering module is enabled, the initialized part and the output value of the update module are reordered to obtain the decoding result.
[0102] Specifically, when the deordering module is enabled, the output of the partial sum update module is deordered within one clock cycle. The partial sum update result is addressed and rearranged using the address register [8:0]addr_re[511:0] of the deordering module described in step S123 above. The value of the i-th bit of the partial sum update result is assigned to the storage space corresponding to address addr_re[i]. For 0≤i≤511, after the deordering is completed, for 0≤i... N If the value is ≤1023, the processing unit group will transition to the state in the next clock cycle. If 0≤i N If i < 1023, then write it to the decoder's storage module; if i N If the value is 1023, then the output will be the decoding result of a complete code block.
[0103] Reference Figure 2 A semi-parallel SC decoder implementation system based on FPGA, comprising:
[0104] The initialization module is used to set the decoder parameters and initialize the partial update module and the reverse ordering module to obtain the initialized decoder.
[0105] The decision module, based on the initialized decoder, has the processing unit group performing decoding operations on the processing unit and making bit decisions based on the operation results to obtain the decision result;
[0106] The update module is used to update and reorder the decoder components and update module in sequence according to the decision result, and output the decoding result.
[0107] The content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.
[0108] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.
Claims
1. A method for implementing a semi-parallel SC decoder based on FPGA, characterized in that, Includes the following steps: Set the decoder parameters and initialize the partial and update modules and the reverse ordering module to obtain the initialized decoder; Based on the initialized decoder, the processing unit group performs decoding operations on the processing unit and makes bit decisions based on the operation results to obtain the decision results; Based on the judgment result, the decoder's parts and update modules are updated and reordered sequentially, and the decoding result is output; specifically including: Based on the judgment result, the initialized portion and the update module are updated to obtain the enable value; the specific update algorithm for the initialized portion and the update module is as follows: In the above formula, This indicates the bit index within the partial and update modules. The corresponding register group has a bit width of N / 2 bits. Representing the bit index in the part and update module The corresponding register set, This represents the indices in registers G and r. This represents the "XOR" operation. Represents bit index The corresponding bit decision result, This represents a register with a bit width of N / 2; The initialization of the reverse ordering module is enabled based on the enable value; Once the deordering module is detected as enabled, the initialized part and the output value of the update module are reordered to obtain the decoding result.
2. The method for implementing a semi-parallel SC decoder based on FPGA according to claim 1, characterized in that, The step of setting the decoder parameters and initializing the partial update module and the reverse ordering module to obtain the initialized decoder specifically includes: Set the parameters of the decoder and set the fixed-point scheme of the system. The parameters of the decoder include the code length of the polar code to be decoded, the code rate of the polar code to be decoded, the system clock frequency corresponding to the decoder, the bit width of the channel input to the decoder in each clock cycle, and the number of processing units in the decoder processing unit group. Based on the decoder parameters, initialize the decoder's partial sum update module and reverse ordering module to obtain the initialized partial sum update module and the initialized reverse ordering module; Based on the decoder's parameters, the decoder's storage module is instantiated, and the decoder's log-likelihood ratio is written into the decoder's storage module. Based on the log-likelihood ratio of the decoder, the processing unit group of the decoder is enabled to obtain the initialized decoder.
3. The method for implementing a semi-parallel SC decoder based on FPGA according to claim 2, characterized in that, The step of initializing the partial sum update module and the reverse ordering module of the decoder according to the decoder parameters to obtain the initialized partial sum update module and the initialized reverse ordering module specifically includes: Based on the decoder parameters, the decoded bit index is calculated using the jump column order calculation method to obtain the column number of the bit index; Based on the decoder's parameters, the decoder's polar code is constructed to obtain the decoder's frozen bit index; The decoder's partial sum update module and reverse ordering module are initialized based on the decoded bit index, resulting in the initialized partial sum update module and the initialized reverse ordering module.
4. The method for implementing a semi-parallel SC decoder based on FPGA according to claim 3, characterized in that, The step of processing unit group performing decoding operations on processing units based on the initialized decoder, and performing bit decision based on the operation results to obtain the decision result specifically includes: Based on the initialized decoder, the processing unit group determines how many clock cycles to calculate and activates the processing unit according to the column number of the processing unit. The value of the current execution indicator function is used to determine the execution function of the processing unit group in this clock cycle, and the corresponding execution function is selected. The corresponding execution functions include functions and function; Based on the execution function, the log-likelihood ratio of the processing unit group under that clock cycle is calculated, and the value of the log-likelihood ratio is output. Based on the frozen bit index, a decision is made on the current decoded bit index according to the value of the log-likelihood ratio, and the decision result is obtained.
5. The method for implementing a semi-parallel SC decoder based on FPGA according to claim 4, characterized in that, The currently executing instruction function is as follows: In the above formula, This indicates the currently executing function of the processing unit group. This indicates the current bit index column number of the processing unit. This indicates the decoded bit index.
6. The method for implementing a semi-parallel SC decoder based on FPGA according to claim 5, characterized in that, The step of determining the current decoded bit index based on the value of the log-likelihood ratio, based on the frozen bit index, to obtain the decision result specifically includes: Determine the current decoded bit index; If the current decoded bit index is determined to be a frozen bit index, the output decision result is "0"; When it is determined that the current decoded bit index does not belong to the frozen bit index and the column number of the processing unit is "0", the highest bit of the log-likelihood ratio is judged. If the highest bit of the log-likelihood ratio is "0", output the decision result as "0". If the highest bit of the log-likelihood ratio is not "0", the output decision result is "1".
7. The method for implementing a semi-parallel SC decoder based on FPGA according to claim 6, characterized in that, The execution function The function is shown below: In the above formula, express The corresponding parts and, It represents the log-likelihood ratio.
8. A semi-parallel SC decoder implementation system based on FPGA, characterized in that, Includes the following modules: The initialization module is used to set the decoder parameters and initialize the partial update module and the reverse ordering module to obtain the initialized decoder. The decision module, based on the initialized decoder, has the processing unit group performing decoding operations on the processing unit and making bit decisions based on the operation results to obtain the decision result; The update module is used to update and reorder parts of the decoder and the update module sequentially according to the decision result, and output the decoding result; specifically, it includes: Based on the judgment result, the initialized portion and the update module are updated to obtain the enable value; the specific update algorithm for the initialized portion and the update module is as follows: In the above formula, This indicates the bit index within the partial and update modules. The corresponding register group has a bit width of N / 2 bits. Representing the bit index in the part and update module The corresponding register set, This represents the indices in registers G and r. This represents the "XOR" operation. Represents bit index The corresponding bit decision result, This represents a register with a bit width of N / 2; The initialization of the reverse ordering module is enabled based on the enable value; Once the deordering module is detected as enabled, the initialized part and the output value of the update module are reordered to obtain the decoding result.