A tdc-based false target augmentation system

Abstract

The application provides a false target supplement system based on a TDC, comprising a photoelectric collection circuit module, which is used for sending a sampling signal to a logic gate circuit module and a TDC circuit module; a timer circuit module, which is used for sending a continuous pulse signal to the logic gate circuit module; the logic gate circuit module, which is used for supplementing the number of targets of an echo signal by using the sampling signal and the pulse signal, and then sending the supplemented echo signal to the TDC circuit module; and the TDC circuit module, which is used for receiving the signals sent by the logic gate circuit module and the photoelectric collection circuit module. The application supplements the echo signal returned by the target without affecting the real target, so that the TDC chip can collect the set number of targets and calculate the distance of multiple targets.

Description

Technical Field

[0001] This invention belongs to the field of time-to-digital converters (TDC), and particularly relates to a dummy target supplementation system based on TDC. Background Technology

[0002] The method of acquiring target distance information using TDC chips is gaining increasingly widespread application, especially in the field of ranging. It uses the moment of light emission as the start of time calculation and the echo signal from the first target as the stop time. The time difference between these two moments is the time of flight of light, from which distance can be calculated. This method is widely used in ranging.

[0003] Patents 201420829174.4 and 20192007354.0 provide application solutions in terms of connection methods, ranging methods, and error calculation. However, these patents mainly protect the method of supplementing a single target into multiple targets in a multi-target measurement mode using a TDC chip without affecting the ranging of multiple targets. They do not cover specific details such as data processing and the connection method of the ranging system.

[0004] TDC (Target Divergence Control) is primarily used in high-precision rangefinders. It has a limitation on the number of targets it can simultaneously acquire, and once the target number is set, it can only acquire that fixed number of targets; targets fewer than the set number are not acquired. Currently available TDC chips can perform single-target and multi-target measurements. However, in multi-target measurement mode, if only a single target is returned, the TDC chip cannot respond, thus failing to achieve accurate measurements for both single and multiple targets. Summary of the Invention

[0005] This invention addresses the technical problems existing in the prior art by providing a TDC-based false target supplementation system. Without affecting the real target, the system supplements the target echo, enabling the TDC chip to collect the set number of targets.

[0006] The technical solution adopted in this invention is: a pseudo-target supplementation system based on TDC, comprising:

[0007] The photoelectric acquisition circuit module is used to send sampling signals to the logic gate circuit module and the TDC circuit module;

[0008] The timer circuit module is used to send continuous pulse signals to the logic gate circuit module;

[0009] The logic gate circuit module is used to supplement the echo signal with the target quantity using the sampling signal and the pulse signal, and then send the supplemented echo signal to the TDC circuit module.

[0010] The TDC circuit module is used to receive signals sent by the logic gate circuit module and the photoelectric acquisition circuit module.

[0011] Preferably, the logic gate circuit module uses an OR gate to form an additional false target using the sampled signal and the pulse signal. The additional false target is located after the echo signal of the target.

[0012] Preferably, the pulse signal emitted by the timer circuit module is a square wave.

[0013] Preferably, the circuit structure of the logic gate module is as follows: pins 1 and 2 of the OR gate chip N1 are input pins, connected to the sampling signal of the photoelectric acquisition circuit module and the pulse signal of the timer circuit module, respectively; pin 5 of the OR gate chip N1 is a power supply pin connected to +5V; pin 3 of the OR gate chip N1 is a ground pin, directly connected to ground; pin 4 of the OR gate chip N1 is an output pin, connected to the base (b) of transistor Q1 through resistor R8; the emitter (e) of transistor Q1 is grounded, and the collector (C) of transistor Q1 is connected to +5V through resistor R6, and simultaneously connected to pin 1 of the OR gate chip N3 through resistor R7; pin 2 of the OR gate chip N3 is an input pin, connected to the received echo signal; pin 4 of the OR gate chip N3 is an output pin, connected to the TDC circuit module; pin 5 of the OR gate chip N3 is a power supply pin connected to +5V; pin 3 of the OR gate chip N3 is a ground pin, directly connected to ground.

[0014] Preferably, the circuit structure of the timer circuit module is as follows: pin 1 of the timer chip N2 is grounded, and pin 5 is grounded through capacitor C1; pins 4 and 8 of the timer chip N2 are connected to +5V; pins 2 and 6 of the timer chip N2 are connected to ground through capacitor C2; pin 7 of the timer chip N2 is connected to +5V through resistor R1, and is also connected to pin 2 through resistor R3; pin 3 of the timer chip N2 is an output pin; the timer chip N2 uses GCM7555.

[0015] Preferably, the circuit structure of the photoelectric acquisition circuit module is as follows: pins 3 and 16 of the monostable chip D4A are connected to +5V; pins 8 and 1 of the monostable chip D4A are grounded; pin 15 of the monostable chip D4A is connected to pin 14 through capacitor C47 and grounded, and connected to +5V through resistor R52; pin 2 of the monostable chip D4A is the input pin of the monostable chip, and pin 2 is connected to the anode of diode D1 through resistors R58 and C49; the cathode of diode D1 is connected to +5V through resistor R50; the anode of light-emitting diode D6 is connected to pin 3 of the monostable chip D4A; the cathode of light-emitting diode D6 is connected to pin 4 of the monostable chip D4A through resistor R66; pin 13 of the monostable chip D4A is the output pin; the monostable chip D4A uses SN74LS123.

[0016] Preferably, the circuit structure of the TDC circuit module is as follows: pin 1 of TDC chip U1 is an active crystal oscillator input pin, connected to pin 3 of crystal oscillator B1 through a series resistor R9 and C5; pins 3 and 22 of TDC chip U1 are the power supply input terminals of the chip's I / O ports, connected to +5V; pins 4, 16, 17, 21, and 28 of TDC chip U1 are connected to ground; pin 7 of TDC chip U1 is connected to ground through R11; pin 26 of TDC chip U1 is connected to... Resistor R2 is connected to 3.3V; pin 32 of TDC chip U1 is connected to 3.3V through resistor R4; pin 31 of TDC chip U1 is connected to the photoelectric acquisition circuit module; pin 30 of TDC chip U1 is connected to the logic gate circuit module; pins 14 and 29 of TDC chip U1 are power supply pins connected to 3.3V; pin 13 of TDC chip U1 is connected to 3.3V through resistor R10 and grounded through capacitor C6; pins 8, 9, and 10 of TDC chip U1 are connected to the main control chip.

[0017] Working Principle: A false target is added without affecting the target signal return time. That is, a certain number of signals appear after a period of time following the target's echo signal, serving as false targets. The logic gate module ORs the photoelectric acquisition circuit module signal CYO and the timer circuit module signal OUT555 to form signal Q555. This Q555 signal is then inverted and ORed with the returned echo signal SigBack0 to form signal SigBack1, adding the false target after the original returned target. The addition of false targets is independent of the number of original returned targets and does not affect the original returned targets. When the TDC chip is set to multi-target acquisition, it can still correctly detect a single target, achieving simultaneous detection of single and multiple targets. Furthermore, the signal response speed is fast and does not depend on the error caused by the crystal oscillator when generating digital signals. The timer circuit module emits a continuous pulse signal with a fixed frequency. The output frequency and duty cycle of the pulse signal are controlled by internal capacitors and resistors, unaffected by the crystal oscillator.

[0018] Compared with the prior art, the beneficial effects of this invention are:

[0019] 1. This invention supplements the returned targets without affecting the actual targets, enabling the TDC chip to collect the set number of targets.

[0020] 2. This invention achieves fast signal response time through the construction of analog circuits.

[0021] 3. Compared with traditional embedded chips that generate supplementary signals, this invention has a stable signal output, does not depend on the generation of crystal oscillators, and reduces the error introduced during crystal oscillation. Attached Figure Description

[0022] Figure 1 This is a structural block diagram of an embodiment of the present invention;

[0023] Figure 2 This is a circuit diagram of the photoelectric acquisition circuit module according to an embodiment of the present invention;

[0024] Figure 3 This is a circuit diagram of the timer circuit module according to an embodiment of the present invention;

[0025] Figure 4 The circuit diagram is shown for the logic gate circuit module of an embodiment of the present invention;

[0026] Figure 5 This is a circuit diagram of the TDC circuit module according to an embodiment of the present invention;

[0027] Figure 6 This is a timing diagram of the signal supplementation process in an embodiment of the present invention.

[0028] In the diagram, 1-photoelectric acquisition circuit module, 2-timer circuit module, 3-logic gate circuit module, 4-TDC circuit module. Detailed Implementation

[0029] To enable those skilled in the art to better understand the technical solution of the present invention, the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0030] Embodiments of the present invention provide a TDC-based dummy target augmentation system, such as... Figure 1 As shown, it includes a photoelectric acquisition circuit module 1, which is used to send sampling signals to the logic gate circuit module and the TDC circuit module;

[0031] Timer circuit module 2 is used to send continuous pulse signals to the logic gate circuit module; the pulse signal sent by the timer circuit module is a square wave.

[0032] The logic gate circuit module 3 is used to supplement the target quantity of the return signal using the sampled signal and the pulse signal, and then send the supplemented signal to the TDC circuit module; the logic gate circuit module adopts an OR gate, and uses the sampled signal and the pulse signal to form the supplemented false target, which is after the target's echo signal.

[0033] TDC circuit module 4 is used to receive signals sent by the logic gate circuit module and the photoelectric acquisition circuit module.

[0034] like Figure 2As shown, the circuit structure of the photoelectric acquisition circuit module 1 is as follows: pins 3 and 16 of the monostable chip D4A are connected to +5V; pins 8 and 1 of the monostable chip D4A are grounded; pin 15 of the monostable chip D4A is connected to pin 14 through capacitor C47 and grounded, and connected to +5V through resistor R52; pin 2 of the monostable chip D4A is the input pin of the monostable chip, and pin 2 is connected to the anode of diode D1 through resistors R58 and C49; the anode of diode D1 is grounded through resistor R56; the cathode of diode D1 is connected to +5V through resistor R50 and grounded through capacitor C45; the anode of light-emitting diode D6 is connected to pin 3 of the monostable chip D4A; the cathode of light-emitting diode D6 is connected to pin 4 of the monostable chip D4A through resistor R66; pin 13 of the monostable chip D4A is the output pin, outputting the signal CYO. The monostable chip D4A uses SN74LS123. The rise rate of the signal acquired by diode D1 can be adjusted by resistors R58 and R50, capacitors C49 and C45.

[0035] like Figure 3 As shown, the circuit structure of the timer circuit module 2 is as follows: pin 1 of the timer chip N2 is grounded, and pin 5 is grounded through capacitor C1; pins 4 and 8 of the timer chip N2 are connected to +5V; pins 2 and 6 of the timer chip N2 are connected to ground through capacitor C2; pin 7 of the timer chip N2 is connected to +5V through resistor R1, and is also connected to pin 2 through resistor R3. Pin 3 of the timer chip N2 is an output pin, outputting a OUT555 signal. The timer chip N2 uses a GCM7555. The signal output frequency and duty cycle of pin 3 of the timer chip N2 can be controlled by resistors R1 and R3, and capacitors C1 and C2.

[0036] like Figure 4As shown, the circuit structure of the logic gate module 3 is as follows: pin 1 of the OR gate chip N1 is an input pin, connected to pin 3 of the timer chip N2, inputting signal OUT555; pin 2 of the OR gate chip N1 is an input pin, connected to pin 13 of the monostable multivibrator chip D4, inputting signal CYO; pin 4 of the OR gate chip N1 is an output pin, connected to the base of transistor Q1 through resistor R8, outputting signal Q555 to the base of transistor Q1; pin 5 of the OR gate chip N1 is a power supply pin connected to +5V; pin 3 of the OR gate chip N1 is a ground pin. The transistor Q1 is directly connected to ground; its emitter (e) is grounded; the collector (C) of transistor Q1 is connected to +5V via resistor R6, and simultaneously connected to pin 1 of OR gate chip N3 via resistor R7, outputting the signal Q555N to pin 1 of OR gate chip N3; pin 2 of OR gate chip N3 is an input pin, connected to the received echo signal SigBack0; pin 4 of OR gate chip N3 is an output pin, outputting the signal SigBack1; pin 5 of OR gate chip N3 is a power supply pin connected to +5V; pin 3 of OR gate chip N3 is a ground pin, directly connected to ground. OR gate chips N1 and N2 are TC7S32F.

[0037] like Figure 5 As shown, the circuit structure of the TDC circuit module 4 is as follows: pin 1 of the TDC chip U1 is an active crystal oscillator input pin, connected to pin 3 of the crystal oscillator B1 through a series resistor R9 and C5; pins 3 and 22 of the TDC chip U1 are the power supply input terminals of the chip's I / O port, connected to +5V; pins 4, 16, 17, 21, and 28 of the TDC chip U1 are connected to ground; pin 7 of the TDC chip U1 is connected to ground through R11; pin 26 of the TDC chip U1 is connected to 3.3V through a resistor R2; the TDC chip U... Pin 32 of TDC chip U1 is connected to 3.3V via resistor R4; pin 31 of TDC chip U1 is connected to pin 13 of monostable chip D4A via resistor R57, input signal CYO; pin 30 of TDC chip U1 is connected to pin 4 of OR gate N3, input signal SigBack1; pins 14 and 29 of TDC chip U1 are power supply pins connected to 3.3V; pin 13 of TDC chip U1 is connected to 3.3V via resistor R10 and grounded via capacitor C6; pins 8, 9, and 10 of TDC chip U1 are connected to the main control chip.

[0038] During signal supplementation, the waveforms of signals CYO, OUT555, Q555, Q555N, SigBack0, and SigBack1 are as follows: Figure 6As shown. SigBack1 is the signal supplemented by SigBack0. The TDC chip starts working from the rising edge of the CYO signal. Only the waveform within the dashed box of the SigBack1 signal is recognized by the TDC pin 31 STOP1. No matter how many pulses SigBack0 has, the number of pulses input to the TDC pin 31 will always be more than the set number of pulses, thus completing the supplementation of the SigBack0 signal.

[0039] The aforementioned chips can also be replaced with similar chips, with the circuit structure adjusted accordingly.

[0040] The present invention has been described in detail above through embodiments, but the content described is only an exemplary embodiment of the present invention and should not be considered as limiting the scope of the present invention. The scope of protection of the present invention is defined by the claims. Any technical solutions designed by those skilled in the art using the technical solutions described in the present invention, or designed by those skilled in the art under the inspiration of the technical solutions of the present invention, within the substance and protection scope of the present invention, to achieve the above-mentioned technical effects, or any equivalent changes and improvements made to the scope of the application, should still fall within the patent protection scope of the present invention.

Claims

1. A pseudo-target supplementation system based on TDC, characterized in that: include The photoelectric acquisition circuit module is used to send sampling signals to the logic gate circuit module and the TDC circuit module; The timer circuit module is used to send continuous pulse signals to the logic gate circuit module; The logic gate circuit module is used to supplement the number of targets in the echo signal using the sampling signal and the pulse signal, and then send the supplemented echo signal to the TDC circuit module; the logic gate circuit module uses an OR gate to form a supplemented false target using the sampling signal and the pulse signal, and the supplemented false target is after the target's echo signal; The TDC circuit module is used to receive signals sent by the logic gate circuit module and the photoelectric acquisition circuit module. The circuit structure of the TDC circuit module is as follows: pin 1 of the TDC chip U1 is an active crystal oscillator input pin, connected to pin 3 of the crystal oscillator B1 through a series resistor R9 and C5; pins 3 and 22 of the TDC chip U1 are the power supply input terminals for the chip's I / O ports, connected to +5V; pins 4, 16, 17, 21, and 28 of the TDC chip U1 are connected to ground; pin 7 of the TDC chip U1 is connected to ground through resistor R11. TDC chip U1 pin 26 is connected to 3.3V through resistor R2; TDC chip U1 pin 32 is connected to 3.3V through resistor R4; TDC chip U1 pin 31 is connected to the photoelectric acquisition circuit module; TDC chip U1 pin 30 is connected to the logic gate circuit module; TDC chip U1 pins 14 and 29 are power supply pins connected to 3.3V; TDC chip U1 pin 13 is connected to 3.3V through resistor R10 and grounded through capacitor C6; TDC chip U1 pins 8, 9, and 10 are connected to the main control chip.

2. The TDC-based false target supplementation system as described in claim 1, characterized in that: The pulse signal emitted by the timer circuit module is a square wave.

3. The TDC-based false target supplementation system as described in claim 1, characterized in that: The circuit structure of the logic gate circuit module is as follows: pins 1 and 2 of OR gate chip N1 are input pins, connected to the sampling signal of the photoelectric acquisition circuit module and the pulse signal of the timer circuit module, respectively; pin 5 of OR gate chip N1 is a power supply pin connected to +5V; pin 3 of OR gate chip N1 is a ground pin, directly connected to ground; pin 4 of OR gate chip N1 is an output pin, connected to the base (b) of transistor Q1 through resistor R8; the emitter (e) of transistor Q1 is grounded, and the collector (C) of transistor Q1 is connected to +5V through resistor R6, and simultaneously connected to pin 1 of OR gate chip N3 through resistor R7; pin 2 of OR gate chip N3 is an input pin, connected to the received return signal; pin 4 of OR gate chip N3 is an output pin, connected to the TDC circuit module; pin 5 of OR gate chip N3 is a power supply pin connected to +5V; pin 3 of OR gate chip N3 is a ground pin, directly connected to ground.

4. The TDC-based false target supplementation system as described in claim 1, characterized in that: The circuit structure of the timer circuit module is as follows: pin 1 of timer chip N2 is grounded, and pin 5 is grounded through capacitor C1; pins 4 and 8 of timer chip N2 are connected to +5V; pins 2 and 6 of timer chip N2 are connected to ground through capacitor C2; pin 7 of timer chip N2 is connected to +5V through resistor R1, and is also connected to pin 2 through resistor R3; pin 3 of timer chip N2 is an output pin; the timer chip N2 uses GCM7555.

5. The TDC-based dummy target supplementation system as described in claim 1, characterized in that: The circuit structure of the photoelectric acquisition circuit module is as follows: pins 3 and 16 of the monostable chip D4A are connected to +5V; pins 8 and 1 of the monostable chip D4A are grounded; pin 15 of the monostable chip D4A is connected to pin 14 through capacitor C47 and grounded, and connected to +5V through resistor R52; pin 2 of the monostable chip D4A is the input pin of the monostable chip, and pin 2 is connected to the anode of diode D1 through resistors R58 and C49; the cathode of diode D1 is connected to +5V through resistor R50; the anode of light-emitting diode D6 is connected to pin 3 of the monostable chip D4A; the cathode of light-emitting diode D6 is connected to pin 4 of the monostable chip D4A through resistor R66; pin 13 of the monostable chip D4A is the output pin; the monostable chip D4A uses SN74LS123.

Images