Display device

Abstract

A display device is provided. A high-resolution display device configured to display high-quality images includes an organic light emitting diode, a driving transistor configured to control an amount of current flowing from a second node to the organic light emitting diode according to a voltage applied to a first node, the second node electrically connected to a power voltage line, and a first bottom metal layer disposed under the driving transistor and electrically connected to the driving transistor.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and benefit to Korean Patent Application No. 10-2020-0188077, filed on December 30, 2020, which is incorporated herein by reference for all purposes as if fully set forth herein. Technical Field

[0003] The embodiments generally relate to display devices, and more specifically, to high-resolution display devices capable of displaying high-quality images. Background Technology

[0004] Typically, a display device includes multiple pixels. Each pixel includes a display element and pixel circuitry configured to control the display element. The pixel circuitry includes thin-film transistors (TFTs) and storage capacitors.

[0005] In order to control whether the display element emits light and to accurately control the degree of light emission, the number of transistors electrically connected to a display element has been increased.

[0006] The information disclosed in this background section is only for understanding the background of the inventive concept, and therefore may contain information that does not constitute prior art. Summary of the Invention

[0007] However, in display devices based on related technologies, high-quality images are not easy to display or the layered structure is complex.

[0008] One or more embodiments include a high-resolution display device capable of displaying high-quality images. However, such technical problems are examples, and this disclosure is not limited thereto.

[0009] Additional features of the inventive concept will be set forth in the description which follows, and will be apparent in part from the description, or may be learned by practice of the inventive concept.

[0010] According to one or more embodiments, a display device includes: an organic light-emitting diode; a driving transistor configured to control the amount of current flowing from a second node to the organic light-emitting diode based on a voltage applied to a first node, the second node being electrically connected to a power supply voltage line; and a first bottom metal layer disposed below the driving transistor and electrically connected to the driving transistor.

[0011] The display device may further include a first initialization transistor connected between a first node and a first initialization voltage line, wherein a first bottom metal layer can electrically connect a driving transistor to the first initialization transistor.

[0012] The driving semiconductor layer of the driving transistor and the first initialization semiconductor layer of the first initialization transistor can be disposed in different layers.

[0013] The first initialization semiconductor layer can be disposed on an insulating layer covering the driving gate electrode of the driving transistor.

[0014] The display device may further include a connection electrode disposed on the first initialization semiconductor layer and connected to the first bottom metal layer through a contact hole.

[0015] When viewed from a direction perpendicular to the first bottom metal layer, the first bottom metal layer may overlap with the first initial semiconductor layer.

[0016] The driving semiconductor layer may include a silicon semiconductor, and the first initialization semiconductor layer may include an oxide semiconductor.

[0017] The driving gate electrode of the driving transistor can be electrically connected to the first bottom metal layer.

[0018] The driving gate electrode can be disposed on the driving semiconductor layer of the driving transistor and connected to the first bottom metal layer through contact holes defined in the insulating layer between the driving semiconductor layer and the driving gate electrode and in the insulating layer between the first bottom metal layer and the driving semiconductor layer.

[0019] The driving semiconductor layer can be bent to surround a portion of the contact hole.

[0020] The display device may further include: an emission control transistor connected between the driving transistor and the organic light-emitting diode and turned on when an emission control signal is supplied through the emission control line; a second initialization transistor connected between the emission control transistor and the second initialization voltage line; and a second bottom metal layer disposed below the emission control transistor and the second initialization transistor and electrically connecting the emission control transistor to the second initialization transistor.

[0021] The emitter control semiconductor layer of the emitter control transistor and the second initialization semiconductor layer of the second initialization transistor can be disposed in different layers.

[0022] The second initialization semiconductor layer can be disposed on top of the insulating layer covering the emitter control gate electrode of the emitter control transistor.

[0023] The display device may further include: a first connection electrode disposed on the second initialization semiconductor layer and electrically connected to the second initialization semiconductor layer through a contact hole; and a second connection electrode disposed in the same layer as the first connection electrode and connected to the emission control semiconductor layer through a contact hole.

[0024] The emission control semiconductor layer may include a silicon semiconductor, and the second initialization semiconductor layer may include an oxide semiconductor.

[0025] The second bottom metal layer can be disposed in the same layer as the first bottom metal layer.

[0026] The display device may further include: a storage capacitor connected between a first node and a power supply voltage line and including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode and the driving gate electrode of a driving transistor are integrally formed into a single unit, and the second capacitor electrode is disposed on the first capacitor electrode; an operation control transistor connected between the driving transistor and the power supply voltage line and turned on when a transmit control signal is supplied through the transmit control line; and a third bottom metal layer disposed below the operation control transistor and electrically connecting the operation control transistor to the second capacitor electrode.

[0027] The display device may further include a connection electrode disposed in the same layer as the second capacitor electrode and connecting the operation control semiconductor layer of the operation control transistor to the third bottom metal layer, wherein the second capacitor electrode may be electrically connected to the third bottom metal layer.

[0028] According to one or more embodiments, a display device includes: a substrate; a first active layer including a driving semiconductor layer disposed on the substrate; a first gate layer including a driving gate electrode disposed on the driving semiconductor layer; an organic light-emitting diode, wherein the brightness of the organic light-emitting diode is controlled by a current flowing through the driving semiconductor layer based on a voltage applied to the driving gate electrode; and a bottom metal layer disposed below the first active layer and including the first bottom metal layer connected to the driving gate electrode.

[0029] The first gate layer may further include a first source electrode or a first drain electrode that contacts the first active layer.

[0030] The first source electrode or the first drain electrode can contact the first wiring of the bottom metal layer.

[0031] The display device may further include: a second active layer disposed above the first gate layer and including a first initialization semiconductor layer; a second gate layer disposed between the first gate layer and the second active layer and including a bottom initialization line having a portion overlapping with the first initialization semiconductor layer; and a third gate layer disposed above the second active layer and including a top initialization line having a portion overlapping with the first initialization semiconductor layer, wherein the first bottom metal layer can electrically connect a driving gate electrode to the first initialization semiconductor layer.

[0032] The display device may further include a source / drain layer disposed on the third gate layer and including a connection electrode that connects the first initialization semiconductor layer to the first bottom metal layer through a contact hole.

[0033] When viewed from a direction perpendicular to the substrate, the first bottom metal layer may overlap with the first initial semiconductor layer.

[0034] The first active layer may include a silicon semiconductor, and the second active layer may include an oxide semiconductor.

[0035] The first active layer may further include an emission control semiconductor layer, the second active layer may further include a second initialization semiconductor layer, and the bottom metal layer may further include a second bottom metal layer that electrically connects the emission control semiconductor layer to the second initialization semiconductor layer.

[0036] The third gate layer may further include a first connection electrode and a second connection electrode, wherein the first connection electrode connects the second initialization semiconductor layer to the second bottom metal layer through a contact hole, and the second connection electrode connects the emission control semiconductor layer to the second bottom metal layer through a contact hole.

[0037] The second gate layer may further include a second source electrode or a second drain electrode that contacts the second active layer.

[0038] The second source electrode or the second drain electrode can contact the second wiring of the bottom metal layer.

[0039] The third gate layer may further include a first source electrode or a first drain electrode that contacts the first active layer and a second source electrode or a second drain electrode that contacts the second active layer.

[0040] The first source electrode or the first drain electrode may contact the first wiring of the bottom metal layer, and the second source electrode or the second drain electrode may contact the second wiring of the bottom metal layer.

[0041] The drive gate electrode can be connected to the first bottom metal layer through contact holes defined in the insulating layer between the first active layer and the first gate layer and in the insulating layer between the first bottom metal layer and the first active layer.

[0042] The driving semiconductor layer can be bent to surround a portion of the contact hole.

[0043] The display device may further include a second gate layer disposed above the first gate layer and including a second capacitor electrode that at least partially overlaps with the driving gate electrode, wherein the first active layer may further include an operation control semiconductor layer, wherein the first gate layer may further include a bottom emission control line that overlaps with the operation control semiconductor layer, and wherein the bottom metal layer may further include a third bottom metal layer that electrically connects the operation control semiconductor layer to the second capacitor electrode.

[0044] The second gate layer may further include a connection electrode that connects the operation control semiconductor layer to the third bottom metal layer, and the second capacitor electrode may be connected to the third bottom metal layer.

[0045] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments, drawings, and claims.

[0046] It should be understood that both the foregoing general description and the following detailed description are exemplary and illustrative, and are intended to provide further explanation of the claimed invention. Attached Figure Description

[0047] The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept. In the drawings:

[0048] Figure 1 This is a conceptual diagram illustrating an organic light-emitting display device according to an embodiment;

[0049] Figure 2 yes Figure 1 The equivalent circuit diagram of the pixels of the display device in the image;

[0050] Figure 3 It shows the driver Figure 2 Waveform diagram of the pixel method in the image;

[0051] Figure 4 It is shown Figure 2 A layout diagram showing the positions of transistors and capacitors in the pixels;

[0052] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 and Figure 11 Such as Figure 4 A layout diagram of each layer of transistors and capacitors;

[0053] Figure 12 It is along Figure 4 A cross-sectional view of the display device taken by lines A-A', B-B', and C-C';

[0054] Figure 13 This is a cross-sectional view showing a portion of a display device according to an embodiment;

[0055] Figure 14 This is a cross-sectional view showing a portion of a display device according to an embodiment;

[0056] Figure 15 yes Figure 14 A conceptual side view of a portion of a display device;

[0057] Figure 16This is a cross-sectional view showing a portion of a display device according to an embodiment;

[0058] Figure 17 This is a cross-sectional view showing a portion of a display device according to an embodiment;

[0059] Figure 18 This is a cross-sectional view showing a portion of a display device according to an embodiment;

[0060] Figure 19 This is a cross-sectional view showing a portion of a display device according to an embodiment;

[0061] Figure 20 This is an equivalent circuit diagram showing the pixels of a display device according to an embodiment;

[0062] Figure 21 It is shown Figure 20 A layout diagram showing the positions of transistors and capacitors in the pixels;

[0063] Figure 22 , Figure 23 , Figure 24 , Figure 25 , Figure 26 , Figure 27 and Figure 28 Such as Figure 21 A layout diagram of each layer of transistors and capacitors;

[0064] Figure 29 It is along Figure 21 A cross-sectional view of the display device taken by lines D-D', E-E', and F-F'; and

[0065] Figure 30 This is a cross-sectional view showing a portion of a display device according to an embodiment. Detailed Implementation

[0066] In the following description, numerous specific details are set forth for purposes of explanation in order to provide a thorough understanding of various exemplary embodiments or implementations of the invention. As used herein, “embodiment” and “implementation” are interchangeable terms and are non-limiting examples employing one or more inventive concepts disclosed herein. However, it will be apparent that various exemplary embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are illustrated in block diagram form to avoid unnecessarily obscuring the various exemplary embodiments. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and features of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0067] Unless otherwise specified, the exemplary embodiments shown should be understood as providing exemplary features of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise specified, features, components, modules, layers, films, panels, areas and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0068] The use of crosshairs and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Therefore, unless otherwise specified, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for a particular material, material properties, size, scale, commonalities between the elements shown, or any other characteristics, properties, etc., of the elements. Furthermore, in the drawings, the size and relative size of elements may be exaggerated for clarity and / or descriptive purposes. When exemplary embodiments can be implemented differently, a particular process sequence may be performed differently than the described sequence. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Moreover, the same reference numerals denote the same elements.

[0069] When an element, such as a layer, is referred to as being "on" another element, "connected to," or "coupled to" another element, the element may be directly on, connected to, or coupled to that other element, or an intermediary element may be present. However, when an element is referred to as being "directly on" another element, "directly connected to," or "directly coupled to" another element, an intermediary element is not present. Therefore, the term "connection" can refer to a physical, electrical, and / or fluid connection, with or without an intermediary element. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items.

[0070] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, the first element discussed below may be referred to as the second element without departing from the teachings of this disclosure.

[0071] Spatial relative terms such as “below,” “under,” “below,” “down,” “above,” “above,” “higher,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes and thus to describe the relationship of one element to another(s) as shown in the accompanying drawings. Spatial relative terms are intended to cover different orientations of the device in use, operation, and / or manufacture, other than those depicted in the drawings. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will be oriented “above” other elements or features. Thus, the exemplary term “below” can cover both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatial relative descriptive terms used herein should be interpreted accordingly.

[0072] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. Furthermore, when used in this specification, the terms “comprising,” “including,” “containing,” and / or “having” designate the presence of said features, integrals, steps, operations, elements, components, and / or groups thereof, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof. It should also be noted that, as used herein, the terms “substantially,” “about,” and other similar terms are used as approximate terms rather than terms of degree, and are therefore used to explain the inherent biases in measurements, calculated values, and / or provided values ​​that will be recognized by those skilled in the art.

[0073] Various exemplary embodiments are described herein with reference to cross-sectional and / or exploded views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Consequently, the exemplary embodiments disclosed herein should not necessarily be construed as limited to the shapes of specific illustrated areas, but rather include, for example, deviations in shape due to manufacturing processes. In this way, the areas shown in the figures may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and are therefore not necessarily intended to be limiting.

[0074] As is customary in the art, exemplary embodiments are described and illustrated in the accompanying drawings from the perspective of functional blocks, units, and / or modules. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, etc.) that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or can be implemented as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Furthermore, each block, unit, and / or module in some exemplary embodiments may be physically divided into two or more interactive and discrete blocks, units, and / or modules without departing from the scope of the inventive concept. Furthermore, some exemplary embodiments of blocks, units, and / or modules can be physically combined into more complex blocks, units, and / or modules without departing from the scope of the inventive concept.

[0075] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure is part, and terms such as those defined in common dictionaries shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0076] Figure 1 This is a conceptual diagram illustrating an organic light-emitting display device according to an embodiment.

[0077] The display device according to the embodiments can be implemented as an electronic device such as a smartphone, mobile phone, navigation device, game console, television, head unit for automobiles, notebook computer, laptop computer, tablet computer, personal multimedia player (PMP), and personal digital assistant (PDA). Additionally, the electronic device can be a flexible device.

[0078] An organic light-emitting display device according to an embodiment includes a display area DA, a scan driver SD, a data driver DD, and a timing controller TC. The display area DA includes pixels PX. The timing controller TC is configured to control the scan driver SD and the data driver DD.

[0079] The scan driver SD is configured to supply scan signals GW[1] to GW[n], initialization signals GI[1] to GI[n], compensation control signals GC[1] to GC[n], and transmit control signals EM[1] to EM[n] to a scan line extending in the first direction DR1 under the control of the timing controller TC. As an example, the scan driver SD sequentially supplies scan signals GW[1] to GW[n], initialization signals GI[1] to GI[n], compensation control signals GC[1] to GC[n], and transmit control signals EM[1] to EM[n] to the scan line, initialization line, compensation control line, and transmit control line, respectively.

[0080] Each of the scan signals GW[1] to GW[n], the initialization signals GI[1] to GI[n], the compensation control signals GC[1] to GC[n], and the transmit control signals EM[1] to EM[n] can have a high voltage or a low voltage. Depending on the characteristics of the transistor, each transistor can be turned on when a high voltage is applied and turned off when a low voltage is applied, or turned off when a high voltage is applied and turned on when a low voltage is applied.

[0081] The data driver DD is configured to supply data signals D[1] to D[m] to data lines extending in the second direction DR2 under the control of the timing controller TC. The data driver DD supplies data signals D[1] to D[m] synchronously with scan signals GW[1] to GW[n]. Accordingly, data signals D[1] to D[m] are supplied to the pixel PX selected by the scan signals GW[1] to GW[n].

[0082] The timing controller TC controls the scan driver SD and the data driver DD based on the synchronization signal supplied from the outside.

[0083] Power supply voltage ELVDD and electrode voltage ELVSS are supplied to the pixel PX inside the display area DA. The pixel PX supplied with power supply voltage ELVDD and electrode voltage ELVSS controls the amount of current flowing from the power supply voltage line through the organic light-emitting diode to the electrode power line according to the data signals D[1] to D[m], and generates light with a brightness corresponding to the data signals D[1] to D[m]. Power supply voltage ELVDD is applied to the power supply voltage line, and electrode voltage ELVSS is applied to the electrode power line.

[0084] Despite Figure 1 The illustration shows pixels PX arranged sequentially in the first direction DR1 and the second direction DR2 within the display area DA, but this disclosure is not limited thereto. As an example, pixels PX can be arranged in various configurations such as a honeycomb configuration, a mosaic configuration, and a stripe configuration. Additionally, as... Figure 1As shown, the display area DA can be rectangular in shape in a plan view. In contrast, the display area DA can be polygonal, circular, elliptical, or irregular in shape, such as a triangle, pentagon, or hexagon.

[0085] Figure 2 yes Figure 1 The equivalent circuit diagram of the pixels of the display device in the image.

[0086] refer to Figure 2 Pixel PX includes first transistors T1 to seventh transistors T7, bias capacitor Cbia, storage capacitor Cst, organic light-emitting diode (OLED), first initialization voltage line VIL1, second initialization voltage line VIL2, power supply voltage line PL, and signal lines. The signal lines may include data line DL, scan line SL, initialization line IL, compensation control line CL, and emission control line EL. At least one of the signal lines, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and / or the power supply voltage line PL may be shared by adjacent pixels PX.

[0087] The power supply voltage line PL can be configured to transmit the power supply voltage ELVDD to the first transistor T1. The first initialization voltage line VIL1 can be configured to transmit a first initialization voltage Vint1 to the pixel PX, which initializes the first transistor T1. The second initialization voltage line VIL2 can be configured to transmit a second initialization voltage Vint2 to the pixel PX, which initializes the organic light-emitting diode (OLED). As an example, the first initialization voltage Vint1 can be approximately -5V, and the second initialization voltage Vint2 can be approximately -7V to approximately -6V. Accordingly, the first initialization voltage Vint1 can be greater than the second initialization voltage Vint2.

[0088] Scan line SL, initialization line IL, compensation control line CL, transmit control line EL, first initialization voltage line VIL1, and second initialization voltage line VIL2 may extend in the first direction DR1 and be separated from each other in each row. Data line DL and power supply voltage line PL may extend in the second direction DR2 and be separated from each other in each column.

[0089] exist Figure 2The diagram shows that among the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 are implemented as N-channel metal-oxide-semiconductor field-effect transistors (NMOS-FETs), and the remaining transistors among the first to seventh transistors T1, T2, T3, T4, T5, T6, and T7 are implemented as P-channel metal-oxide-semiconductor field-effect transistors (PMOS-FETs).

[0090] The first transistor T1 is connected to the power supply voltage line PL via the fifth transistor T5, and is electrically connected to the organic light-emitting diode (OLED) via the sixth transistor T6. The first transistor T1 is a driving transistor that receives the data signal D[j] based on the voltage applied to the first node N1, and controls the driving current I flowing from the second node N2 through the OLED to the electrode power line. OLED The quantity, the second node N2 is connected to the power supply voltage line PL.

[0091] The second transistor T2, acting as a switching transistor, is connected to the scan line SL and the data line DL, and is connected to the power supply line PL via the fifth transistor T5, which acts as an operation control transistor. The second transistor T2 in the i-th row of a total of n rows is turned on according to the scan signal GW[i] received via the scan line SL, and performs a switching operation to transmit the data signal D[j] to the second node N2, which is transmitted to the data line DL in the j-th column of a total of m columns. Here, i is a natural number equal to or greater than 1 and equal to or less than n, and j is a natural number equal to or greater than 1 and equal to or less than m. As an example, the second transistor T2 can be turned on according to a low-voltage scan signal GW[i].

[0092] The third transistor T3, acting as a compensation transistor, is connected to the compensation control line CL and, via the sixth transistor T6, acting as the emission control transistor, is connected to the organic light-emitting diode (OLED). The third transistor T3 is turned on according to the compensation control signal GC[i] transmitted via the compensation control line CL, and is diode-connected to the first transistor T1. As an example, the third transistor T3 can be turned on according to a high-voltage compensation control signal GC[i].

[0093] The fourth transistor T4, serving as the first initialization transistor, is connected to the initialization line IL and the first initialization voltage line VIL1. It is turned on according to the initialization signal GI[i] transmitted through the initialization line IL, and transmits the first initialization voltage Vint1 from the first initialization voltage line VIL1 to the first gate electrode of the first transistor T1, thereby initializing the voltage of the first gate electrode of the first transistor T1. As an example, the fourth transistor T4 can be turned on according to the high-voltage initialization signal GI[i].

[0094] The fifth transistor T5, acting as the operation control transistor, and the sixth transistor T6, acting as the emitter control transistor, are connected to the emitter control line EL. They are simultaneously turned on according to the emitter control signal EM[i] transmitted through the emitter control line EL to form a current path, thereby driving the current I... OLED The power supply voltage line PL flows to the organic light-emitting diode (OLED). As an example, the fifth transistor T5 and the sixth transistor T6 can be turned on according to the low-voltage emitter control signal EM[i].

[0095] The seventh transistor T7, acting as the second initialization transistor, is connected to the emitter control line EL and the second initialization voltage line VIL2. It is turned on according to the emitter control signal EM[i] transmitted via the emitter control line EL, and transmits the second initialization voltage Vint2 from the second initialization voltage line VIL2 to the organic light-emitting diode (OLED), thereby initializing the OLED. As an example, the seventh transistor T7 can be turned on according to a high-voltage emitter control signal EM[i]. The seventh transistor T7 can be omitted.

[0096] The storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2. The first capacitor electrode CE1 is connected to or integrated with the first gate electrode of the first transistor T1, and the second capacitor electrode CE2 is connected to the power supply voltage line PL. The storage capacitor Cst can store and maintain a voltage corresponding to the difference between the voltage of the power supply voltage line PL and the voltage of the first gate electrode of the first transistor T1, thereby maintaining the voltage applied to the first gate electrode of the first transistor T1.

[0097] The bias capacitor Cbia connected between the second node N2 and the transmit control line EL includes a third capacitor electrode CE3 and a fourth capacitor electrode CE4. The third capacitor electrode CE3 is connected to the power supply voltage line PL via a fifth transistor T5, and the fourth capacitor electrode CE4 is connected to the transmit control line EL. When a high-voltage transmit control signal EM[i] is applied through the transmit control line EL, the fifth transistor T5 and the sixth transistor T6, whose gate electrodes are connected to the transmit control line EL, are turned off, and when a low-voltage initialization signal GI[i] is applied through the initialization line IL, the fourth transistor T4, whose gate electrode is connected to the initialization line IL, is turned off. Accordingly, the first transistor T1 becomes biased and is thus initialized.

[0098] The first initialization voltage Vint1 can be approximately -5V, and the second initialization voltage Vint2 can be approximately -7V to approximately -6V. As mentioned above, the first initialization voltage Vint1 can be greater than the second initialization voltage Vint2. Accordingly, when the first transistor T1 becomes in the on-bias state, the data voltage of the current frame input thereafter always becomes lower than the on-bias voltage and is therefore independent of the voltage of the previous frame. Accordingly, hysteresis and step efficiency problems do not occur, or their occurrence rate is reduced. For reference, the hysteresis problem means that when the data voltage of the current frame is higher than the data voltage of the previous frame, the gate-source voltage to source-drain current curve of the first transistor T1 becomes different from that when the data voltage of the current frame is lower than the data voltage of the previous frame. The step efficiency problem means that when the grayscale changes rapidly on a frame-by-frame basis (e.g., when the grayscale of the previous frame is black and the grayscale of the current frame is white), due to the aforementioned change in the voltage-to-current curve, a brightness corresponding to the intermediate grayscale appears in the pixel instead of a brightness corresponding to the target grayscale.

[0099] Organic light-emitting diodes (OLEDs) include pixel electrodes 310, counter electrodes 330, and an intermediate layer 320 therebetween (e.g., such as...). Figure 12 As shown in the diagram, the intermediate layer 320 includes an emission layer. An electrode voltage ELVSS is applied to the counter electrode 330, which is integrally formed across multiple pixel PX layers. The organic light-emitting diode (OLED) receives a drive current I from the first transistor T1. OLED The light emitted allows the display device to display an image. For reference, the counter electrode 330 extends outside the display area DA to connect to the electrode power line. The electrode voltage ELVSS is applied to the electrode power line.

[0100] Reference as a driving indicator Figure 2 The waveform diagram of the pixel PX method shown. Figure 3 The specific operation of each pixel PX according to the embodiment is described.

[0101] First, during time period t12, a high-voltage transmit control signal EM[i] is applied to pixel PX in the i-th row via transmit control line EL, a low-voltage compensation control signal GC[i] is applied to pixel PX in the i-th row via compensation control line CL, a high-voltage scan signal GW[i] is applied to pixel PX in the i-th row via scan line SL, and a low-voltage initialization signal GI[i] is applied to pixel PX in the i-th row via initialization line IL. Accordingly, because transistors T2 through T6 are turned off, transistor T1 becomes biased due to bias capacitor Cbia and is therefore initialized. In this case, transistor T7 is turned on, and current flows through the second initialization voltage line VIL2 instead of the organic light-emitting diode OLED. Accordingly, the organic light-emitting diode OLED is initialized.

[0102] Next, during time period t23, the compensation control signal GC[i] and the initialization signal GI[i] are changed to high voltage. Accordingly, the third transistor T3 and the fourth transistor T4 are turned on, and the voltage of the first gate electrode of the first transistor T1 is initialized by the first initialization voltage Vint1 supplied from the first initialization voltage line VIL1.

[0103] Additionally, during time period t34, the initialization signal GI[i] is changed to a low voltage, and the fourth transistor T4 is turned off. Next, during time period t45, the scan signal GW[i] is changed to a low voltage, and the second transistor T2 is turned on. Accordingly, during time period t45, a voltage corresponding to the data signal D[j] supplied from the data line DL is applied to the second node N2. Next, during time period t56, the scan signal GW[i] is changed to a high voltage, and the second transistor T2 is turned off. Because the third transistor T3 is kept on, the first transistor T1 is diode-connected and forward-biased by the third transistor T3. As a result, the threshold voltage (Vth) of the first transistor T1, compensated according to the data signal D[j] supplied from the data line DL, is applied to the first gate electrode of the first transistor T1 (i.e., the first node N1). Accordingly, the power supply voltage ELVDD and the compensated voltage are applied to the two opposite ends of the storage capacitor Cst, and the charge corresponding to the voltage difference between the two opposite ends is stored in the storage capacitor Cst.

[0104] Next, during time period t67, the compensation control signal GC[i] is changed to a low voltage, and the third transistor T3 becomes off. During time period t78, the transmit control signal EM[i] is changed to a low voltage, the seventh transistor T7 becomes off, the fifth transistor T5 and the sixth transistor T6 become on, and the drive current I corresponding to the voltage difference between the power supply voltage ELVDD and the voltage of the first gate electrode of the first transistor T1 is generated. OLED Appearance. Drive current I OLED The OLED is supplied with light through the sixth transistor T6, and the OLED emits light.

[0105] In an embodiment, at least one of the first transistor T1 to the seventh transistor T7 includes a semiconductor layer comprising an oxide layer, and the remaining transistors include a semiconductor layer comprising silicon. Specifically, the first transistor T1, which directly affects the brightness of the display device, includes a semiconductor layer comprising polycrystalline silicon with high reliability. In this way, a high-resolution display device can be realized.

[0106] Furthermore, because oxide semiconductors possess high carrier mobility and low leakage current, the voltage drop is minimal even with long driving times. That is, when using thin-film transistors (TFTs) including oxide semiconductors, the color change in the image caused by the voltage drop is minimal even when the TFT is driven at low frequencies. Because oxide semiconductors have the advantage of low leakage current, at least one of the third transistor T3 and the fourth transistor T4 connected to the first gate electrode of the first transistor T1 can include an oxide semiconductor, thus preventing leakage current that might flow to the first gate electrode of the first transistor T1 and simultaneously reducing power consumption. Additionally, the seventh transistor T7 can include an oxide semiconductor, and the seventh transistor T7 prevents current from flowing through the organic light-emitting diode (OLED) before it begins to emit light according to the emission control signal EM[i]. Accordingly, leakage current that might flow through the OLED can be prevented, and power consumption can be reduced simultaneously.

[0107] Figure 4 It is shown Figure 2 A layout diagram showing the positions of transistors and capacitors in the pixels. Figure 4 This shows a pair of pixels PX arranged in the same row of adjacent columns. Figure 4 The pixel circuitry of pixel PX in the left pixel region shown is arranged in... Figure 4 The pixel circuit of pixel PX in the right pixel region shown has a horizontally symmetrical structure. For reference, and for ease of description, Figure 4 Organic light-emitting diodes (OLEDs) are not shown. That is, Figure 4This is a layout diagram showing the location of the pixel circuitry for pixel PX.

[0108] Figures 5 to 11 Such as Figure 4 A layout diagram of each layer of transistors and capacitors. Figure 12 It is along Figure 4 The cross-sectional view of the display device taken by lines A-A', B-B', and C-C'. (See figure) Figures 5 to 11 The order shown in the middle, Figure 5 BML, the bottom metal layer Figure 6 The first active layer AL1, Figure 7 The first gate layer GL1, Figure 8 The second gate layer GL2, Figure 9 The second active layer AL2, Figure 10 The third gate layer GL3 and Figure 11 The source / drain layer SDL is positioned in a direction away from the substrate from the vicinity of the substrate.

[0109] In addition, an insulating layer is disposed between these layers. Specifically, a first buffer layer 111a may be disposed between the substrate 101 and... Figure 5 Between the bottom metal layers BML, the second buffer layer 111b can be set Figure 5 The bottom metal layer BML and Figure 6 Between the first active layers AL1, the first gate insulating layer 112 can be disposed Figure 6 The first active layer AL1 and Figure 7 Between the first gate layer GL1, the second gate insulating layer 113 can be disposed Figure 7 The first gate layer GL1 and Figure 8 Between the second gate layer GL2, the third gate insulating layer 114 can be disposed. Figure 8 The second gate layer GL2 and Figure 9 Between the second active layer AL2, the fourth gate insulating layer 115 can be disposed Figure 9 The second active layer AL2 and Figure 10 Between the third gate layer GL3, and the interlayer insulating layer 117 can be disposed. Figure 10 The third gate layer GL3 and Figure 11 The source and drain layers (SDLs) are located between the source and drain layers. These insulating layers may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide. When implemented, each insulating layer may be a single layer or multiple layers. Components in different layers can be electrically connected to each other through contact holes defined in the insulating layers.

[0110] Figure 5The bottom metal layer (BML) shown may include a metal such as silver, copper, or aluminum. The bottom metal layer (BML) protects the second active layer (AL2). Additionally, the bottom metal layer (BML) serves as wiring for the electrical interconnection of various components of the display device. This is described below.

[0111] like Figure 12 As shown, for example, a bottom metal layer (BML) is disposed on a substrate 101. The substrate 101 may include glass, metal, or a polymer resin. When at least a portion of the display device is bent or the display device is flexible, the substrate 101 may be configured to be flexible or bendable. In this case, the substrate 101 may include a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. Alternatively, the substrate 101 may include a multilayer structure comprising two layers and a barrier layer between the two layers comprising an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, etc.), the two layers comprising a polymer resin. Various modifications are possible.

[0112] A first buffer layer 111a can be disposed between the substrate 101 and the bottom metal layer BML. A second buffer layer 111b can be disposed on the bottom metal layer BML. The first buffer layer 111a and / or the second buffer layer 111b can prevent metal atoms or impurities from the substrate 101 or the bottom metal layer BML from diffusing to the first active layer AL1, etc. When implemented, the buffer layer can have a single-layer structure or a multi-layer structure. In a multi-layer structure, a portion of the layers can be referred to as a barrier layer.

[0113] like Figure 6 As shown, the first active layer AL1 may include a semiconductor layer having polysilicon. The source and drain regions of the first active layer AL1 may be doped with impurities. The impurities may include N-type or P-type impurities. The source and drain regions may correspond to the source electrode and drain electrode, respectively. The source and drain regions may be interchanged depending on the characteristics of the transistor. In the following text, the source region and drain region are used to represent the source electrode and drain electrode, respectively. Figure 2 The equivalent circuit diagram shows that a specific portion of the first active layer AL1 is doped with P-type impurities, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are implemented as PMOS-FETs. Additionally, other portions of the first active layer AL1 may be doped with impurities to serve as wiring for electrically connecting transistors and / or capacitors, or as capacitor electrodes, etc.

[0114] Figure 7 The first gate layer GL1, Figure 8 The second gate layer GL2 and Figure 10Each of the third gate layers GL3 may comprise at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). Each layer may have a single-layer structure or a multi-layer structure. In the case of a multi-layer structure, the layer may comprise various materials. As an example, Figure 7 The first gate layer GL1, Figure 8 The second gate layer GL2 and Figure 10 Each of the third gate layers GL3 can have a two-layer structure of molybdenum layer / aluminum layer or a three-layer structure of molybdenum layer / aluminum layer / molybdenum layer.

[0115] Figure 9 The second active layer AL2 may include a semiconductor layer comprising an oxide. As an example, the second active layer AL2 may include a Zn oxide-based material, and may include, for example, Zn oxide, In-Zn oxide, or Ga-In-Zn oxide. Because various modifications are possible, the second active layer AL2 may include an oxide semiconductor, such as an In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO) semiconductor that includes a metal such as indium (In), gallium (Ga), or tin (Sn) in ZnO.

[0116] For reference only. Figure 7 The contact hole 31 shown is defined within the second buffer layer 111b and the first gate insulating layer 112 to allow for... Figure 7 The layer shown is electrically connected to the layer disposed below it. Figure 5 The bottom metal layer BML. Figure 8 The contact holes 32 and 35 shown are defined in the second buffer layer 111b, the first gate insulating layer 112, and the second gate insulating layer 113 to allow for... Figure 8 The layer shown is electrically connected to the layer disposed below it. Figure 5 The bottom metal layer BML. Figure 8 The contact hole 34 shown is defined in the first gate insulating layer 112 and the second gate insulating layer 113 to allow for the connection of the contact hole 34 to be inserted into the first gate insulating layer 112 and the second gate insulating layer 113. Figure 8 The layer shown is electrically connected to the layer disposed below it. Figure 6 The first active layer AL1.

[0117] in addition, Figure 10 The contact hole 36 shown is defined in the second gate insulating layer 113 to the fourth gate insulating layer 115 to allow for the... Figure 10 The layer shown is electrically connected to the layer disposed below it. Figure 7 The first gate layer GL1. Figure 10The contact holes 33 and 39 shown are defined in the second buffer layer 111b and the first gate insulating layer 112 to the fourth gate insulating layer 115 to allow for... Figure 10 The layer shown is electrically connected to the layer disposed below it. Figure 5 The bottom metal layer BML. Figure 10 The contact hole 37 shown is defined in the first gate insulating layer 112 to the fourth gate insulating layer 115 to allow for the... Figure 10 The layer shown is electrically connected to the layer disposed below it. Figure 6 The first active layer AL1. Figure 10 The contact holes 43, 47, and 49 shown are defined in the fourth gate insulating layer 115 to allow for... Figure 10 The layer shown is electrically connected to the layer disposed below it. Figure 9 The second active layer AL2.

[0118] Figure 11 The source / drain layer SDL may include at least one of aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu). This layer may have a single-layer or multi-layer structure. In the case of a multi-layer structure, the layer may include various materials. As an example, the source / drain layer SDL may have a two-layer structure of titanium / aluminum or a three-layer structure of titanium / aluminum / titanium.

[0119] For reference only. Figure 11 The contact holes 61 and 65 shown are defined in the first gate insulating layer 112 to the fourth gate insulating layer 115 and the interlayer insulating layer 117 to allow for the placement of contact holes. Figure 11 The layer shown is electrically connected to the layer disposed below it. Figure 6 The first active layer AL1. Figure 11 The contact hole 67 shown is defined in the second buffer layer 111b, the first gate insulating layer 112 to the fourth gate insulating layer 115, and the interlayer insulating layer 117, so as to... Figure 11 The layer shown is electrically connected to the layer disposed below it. Figure 5 The bottom metal layer BML. Figure 11 The contact hole 66 shown is defined in the third gate insulating layer 114, the fourth gate insulating layer 115, and the interlayer insulating layer 117 to allow for... Figure 11 The layer shown is electrically connected to the layer disposed below it. Figure 8 The second gate layer GL2. Figure 11 The contact holes 41 and 45 shown are defined in the fourth gate insulating layer 115 and the interlayer gate insulating layer 117 to allow for... Figure 11 The layer shown is electrically connected to the layer disposed below it. Figure 9The second active layer AL2. Figure 11 The contact hole 63 shown is defined in the interlayer insulating layer 117 to allow for... Figure 11 The layer shown is electrically connected to the layer disposed below it. Figure 10 The connecting electrode is 167.

[0120] Although for ease of description in Figure 11 Contact hole 64 is shown, but contact hole 64 is not a contact hole for connecting electrode 185 to the layer disposed below it. Contact hole 64 is defined in the cover Figure 11 In the planarization layer 118 of the source / drain layer SDL shown, pixel electrodes 310 of an organic light-emitting diode (OLED) disposed on the planarization layer 118 are electrically connected to connection electrodes 185. The planarization layer 118 may include organic materials such as propylene, benzocyclobutene (BCB), polyimide, or hexamethyldisiloxane (HMDSO). This disclosure is not limited thereto, and the planarization layer 118 may include inorganic materials and, when implemented, has a single-layer or multi-layer structure.

[0121] The pixel circuit includes a scan line SL, an initialization line IL, a compensation control line CL, an emission control line EL, a first initialization voltage line VIL1, and a second initialization voltage line VIL2, each extending in a first direction DR1, and includes a data line DL and a power supply voltage line PL, each extending in a second direction DR2 that intersects the first direction DR1.

[0122] The bottom emission control line 136 of the first initialization voltage line VIL1 (137), scan line SL (134), and emission control line EL may include the same material as the first gate electrode G1, and may be disposed together with the first gate electrode G1 in the first gate layer GL1, such as Figure 7 As shown in the diagram. The second initialization voltage line VIL2 (169) can be set in the third gate layer GL3, as shown in the diagram. Figure 10 As shown in the image.

[0123] Additionally, some wiring in the wiring may include two conductive layers disposed in different layers. As an example, the initialization line IL may include a bottom initialization line 143 and a top initialization line 163 disposed in different layers. Figure 8 As shown, the bottom initialization line 143 may include the same material as the second capacitor electrode CE2 of the storage capacitor Cst, and may be disposed together with the second capacitor electrode CE2 in the second gate layer GL2. Figure 10 As shown, the top initialization line 163 may include the same material as the fourth capacitor electrode CE4 of the bias capacitor Cbia, and may be disposed in the third gate layer GL3 together with the fourth capacitor electrode CE4.

[0124] The bottom initialization line 143 in the second gate layer GL2 may overlap with at least a portion of the top initialization line 163 in the third gate layer GL3. Additionally, the bottom initialization line 143 may be electrically connected to the top initialization line 163. As an example, the bottom initialization line 143 may contact the top initialization line 163 outside the display area DA, or it may be electrically connected to the top initialization line 163 via a connecting electrode. Because the first portion of the bottom initialization line 143 (G4a) and the second portion of the top initialization line 163 (G4b) are elements of the fourth gate electrode G4 of the fourth transistor T4, the fourth transistor T4 may have a dual-gate structure including control electrodes located above and below the semiconductor layer, respectively. That is, the first portion of the bottom initialization line 143 (G4a) is the 4-1 gate electrode, and the second portion of the top initialization line 163 (G4b) is the 4-2 gate electrode. The fourth gate electrode G4 of the fourth transistor T4 may have a dual-gate structure including the 4-1 gate electrode and the 4-2 gate electrode. The dimensions of part G4a of the bottom initialization line 143 can be substantially the same as the dimensions of part G4b of the top initialization line 163.

[0125] Additionally, the compensation control line CL may include a bottom compensation control line 145 and a top compensation control line 165 disposed in different layers. For example... Figure 8 As shown, the bottom compensation control line 145 of the second gate layer GL2 may include the same material as the material of the second capacitor electrode CE2 of the storage capacitor Cst, and may be disposed in the same layer as the second capacitor electrode CE2. Figure 8 The bottom compensation control line 145 and the second capacitor electrode CE2 are shown both in the second gate layer GL2. Figure 10 As shown, the top compensation control line 165 of the third gate layer GL3 may include the same material as the fourth capacitor electrode CE4 of the bias capacitor Cbia, and may be disposed in the same layer as the fourth capacitor electrode CE4. Figure 10 The top compensation control line 165 and the fourth capacitor electrode CE4 are shown in the third gate layer GL3.

[0126] The bottom compensation control line 145 may at least partially overlap with the top compensation control line 165. Additionally, the bottom compensation control line 145 may be electrically connected to the top compensation control line 165. As an example, the bottom compensation control line 145 and the top compensation control line 165 may be in contact with each other outside the display area DA, or they may be electrically connected to each other via connecting electrodes. Because portions G3a of the bottom compensation control line 145 and G3b of the top compensation control line 165 are elements of the third gate electrode G3 of the third transistor T3, the third transistor T3 may have a dual-gate structure including control electrodes respectively above and below the semiconductor layer. The portion G3a of the bottom compensation control line 145 may be larger than the portion G3b of the top compensation control line 165 in the second direction DR2.

[0127] Additionally, the emission control line EL may include a bottom emission control line 136 and a top emission control line 166 disposed in different layers. The bottom emission control line 136 of the first gate layer GL1 may include the same material as the first gate electrode G1, and may be disposed in the same layer as the first gate electrode G1, such as... Figure 7 As shown in the image. Figure 7 The diagram shows that both the bottom emitter control line 136 and the first gate electrode G1 are disposed in the first gate layer GL1. The top emitter control line 166 of the third gate layer GL3 may include the same material as the fourth capacitor electrode CE4 of the bias capacitor Cbia, and may be disposed in the same layer as the fourth capacitor electrode CE4, such as... Figure 10 As shown in the image. Figure 10 The diagram shows that both the top emitter control line 166 and the fourth capacitor electrode CE4 are disposed in the third gate layer GL3. Specifically, the top emitter control line 166 may be integrated with the fourth capacitor electrode CE4.

[0128] Bottom emission control line 136 may at least partially overlap with top emission control line 166. Additionally, bottom emission control line 136 may be electrically connected to top emission control line 166. As an example, bottom emission control line 136 and top emission control line 166 may be in contact with each other outside the display area DA, or they may be electrically connected to each other via connecting electrodes. Because the third portion of portion G7a of bottom emission control line 136 and the fourth portion of portion G7b of top emission control line 166 overlap with the second active layer AL2 and are elements of the seventh gate electrode G7 of the seventh transistor T7, the seventh transistor T7 may have a dual-gate structure including control electrodes respectively above and below the semiconductor layer. That is, the third portion of portion G7a of bottom emission control line 136 is the 7-1 gate electrode, and the fourth portion of portion G7b of top emission control line 166 is the 7-2 gate electrode. The seventh gate electrode G7 of the seventh transistor T7 may have a dual-gate structure including the 7-1 gate electrode and the 7-2 gate electrode. The portion G7a of the bottom emission control line 136 can be larger than the portion G7b of the top emission control line 166 in the second direction DR2.

[0129] The pixel circuit may include a first transistor T1 to a seventh transistor T7, a storage capacitor Cst, and a bias capacitor Cbia.

[0130] The first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 can each be a thin-film transistor comprising silicon semiconductor. The third transistor T3, the fourth transistor T4, and the seventh transistor T7 can each be a thin-film transistor comprising oxide semiconductor.

[0131] The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 are disposed in the same layer and comprise the same material, such as Figure 6 As shown in the figure. As an example, the semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may comprise polysilicon. The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may be interconnected and may be bent into various shapes, such as... Figure 6 As shown in the image.

[0132] The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may each include an active region, a source region, and a drain region, where the active region is a channel region, and the source and drain regions are located on opposite sides of the active region. As an example, the source and drain regions may be doped with impurities. These impurities may include N-type or P-type impurities. The source and drain regions may correspond to the source electrode and the drain electrode, respectively. The source and drain regions may be interchanged depending on the characteristics of the transistor. In the following text, the source region and drain region will be used to represent the source electrode and the drain electrode, respectively.

[0133] The first transistor T1, serving as the driving transistor, includes a first semiconductor layer and a first gate electrode G1. The first semiconductor layer, serving as the driving semiconductor layer, includes a first active region A1, a first source region S1, and a first drain region D1, with the first source region S1 and the first drain region D1 located on opposite sides of the first active region A1. The first semiconductor layer can have a curved shape, and therefore, the first active region A1 can be longer than the other active regions A2 to A7. As an example, because the first semiconductor layer has a shape that is bent multiple times (such as...), (e.g., “S”, “M”, “W”), so a long channel can be formed in a small space. Because the first active region A1 is long, the driving range of the gate voltage applied to the first gate electrode G1, which serves as the driving gate electrode, is widened. Accordingly, the grayscale of the light emitted from the organic light-emitting diode OLED can be controlled more precisely, and the display quality can be improved. When implemented, the first semiconductor layer can have a straight shape instead of a curved shape. As described below, because the first capacitor electrode CE1 of the first gate layer GL1 is electrically connected to the first bottom metal layer BML1 disposed below it through the contact hole 31, the first active region A1 of the first semiconductor layer, which serves as the driving semiconductor layer, can be bent into a shape that surrounds a portion of the contact hole 31.

[0134] like Figure 7 As shown, the first gate electrode G1 can have an isolated shape and can overlap with the first active region A1. As described above, the first gate insulating layer 112 can be disposed between the first active region A1 and the first gate electrode G1.

[0135] Storage capacitor Cst( Figure 4 (As shown) can overlap with the first transistor T1. The storage capacitor Cst includes a first capacitor electrode CE1 and a second capacitor electrode CE2. The first gate electrode G1 can be used as the first capacitor electrode CE1 of the storage capacitor Cst and the control electrode of the first transistor T1. That is, the first gate electrode G1 and the first capacitor electrode CE1 can be integrally formed into a single unit. The second capacitor electrode CE2 of the storage capacitor Cst is disposed on top of the first capacitor electrode CE1 to overlap with the first capacitor electrode CE1. Because the second gate insulating layer 113 is disposed between the first capacitor electrode CE1 and the second capacitor electrode CE2, the second gate insulating layer 113 can be used as the dielectric layer of the storage capacitor Cst.

[0136] The second capacitor electrode CE2 may include an opening SOP. The opening SOP is formed by removing a portion of the second capacitor electrode CE2. The second capacitor electrode CE2 may have a closed shape.

[0137] The second capacitor electrodes CE2 of adjacent pixels PX can be connected to each other via bridge 141. Bridge 141 is a portion protruding from the second capacitor electrode CE2 in the first direction DR1, and can be integrally formed with the second capacitor electrode CE2.

[0138] Connection electrode 187 of source / drain layer SDL ( Figure 11 The first capacitor electrode CE1 of the first gate layer GL1 is electrically connected to the third and fourth semiconductor layers of the second active layer AL2 via contact hole 41, and to the first bottom metal layer BML1 of the bottom metal layer BML disposed below the source / drain layer SDL via contact hole 67. Additionally, the first capacitor electrode CE1 of the first gate layer GL1 is electrically connected to the first bottom metal layer BML1 disposed below it via contact hole 31, and thus electrically connected to the third and fourth semiconductor layers of the second active layer AL2. The second capacitor electrode CE2 can be electrically connected to the power supply voltage line 183(PL) of the source / drain layer SDL disposed above the second gate layer GL2 via contact hole 66. The power supply voltage line 183 can extend in the second direction DR2. The second capacitor electrode CE2 can extend in the first direction DR1 and can be configured to transmit the power supply voltage ELVDD in the first direction DR1. Accordingly, the multiple power supply voltage lines 183 and multiple second capacitor electrodes CE2 in the display area DA can have a mesh structure in the plan view.

[0139] refer to Figure 4 The second transistor T2 includes a second semiconductor layer and a second gate electrode G2. The second semiconductor layer includes a second active region A2, a second source region S2, and a second drain region D2, with the second source region S2 and the second drain region D2 located on opposite sides of the second active region A2. The second source region S2 can be electrically connected to the data line 181 of the source-drain layer SDL disposed above the first active layer AL1 via a contact hole 61. The second drain region D2 can be electrically connected to the first source region S1 of the first transistor T1. In this case, because the third capacitor electrode CE3 of the bias capacitor Cbia is connected to... Figure 6 The first semiconductor layer or the second semiconductor layer shown is formed in the same semiconductor layer, so the second drain region D2 can be electrically connected to the first source region S1 of the first transistor T1 through the third capacitor electrode CE3. Figure 6 The third capacitor electrode CE3, the first semiconductor layer, and the second semiconductor layer are integrally formed into a single unit. The second gate electrode G2 is the portion of scan line 134 that overlaps with the second semiconductor layer.

[0140] The fifth transistor T5 includes a fifth semiconductor layer and a fifth gate electrode G5. The fifth semiconductor layer includes a fifth active region A5, a fifth source region S5, and a fifth drain region D5, with the fifth source region S5 and the fifth drain region D5 located on opposite sides of the fifth active region A5. The fifth source region S5 can be electrically connected to the power supply voltage line 183 of the source-drain layer SDL via the connection electrode 147 of the second gate layer GL2, the third bottom metal layer BML3 of the bottom metal layer BML, and the second capacitor electrode CE2 of the second gate layer GL2, and the fifth drain region D5 can be connected to the first source region S1. That is, the third bottom metal layer BML3 can electrically connect the fifth transistor T5 to the second capacitor electrode CE2, and thus electrically connect the fifth transistor T5 to the power supply voltage line 183. The fifth gate electrode G5 may be the portion of the bottom emitter control line 136 that overlaps with the first active layer AL1.

[0141] The sixth transistor T6 includes a sixth semiconductor layer and a sixth gate electrode G6. The sixth semiconductor layer includes a sixth active region A6, a sixth source region S6, and a sixth drain region D6, with the sixth source region S6 and the sixth drain region D6 located on opposite sides of the sixth active region A6. The sixth source region S6 is connected to the first drain region D1. The sixth drain region D6 can be electrically connected to the seventh semiconductor layer of the second active layer AL2 via the connection electrode 167 of the third gate layer GL3, the second bottom metal layer BML2 of the bottom metal layer BML, and the connection electrode 161 of the third gate layer GL3. That is, the second bottom metal layer BML2 can electrically connect the sixth transistor T6 to the seventh transistor T7. In addition, the sixth drain region D6 can be electrically connected to the pixel electrode 310 of the organic light-emitting diode OLED via the connection electrode 167 of the third gate layer GL3 and the connection electrode 185 of the source / drain layer SDL, and is thus electrically connected to the pixel electrode 310. The sixth gate electrode G6 may be the portion of the bottom emission control line 136 that overlaps with the first active layer AL1. Connecting electrode 161 may be referred to as the first connecting electrode, and connecting electrode 167 may be referred to as the second connecting electrode.

[0142] As described above, the second active layer AL2 may include an oxide semiconductor. Furthermore, the third transistor T3, the fourth transistor T4, and the seventh transistor T7 may include portions of the second active layer AL2 as components, such as... Figure 9 As shown in the image.

[0143] The second active layer AL2, comprising an oxide semiconductor, may include an active region, a source region, and a drain region, with the source and drain regions located on opposite sides of the active region, respectively. As an example, the source and drain regions may be regions where the carrier concentration has been increased by performing plasma treatment on the oxide semiconductor using a hydrogen (H)-type gas, a fluorine (F)-type gas, or a combination thereof. The source and drain regions may correspond to a source electrode and a drain electrode, respectively. Hereinafter, the source region and drain region will be used instead of the source electrode and drain electrode, respectively.

[0144] The third transistor T3 includes a third semiconductor layer and a third gate electrode G3. The third semiconductor layer includes an oxide semiconductor. The third semiconductor layer includes a third active layer A3, a third source region S3, and a third drain region D3, with the third source region S3 and the third drain region D3 located on opposite sides of the third active layer A3. Because the third source region S3 is connected to the first gate electrode G1 of the first gate layer GL1 through the connection electrode 187 of the source-drain layer SDL and the first bottom metal layer BML1 of the bottom metal layer BML, the third source region S3 can therefore be connected to the first gate electrode G1. Furthermore, the third source region S3 can be connected to a fourth drain region D4 disposed in the same layer. Figure 9 The third source region S3 and the fourth drain region D4 are shown to be integrally formed into a single unit. That is, the fourth semiconductor layer including the fourth drain region D4 is electrically connected to the first transistor T1 including the first gate electrode G1 through the first bottom metal layer BML1.

[0145] The third drain region D3 can be electrically connected to the first semiconductor layer of the first transistor T1 and the sixth semiconductor layer of the sixth transistor T6 via the connection electrode 189 of the source-drain layer SDL. The third gate electrode G3 may include a portion G3b of the top compensation control line 165 intersecting with the second active layer AL2 and a portion G3a of the bottom compensation control line 145 intersecting with the second active layer AL2. That is, the third gate electrode G3 may have a dual-gate structure including control electrodes respectively above and below the semiconductor layer.

[0146] The fourth transistor T4 includes a fourth semiconductor layer and a fourth gate electrode G4. The fourth semiconductor layer includes an oxide semiconductor. The fourth semiconductor layer includes a fourth active layer A4, a fourth source region S4, and a fourth drain region D4, with the fourth source region S4 and the fourth drain region D4 located on opposite sides of the fourth active region A4. The fourth source region S4 can be electrically connected to the first initialization voltage line 137 via the connection electrode 168 of the third gate layer GL3. The fourth drain region D4 can be electrically connected to the first gate electrode G1 via the connection electrode 187 of the source / drain layer SDL and the first bottom metal layer BML1 of the bottom metal layer BML. The fourth gate electrode G4 may include a portion G4b of the top initialization line 163 intersecting with the second active layer AL2 and a portion G4a of the bottom initialization line 143 intersecting with the second active layer AL2. That is, the fourth gate electrode G4 may have a dual-gate structure including control electrodes located above and below the semiconductor layer, respectively.

[0147] The seventh transistor T7 includes a seventh semiconductor layer and a seventh gate electrode G7. The seventh semiconductor layer includes a seventh active region A7, a seventh source region S7, and a seventh drain region D7, with the seventh source region S7 and the seventh drain region D7 located on opposite sides of the seventh active region A7. The seventh source region S7 can be electrically connected to the second initialization voltage line 169 of the third gate layer GL3 disposed above the second active layer AL2 via a contact hole 43. The seventh drain region D7 can be electrically connected to the sixth drain region D6 via the connection electrode 161 of the third gate layer GL3, the second bottom metal layer BML2 of the bottom metal layer BML, and the connection electrode 167 of the third gate layer GL3. The seventh gate electrode G7 may include a portion G7b of the top emitter control line 166 overlapping with the second active layer AL2 and a portion G7a of the bottom emitter control line 136 overlapping with the second active layer AL2. That is, the seventh gate electrode G7 may have a dual-gate structure including control electrodes located above and below the semiconductor layer, respectively.

[0148] The bias capacitor Cbia includes a third capacitor electrode CE3 and a fourth capacitor electrode CE4. The third capacitor electrode CE3 can be formed in the first active layer AL1, such as... Figure 6 As shown in the diagram. Specifically, the third capacitor electrode CE3 can be formed by using the aforementioned impurity-doped polysilicon layer. The third capacitor electrode CE3 can be integral with the first source region S1 of the first transistor T1 and the fifth drain region D5 of the fifth transistor T5. The fourth capacitor electrode CE4 overlaps with the third capacitor electrode CE3. Figure 10 As shown, the fourth capacitor electrode CE4 can be part of the top emission control line 166 of the emission control line EL. That is, the top emission control line 166 and the fourth capacitor electrode CE4 can be integrally formed into a single unit. Because the first gate insulating layer 112 to the fourth gate insulating layer 115 are disposed between the third capacitor electrode CE3 and the fourth capacitor electrode CE4, the gate insulating layer can be used as the dielectric layer of the bias capacitor Cbia. Figure 10 As shown, two adjacent pixels PX in the i-th row can share the fourth capacitor electrode CE4.

[0149] like Figure 12 As shown, a pixel defining layer 119 can be disposed on a planarization layer 118. The pixel defining layer 119 defines a pixel PX by including an opening corresponding to each of the sub-pixels (i.e., an opening exposing at least the central portion of the pixel electrode 310). Furthermore, the pixel defining layer 119 prevents arcing or the like at the edges of the pixel electrode 310 by increasing the distance between the edge of the pixel electrode 310 and the counter electrode 330 above the pixel electrode 310. For example, the pixel defining layer 119 may comprise an organic material such as polyimide or HMDSO.

[0150] The intermediate layer 320 of an organic light-emitting diode (OLED) can comprise a low molecular weight material or a polymer material. When the intermediate layer 320 comprises a low molecular weight material, it can have a structure in which a hole injection layer (HIL), a hole transport layer (HTL), an emitter layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL) are stacked in a single or composite configuration. These layers can be formed by vacuum deposition. When the intermediate layer 320 comprises a polymer material, it can have a structure including both an HTL and an EML. In this case, the HTL can comprise poly(3,4-ethylenedioxythiophene) (PEDOT), and the EML can comprise polymer materials such as poly(p-phenylenevinylene) (PPV) and polyfluorene. The intermediate layer 320 can be formed by screen printing, inkjet printing, laser-induced thermal imaging (LITI), etc. The intermediate layer 320 is not limited to these methods and can have various structures. Alternatively, the intermediate layer 320 may include an integral portion of the plurality of pixel electrodes 310, or may include a layer patterned to correspond to each of the plurality of pixel electrodes 310.

[0151] The counter electrode 330 can cover the display area DA. That is, the counter electrode 330 can be integrated across multiple organic light-emitting diode (OLED) units to correspond to multiple pixel electrodes 310. The counter electrode 330 can cover the display area DA and can extend to the peripheral area outside the display area DA.

[0152] The display device according to an embodiment includes a bottom metal layer BML to protect a second active layer AL2, including an oxide semiconductor, from external light and the like. Accordingly, a display device capable of displaying high-quality images can be realized. Furthermore, when implemented using a first bottom metal layer BML1 and a third bottom metal layer BML3, various components of the display device can be electrically connected. This simplifies the layer structure of a multi-layered display device.

[0153] Figure 13 This is a cross-sectional view showing a portion of a display device according to another embodiment. The display device according to the embodiment and reference... Figure 12 The difference in the display device described above is that the portion G4a, which is part of the bottom initialization line 143 of the second gate layer GL2 and the 4-1 gate electrode of the fourth transistor T4, is connected to the first bottom metal layer BML1 of the bottom metal layer BML through contact holes defined in the second buffer layer 111b, the first gate insulating layer 112, and the second gate insulating layer 113. In this case, the portion of the first bottom metal layer BML1 connected to the 4-1 gate electrode can be electrically insulated from the portion of the first bottom metal layer BML1 connected to the first gate electrode G1. With this configuration, the voltage stability of the 4-1 gate electrode can be improved even further.

[0154] Figure 13 The display device shown can be manufactured using the following process: patterning Figure 5 The first mask process of the bottom metal layer BML shown in the figure is patterning. Figure 6 The second mask process for the first active layer AL1 shown, and the third mask process for forming contact holes in the first gate insulating layer 112, etc., are patterned. Figure 7 The fourth mask process of the first gate layer GL1 shown is patterned. Figure 8 The fifth mask process of the second gate layer GL2 shown in the figure, patterning Figure 9 The sixth mask process of the second active layer AL2 shown, and the seventh mask process of forming contact holes in the fourth gate insulating layer 115, etc., are patterned. Figure 10 The eighth mask process of the third gate layer GL3 shown, and the ninth mask process that forms contact holes in the interlayer insulating layer 117, are patterned. Figure 11 The tenth mask process of the source / drain layer SDL shown, the eleventh mask process of forming contact holes in the planarization layer 118, the twelfth mask process of patterning the pixel electrode 310, and the thirteenth mask process of patterning the pixel limiting layer 119 are shown.

[0155] As described above, in the display device according to the embodiment, a first active layer AL1 comprising a silicon semiconductor and a second active layer AL2 comprising an oxide semiconductor are used, and a bottom metal layer BML is formed not only to protect the second active layer AL2, but also to serve as a connection electrode or wiring, etc. Therefore, the display device can be manufactured using only 13 mask processes.

[0156] Figure 14 This is a cross-sectional view showing a portion of a display device according to another embodiment, and Figure 15 yes Figure 14 A conceptual side view of a portion of a display device.

[0157] like Figure 15 As shown, the display panel 10 of the display device may include a main area MR, a flexible area BR outside the main area MR, and a sub-area SR positioned around the flexible area BR opposite to the main area MR. Figure 15 As shown, the display panel 10 is bent in the flexible region BR, and in a view along the Z-axis, at least a portion of the sub-region SR may overlap with the main region MR. A driver chip 20 may be arranged in the sub-region SR of the display panel 10. The driver chip 20 may include an integrated circuit that drives the display panel 10. Although the integrated circuit may be a data-driven integrated circuit that generates data signals, this disclosure is not limited thereto. Figure 15 The X-axis and Y-axis directions, which can correspond to the first direction DR1 and the second direction DR2 respectively, are also shown.

[0158] The driver chip 20 can be mounted in the sub-region SR of the display panel 10. Although the driver chip 20 is mounted on the same plane as the display surface of the display area DA, because the display panel 10 is bent in the flexible area BR as described above, the driver chip 20 can be disposed on the back side of the main area MR. The printed circuit board 30, etc., can be attached to the end of the sub-region SR of the display panel 10. The printed circuit board 30, etc., can be electrically connected to the driver chip 20, etc., through pads (not shown) on the substrate 101.

[0159] like Figure 15 As shown, because the display panel 10 is bent in the bendable region BR, the non-display area may not be seen when the display device is viewed from the front (-Z axis direction), or even if the non-display area is seen, the area that can be seen may be reduced. Figure 14 This is a cross-sectional view of a portion of the flexible region BR of the display device. (Example) Figure 14 As shown, at least a portion of the first buffer layer 111a, the second buffer layer 111b, the first gate insulating layer 112 to the fourth gate insulating layer 115, and the interlayer insulating layer 117 can be removed from the bendable region BR. Because the first buffer layer 111a, the second buffer layer 111b, the first gate insulating layer 112 to the fourth gate insulating layer 115, and the interlayer insulating layer 117 comprise inorganic materials, when these layers exist in the bendable region BR, cracks may appear within these layers when the substrate 101, etc., is bent. Therefore, as... Figure 14 As shown, at least a portion of the first buffer layer 111a, the second buffer layer 111b, the first gate insulating layer 112 to the fourth gate insulating layer 115, and the interlayer insulating layer 117 can be removed from the flexible region BR.

[0160] Additionally, because the main area MR can be electrically connected to the sub-area SR, the second wiring W2 can pass through the flexible area BR, such as... Figure 14 As shown in the diagram. The second wiring W2 may include the same material as the source / drain layer SDL. Additionally, the second wiring W2 may be electrically connected to the first wiring W1 and / or the third wiring W3 outside the flexible region BR. The first wiring W1 and / or the third wiring W3 may include the same material as the third gate layer GL3. That is, the first wiring W1 and / or the third wiring W3 may be wiring within the third gate layer GL3.

[0161] In the bendable region BR, a planarization layer 118 can be disposed on the second wiring W2. Because the planarization layer 118 comprises an organic material, the magnitude of the stress occurring inside the planarization layer 118 may be small despite bending. Because the pixel defining layer 119 comprises an organic material, the pixel defining layer 119 can be disposed on the planarization layer 118 inside the bendable region BR.

[0162] Figure 16 This is a cross-sectional view showing a portion of a display device according to another embodiment. The display device according to this embodiment differs from the display device according to the previous embodiment in that the first gate layer GL1 includes a first source electrode GL1a and a first drain electrode GL1b.

[0163] That is, in the display device according to the embodiment, the second buffer layer 111b covers the bottom metal layer BML on the first buffer layer 111a, and the semiconductor layer AL1a of the first active layer AL1 is disposed on the second buffer layer 111b. Additionally, a first gate insulating layer 112 is disposed on the semiconductor layer AL1a, and the first source electrode GL1a, the first drain electrode GL1b, and the gate electrode GL1c of the first gate layer GL1 are disposed on the first gate insulating layer 112. When implemented, when the first source electrode GL1a, the first drain electrode GL1b, and the gate electrode GL1c are patterned during the manufacturing process, the first source electrode GL1a, the first drain electrode GL1b, and the gate electrode GL1c can be patterned simultaneously with the first gate insulating layer 112 beneath them. Accordingly, the edge of each of the first source electrode GL1a, the first drain electrode GL1b, and the gate electrode GL1c can coincide with the edge of the first gate insulating layer 112 disposed beneath it.

[0164] The first source electrode GL1a and the first drain electrode GL1b may contact the semiconductor layer AL1a to allow electrical signals to be transmitted between the first source electrode GL1a and the first drain electrode GL1b according to the electrical signal applied to the gate electrode GL1c. At least one of the first source electrode GL1a and the first drain electrode GL1b may contact the first wiring of the bottom metal layer BML. Figure 16 The diagram shows the wiring corresponding to the contact between the first source electrode GL1a and the first drain electrode GL1b.

[0165] In the display device according to the embodiment, the bottom metal layer BML can protect the thin-film transistor disposed on the bottom metal layer BML and can also be used as wiring. In the display device according to the embodiment, the structure of the metal layer on the first active layer AL1 can be simplified.

[0166] The second gate layer GL2 can be disposed between the second gate insulating layer 113 and the third gate insulating layer 114, with the second gate insulating layer 113 covering the first gate layer GL1. Figure 16The second gate layer GL2 is shown to include a first portion GL2b and a second portion GL2a. The first portion GL2b corresponds to the gate electrode GL1c disposed below the second gate layer GL2, and the second portion GL2a corresponds to the gate electrode GL3c disposed above the second gate layer GL2, as described below. Additionally, the semiconductor layer AL2a of the second active layer AL2 is disposed on the third gate insulating layer 114. A fourth gate insulating layer 115 is disposed on the semiconductor layer AL2a. The second source electrode GL3a, the second drain electrode GL3b, and the gate electrode GL3c of the third gate layer GL3 are disposed on the fourth gate insulating layer 115.

[0167] When implemented, when the second source electrode GL3a, the second drain electrode GL3b, and the gate electrode GL3c are patterned during the manufacturing process, the second source electrode GL3a, the second drain electrode GL3b, and the gate electrode GL3c can be patterned simultaneously with the fourth gate insulating layer 115 beneath them. Accordingly, the edge of each of the second source electrode GL3a, the second drain electrode GL3b, and the gate electrode GL3c can coincide with the edge of the fourth gate insulating layer 115 disposed therebelow.

[0168] The second source electrode GL3a and the second drain electrode GL3b can contact the semiconductor layer AL2a to allow electrical signals to be transmitted between the second source electrode GL3a and the second drain electrode GL3b according to the electrical signal applied to the gate electrode GL3c. Additionally, at least one of the second source electrode GL3a and the second drain electrode GL3b can contact the second wiring of the bottom metal layer BML. Figure 16 The diagram shows the wiring corresponding to the contact between the second source electrode GL3a and the second drain electrode GL3b.

[0169] In the display device according to the embodiment, the bottom metal layer BML can protect the thin-film transistor disposed on the bottom metal layer BML and can also be used as wiring. In the display device according to the embodiment, the structure of the metal layer on the second active layer AL2 can be simplified.

[0170] The source / drain layer SDL disposed on the interlayer insulating layer 117 covering the third gate layer GL3 can be electrically connected to the thin-film transistor disposed below the source / drain layer SDL. Figure 16 The diagram shows the source / drain layer SDL connected to the first drain electrode GL1b. Because the pixel electrode 310 on the planarization layer 118 covering the source / drain layer SDL can be electrically connected to the source / drain layer SDL, the pixel electrode 310 can receive electrical signals from the thin-film transistor disposed below the source / drain layer SDL.

[0171] Figure 17 This is a cross-sectional view showing a portion of a display device according to another embodiment. The display device according to the embodiment and reference... Figure 16The difference in the described display device is that the second portion GL2a of the second gate layer GL2 is connected to the bottom metal layer BML via a contact hole defined in the insulating layer beneath it. The bottom metal layer BML connected to the second portion GL2a is electrically connected to the gate electrode GL3c, such that the second portion GL2a of the second gate layer GL2 and the gate electrode GL3c above the second portion GL2a operate as a dual-gate electrode.

[0172] Figure 18 This is a cross-sectional view showing a portion of a display device according to another embodiment.

[0173] In the display device according to the embodiment, a second buffer layer 111b covers the bottom metal layer BML on the first buffer layer 111a, and the semiconductor layer AL1a of the first active layer AL1 is disposed on the second buffer layer 111b. Additionally, a first gate insulating layer 112 is disposed on the semiconductor layer AL1a in the OLED region, and the gate electrode GL1c of the first gate layer GL1 is disposed on the first gate insulating layer 112. When implemented, when the gate electrode GL1c is patterned during the manufacturing process, the first gate insulating layer 112 below the gate electrode GL1c can be patterned simultaneously with the gate electrode GL1c. Accordingly, the edge of the gate electrode GL1c can coincide with the edge of the first gate insulating layer 112 below the gate electrode GL1c.

[0174] Alternatively, the second gate layer GL2 can be disposed between the third gate insulating layer 114 and the second gate insulating layer 113 covering the first gate layer GL1. Figure 18 The second gate layer GL2 is shown to include a first portion GL2b and a second portion GL2a. The first portion GL2b corresponds to the gate electrode GL1c below the second gate layer GL2, and the second portion GL2a corresponds to the gate electrode GL3c above the second gate layer GL2. Additionally, the semiconductor layer AL2a of the second active layer AL2 is disposed on the third gate insulating layer 114. A fourth gate insulating layer 115 is disposed on the semiconductor layer AL2a, and the first source electrode GL3d, the first drain electrode GL3e, the second source electrode GL3a, the second drain electrode GL3b, and the gate electrode GL3c of the third gate layer GL3 are disposed on the fourth gate insulating layer 115.

[0175] When implemented, when the first source electrode GL3d, the first drain electrode GL3e, the second source electrode GL3a, the second drain electrode GL3b, and the gate electrode GL3c are patterned during the manufacturing process, the fourth gate insulating layer 115 beneath them can be patterned simultaneously with the first source electrode GL3d, the first drain electrode GL3e, the second source electrode GL3a, the second drain electrode GL3b, and the gate electrode GL3c. Accordingly, the edge of each of the first source electrode GL3d, the first drain electrode GL3e, the second source electrode GL3a, the second drain electrode GL3b, and the gate electrode GL3c can coincide with the edge of the fourth gate insulating layer 115 disposed therebelow.

[0176] The first source electrode GL3d and the first drain electrode GL3e may contact the semiconductor layer AL1a to allow electrical signals to be transmitted between the first source electrode GL3d and the first drain electrode GL3e based on the electrical signal applied to the gate electrode GL1c. The second source electrode GL3a and the second drain electrode GL3b may contact the semiconductor layer AL2a to allow electrical signals to be transmitted between the second source electrode GL3a and the second drain electrode GL3b based on the electrical signal applied to the gate electrode GL3c.

[0177] At least one of the first source electrode GL3d and the first drain electrode GL3e can contact the first wiring of the bottom metal layer BML. Figure 18 The diagram shows the first source electrode GL3d and the first drain electrode GL3e contacting corresponding wiring. Additionally, at least one of the second source electrode GL3a and the second drain electrode GL3b may contact the second wiring of the bottom metal layer BML. Figure 18 The diagram shows the wiring corresponding to the contact between the second source electrode GL3a and the second drain electrode GL3b.

[0178] In the display device according to the embodiment, the bottom metal layer BML can protect the thin-film transistor disposed on the bottom metal layer BML and can also be used as wiring. In the display device according to the embodiment, the structure of the metal layers on the first active layer AL1 and / or the second active layer AL2 can be simplified.

[0179] Because the pixel electrode 310 disposed on the planarization layer 118 covering the third gate layer GL3 is connected to, for example, the first drain electrode GL3e, the pixel electrode 310 can receive electrical signals from the thin-film transistor below it.

[0180] Figure 19 This is a cross-sectional view showing a portion of a display device according to another embodiment. The display device according to the embodiment and reference... Figure 18The difference in the described display device is that a second portion GL2a of the second gate layer GL2 is connected to a bottom metal layer BML via a contact hole defined in an insulating layer beneath it. The bottom metal layer BML to which the second portion GL2a is connected is electrically connected to the gate electrode GL3c, such that the second portion GL2a of the second gate layer GL2 and the gate electrode GL3c above the second portion GL2a operate as a dual-gate electrode.

[0181] Figure 20 This is an equivalent circuit diagram showing the pixels of a display device according to another embodiment. Figure 20 Equivalent circuit diagram and Figure 2 The equivalent circuit diagrams differ. As described above, the embodiments are applicable to display devices that include pixels PX corresponding to various equivalent circuits.

[0182] refer to Figure 20 Pixel PX includes first transistors T1 to seventh transistors T7, storage capacitor Cst, organic light-emitting diode (OLED), first initialization voltage line VIL1, second initialization voltage line VIL2, power supply voltage line PL, and signal lines. The signal lines may include data line DL, scan line SL, previous scan line SL', initialization line IL, compensation control line CL, and emission control line EL. At least one of the signal lines, the first initialization voltage line VIL1, the second initialization voltage line VIL2, and / or the power supply voltage line PL may be shared by adjacent pixels PX.

[0183] Equivalent circuit and reference according to the embodiment Figure 2 The difference in the described equivalent circuit is that, according to the embodiment, the equivalent circuit does not have a bias capacitor Cbia connected between the second node N2 and the emitter control line EL, the seventh transistor T7, which is the second initialization transistor, is implemented as a PMOS-FET instead of an NMOS-FET, and the gate electrode of the seventh transistor T7 is connected to the previous scan line SL' instead of the emitter control line EL and is turned on according to the previous scan signal GW[i-1] transmitted through the previous scan line SL' to transmit the second initialization voltage Vint2 from the second initialization voltage line VIL2, thereby initializing the organic light-emitting diode OLED. In some embodiments, the seventh transistor T7 may be omitted.

[0184] refer to Figure 2 The descriptions in the embodiments are applicable to other elements, and therefore, for ease of description, their descriptions are omitted.

[0185] Figure 21 It shows having Figure 20 The layout diagram of the positions of the transistors and capacitors of the pixels in the equivalent circuit. Figure 20 A pixel PX is shown.

[0186] Figures 22 to 28 Such as Figure 21 A layout diagram of each layer of transistors and capacitors. Figure 29 According to another embodiment, along Figure 21 The cross-sectional view of the display device taken by lines D-D', E-E', and F-F'. (See figure) Figures 22 to 28 The order shown in the middle, Figure 22 BML, the bottom metal layer Figure 23 The first active layer AL1, Figure 24 The first gate layer GL1, Figure 25 The second gate layer GL2, Figure 26 The second active layer AL2, Figure 27 The third gate layer GL3 and Figure 28 The source / drain layer SDL is positioned in a direction away from the substrate from the vicinity of the substrate.

[0187] An insulating layer is disposed between these layers. Specifically, a first buffer layer 111a may be disposed between the substrate 101 and... Figure 22 Between the bottom metal layers BML, the second buffer layer 111b can be set Figure 22 The bottom metal layer BML and Figure 23 Between the first active layers AL1, the first gate insulating layer 112 can be disposed Figure 23 The first active layer AL1 and Figure 24 Between the first gate layer GL1, the second gate insulating layer 113 can be disposed Figure 24 The first gate layer GL1 and Figure 25 Between the second gate layer GL2, the third gate insulating layer 114 can be disposed. Figure 25 The second gate layer GL2 and Figure 26 Between the second active layer AL2, the fourth gate insulating layer 115 can be disposed Figure 26 The second active layer AL2 and Figure 27 Between the third gate layer GL3, and the interlayer insulating layer 117 can be disposed. Figure 27 The third gate layer GL3 and Figure 28 The source and drain layers (SDLs) are located between the source and drain layers. These layers may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, and / or zinc oxide. When implemented, each insulating layer may be a single layer or multiple layers. Components in different layers can be electrically connected to each other through contact holes defined in the insulating layers.

[0188] refer to Figures 5 to 11 The content described in the embodiments is applicable to settings Figures 22 to 28 The layers between the layers shown are, and therefore, for ease of description, their descriptions are omitted. References Figures 5 to 11 The content described in the embodiments is applicable to the formation of Figures 22 to 28 The methods of the layers shown or the materials of these layers are described, and therefore, for ease of description, their common descriptions are omitted.

[0189] Figure 22 The bottom metal layer BML shown may include a metal such as silver, copper, or aluminum. The bottom metal layer BML can protect at least a portion of the first active layer AL1 and / or at least a portion of the second active layer AL2 described below. Additionally, the bottom metal layer BML can serve as wiring for electrically connecting various components of the display device to each other. Figure 22 The diagram shows a bottom metal layer BML including a first initialization voltage line VIL1-1 and a second initialization voltage line VIL2 extending in a first direction DR1. Additionally, the bottom metal layer BML may include a connecting electrode BMLC, a first bottom metal layer BML1', and a second bottom metal layer BML2', the connecting electrode BMLC having a shape patterned to be separate from each other.

[0190] Figure 23 The first active layer AL1 shown may be a semiconductor layer comprising polycrystalline silicon. Figure 20 The equivalent circuit diagram shows that a specific portion of the first active layer AL1 is doped with P-type impurities, and the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are implemented as PMOS-FETs. Additionally, other portions of the first active layer AL1 may be doped with impurities and may be used as wiring to electrically connect transistors and / or capacitors to each other, or as capacitor electrodes, etc.

[0191] Figure 26 The second active layer AL2 may be a semiconductor layer including an oxide layer. The second active layer AL2 according to the embodiment is compared with a reference layer. Figure 9 The difference in the second active layer AL2 in the described embodiment is that only the third transistor T3 and the fourth transistor T4 include the second active layer AL2.

[0192] Figure 24 , Figure 25 and Figure 27 The materials and references of the first gate layer GL1 to the third gate layer GL3 shown are as follows. Figure 7 , Figure 8 and Figure 10 The materials of the first gate layer GL1 to the third gate layer GL3 are the same.

[0193] Figure 24The first gate layer GL1 shown may include a scan line SL, an emission control line EL, and a previous scan line SL' each extending in the first direction DR1, and includes interconnecting electrodes GLC1, GLC2, and GLC3 separated from each other, as well as a first gate electrode G1. The first gate electrode G1 may be integral with the first capacitor electrode CE1.

[0194] Figure 25 The second gate layer GL2 shown includes a first initialization line IL1 and a first compensation control line CL1, each extending in the first direction DR1. Additionally, the second gate layer GL2 may include a second capacitor electrode CE2 disposed above the first capacitor electrode CE1 and cooperating with the first capacitor electrode CE1 to form a storage capacitor Cst.

[0195] like Figure 27 As shown, the third gate layer GL3 includes a first-second initialization voltage line VIL1-2, a second initialization line IL2, and a second compensation control line CL2, each extending along a first direction DR1. The first-second initialization voltage line VIL1-2 and the first-first initialization voltage line VIL1-1 together constitute the first initialization voltage line VIL1. The second initialization line IL2 and the first initialization line IL1 together constitute the initialization line IL. Additionally, the second compensation control line CL2 and the first compensation control line CL1 together constitute the compensation control line CL. The third gate layer GL3 may include a connection electrode GLC4.

[0196] For reference only. Figure 24 The contact hole GLT1 shown is defined in the first gate insulating layer 112 to allow for... Figure 24 The connecting electrode GLC1 shown is electrically connected to the electrode disposed below it. Figure 23 The second source region S2 of the first active layer AL1. Figure 24 The contact hole GLT2 shown is defined in the first gate insulating layer 112 to allow for... Figure 24 The connecting electrode GLC2 shown is electrically connected to the electrode located below it. Figure 23 The fifth source region S5 of the first active layer AL1. Additionally... Figure 24 The contact hole GLT3 shown is defined in the first gate insulating layer 112 to allow for... Figure 24 The connecting electrode GLC3 shown is electrically connected to the electrode located below it. Figure 23 The seventh source region S7 of the first active layer AL1.

[0197] Figure 25 The contact hole GLT4 shown is defined in the second gate insulating layer 113 to allow for... Figure 25 The second capacitor electrode CE2 shown is electrically connected to the electrode disposed below it. Figure 24 The connection electrode is GLC2. Accordingly, Figure 25 The second capacitor electrode CE2 shown is passed through Figure 24 The connecting electrode GLC2 is electrically connected to Figure 23 The fifth source region S5 is shown in the diagram.

[0198] Figure 26 The contact hole ALT1 shown is defined in the first gate insulating layer 112, the second gate insulating layer 113, and the third gate insulating layer 114 to allow for... Figure 26 The third drain region D3 of the second active layer AL2 shown is electrically connected to Figure 23 The first drain region D1 of the first active layer AL1 is shown. Additionally, Figure 26 The contact hole ALT2 shown is defined within the second buffer layer 111b, the second gate insulating layer 113, and the third gate insulating layer 114 to allow for... Figure 26 The fourth source region S4 of the second active layer AL2 shown is electrically connected to Figure 22 The first initialization voltage line VIL1-1 of the bottom metal layer BML shown is shown.

[0199] Figure 27 The contact hole GLT5 shown is defined in the fourth gate insulating layer 115 to allow for... Figure 27 The first-second initialization voltage line VIL1-2 shown is electrically connected to the line located below it. Figure 26 The fourth source region S4 of the second active layer AL2. Additionally... Figure 27 The contact hole GLT6 shown is defined in the fourth gate insulating layer 115 to allow for... Figure 27 The connecting electrode GLC4 shown is electrically connected to the electrode located below it. Figure 26 The fourth drain region D4 or the third source region S3 of the second active layer AL2.

[0200] Figure 28 The source / drain layer SDL includes a data line DL and a power supply voltage line PL extending in a near-second direction DR2. The second direction DR2 may be a direction intersecting the first direction DR1. The source / drain layer SDL may include connection electrodes SDC1 and SDC2.

[0201] Figure 28 The data line DL shown is electrically connected to the connection electrode GLC1 of the first gate layer GL1 through the contact hole SDLT1 defined in the second gate insulating layer 113, the third gate insulating layer 114, the fourth gate insulating layer 115 and / or the interlayer insulating layer 117, and is thus electrically connected to the second source region S2 of the first active layer AL1 through the connection electrode GLC1. Figure 28One end of the power supply voltage line PL shown is electrically connected to the second capacitor electrode CE2 of the second gate layer GL2 through a contact hole SDLT2 defined in the third gate insulating layer 114, the fourth gate insulating layer 115 and / or the interlayer insulating layer 117. Figure 28 The other end of the power supply voltage line PL shown is electrically connected to the second capacitor electrode CE2 of the second gate layer GL2 through a contact hole SDLT3 defined in the third gate insulating layer 114, the fourth gate insulating layer 115, and / or the interlayer insulating layer 117. Accordingly, although in Figure 28 The diagram shows that the power supply voltage line PL is disconnected in the middle, but the power supply voltage line PL can be electrically connected through the second capacitor electrode CE2 and multiple pixels PX arranged in the second direction DR2.

[0202] Figure 28 One end of the connecting electrode SDC1 shown is electrically connected to the connecting electrode GLC4 of the third gate layer GL3 through a contact hole SDLT4 defined in the interlayer insulating layer 117, and therefore can be electrically connected to the third source region S3 or the fourth drain region D4 of the second active layer AL2. The other end of the connecting electrode SDC1 can be electrically connected to the first capacitor electrode CE1 of the first gate layer GL1 through a contact hole SDLT5 defined in the second gate insulating layer 113, the third gate insulating layer 114, the fourth gate insulating layer 115 and / or the interlayer insulating layer 117. That is, the connecting electrode SDC1 can electrically connect the third source region S3 or the fourth drain region D4 of the second active layer AL2 to the first capacitor electrode CE1.

[0203] Figure 28 The connecting electrode SDC2 shown is electrically connected to the sixth drain region D6 and the seventh drain region D7 of the first active layer AL1 through contact holes SDLT6 defined in the first gate insulating layer 112, the second gate insulating layer 113, the third gate insulating layer 114, the fourth gate insulating layer 115 and / or the interlayer insulating layer 117. Although for ease of description... Figure 28 The image shows contact hole SDLT7, but contact hole SDLT7 is not a contact hole for connecting electrode SDC2 to the layer disposed beneath it. Contact hole SDLT7 is defined within the cover. Figure 28 In the planarization layer 118 of the source / drain layer SDL shown, the pixel electrode 310 of the organic light-emitting diode (OLED) disposed on the planarization layer 118 is electrically connected to the connection electrode SDC2.

[0204] When various wirings overlap with the active layer, the overlapping portion of the wiring can be used as a gate electrode. For example, the portion of the scan line SL of the first gate layer GL1 that overlaps with the first active layer AL1 can be disposed above the second active region A2 to serve as a second gate electrode. Similarly, the portion of the emitter control line EL of the first gate layer GL1 that overlaps with the first active layer AL1 can be disposed above the fifth active region A5 and the sixth active region A6 to serve as the fifth and sixth gate electrodes, and the portion of the previous scan line SL' of the first gate layer GL1 that overlaps with the first active layer AL1 can be disposed above the seventh active region A7 to serve as the seventh gate electrode.

[0205] The portions of the first initialization line IL1 of the second gate layer GL2 and the second initialization line IL2 of the third gate layer GL3 that overlap with the second active layer AL2 can be respectively disposed above and below the fourth active region A4 to serve as the fourth gate electrode. In this case, the fourth gate electrode can be understood as having a dual-gate structure. The portions of the first compensation control line CL1 of the second gate layer GL2 and the second compensation control line CL2 of the third gate layer GL3 that overlap with the second active layer AL2 can be respectively disposed above and below the third active region A3 to serve as the third gate electrode. In this case, the third gate electrode can be understood as having a dual-gate structure.

[0206] The first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be thin-film transistors comprising silicon semiconductors. The third transistor T3 and the fourth transistor T4 can be thin-film transistors comprising oxide semiconductors.

[0207] The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are disposed in the same layer, such as Figure 23 As shown, and includes the same materials. Figure 23 The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are shown to be integrally formed into a single unit. The semiconductor layers of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be interconnected and can be bent into various shapes, such as... Figure 23 As shown in the image.

[0208] As described above, the second active layer AL2 may include an oxide semiconductor. Additionally, as... Figure 26 As shown, the third transistor T3 and the fourth transistor T4 may include portions of the second active layer AL2 as components, such as... Figure 26 As shown in the diagram. The semiconductor layers of the third transistor T3 and the fourth transistor T4 can be connected to each other, as shown in the diagram. Figure 26 As shown in the image.

[0209] A pixel defining layer 119 can be disposed on a planarization layer 118. An organic light-emitting diode (OLED) can be disposed on a planarization layer 118. Its detailed description has been described above, and therefore its detailed description is omitted hereafter.

[0210] In the display device according to the embodiment, a bottom metal layer BML is provided to protect the first active layer AL1 and the second active layer AL2, which includes an oxide semiconductor, from external light and the like. Accordingly, a display device capable of displaying high-quality images can be realized. Figure 22 The diagram shows that the bottom metal layer BML includes a first bottom metal layer BML1' and a second bottom metal layer BML2', the first bottom metal layer BML1' corresponds to a first active region A1, and the second bottom metal layer BML2' corresponds to a third active region A3 and a fourth active region A4.

[0211] Furthermore, when implemented, the bottom metal layer BML may include a first initialization voltage line VIL1-1 and a second initialization voltage line VIL2, and the various components of the display device are electrically connected to each other via connection electrodes BMLC. Therefore, the layer structure in a display device with a multilayer structure can be simplified.

[0212] Figure 30 This is a cross-sectional view showing a portion of a display device according to another embodiment. The display device according to the embodiment and the one according to reference... Figure 29 The difference in the described embodiment of the display device is that the first-2 initialization voltage line VIL1-2 in the third gate layer GL3 is not only connected to the fourth source region S4 of the second active layer AL2, but the contact hole GLT5 is also defined in the second buffer layer 111b, the second gate insulating layer 113, and the third gate insulating layer 114. Therefore, the first-2 initialization voltage line VIL1-2 is directly connected to the first-1 initialization voltage line VIL1-1 of the bottom metal layer BML. Various modifications are possible.

[0213] In this respect, although an organic light-emitting display device has been described, this disclosure is not limited thereto, and any display device including a pixel PX having the above-described structure falls within the scope of this disclosure.

[0214] According to the embodiments, a high-resolution display device capable of displaying high-quality images can be realized. However, the scope of this disclosure is not limited to this effect.

[0215] Although certain embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the inventive concept is not limited to these embodiments, but is limited to the broader scope of the appended claims and various modifications and equivalents that will be apparent to those skilled in the art.

Claims

1. A display device, comprising: Organic light-emitting diode; A driving transistor is configured to control the amount of current flowing from a second node to the organic light-emitting diode based on the voltage applied to a first node, the second node being electrically connected to a power supply voltage line; A first bottom metal layer is disposed below the driving transistor and electrically connected to the driving transistor; as well as A first initialization transistor is connected between the first node and the first initialization voltage line. Wherein, the first bottom metal layer electrically connects the driving transistor to the first initialization transistor, and When viewed from a direction perpendicular to the first bottom metal layer, the first bottom metal layer overlaps with the first initialization semiconductor layer of the first initialization transistor.

2. The display device according to claim 1, wherein, The driving semiconductor layer of the driving transistor and the first initialization semiconductor layer of the first initialization transistor are disposed in different layers.

3. The display device according to claim 2, wherein, The first initialization semiconductor layer is disposed on an insulating layer covering the driving gate electrode of the driving transistor.

4. The display device according to claim 3, further comprising: A connecting electrode is disposed on the first initialization semiconductor layer and the first initialization semiconductor layer is connected to the first bottom metal layer through a contact hole.

5. The display device according to claim 2, wherein, The driving semiconductor layer includes a silicon semiconductor, and the first initialization semiconductor layer includes an oxide semiconductor.

6. The display device according to claim 1, wherein, The driving gate electrode of the driving transistor is electrically connected to the first bottom metal layer.

7. The display device according to claim 6, wherein, The driving gate electrode is disposed on the driving semiconductor layer of the driving transistor and is connected to the first bottom metal layer through contact holes defined in the insulating layer between the driving semiconductor layer and the driving gate electrode and in the insulating layer between the first bottom metal layer and the driving semiconductor layer.

8. The display device according to claim 7, wherein, The driving semiconductor layer is bent to surround a portion of the contact hole.

9. A display device, comprising: Organic light-emitting diode; A driving transistor is configured to control the amount of current flowing from a second node to the organic light-emitting diode based on the voltage applied to a first node, the second node being electrically connected to a power supply voltage line; A first bottom metal layer is disposed below the driving transistor and electrically connected to the driving transistor; An emission control transistor is connected between the driving transistor and the organic light-emitting diode and is turned on when an emission control signal is supplied through the emission control line; A second initialization transistor is connected between the emitter control transistor and the second initialization voltage line; as well as A second bottom metal layer is disposed below the emitter control transistor and the second initialization transistor, and the emitter control transistor is electrically connected to the second initialization transistor.

10. The display device according to claim 9, wherein, The emitter control semiconductor layer of the emitter control transistor and the second initialization semiconductor layer of the second initialization transistor are disposed in different layers.

11. The display device according to claim 10, wherein, The second initialization semiconductor layer is disposed on an insulating layer covering the emitter control gate electrode of the emitter control transistor.

12. The display device according to claim 11, further comprising: A first connection electrode is disposed on the second initialization semiconductor layer and electrically connects the second initialization semiconductor layer to the second bottom metal layer through a contact hole; as well as The second connection electrode is disposed in the same layer as the first connection electrode and connects the emission control semiconductor layer to the second bottom metal layer through a contact hole.

13. The display device according to claim 10, wherein, The emission control semiconductor layer comprises a silicon semiconductor, and the second initialization semiconductor layer comprises an oxide semiconductor.

14. The display device according to claim 9, wherein, The second bottom metal layer is disposed in the same layer as the first bottom metal layer.

15. A display device, comprising: Organic light-emitting diode; A driving transistor is configured to control the amount of current flowing from a second node to the organic light-emitting diode based on the voltage applied to a first node, the second node being electrically connected to a power supply voltage line; A first bottom metal layer is disposed below the driving transistor and electrically connected to the driving transistor; A storage capacitor is connected between the first node and the power supply voltage line and includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode and the driving gate electrode of the driving transistor are integrally formed into a single unit, and the second capacitor electrode is disposed on the first capacitor electrode. An operation control transistor is connected between the drive transistor and the power supply voltage line and is turned on when a transmit control signal is supplied through the transmit control line; as well as A third bottom metal layer is disposed below the operation control transistor and the operation control transistor is electrically connected to the second capacitor electrode.

16. The display device according to claim 15, further comprising: The connecting electrode is disposed in the same layer as the second capacitor electrode, and the operation control semiconductor layer of the operation control transistor is connected to the third bottom metal layer. The second capacitor electrode is electrically connected to the third bottom metal layer.

17. A display device, comprising: substrate; The first active layer includes a driving semiconductor layer disposed on the substrate; The first gate layer includes a driving gate electrode disposed on the driving semiconductor layer; An organic light-emitting diode, wherein the brightness of the organic light-emitting diode is controlled by the current flowing through the driving semiconductor layer based on the voltage applied to the driving gate electrode; as well as A bottom metal layer is disposed below the first active layer and includes a first bottom metal layer connected to the drive gate electrode. Wherein, the first gate layer further includes a first source electrode or a first drain electrode that contacts the first active layer, and The first source electrode or the first drain electrode contacts the first wiring of the bottom metal layer.

18. The display device according to claim 17, wherein, The driving gate electrode is connected to the first bottom metal layer through contact holes defined in the insulating layer between the first active layer and the first gate layer and in the insulating layer between the first bottom metal layer and the first active layer.

19. The display device according to claim 18, wherein, The driving semiconductor layer is bent to surround a portion of the contact hole.

20. A display device, comprising: substrate; The first active layer includes a driving semiconductor layer disposed on the substrate; The first gate layer includes a driving gate electrode disposed on the driving semiconductor layer; An organic light-emitting diode, wherein the brightness of the organic light-emitting diode is controlled by the current flowing through the driving semiconductor layer based on the voltage applied to the driving gate electrode; A bottom metal layer is disposed below the first active layer and includes a first bottom metal layer connected to the drive gate electrode; The second active layer is disposed above the first gate layer and includes a first initialization semiconductor layer; A second gate layer is disposed between the first gate layer and the second active layer and includes a bottom initialization line having a portion overlapping the first initialization semiconductor layer; as well as A third gate layer is disposed above the second active layer and includes a top initialization line having a portion overlapping with the first initialization semiconductor layer. The first bottom metal layer electrically connects the driving gate electrode to the first initialization semiconductor layer.

21. The display device according to claim 20, further comprising: A source / drain layer is disposed above the third gate layer and includes a connection electrode that connects the first initialization semiconductor layer to the first bottom metal layer through a contact hole.

22. The display device according to claim 20, wherein, When viewed from a direction perpendicular to the substrate, the first bottom metal layer overlaps with the first initial semiconductor layer.

23. The display device according to claim 20, wherein, The first active layer comprises a silicon semiconductor, and the second active layer comprises an oxide semiconductor.

24. The display device according to claim 20, wherein, The first active layer further includes an emission control semiconductor layer. The second active layer further includes a second initialization semiconductor layer, and The bottom metal layer further includes a second bottom metal layer that electrically connects the emission control semiconductor layer to the second initialization semiconductor layer.

25. The display device according to claim 24, wherein, The third gate layer further includes a first connection electrode and a second connection electrode, wherein the first connection electrode connects the second initialization semiconductor layer to the second bottom metal layer through a contact hole, and the second connection electrode connects the emission control semiconductor layer to the second bottom metal layer through a contact hole.

26. The display device according to claim 20, wherein, The third gate layer further includes a second source electrode or a second drain electrode that contacts the second active layer.

27. The display device according to claim 26, wherein, The second source electrode or the second drain electrode contacts the second wiring of the bottom metal layer.

28. The display device according to claim 20, wherein, The third gate layer further includes a first source electrode or a first drain electrode that contacts the first active layer and a second source electrode or a second drain electrode that contacts the second active layer.

29. The display device according to claim 28, wherein, The first source electrode or the first drain electrode contacts the first wiring of the bottom metal layer, and the second source electrode or the second drain electrode contacts the second wiring of the bottom metal layer.

30. A display device, comprising: substrate; The first active layer includes a driving semiconductor layer disposed on the substrate; The first gate layer includes a driving gate electrode disposed on the driving semiconductor layer; An organic light-emitting diode, wherein the brightness of the organic light-emitting diode is controlled by the current flowing through the driving semiconductor layer based on the voltage applied to the driving gate electrode; A bottom metal layer is disposed below the first active layer and includes a first bottom metal layer connected to the drive gate electrode; as well as A second gate layer is disposed above the first gate layer and includes a second capacitor electrode that at least partially overlaps with the driving gate electrode. The first active layer further includes an operation control semiconductor layer. The first gate layer further includes a bottom emission control line overlapping the operation control semiconductor layer, and The bottom metal layer further includes a third bottom metal layer that electrically connects the operation control semiconductor layer to the electrode of the second capacitor.

31. The display device according to claim 30, wherein, The second gate layer further includes a connection electrode connecting the operation control semiconductor layer to the third bottom metal layer, and the second capacitor electrode is connected to the third bottom metal layer.

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