Semiconductor device and method of controlling the same

Abstract

The present disclosure relates to a semiconductor device and a control method thereof. A semiconductor device includes a flash memory including a plurality of electrically erasable memory cells and configured to output a verification result signal indicating whether erasure is successful, and a control block configured to control the flash memory. The control block includes a bulk erase range control circuit indicating a collective erase range in the flash memory. After erasure is performed, when the verification result signal VR indicates that erasure of sectors in a first range designated by the bulk erase range control circuit fails, a second range in which erasure is to be performed again is calculated based on a failed sector address designating the sectors for which erasure failed and an end sector address designating an end of the first range, the designated second range is set to the bulk erase range control circuit, and erasure is performed on sectors in the second range.

Description

[0001] Cross-references to related applications

[0002] The disclosure of Japanese Patent Application No. 2020-216102, filed on December 25, 2020, including the specification, drawings and abstract, is incorporated herein by reference in its entirety. Technical Field

[0003] This invention relates to a semiconductor device and a method for controlling the same. In particular, the invention relates, for example, to a semiconductor device provided with a memory and a method for controlling the same, the memory being capable of collectively erasing (or batch erasing) multiple sectors by using a predetermined number of electrically erasable memory cells as a sector. Background Technology

[0004] For example, Patent Document 1 describes a batch erasable memory provided with multiple electrically erasable memory cells as a flash memory. Furthermore, Patent Document 1 describes a batch erase operation for centrally erasing multiple basic memory blocks, each basic memory block having multiple memory cells.

[0005] The publicly available technologies are listed below.

[0006] [Patent Document 1] Japanese Unexamined Patent Application Publication No. 2008-293654 Summary of the Invention

[0007] The basic memory block (hereinafter also referred to as a "block") described in Patent Document 1 consists, for example, a predetermined number of electrically erasable memory cells, and multiple blocks are to be erased collectively. In this case, the area to be erased (erasure range: for example, the number of consecutive blocks) is determined at the start of the batch erase operation, and changes in the erase range during the erase operation are not considered.

[0008] In memories such as flash memory, an erase operation includes: an erase operation that changes the threshold of a memory cell to a predetermined value (hereinafter also referred to as an "erase / write operation"); and a verification operation that confirms whether the threshold of the memory cell was changed to the predetermined value during the erase / write operation (i.e., whether the erase was successful). Therefore, in the following text, an erase operation is also referred to as an erase verification operation.

[0009] When multiple blocks undergo batch erasure and the unsuccessful (i.e., failed) blocks are confirmed by the verification operation, an erasure verification operation is performed on the erasure range determined at the start of the batch erasure operation. Therefore, there is a problem of increased erasure verification time. Patent Document 1 does not describe or acknowledge this problem.

[0010] The following is a brief summary of one of the representative embodiments disclosed in this application.

[0011] That is, the semiconductor device according to a representative embodiment includes: a memory provided with a plurality of electrically erasable memory cells and configured to output a verification result signal indicating whether erasure was successful; and a control block configured to control the memory. Here, the control block includes a batch erase range control circuit that indicates a range in the memory to be collectively erased. After erasure is performed, when the verification result signal indicates that erasure of sectors in a first range specified by the batch erase range control circuit has failed, a second range is specified for further erasure based on the failed sector address and the end sector address, the failed sector address specifying the sector that failed to be erased, and the end sector address specifying the end of the first range, and the specified second range is set to the batch erase range control circuit, and erasure of sectors in the second range is performed.

[0012] Other objects and novel features will become apparent from the description in this specification and the accompanying drawings.

[0013] According to one embodiment, a semiconductor device provided with a memory capable of shortening the time of an erase operation can be provided. Attached Figure Description

[0014] Figure 1 This is a block diagram illustrating the configuration of a semiconductor device according to the first embodiment.

[0015] Figure 2 This is a block diagram illustrating the configuration of the control block according to the first embodiment.

[0016] Figure 3 This is a flowchart illustrating the batch erasure operation according to the first embodiment.

[0017] Figure 4 This is a view used to schematically illustrate the batch erase operation according to the first embodiment.

[0018] Figure 5 This is a view used to schematically illustrate the batch erase operation according to the first embodiment.

[0019] Figure 6 This is a view used to schematically illustrate the batch erase operation according to the first embodiment.

[0020] Figure 7 This is a view used to schematically illustrate the batch erase operation according to the first embodiment.

[0021] Figure 8 This is a view used to schematically illustrate the batch erase operation according to the first embodiment.

[0022] Figure 9This is a block diagram illustrating the configuration of the control block according to the second embodiment.

[0023] Figure 10 This is a flowchart illustrating the batch erasure operation according to the second embodiment.

[0024] Figure 11 This is a view used to schematically illustrate the batch erasure operation according to the second embodiment.

[0025] Figure 12 This is a view used to schematically illustrate the batch erasure operation according to the second embodiment.

[0026] Figure 13 This is a view used to schematically illustrate the batch erasure operation according to the second embodiment.

[0027] Figure 14 This is a block diagram illustrating the configuration of the control block according to the third embodiment.

[0028] Figure 15 This is a flowchart illustrating the batch erasure operation of the third embodiment.

[0029] Figure 16 This is a view used to schematically illustrate the batch erase operation according to the third embodiment.

[0030] Figure 17 This is a view used to schematically illustrate the batch erase operation according to the third embodiment.

[0031] Figure 18 This is a view used to schematically illustrate the batch erase operation according to the third embodiment.

[0032] Figure 19 This is a view used to schematically illustrate the batch erase operation according to the third embodiment.

[0033] Figure 20 This is a view used to schematically illustrate the batch erase operation according to the third embodiment.

[0034] Figure 21A and Figure 21B It is a view used to illustrate a problem.

[0035] Figure 22 It is a view used to illustrate a problem. Detailed Implementation

[0036] In the following description, corresponding embodiments of the invention will be illustrated with reference to the accompanying drawings. Note that this disclosure is merely an example, and appropriate modifications that can be readily conceived by those skilled in the art without departing from the spirit of the invention are of course included within the scope of the invention.

[0037] Furthermore, in this specification and the corresponding drawings, the same reference numerals are assigned to similar components described in the drawings, which have already been described. Their detailed description may be omitted as appropriate.

[0038] (First Embodiment)

[0039] In the following description, as an example, a semiconductor device provided with flash memory as memory will be described. Furthermore, sectors in the flash memory will be described as blocks to be erased by a batch erase operation, as an example. For example, a sector consists of electrically rewritable memory cells with 512 bytes. For example, if the memory cells are for storing binary data and one byte is 8 bits, a sector consists of 512 × 8 memory cells. Of course, the number of memory cells constituting a sector is not limited to this. Furthermore, a sector is merely an example, and a block is not limited to a sector.

[0040] Before explaining the semiconductor device according to the first embodiment, the problems discovered by the inventors of this application will be described with reference to the accompanying drawings.

[0041] <Problem Description>

[0042] Figure 21 and Figure 22 This is a view used to illustrate the problem addressed in this application. Here, Figure 21A This is a schematic diagram used to illustrate batch erasure operations, and Figure 21B This is a flowchart of a batch erase operation.

[0043] Figure 21 illustrates a memory configuration with 32 or more sectors, and as shown in Figure 21, Figure 21A The diagram illustrates a batch erase operation on 32 consecutive sectors, from sector 0 to sector 31. Additionally, as an example, Figure 21 illustrates a case where erasure fails in sector 30. Sector addresses are assigned to sectors 0 through 31, respectively. The starting sector address specifies sector 0, and the ending sector address specifies sector 31.

[0044] like Figure 21B As shown, in step S0, sector addresses are set to specify the multiple sectors to be erased. Here, a start sector address and an end sector address are set. Next, a sector erase command is issued in step S1. In step S2, the batch erase range of the multiple sectors is set. That is, the range represented by the start sector address and end sector address set in step S0 is set as the batch erase range.

[0045] In step S3, an erase / write operation is performed; in step S4, a verification operation is performed; in step S5, a determination is made as to whether the erase was successful (verification passed?). If the erase is successful in step S5, the batch erase operation is terminated in step S6. If the erase fails, the process returns to step S3, and the procedures in steps S3 to S5 are executed again. That is, in steps S3 to S5, the erase verification operation configured by the erase / write operation and the subsequent verification operation is executed again.

[0046] exist Figure 21A In the diagram, EV_1 represents the first round of erase verification operations, and EV_2 represents the second round of erase verification operations. Erasing of sectors 0 to 31 is performed through the erase / write operations in erase verification operation EV_1. The verification operation confirms whether the erasure of each sector was successful. Figure 21A In the example, the erasure in sector 30 was confirmed to have failed, and the verification operation was stopped. That is, in Figure 21B The result at step S5 is "no". As a result, step S3 is executed again, and the erase verification operation EV_2 begins. In erase verification operation EV_2, sectors 0 to 31 are erased via erase / write operations, and then the verification operation is performed. Figure 21A In the example shown, the verification operation in the second round of erase verification operation EV_2 confirms that the erasure of each sector from sector 0 to sector 31 was successful, and the batch erase operation is terminated.

[0047] Therefore, even if the erasure of sectors 0 to 29 is successful in the first round of erase verification operation EV_1, the erase verification operation EV_2 for sectors 0 to 31 is executed again. This results in a longer erase time. Furthermore, since two erase / write operations are performed on sectors 0 to 29, there are concerns that the increased number of erase operations may accelerate the degradation of memory cell characteristics.

[0048] In Figure 21, the batch erase range is the range specified by sector addresses that are powers of two. That is, the end sector address is represented by a power of two. It is expected that the batch erase range will be represented by a power of two. However, for example, if the end sector address is not represented by a power of two, and the end sector address specifies sector 30, such as... Figure 22As shown, erase verification operations are performed simultaneously with switching the erase range. Specifically, erase verification operation EV_1 performs erase / write and verification operations on 16 sectors, and erase verification operation EV_2 performs erase / write and verification operations on four sectors. Then, erase verification operation EV_3 performs erase / write and verification operations on two sectors, and erase verification operation EV_4 performs erase / write and verification operations on one sector. In this case, even if no erase failure is confirmed, the number of erase verification operations increases, resulting in a longer erase time.

[0049] <Configuration of the semiconductor device according to the first embodiment>

[0050] Figure 1 This is a block diagram illustrating the configuration of a semiconductor device according to a first embodiment. Figure 1 In the accompanying drawings, reference numeral 1 denotes a semiconductor device. For example, in a first embodiment, the semiconductor device 1 is composed of a microcontroller. The semiconductor device (microcontroller) 1 includes various circuit blocks, etc., but... Figure 1 The diagram illustrates the circuit blocks required for the following instructions. Figure 1 In the figure, reference numeral 2 indicates the processor (CPU), reference numeral 3 indicates the input / output block (I / O), and reference numeral 4 indicates volatile memory (RAM). Furthermore, reference numeral 5 indicates flash memory provided with multiple memory cells that can be electrically erased and written, and reference numeral 6 indicates a control block (FCB) configured to control the flash memory 5.

[0051] Each of the processor 2, input / output block 3, volatile memory 4, flash memory 5, and control block 6 is connected to bus 7 and transmits and receives data between them. Data to be written is provided from processor 2 to flash memory 5, for example, via bus 7, and data read from flash memory 5 is provided to processor 2, for example, via bus 7. Commands from processor 2 (e.g., sector erase commands) are provided to control block 6, which controls flash memory 5 according to the provided commands, thereby enabling writing and erasing to and from flash memory 5.

[0052] <<Control Block Configuration>>

[0053] Figure 2 This is a block diagram illustrating the configuration of the control block according to the first embodiment. Control block 6 includes multiple circuit blocks for controlling the flash memory 5. However, Figure 2 Only the circuit block related to erasure is shown (which is necessary for the following explanation). Furthermore, to illustrate the signals transmitted and received between flash memory 5 and control block 6, Figure 2 The diagram also shows flash memory 5.

[0054] Flash memory 5 includes multiple memory cells (not shown) and control circuitry (not shown). When an erase command signal EIR is provided from control block 6, the control circuitry performs an erase verification operation on the sector specified by the sector address indicated by the erase command signal EIR. As described above, the erase verification operation includes an erase / write operation and a verification operation. The control circuitry provides the result of the verification operation to control block 6 as a Verify result signal VR.

[0055] Next, the configuration of control block 6 will be described. Control block 6 includes a batch erase range control circuit 6_1, an address and mode control circuit 6_2, an address switching circuit 6_3, and a selector 6_4.

[0056] The erase end sector address is provided from the address and mode control circuit 6_2 to the bulk erase range control circuit 6_1. Additionally, the selector address selected by selector 6_4 is also provided to the bulk erase range control circuit 6_1. The bulk erase range control circuit 6_1 stores a range of sector addresses specified by the erase end sector address and the sector address from selector 6_4 (as the bulk erase range) and provides this range to the address and mode control circuit 6_2 as an erase range signal.

[0057] Processor 2 provides the erase start sector address and erase end sector address (which specify the range of the batch erase) to address and mode control circuit 6_2. Address and mode control circuit 6_2 provides the erase start sector address to selector 6_4 and the erase end sector address to batch erase range control circuit 6_1.

[0058] The verification result signal VR is provided to the address and mode control circuit 6_2. If the verification result signal VR indicates an erasure failure, the address and mode control circuit 6_2 provides the sector address (as the failed sector address) of the sector that failed to be erased to the address switching circuit 6_3. Furthermore, the address and mode control circuit 6_2 provides the erase command signal EIR to the flash memory 5. The erase command signal EIR is used to instruct a batch erase to be performed on the sector range indicated by the erase range signal provided by the batch erase range control circuit 6_1.

[0059] The verification result signal VR is provided from flash memory 5 to address switching circuit 6_3. If the verification result signal VR indicates an erase failure, address switching circuit 6_3 provides the failed sector address from address and mode control circuit 6_2 to selector 6_4 and outputs an address switching signal (i.e., a select signal) to selector 6_4. In response to this address switching signal, selector 6_4 provides the failed sector address to bulk erase range control circuit 6_1 instead of providing the erase start selector address.

[0060] <<Batch Erasure Operation>>

[0061] Next, the operation when a sector erase command for instructing bulk erasure is provided from processor 2 to control block 6 will be described with reference to the accompanying drawings. Figure 3 This is a flowchart illustrating the batch erasure operation according to the first embodiment. Furthermore, Figures 4 to 8 This is a view used to schematically illustrate the batch erase operation according to the first embodiment.

[0062] exist Figure 3 In step S00, processor 2 (see...) Figure 1 The erase start sector address and erase end sector address (both specifying the erase range for batch erasure) are set to the address and mode control circuit 6_2. In step S01, the processor 2 issues a sector erase command (i.e., a batch sector erase command) to the control block 6. By issuing the sector erase command, in step S02, via selector 6_4, the address and mode control circuit 6_2 provides the set erase end sector address to the batch erase range control circuit 6_1, and also provides the erase start sector address to the batch erase range control circuit 6_1. As a result, multiple sectors, including the range specified by the erase start sector address and erase end sector address, are set to (or stored in) the batch erase range control circuit 6_1 as a batch erase range (i.e., a first range), and the set batch erase range is output to the address and mode control circuit 6_2 as an erase range signal.

[0063] Next, in step S03, the address and mode control circuit 6_2 operates in erase / write mode. That is, the address and mode control circuit 6_2 provides the flash memory 5 with an erase command signal EIR, which instructs the erasure of multiple sectors specified by the erase range signal. Figure 4 The erasure operation at step S03 is illustrated schematically. Figure 4 The diagram illustrates a batch erase range from sector 0 to sector 31. Here, the erase start sector address specifies sector 0, and the erase end sector address specifies sector 31. Although not specifically limited, the address and mode control circuit 6_2 outputs an erase command signal EIR to indicate sector erasure and to specify the sector address to be erased. That is, in step S03, the address and mode control circuit 6_2 outputs the erase command signal EIR to perform the erase, while continuously updating the sector address from the erase start sector address to the erase end sector address. As a result, in the flash memory 5, as... Figure 4 As shown, erase / write operations are performed on sectors 0 to 31, thereby erasing 32 consecutive sectors.

[0064] Back Figure 3 Next, the processes in steps S03 and S04 are executed. In step S04, a verification operation is performed. That is, in step S04, the address and mode control circuit 6_2 operates in verification operation mode. In verification operation mode, the address and mode control circuit 6_2 outputs an instruction for performing the verification operation as an erase command signal EIR, while continuously updating the sector address from the erase start sector address to the erase end sector address. When the verification operation instruction is received, the flash memory 5 performs a verification operation on the sector specified by the currently provided sector address. That is, the flash memory 5 determines whether the threshold of each memory cell included in the specified sector has changed to a predetermined value. If the threshold has changed to the predetermined threshold, the flash memory 5 outputs a verification result signal VR indicating successful erasure. On the other hand, if the threshold has not changed to the predetermined threshold, the flash memory 5 outputs a verification result signal VR indicating erase failure. Figure 5 The illustration shows the status of the verification operation in progress. For example... Figure 5 As shown, the verification operations are performed sequentially from sector 0 toward sector 31.

[0065] Each time the verification operation for a sector is completed, execute Figure 3 The process at step S05 is illustrated in the diagram. At step S05, the address and mode control circuit 6_2 determines whether the verification result signal VR indicates erasure failure. If the verification result signal VR indicates successful erasure, the address and mode control circuit 6_2 updates the sector address and outputs an erase command signal EIR to indicate the verification operation. If the updated sector address reaches the erase end sector address and the verification result signal VR for sector 31 specified by the erase end sector address indicates successful erasure in step S05, the address and mode control circuit 6_2 executes the process at step S06. At step S06, the batch erase operation on the erase range from sector 0 to sector 31 is terminated.

[0066] On the other hand, if the verification result signal VR at step S05 indicates that erasure has failed, the address and mode control circuit 6_2 stops the verification operation. That is, the address and mode control circuit 6_2 stops updating the sector address and stops the verification operation. Figure 6 The schematic diagram illustrates the erase failure state in sector 30. Figure 6In this process, the "×" mark attached to sector 30 indicates an erasure failure. The erasure failure is notified to the address and mode control circuit 6_2 via a verification result signal VR. Upon receiving this notification, the address and mode control circuit 6_2 outputs the current sector address to the address switching circuit 6_3 as the failed sector address for specifying the sector where the erasure failed. Furthermore, after step S05, the process in step S07 is executed instead of the process in step S06.

[0067] In step S07, since the verification result signal VR indicates erasure failure, the address switching circuit 6_3 provides the failed sector address output from the address and mode control circuit 6_2 to the selector 6_4. At this time, the address switching circuit 6_3 controls the selector 6_4 through the address switching signal, so that the selector 6_4 selects the failed sector address. As a result, the failed sector address is provided from the selector 6_4 to the batch erase range control circuit 6_1 as the sector address, and the range specified by the failed sector address and the erase end sector address (i.e., the second range) is stored and reset as the erase range.

[0068] Figure 7 The state during the process at step S07 is illustrated schematically. Since erasure failed in sector 30, the two sectors, including sector 30 specified by the failed sector address and sector 31 specified by the erase end sector address, are reset to the batch erase range control circuit 6_1 as the erase range.

[0069] When the process at step S07 is completed, the processing flow returns to step S03. Erasure range signals indicating sectors 30 and 31 (for resetting the erase range) are provided from the bulk erase range control circuit 6_1 to the address and mode control circuit 6_2. At step S03, the address and mode control circuit 6_2 provides the flash memory 5 with erase command signals EIR for erasing sectors 30 and 31. Next, at step S04, the address and mode control circuit 6_2 causes the flash memory 5 to perform a verification operation on sectors 30 and 31. Figure 8 The current state is illustrated schematically. As a result, erase / write operations are performed in the first round of erase verification operation EV_1, but no erase / write or verification operations are performed on sectors that were successfully erased during the verification operation. A second round of erase verification operation EV_2 (including the re-erasure step of the erase / write operation and the verification step) is performed on the range from the sectors that failed to be erased to the sector specified by the erase end sector address.

[0070] According to the first embodiment, even if the erase operation confirms that the erase has failed, the erase verification operation can be prevented from being performed again on the successfully erased sectors. This prevents the erase time from becoming longer. Furthermore, it also helps to suppress the degradation of memory cell characteristics.

[0071] (Second Embodiment)

[0072] In the first embodiment, in Figure 3 An example of suppressing the increase in erase time has been described in step S07 of the diagram where the reset erase range is expressed as a power of two. In the second embodiment, a semiconductor device is provided that can suppress the increase in erase time when the reset erase range is not expressed as a power of two.

[0073] Figure 9 This is a block diagram illustrating the configuration of the control block according to the second embodiment. Figure 9 Similar to Figure 2 The difference between the two is that... Figure 9 A power address calculation circuit 6_5 was added. The address of the failed sector is provided to the power address calculation circuit 6_5 from the address switching circuit 6_3. The address of the erase end sector is provided to the power address calculation circuit 6_5 from the address and mode control circuit 6_2. The power sector address calculated by the power address calculation circuit 6_5, replacing the address of the failed sector, is provided to the selector 6_4.

[0074] Figure 10 This is a flowchart illustrating the batch erasure operation according to the second embodiment. Figure 10 Similar to Figure 3 The difference between the two is that... Figure 10 A power address range calculation step S10 has been added. If the verification result signal VR at step S05 indicates that the erasure has failed, the process at step S10 is executed, and at step S07, the erasure range calculated at step S10 is set to the batch erasure range control circuit 6_1.

[0075] Figures 11 to 13 This is a view used to schematically illustrate the batch erasure operation according to the second embodiment.

[0076] Similar to the first embodiment, the scenario where a bulk erase operation is instructed to perform a bulk erase of sectors 0 to 31 in the flash memory 5 will be described. Figure 10 In step S02, sectors 0 to 31 are set to the batch erase range control circuit 6_1 as the erase range. In step S03, erase / write operations are performed on 32 sectors (sectors 0 to 31), and as follows... Figure 11 As shown, 32 sectors were erased.

[0077] Suppose that the threshold of the memory cells in sector 29 does not reach a predetermined value, and the erase failure in sector 29 is notified by the verification result signal VR. In this case, as... Figure 11As shown, the verification operation for sector 29 is stopped at step S05. In this case, the range where no verification operation is performed becomes three sectors, and this range cannot be represented by a power of two.

[0078] In the second embodiment, the power address calculation circuit 6_5 calculates and outputs a power address for a specified range, which includes the addresses of failed sectors and becomes a power of two between this power address and the erase end sector address. At this time, the power address calculation circuit 6_5 calculates the power sector address, making the range the minimum possible range. Figure 12 The illustration shows the calculation of the power sector address by the power address calculation circuit 6_5 during range calculation. The power sector address includes the failed sector address and becomes the minimum range. In this case, the power address calculation circuit 6_5 calculates a power sector address that specifies a range of four sectors between the failed sector address and the erase end sector address, including sector 29 specified by the failed sector address. Here, the power sector address is the sector address that specifies sector 28.

[0079] At step S07, the power sector address is provided and set to the bulk erase range control circuit 6_1 via selector 6_4. Then, the process in steps S03 to S05 is executed again. The result is as follows: Figure 13 As shown, in the second round of erase verification operation EV_2, erase / write operations and verification operations are performed on four sectors 28 to 31, the process transitions to step S06, and the batch erase operation is terminated.

[0080] According to the second embodiment, the reset range can be represented by a power of two, which makes it possible to shorten the erasure time.

[0081] (Third Embodiment)

[0082] In a third embodiment, a semiconductor device is provided that is configured to automatically switch between a configuration according to the first embodiment and a configuration according to the second embodiment, depending on the erase range to be reset to the batch erase range control circuit 6_1, in other words, depending on the number of remaining sectors (hereinafter referred to as "remaining sectors") (because they were not determined to be erased successfully in a previous (e.g., first round) erase verification operation).

[0083] Figure 14 This is a block diagram illustrating the configuration of the control block according to the third embodiment. Figure 14 Similar to Figure 9 The difference between the two is that... Figure 14A comparator circuit 6_6 and a selector 6_7 were added. Comparator circuit 6_6 compares the failed sector address output from address switching circuit 6_3 with the erase end sector address, and outputs the comparison result as an erase range selection signal. The failed sector address and the exponential sector address from address switching circuit 6_3 are provided to selector 6_7. Selector 6_7 selects either the failed sector address or the exponential sector address according to the erase range selection signal, and provides the selected address instead of the exponential sector address to selector 6_4.

[0084] Selectors 6_4 and 6_7 can be considered as a single selector. In this case, the single selector is controlled by the selection signal from the address switching circuit 6_3 and the erase range selection signal from the comparator circuit 6_6. That is, the selector is controlled by the verification result signal VR and the comparison result of the comparator circuit 6_6.

[0085] Figure 15 This is a flowchart illustrating the batch erasure operation according to the third embodiment. Figure 15 Similar to Figure 10 The difference between the two lies in the direction... Figure 15 Step S20 is added, where address determination is performed. In step S05, if the verification operation stops, step S20 determines whether the number of remaining sectors is a predetermined value (i.e., a number threshold) or higher. If the number of remaining sectors is determined to be the number threshold or higher, the process in step S10 is then executed. If the number of remaining sectors is determined to be less than the number threshold, the process in step S07 is executed.

[0086] Figures 16 to 20 This is a view used to schematically illustrate the batch erase operation according to the third embodiment. Here, as... Figure 16 The diagram illustrates a batch erasure of 64 sectors (sectors 0 to 63) that constitute the erasure range. Furthermore, the case where erasure failed in sector 3 will be described first, followed by the case where erasure failed in sector 62.

[0087] First, in step S03, 64 sectors are erased. If erasure fails in sector 3, as... Figure 17 As shown, the verification operation is stopped in sector 3, and the address of the failed sector specified in sector 3 is output from the address switching circuit 6_3.

[0088] In step S20, comparator circuit 6_6 calculates the difference between the address of the failed sector (sector 3) and the address of the erased sector (sector 63), calculates the number of remaining sectors as 60, and compares the calculated number of sectors with a number threshold. Here, as an example, the case where the number threshold is 33 will be described.

[0089] Since the number of remaining sectors is 33 or more, the process at step S10 is then executed. Furthermore, in this case, comparator circuit 6_6 instructs selector 6_7 to select an exponential sector address via an erase range selection signal. At step S10, as described in the second embodiment, the exponential sector address is calculated. The calculated exponential sector address is provided to batch erase range control circuit 6_1 via selectors 6_7 and 6_4. As a result, at step S07, the erase range specified by the exponential sector address and the erase end sector address is reset to the batch erase range control circuit 6_1. In this case, the exponential sector address specifies sector 0, such as... Figure 18 As shown, the erasure range becomes the range from sector 0 to sector 63. That is, as... Figure 18 As shown, the second round of erase verification operation EV_2 is performed on sectors 0 to 63.

[0090] If, in the second round of erase verification operation EV_2, it is determined that the erase was successful in sector 3, and this time it is determined that the erase failed in sector 62, then... Figure 19 As shown, the verification operation stops at step S05 in the second round of erase verification operation EV_2, and the failure sector address of sector 62 is output from the address switching circuit 6_3. The number of remaining sectors is calculated in the comparator circuit 6_6, and it is determined that the number of remaining sectors is 2, and that the number of remaining sectors is less than 33 (32 or less). Based on this determination, the comparator circuit 6_6 controls the selector 6_7 via the erase range selection signal to select the failure sector address output from the address switching circuit 6_3.

[0091] Therefore, the failed sector address, instead of the power sector address, is provided to the bulk erase range control circuit 6_1, and the erase range indicated by the failed sector address and the erase end sector address is reset. As a result, Figure 20 As shown, the third round of erase verification operation EV_3 is performed, and in the third round of erase verification operation EV_3, erase / write operations and verification operations are performed on the remaining sectors 62 and 63.

[0092] According to the third embodiment, by using a number threshold as a boundary, the configuration described in the first embodiment and the configuration described in the second embodiment can be automatically selected. According to the first embodiment, compared to using power-law sector addresses, the erase range can be set to a minimum range, which allows for suppression of memory cell characteristic degradation. On the other hand, according to the second embodiment, since the erase range is specified by power-law sector addresses, the erase time can be minimized.

[0093] As described above, the invention made by the inventors(s) of this application has been specifically described based on embodiments. However, the invention is not limited to the above embodiments, and needless to say, the invention can be modified in various forms without departing from its essence. For example, when the verification result signal VR indicates an erasure failure, the address and mode control circuit 6_2 outputs the failure sector address. However, in this case, the address and mode control circuit 6_2 can output the failure address that directly specifies the memory cell that failed to be erased. In this case, for example, the address switching circuit 6_3 converts the failure address into a failure sector address that includes it and outputs the failure sector address.

Claims

1. A semiconductor device, comprising: The memory is provided with a plurality of electrically erasable memory cells, and the memory is configured to output a verification result signal indicating whether the erasure was successful; as well as The control block is configured to control the memory. The control block includes a batch erase range control circuit that indicates the range to be collectively erased in the memory. After erasure is performed, when the verification result signal indicates that erasure of sectors within the first range specified by the batch erasure range control circuit has failed, a second range is specified for re-execution based on the failure sector address of the sector that failed to be erased and the end sector address of the first range. This second range is then set to the batch erasure range control circuit, and erasure is performed on the sectors within this second range. The control block includes: The selector is configured to provide a start sector address and the failure sector address, the start sector address specifying the beginning of the first range; and The switching circuit is configured to output a selection signal, based on the verification result signal, to control the selection of the selector. The control block includes: A power-law address calculation circuit is configured to: calculate a sector address based on the end sector address and the failed sector address, the sector address including the sectors that failed to be erased and indicating a quadratic power range that can be collectively erased; and provide the calculated sector address to the selector; and The comparator circuit is configured to: determine the number of sectors for which a confirmation of whether erasure was successful has not yet been performed based on the failed sector address and the ended sector address, and compare the number of sectors with a number threshold. The selector is configured to select a sector address based on the verification result signal and the determination result of the comparator circuit.

2. The semiconductor device according to claim 1, The control block is configured to: calculate a sector address based on the end sector address and the failed sector address, and erase the sector address as a second range, the sector address indicating a power-square range that can be collectively erased, the power-square range including the sectors that failed to be erased.

3. The semiconductor device according to claim 2, The control block includes a power address calculation circuit configured to calculate a quadratic sector address that is the smallest possible range, including the failed sector address.

4. A method for controlling a semiconductor device, the semiconductor device being provided with a memory including a plurality of electrically erasable memory cells, the memory being configured to output a verification result signal indicating whether erasure was successful, the method comprising: The erasure step is configured to erase multiple sectors in a first range, the first range being specified by a start sector address and an end sector address; The verification step is configured to: after the erasure step, confirm whether the sectors in the first range have been erased; When sectors that were not erased in the verification step are confirmed, the number of sectors that have not yet been confirmed as having been erased is determined based on the failure sector address and the end sector address of the specified unerased sectors, and the number of sectors is compared with a number threshold. as well as The re-erase step is configured to: dynamically select and erase sectors in the second range based on the comparison results. When the number of sectors is greater than or equal to the number threshold, the second range is a collectively erasable power-of-two range specified by the power-of-two sector address and the end sector address, including the failed sector address. When the number of sectors is less than the number threshold, the second range is the range specified by the failed sector address and the ended sector address.

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