Anti-fuse memory cell and data writing method and reading method thereof, electronic device

Abstract

The present disclosure provides an antifuse memory cell and its data writing method and reading method, and an electronic device. The antifuse memory cell can include a semiconductor substrate, a gate oxide layer, a first bit line, a second bit line and a word line. A transistor is formed on the semiconductor substrate, and one antifuse memory cell has one transistor, which includes a gate, a source and a drain. The gate oxide layer is arranged between the semiconductor substrate and the gate. The first bit line is connected with the source, and the second bit line is connected with the drain, and the two bit lines can be used for data writing and data reading, respectively. The word line is connected with the gate. The present disclosure can use two bit lines on one antifuse memory cell, so that the semiconductor device using the technical solution of the present disclosure has higher yield and reliability. The present disclosure can significantly reduce the processing difficulty of the antifuse memory cell, and can further reduce the size of the antifuse memory cell, and has a very broad market prospect.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and more specifically, this disclosure can provide antifuse memory cells and their data writing and reading methods, as well as electronic devices. Background Technology

[0002] Currently, anti-fuse memory is used as an auxiliary memory. Anti-fuse memory is generally used to store data such as semiconductor device serial numbers, die serial numbers, device configuration parameters, keys, or boot programs, and has advantages such as programmability, low power consumption, and high security.

[0003] The smallest unit of an antifuse memory typically consists of a programming transistor and a select transistor. The select transistor functions as a switch, turning on or off based on an applied voltage to control whether data is stored. The programming transistor stores the data, either "1" or "0". It is evident that a typical antifuse memory cell requires two transistors, occupying a relatively large space in the semiconductor device. With the continuous development of semiconductor technology, the integration density of semiconductor devices is increasing. This necessitates a reduction in the size of antifuse memories and an increase in storage capacity. Traditional antifuse memory cells can no longer meet the actual needs of semiconductor devices and urgently require improvement. Summary of the Invention

[0004] To address the issues of large size and inability to meet the high integration requirements of semiconductor devices in traditional antifuse memory cells, this disclosure provides an antifuse memory cell, its data writing and reading methods, and an electronic device, thereby achieving the goals of reducing the size of the antifuse memory cell and improving the integration and reliability of semiconductor devices.

[0005] To achieve the aforementioned technical objectives, this disclosure specifically provides an antifuse memory cell. This antifuse memory cell may include, but is not limited to, a semiconductor substrate, a gate oxide layer, a first bit line, a second bit line, and a word line. A transistor is formed on the semiconductor substrate, and each antifuse memory cell has one transistor, which includes a gate, a source, and a drain. The gate oxide layer is disposed between the semiconductor substrate and the gate. The first bit line is connected to the source, and the second bit line is connected to the drain; these two bit lines can be used for data writing and data reading, respectively. The word line is connected to the gate.

[0006] To achieve the above-mentioned technical objectives, this disclosure also provides an electronic device, which may include, but is not limited to, the antifuse storage unit in any embodiment of this disclosure.

[0007] To achieve the above technical objectives, this disclosure provides a data writing method for an antifuse memory cell. This data writing method includes, but is not limited to, the following steps: providing an antifuse memory cell having write bit lines and read bit lines in any embodiment of this disclosure; applying a first preset voltage to the word line, applying a second preset voltage to the write bit line, and applying a third preset voltage to the read bit line to break down the gate oxide layer and write "1" into the antifuse memory cell; wherein the difference between the first preset voltage and the second preset voltage is greater than a first threshold, and the difference between the first preset voltage and the third preset voltage is less than a second threshold.

[0008] To achieve the above technical objectives, this disclosure also specifically provides a data reading method for an antifuse memory cell, providing an antifuse memory cell with read bit lines and write bit lines in any embodiment of this disclosure, applying a power supply voltage to the read bit lines and applying a ground terminal voltage to the word lines; determining whether the data stored on the antifuse memory cell is "1" or "0" based on the voltage or current on the read bit lines.

[0009] The beneficial effects of this disclosure are as follows: This disclosure innovatively uses two bit lines on a single smallest cell of an antifuse memory, which can be used for writing and reading data respectively, thereby enabling semiconductor devices using the technical solution of this disclosure to have higher yield and reliability. Because this disclosure employs a write bit line and read bit line structure design, it can greatly reduce the fabrication difficulty of the antifuse memory cell. With the reduced fabrication difficulty, this disclosure can further reduce the size of the antifuse memory cell.

[0010] The antifuse memory cell provided in this disclosure uses only one transistor, so the antifuse memory manufactured based on this disclosure is smaller and has a more streamlined structure. Therefore, this disclosure can meet the requirements of semiconductor device integration and small size, and greatly improves the storage density of antifuse memory.

[0011] The gate oxide layer of the antifuse memory cell disclosed herein has a single thickness, indicating that the thickness of the gate oxide layer provided herein does not change with position. Based on the gate oxide layer design with a constant thickness, this disclosure can further reduce the fabrication difficulty of the antifuse memory cell. Therefore, this disclosure can significantly improve the yield of semiconductor devices and reduce the fabrication cost of semiconductor devices in terms of processing technology, making its application scope wider and its market prospects better. Attached Figure Description

[0012] Figure 1 A schematic cross-sectional view of an antifuse memory cell is shown in some embodiments of this disclosure.

[0013] Figure 2A schematic diagram of the device planar structure of a plurality of antifuse memory cells in some embodiments of the present disclosure is shown.

[0014] Figure 3 A schematic diagram of the structural composition of a 5×5 antifuse memory array in some embodiments of this disclosure is shown.

[0015] In the picture,

[0016] 100. Semiconductor substrate.

[0017] 200, Gate.

[0018] 201. Source.

[0019] 202. Drain electrode.

[0020] 300, Gate oxide layer.

[0021] 400, word line.

[0022] 500, the first line.

[0023] 501, Second line.

[0024] 600. First contact section.

[0025] 601. Second contact section.

[0026] 700, Active Region.

[0027] 701. Contact hole.

[0028] 800, Shallow trench isolation layer.

[0029] 900, Sensitive Amplifier. Detailed Implementation

[0030] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0031] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0032] In the context of this disclosure, when a layer / element is referred to as being "above" another layer / element, the layer / element may be directly above the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "above" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element.

[0033] like Figure 1 , 2 As shown, one or more embodiments of this disclosure can provide an antifuse memory cell, which includes, but is not limited to, a semiconductor substrate 100, a transistor, a gate oxide layer 300, a word line 400, a first bit line 500, a second bit line 501, a first contact 600, and a second contact 601. It is evident that an antifuse memory cell provided by this disclosure may have only one transistor but two bit lines (Dual Bit Lines). It is understood that the semiconductor substrate 100 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, a III-V compound semiconductor substrate, or an epitaxial thin film substrate obtained by performing selective epitaxial growth (SEG).

[0034] More specifically, the first bit line 500 is a write bit line (WBL) used to write data to the antifuse memory cell, and the second bit line 501 is a read bit line (RBL) used to read data from the antifuse memory cell. Alternatively, the first bit line 500 is a read bit line (RBL) used to read data from the antifuse memory cell, and the second bit line 501 is a write bit line (WBL) used to write data to the antifuse memory cell. Therefore, the write bit line of this disclosure can be connected to the source / drain, and the read bit line can be connected to the source / drain, but the write bit line and the read bit line are not connected to each other.

[0035] A transistor is formed on a semiconductor substrate 100. Specifically, an active region 700 is formed on the semiconductor substrate 100, and a transistor and a shallow trench isolation (STI) layer 800 are formed on the active region 700. The shallow trench isolation layer 800 is used for insulation and isolation between adjacent transistors.

[0036] The transistor includes a gate 200, a source 201, and a drain 202. The gate 200 can be fabricated from a conductive material, which may include, but is not limited to, doped polysilicon, metals (such as tungsten and tantalum), silicides, etc. (such as alloys of metals and polysilicon). It is understood that the transistor specifically provided in this disclosure can be a PMOS (Positive channel Metal Oxide Semiconductor) transistor or an NMOS (Negative channel Metal Oxide Semiconductor) transistor, and it can also be a CMOS (Complementary Metal Oxide Semiconductor) transistor. Taking a PMOS transistor as an example, the semiconductor substrate 100 is an N-type substrate, the active region 700 is a P-well (P+ doped region), and the source 201 and drain 202 are N-wells (N+ doped regions). The doping principles of NMOS transistors and CMOS transistors are similar, and will not be elaborated further in this embodiment.

[0037] It is worth mentioning that, in some improved embodiments of this disclosure, the transistor is preferably a depletion-mode transistor. Based on the depletion-mode transistor used, some embodiments of this disclosure do not require the conventional method of separately determining the breakdown location of the gate oxide layer. Specifically, based on the gate-source voltage (U... GS The depletion-type transistor exhibits the characteristic of forming a channel when the gate voltage is zero. Upon applying voltage to the gate, the charge carriers within the channel flow rapidly, causing the gate oxide layer at the channel location to break down (at which point the stored data can be "1"). Therefore, this disclosure effectively solves the problems of inaccurate gate oxide layer breakdown location or difficulty in breaking down the gate oxide layer present in conventional technologies. The channel location of the depletion-type transistor in this disclosure is determined before the voltage is increased. The gate oxide layer at this channel location contains a large number of charge carriers and is easily broken down. Therefore, this disclosure significantly improves the reliability of antifuse memory devices and the overall yield of semiconductor devices.

[0038] A gate oxide layer 300 is disposed between the semiconductor substrate 100 and the gate 200. In some preferred embodiments of this disclosure, the gate oxide layer 300 has a substantially uniform thickness, for example, it can be a fixed value, meaning that this disclosure provides a gate oxide layer 300 with a single thickness. It is understood that the gate oxide layer 300 used in this disclosure has the advantage of having the same thickness at different locations, which reduces the requirements for semiconductor device fabrication processes and lowers costs. Existing gate oxide layers often have varying thicknesses, typically including thicker regions and thinner regions, all of which place higher demands on process requirements and increase costs. It is understood that the gate oxide layer 300 can be formed, for example, using silicon oxides, which may include, but are not limited to, silicon dioxide.

[0039] The first bit line 500 is connected to the source 201, and the second bit line 501 is connected to the drain 202. The first bit line 500 and the second bit line 501 may be made of the same or different materials. For example, both the first bit line 500 and the second bit line 501 may be made of at least one of the following materials: doped semiconductor material (e.g., doped silicon or doped germanium), conductive metal nitride (e.g., titanium nitride or tantalum nitride), metal (e.g., tungsten, titanium, or tantalum), and / or metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, or titanium silicide).

[0040] The word line (WL) 400 is connected to the gate 200. The word line 400 may be made of a conductive material, which may include, but is not limited to, doped polysilicon, metals (such as tungsten and tantalum), silicides (such as alloys of metals and polysilicon).

[0041] A first contact portion 600 is formed on the source electrode 201, specifically within a contact hole 701 above the source electrode 201. A first bit line 500 is formed on the first contact portion 600 and connected to it, while the first contact portion 600 is connected to the source electrode 201. A second contact portion 601 is formed on the drain electrode 202, specifically within a contact hole 701 above the drain electrode 202. A second bit line 501 is formed on the second contact portion 601 and connected to it, while the second contact portion 601 is connected to the drain electrode 202. Both the first contact portion 600 and the second contact portion 601 are bitline contacts and can be manufactured using the same conductive material.

[0042] The antifuse memory cell may also include a sense amplifier (SA) 900, each sense amplifier 900 being connected to a read bit line. If the second bit line 501 is a read bit line, then the sense amplifier 900 is connected to the second bit line 501. If the first bit line 500 is a read bit line, then the sense amplifier 900 is connected to the first bit line 500 (not shown in the figure). It is understood that the sense amplifier 900 is used to convert the resistance value of the gate oxide layer into a logic output (e.g., "1" or "0") to determine whether the gate oxide layer has been broken down. Specifically, if the resistance value of the gate oxide layer is large (represented by "1"), it indicates that the gate oxide layer has not been broken down, and the data stored in the antifuse memory cell is "0"; if the resistance value of the gate oxide layer is small (represented by "0"), it indicates that the gate oxide layer has been broken down, and the data stored in the antifuse memory cell is "1".

[0043] This disclosure also includes embodiments that provide an electronic device that may include, but is not limited to, the antifuse memory cells in any of the embodiments of this disclosure. Specifically, the electronic device may include one or more antifuse memory arrays formed by multiple antifuse memory cells of this disclosure. This electronic device includes, but is not limited to, smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks.

[0044] like Figure 3 As shown, other embodiments of this disclosure may also provide a data writing method for an antifuse storage cell, which may include, but is not limited to, at least one of the following steps.

[0045] First, an antifuse memory cell with write bit lines and read bit lines is provided in any embodiment of this disclosure. This embodiment uses... Figure 3 Take the antifuse memory cell located in the third row and third column (the target memory cell in the dashed box, at the intersection of the third word line WL3 and the third double bit lines WBL3 and RBL3) as an example.

[0046] In this embodiment, a first preset voltage is applied to the word line WL3, a second preset voltage is applied to the write bit line WBL3, and a third preset voltage is applied to the read bit line RBL3. The voltage difference between the first and second preset voltages is used to form a breakdown voltage to break down the gate oxide layer, thereby reducing the resistance of the gate oxide layer and enabling the writing of a "1" into the antifuse memory cell. The difference between the first and second preset voltages is greater than a first threshold, and the difference between the first and third preset voltages is less than the second threshold. In some embodiments of this disclosure, both the first and second thresholds are power supply voltages. The first preset voltage is greater than the power supply voltage (VDD), the second preset voltage is zero or negative, and the third preset voltage is the power supply voltage. Alternatively, the first preset voltage is the power supply voltage, the second preset voltage is negative, and the third preset voltage is the power supply voltage.

[0047] Alternatively, in this embodiment, a fourth preset voltage can be applied to the word line WL3, a fifth preset voltage to the write bit line WBL3, and a sixth preset voltage to the read bit line RBL3 to prevent the gate oxide layer from being broken down and to write "0" into the antifuse memory cell. The difference between the fourth and fifth preset voltages is less than a third threshold, and the difference between the fourth and sixth preset voltages is less than the fourth threshold. In this embodiment, the third and fourth thresholds are also power supply voltages; the fourth preset voltage can be a power supply voltage or zero voltage, the fifth preset voltage can be zero voltage, and the sixth preset voltage can be a power supply voltage. It is understood that, by default, the antifuse memory cell provided in this disclosure stores "0".

[0048] In specific implementation, before applying the corresponding preset voltages to word line WL3, bit line WBL3 and bit line RBL3, some embodiments of this disclosure apply a power supply voltage (VDD) to all word lines 400, first bit line 500 and second bit line 501 under the current antifuse memory array.

[0049] This disclosure also provides a data reading method for an antifuse storage cell in some embodiments, which may include, but is not limited to, at least one of the following steps.

[0050] First, let's take an antifuse memory cell (target memory cell at the dashed box, the position where the third word line WL3 intersects with the third double bit lines WBL3 and RBL3) with a write bit line and a read bit line as an example in any embodiment of this disclosure.

[0051] Apply a power supply voltage (VDD) to the read bit line and a ground voltage (VSS) to the word line.

[0052] The data stored in the antifuse memory cell is determined by reading the voltage or current on the bit line; it is either "1" or "0". If the read voltage or current is small, it indicates that the gate oxide layer has been damaged, and the data stored in the antifuse memory cell is "1". If the read voltage or current is large, it indicates that the gate oxide layer has not been damaged, and the data stored in the antifuse memory cell is "0". Figure 3 As shown, some embodiments of this disclosure can use a sensitive amplifier 900 to amplify voltage or current to detect whether the gate oxide layer on the antifuse memory cell has been broken down. Taking voltage as an example, if the voltage detection result obtained by the sensitive amplifier 900 is low, it indicates that the gate oxide layer on the antifuse memory cell has been broken down, and the data stored on the antifuse memory cell is "1"; if the voltage detection result obtained by the sensitive amplifier 900 is high, it indicates that the gate oxide layer on the antifuse memory cell has not been broken down, and the data stored on the antifuse memory cell is "0". The specific method of current detection is similar to that of voltage detection, and will not be described in detail in this embodiment.

[0053] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0054] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. An antifuse memory cell, characterized in that, include: A semiconductor substrate on which a transistor is formed, the transistor including a gate, a source, and a drain; A gate oxide layer is disposed between the semiconductor substrate and the gate. The first line is connected to the source electrode; The second bit line is connected to the drain electrode; Word lines are connected to the gate. The first bit line is a write bit line used to write data to the antifuse memory cell, and the second bit line is a read bit line used to read data from the antifuse memory cell; or, The first bit line is a read bit line and is used to read data from the antifuse memory cell; the second bit line is a write bit line and is used to write data to the antifuse memory cell. A first contact portion is formed on the source electrode; a first bit line is formed on the first contact portion; A second contact portion is formed on the drain electrode; a second bit line is formed on the second contact portion.

2. The antifuse storage unit according to claim 1, characterized in that, The gate oxide layer has a fixed thickness.

3. An electronic device, characterized in that, Includes the antifuse storage unit as described in any one of claims 1-2.

4. The electronic device according to claim 3, characterized in that, This includes smartphones, computers, tablets, wearable smart devices, artificial intelligence devices, and power banks.

5. A method for writing data to an antifuse memory cell, characterized in that, include: Provide an antifuse memory unit as described in any one of claims 1-2; A first preset voltage is applied to the word line, a second preset voltage is applied to the write bit line, and a third preset voltage is applied to the read bit line to break down the gate oxide layer and write "1" into the antifuse memory cell; Wherein, the difference between the first preset voltage and the second preset voltage is greater than the first threshold, and the difference between the first preset voltage and the third preset voltage is less than the second threshold; Both the first threshold and the second threshold are power supply voltages; The first preset voltage is greater than the power supply voltage, the second preset voltage is zero voltage or a negative voltage, and the third preset voltage is the power supply voltage; or the first preset voltage is the power supply voltage, the second preset voltage is a negative voltage, and the third preset voltage is the power supply voltage.

6. The data writing method for the antifuse storage unit according to claim 5, characterized in that, Also includes: A fourth preset voltage is applied to the word line, a fifth preset voltage is applied to the write bit line, and a sixth preset voltage is applied to the read bit line to prevent the gate oxide layer from being broken down, and "0" is written into the antifuse memory cell. Wherein, the difference between the fourth preset voltage and the fifth preset voltage is less than the third threshold, and the difference between the fourth preset voltage and the sixth preset voltage is less than the fourth threshold.

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