Memory devices and memory controllers and storage devices including the same

Abstract

Memory devices and memory controllers configured to repair weak word lines are provided, as well as methods of operating a memory device and a memory controller. A memory device includes: a memory cell array including a plurality of normal word lines and at least one spare word line; and a repair controller configured to set memory cells connected to at least one weak word line to a first mode of operation, and further configured to set memory cells connected to at least one spare word line to a second mode of operation. The at least one weak word line is detected from among the normal word lines based on test results.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0186779, filed on December 29, 2020, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to a memory controller, and more specifically, to a memory device and a memory controller configured to repair weak word lines, and a storage device including the memory device and the memory controller. Background Technology

[0004] Electronic devices, such as telephones, tablets, and personal computers, typically require built-in methods to store data. For example, an electronic device may contain a memory device, which includes memory cells for the purpose of storing data. In some cases, the circuitry within the memory device may have one or more faults, preventing the use of one or more memory cells within the memory device. Traditional manufacturing methods for memory devices can detect these faults and discard dead cells.

[0005] Test operations for detecting weak memory cells can be performed on the memory cell array of the memory chip. Manufacturing yield can be significantly reduced when a memory chip is discarded every time a weak memory cell is detected. In a repair operation, the weak memory cell can be replaced by an additional memory cell that was already included in the memory cell array during manufacturing. For example, the repair operation can be performed on a block-by-block basis.

[0006] When performing repair operations on a block-by-block basis, memory blocks containing weak memory cells can be discarded instead of using additional memory blocks. In this case, replacing all memory blocks containing weak memory cells may lead to inefficiency, even when the number of weak memory cells is too large or they are concentrated in a specific area. Summary of the Invention

[0007] Embodiments of this disclosure include a memory device and a memory controller that can utilize weak word lines that would otherwise be discarded during repair operations, as well as methods for operating a memory device including the memory device and the memory controller.

[0008] A memory device according to one aspect of this disclosure includes: a memory cell array including a plurality of normal word lines and at least one spare word line; and a repair controller configured to set a memory cell connected to at least one weak word line to a first operating mode, and further configured to set a memory cell connected to at least one spare word line to a second operating mode. The at least one weak word line is detected from the normal word lines based on test results.

[0009] According to one aspect of this disclosure, a memory controller is connected to a memory device comprising multiple normal word lines and at least one spare word line. The memory controller sends a command to the memory device, detects that at least one normal word line is a weak word line based on whether the operation performed in response to the command has failed, sets the memory cell connected to the weak word line to a first operating mode, and sets the memory cell connected to the at least one spare word line to a second operating mode.

[0010] According to one aspect of this disclosure, a method for operating a memory device including a memory device and a memory controller, wherein the memory device includes a plurality of normal word lines and at least one spare word line, the method comprising: detecting that at least one of the normal word lines is a weak word line; setting an operating mode of a memory cell connected to the weak word line to a first operating mode, and setting an operating mode of a memory cell connected to the at least one spare word line to a second operating mode; receiving a write request from a host; and writing data to at least one of the memory cells connected to the weak word line and the memory cells connected to the at least one spare word line based on the set operating mode. Attached Figure Description

[0011] Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 This is a block diagram of a test system according to an example embodiment;

[0013] Figure 2 This is a block diagram of a memory device according to an example embodiment.

[0014] Figure 3 This is a circuit diagram of a memory block included in a memory cell array according to an example embodiment;

[0015] Figure 4A and Figure 4B This is a diagram used to explain the repair operation according to the example embodiment;

[0016] Figure 5 This is a table used to explain the repair operations according to the example embodiments;

[0017] Figures 6 to 8This is a flowchart illustrating a method for operating a test system according to an example embodiment;

[0018] Figure 9 This is a block diagram of a storage system according to an example embodiment;

[0019] Figure 10 This is a block diagram of a memory controller according to an example embodiment;

[0020] Figure 11 It is a diagram of the meta region based on the example embodiment;

[0021] Figure 12 This is a table used to explain the weak memory cell information according to the example embodiment;

[0022] Figure 13 This is a table used to explain unit operation mode information according to the example embodiment;

[0023] Figure 14 This is a flowchart of a method for operating a memory controller according to an example embodiment;

[0024] Figure 15 This is a flowchart of a method for operating a memory controller according to an example embodiment;

[0025] Figure 16 This is a flowchart of a method for operating a memory controller according to an example embodiment;

[0026] Figure 17 This is a block diagram of a storage system according to an example embodiment; and

[0027] Figure 18 This is a block diagram of a solid-state drive (SSD) according to an example embodiment. Detailed Implementation

[0028] In the following, embodiments will be described in detail with reference to the accompanying drawings. Similar reference numerals in the drawings may denote similar elements, and to the extent that descriptions of elements have been omitted, it can be understood that an element is at least similar to a corresponding element described elsewhere in the specification.

[0029] Figure 1 This is a block diagram of a test system 1000 according to an example embodiment.

[0030] refer to Figure 1 The test system 1000 may include a test device 100 and a memory device 200. The memory device 200 may include a repair controller 210 and a memory cell array 220. In this example, the memory device 200 may be referred to as the device under test (DUT).

[0031] Test equipment 100 can test memory device 200 corresponding to any of the following: wafer, die, or package. Test equipment 100 can send commands to memory device 200 to perform test operations. In this embodiment, test operations may refer to a series of operations for detecting weak memory cells of memory cell array 220, but are not limited to this. In this embodiment, test equipment 100 can send test data and test mode register set (TMRS) information to memory device 200. TMRS information may include several control signals for setting the operating mode of memory device 200 to test mode.

[0032] The memory device 200 can perform test operations in response to commands received from the test device 100. For example, the memory device 200 can receive write commands or erase commands from the test device 100 and detect memory cells where write or erase operations fail. In the following text, memory cells where test operations fail will be referred to as weak memory cells. As an example, a memory cell where a write operation fails in response to a write command, or a memory cell where an erase operation fails in response to an erase command, can be referred to as a weak memory cell.

[0033] Memory cell array 220 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. An example embodiment in which the plurality of memory cells are NAND flash memory cells will be described below. Memory cell array 220 may include a three-dimensional (3D) memory cell array comprising a plurality of NAND strings, which will be referred to below. Figure 3 Describe it.

[0034] The 3D memory cell array according to embodiments is monolithically formed. The term "monolithic" can mean that the layers of each level of the 3D memory cell array are deposited directly on the layers of each underlying level of the 3D memory cell array. For example, the 3D memory cell array may have at least one physical level containing an array of memory cells with active regions disposed above a silicon substrate, and circuitry associated with the operation of the memory cells, wherein the circuitry may be above or inside the silicon substrate. In embodiments, the 3D memory cell array may include NAND strings, wherein at least one memory cell is located on top of another memory cell in a vertical direction. The at least one memory cell may include a charge trapping layer. The following patent documents, incorporated herein by reference in their entirety, disclose suitable configurations of 3D memory arrays in which the 3D memory array is configured across multiple levels, with word lines and / or bit lines shared between levels: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648.

[0035] The memory cell array 220 may include multiple memory cells connected to multiple word lines. The multiple word lines may include normal word lines 221 and spare word lines 222 connected to multiple redundant memory cells. As used herein, the redundant memory cells may also be referred to as spare memory cells.

[0036] At least one of the multiple memory cells connected to the normal word line 221 may fail. Each of the multiple memory cells can be classified as a weak memory cell or a normal memory cell based on the degree of degradation. A weak memory cell may mean a memory cell with low reliability due to degradation. In the following text, the word line connected to the weak memory cell may be referred to as a weak word line. The weak word line 221 connected to the weak memory cell may be supplemented or replaced by a spare word line 222. This process may be referred to as a repair operation.

[0037] The repair controller 210 can perform repair operations as described above. To supplement the functionality of weak memory cells detected via the test operation, the repair controller 210 can perform a series of operations to enable access to additional spare memory cells. In an embodiment, the repair controller 210 can confirm location information regarding weak word lines and confirm location information regarding spare word lines 222 required to operate the weak word lines.

[0038] When data is written into memory cells, the repair controller 210 may set the cell operation mode of the memory cells. The cell operation mode of each memory cell in the memory cell array 220 may correspond to the number of bits written into the memory cell. For example, the cell operation modes may include any of a single-level cell (SLC) mode for storing 1-bit data, a multi-level cell (MLC) mode for storing 2-bit data, a triple-level cell (TLC) mode for storing 3-bit data, a quad-level cell (QLC) mode for storing 4-bit data, and / or a mode for storing 5 or more bits.

[0039] Furthermore, for each memory cell, the cell operation mode may be different. For example, memory cells in a wafer state may be set to a first operation mode. After a test operation, when the cells are undergoing a repair operation, the repair controller 210 may set the cell operation mode of the memory cells connected to a weak word line to a second operation mode, and set the cell operation mode of the memory cells connected to a spare word line 222 to a third operation mode. For example, the first operation mode may be a mode in which n-bit data (where n is a natural number) is stored in a memory cell, the second operation mode may be a mode in which m-bit data (m is a natural number, m < n) is stored in a memory cell, and the third operation mode may be a mode in which (n-m)-bit data is stored in a memory cell. For example, the first operation mode may be the TLC mode, the second operation mode may be the SLC mode, and the third operation mode may be the MLC mode.

[0040] According to an embodiment, instead of discarding the weak word line, the repair controller 210 may set the weak word line to another cell operation mode to enable the operation of the memory cells, thereby increasing the utilization rate of the memory cells, and thus increasing the yield of memory devices when a large number of weak word lines are present.

[0041] Figure 2 is a block diagram of a non-volatile memory device 200 according to an example embodiment.

[0042] Referring to Figure 2 , the non-volatile memory device 200 may include a memory cell array 220, a voltage generator 230, an address decoder 240, control logic 250, a page buffer 260 and an input / output (I / O) circuit 270. The non-volatile memory device 200 may further include an I / O interface, for example, a SATA interface.

[0043] The memory cell array 220 can be connected to the word line WL, the serial select line SSL, the ground select line GSL, and the bit line BL. The memory cell array 220 can be connected to the address decoder 240 via the word line WL, the serial select line SSL, and the ground select line GSL, and to the page buffer 260 via the bit line BL. The memory cell array 220 can include multiple memory blocks.

[0044] Each memory block may include multiple memory cells and multiple select transistors. Memory cells may be connected to word lines WL, and select transistors may be connected to either serial select line SSL or ground select line GSL.

[0045] The meta-region 223 of the memory cell array 220 may include information about one or more weak memory cells, weak word lines, and spare word lines. This information may be generated by the repair controller 210, and the repair controller 210 may perform repair operations based on the aforementioned information. The meta-region 223 may include memory cells connected to normal word lines of the memory cell array 220.

[0046] Voltage generator 230 can generate various voltages for performing write, read, and erase operations on memory cell array 220 based on the voltage control signal CTRL_vol. Specifically, voltage generator 230 can generate word line voltages VWL, such as programming (write) voltage, read voltage, pass voltage, erase verification voltage, and / or programming (write) verification voltage. Furthermore, voltage generator 230 can generate string select line voltage and ground select line voltage based on the voltage control signal CTRL_Vol. Additionally, voltage generator 230 can generate the erase voltage to be supplied to memory cell array 220.

[0047] Address decoder 240 can select one memory block from multiple memory blocks in memory cell array 220, select one word line WL from the selected memory block, and select one string select line from multiple string select lines SSL.

[0048] Control logic 250 can output various control signals for performing write, read, and erase operations on memory cell array 220 based on command CMD, address ADDR, and control signal CTRL. Control logic 250 can provide row address X-ADDR to address decoder 240, column address Y-ADDR to page buffer 260, and voltage control signal CTRL_Vol to voltage generator 230.

[0049] Control logic 250 may include repair controller 210. Repair controller 210 may be based on... Figure 1The test device 100 receives the command CMD, address ADDR, and control signal CTRL for test operations to detect weak memory cells in the memory cell array 220. Location information about the weak memory cells can be stored in the meta-region 223 of the memory cell array 220.

[0050] The repair controller 210 can determine the weak word line based on the information about the weak memory cell and according to the set criteria, and store the information about the weak word line in the meta region 223.

[0051] The unit of fault detected by the test operation may not be limited to the unit of memory cell, but may be, for example, the unit of memory block. In this case, the repair controller 210 may determine the weak word line based on information about the defective memory block.

[0052] The repair controller 210 can activate at least one spare word line to supplement the weak word line. Therefore, the repair controller 210 can generate a voltage control signal CTRL_Vol for performing write, read, and erase operations on memory cells connected to the spare word line, and provide the voltage control signal CTRL_Vol to the voltage generator 230. Furthermore, the repair controller 210 can provide the address decoder 240 with the row address X-ADDR for performing write, read, and erase operations on memory cells connected to the spare word line, and provide the page buffer 260 with the column address Y-ADDR.

[0053] Page buffer 260 can operate as a write driver or a sense amplifier depending on the operating mode. During a read operation, page buffer 260 can sense the bit line BL of the memory cell selected via control logic 250. The sensed data can be stored in a latch included in page buffer 260. Page buffer 260 can dump the data stored in the latch to I / O circuit 270 under the control of control logic 250.

[0054] I / O circuit 270 can temporarily store commands (CMD), addresses (ADDR), control signals (CTRL), and data (DATA), which are provided to the non-volatile memory device 200 via I / O lines (I / O). The I / O lines (I / O) can connect the non-volatile memory device to an external device, for example, an external device. I / O circuit 270 can temporarily store data read from the non-volatile memory device 200 and output the read data to an external device via the I / O lines (I / O) at specified times.

[0055] Figure 3 This is a circuit diagram of a memory block 280 included in a memory cell array according to an example embodiment.

[0056] refer to Figure 3 The memory block 280 may include NAND strings NS11 to NS33, first word lines WL1 to eighth word lines WL8, first bit lines BL1 to third bit lines BL3, first ground select lines GSL1 to third ground select lines GSL3, first string select lines SSL1 to third string select lines SSL3, and a common source line CSL.

[0057] Here, the number of NAND strings (e.g., NS11 to NS33), word lines (e.g., WL1 to WL8), bit lines (e.g., BL1 to BL3), ground select lines (e.g., GSL1 to GSL3), and string select lines (e.g., SSL1 to SSL3) can vary depending on the embodiment.

[0058] Each NAND string (e.g., NS11) may include a series-connected string select transistor SST, a plurality of memory cells MC, and a ground select transistor GST. In an embodiment, there are eight memory cells MC1 to MC8 among the plurality of memory cells MC, but this disclosure is not limited thereto. The string select transistor SST may be connected to its corresponding first string select line SSL1. The memory cells MC may be connected to their respective corresponding first word lines WL1 to eighth word lines WL8. The ground select transistor GST may be connected to its corresponding first ground select line GSL1. The string select transistor SST may be connected to its corresponding first bit line BL1 to third bit line BL3, and the ground select transistor GST may be connected to the common source line CSL.

[0059] In NAND strings NS11 to NS33, NAND strings NS11, NS12, and NS13 (e.g., in the first row) can be connected together to the first select line SSL1. NAND strings NS21, NS22, and NS23 in the second row can be connected together to the second select line SSL2. NAND strings NS31, NS32, and NS33 in the third row can be connected together to the third select line SSL3.

[0060] According to an embodiment, the first word lines WL1 to the eighth word lines WL8 may include multiple normal word lines NWL and at least one spare word line SWL. For example, the first word lines WL1 to the third word lines WL3 may include spare word lines SWL, and the fourth word lines WL4 to the eighth word lines WL8 may include normal word lines NWL. The number and position of the spare word lines SWL and the number and position of the normal word lines NWL are not limited thereto and may be varied.

[0061] In some cases, to repair weak memory cells, repair operations can be performed on a block-by-block basis (280). In this scenario, even when weak memory cells are concentrated on a specific word line, block 280 can be completely replaced by a spare memory block. Therefore, normal (e.g., non-weak) memory cells included in block 280 may not be used. Consequently, the efficiency and capacity of the memory device may be reduced.

[0062] Multiple word lines can be stacked vertically during the manufacturing process. As the number of stacked word lines increases, the probability of weak word lines appearing may increase. Furthermore, for word lines containing multiple weak memory cells, the memory cells may fail during testing and go undetected. The situation where weak memory cells are concentrated and distributed within a specific word line can be referred to as word line concentration defect.

[0063] According to embodiments of this disclosure, wasted memory cells can be reduced by repairing specific word lines within a set of weak memory cells. For example, the repair operation can be performed not on a block-by-block basis to address defects in the word line set, but at the memory cell and word line level. Furthermore, word lines including weak memory cells can be used in a cell operation mode different from existing cell operation modes instead of being discarded, thus preserving the capacity of the memory device. Additionally, the repair operation can be performed by designating word lines comprising at least a reference number of weak memory cells as weak word lines, so that memory cells connected to weak word lines and subsequently failing may not further impact the memory device. Hereinafter, the threshold number of weak memory cells to which word lines connected are designated as weak word lines may be referred to as the “reference number” of weak memory cells.

[0064] Furthermore, it is assumed here that the unit of the repair operation is the word line unit, but the inventive concept is not limited to this. For example, the unit of the repair operation can be another more specific level than the entire memory block, such as the column unit.

[0065] Figure 4A and Figure 4B This is a diagram used to explain the repair operation according to the example embodiment.

[0066] Memory blocks 280a and 280b may include multiple normal word lines 281a and 281b and multiple spare word lines 282a and 282b. For example, each of memory blocks 280a and 280b may include first normal word lines NWL1 to sixth normal word lines NWL6 and first spare word lines SWL1 to third spare word lines SWL3. (See reference...) Figure 2 describe Figure 4A and Figure 4B .

[0067] refer to Figure 4AEach memory cell in the memory cell array 220 can be configured in TLC mode. In this case, the memory device 200 can correspond to any of the states of wafer, die, and package.

[0068] exist Figure 4A In this configuration, the first normal word lines NWL1 to the sixth normal word lines NWL6 and the first spare word lines SWL1 to the third spare word lines SWL3 can be set to the same unit operation mode, but are not necessarily limited to this. Alternatively or additionally, the unit operation modes of the first spare word lines SWL1 to the third spare word lines SWL3 may not be set.

[0069] Subsequently, in the test equipment (e.g., Figure 1 After the test operation (100) in the middle, the repair controller 210 can detect the weak word line. (Refer to...) Figure 4B This describes an example where the third normal word line, NWL3, is detected as a weak word line. (Refer to...) Figure 7 The method for detecting at least one weak word line from the normal word lines NWL1 to NWL6 is described in detail below.

[0070] When the third normal word line NWL3 is detected as a weak word line, the first spare word line SWL1 can be activated to replace the third normal word line NWL3. Activation can refer to changing the state in which access between the word line and memory cell is blocked to a state in which access is allowed.

[0071] However, in reference Figure 4B In the example, access to the third normal word line NWL3, which is a weak word line, can be unblocked. For example, the unit operation mode of the third normal word line NWL3 can be changed from TLC mode to SLC mode.

[0072] When the cell operation of the third normal word line NWL3 changes, the capacity of data that can be stored in the memory cells connected to the third normal word line NWL3 can be reduced. To compensate for this reduction, the first spare word line SWL1 can be activated, and the cell operation mode of the first spare word line SWL1 can be set to MLC mode. The number and location of the activated spare word lines can be determined by the repair controller 210, and are not necessarily limited to a specific number and location.

[0073] Therefore, as a result of the repair operation according to the embodiment, access to the first spare word line SWL1 and access to the third normal word line NWL3, which is determined to be a weak word line, can be enabled only.

[0074] Figure 5 This is a table used to explain the repair operations according to the example embodiments.

[0075] refer to Figure 5This includes memory cell arrays (e.g., Figure 1 The cell operation mode information 300a and 300b of the memory cells included in the memory cell array 220 can be managed on a word line basis. For example, the cell operation mode information 300a and 300b can be stored in the meta-region of the memory cell array 220 (e.g., Figure 2 In 223), in other embodiments, the unit of the cell operation mode that manages the memory cell is not necessarily limited to the unit of word line.

[0076] Prior to the repair operation, the unit operation mode information 300a may include information about the unit operation mode of each of the active normal word lines (i.e., the first normal word line NWL1 to the sixth normal word line NWL6). For example, the unit operation modes of the first spare word line SWL1 to the third spare word line SWL3 may not be set prior to the repair operation.

[0077] The unit operation mode of each of the normal word lines NWL1 to NWL6 can be changed due to the aforementioned repair operation, and the changed unit operation mode information 300b can include information about the unit operation mode of each word line changed due to the repair operation. For example, the third normal word line NWL3 can be detected as a weak word line, and the unit operation mode of the third normal word line NWL3 can be changed. For example, the unit operation mode of the third normal word line NWL3 can be changed from TLC mode to SLC mode. Furthermore, to replace or supplement a weak word line, the unit operation mode of the first spare word line SWL1 can be set. For example, the unit operation mode of the first spare word line SWL1 can be set to MLC mode.

[0078] Figures 6 to 8 This is a flowchart illustrating a method for operating a test system according to an example embodiment.

[0079] refer to Figure 2 and Figure 6 Test operations can be performed on the memory device 200 (S110). For example, a test device (e.g., Figure 1 The test device 100 can perform a series of operations for testing the memory device 200. For example, the test device 100 can send a write command or erase command to the memory device 200 for a specific memory cell.

[0080] In the method of operating the test system, an operation (S120) can be performed to detect weak word lines included in the memory cell array 220 of the memory device 200. For example, in response to a write command or erase command, the repair controller 210 can detect weak memory cells where the write or erase operation failed. The repair controller 210 can detect weak word lines based on the number of weak memory cells and / or location information about the weak memory cells. According to an embodiment, memory cells can be configured with the same cell operation mode. Furthermore, spare word lines can remain inactive.

[0081] When a weak word line is detected, an operation can be performed to set the cell operation mode of the memory cell connected to the weak word line to a first operation mode (S130). For example, the repair controller 210 can change the cell operation mode of the memory cell connected to the weak word line. For example, the cell operation mode of the memory cell connected to the weak word line can be changed from TLC mode to SLC mode.

[0082] The operation of setting the cell operation mode of the memory cell connected to the spare word line to a second operation mode can be performed (S140). For example, when the cell operation mode of a weak memory cell changes, the repair controller 210 can activate the spare word line to compensate for the reduction in capacity of the memory device 200. The repair controller 210 can determine the number and location of the spare word lines to be activated and set the cell operation mode of the memory cell connected to the spare word line. For example, the cell operation mode of the memory cell connected to the spare word line can be set to MLC mode. Furthermore, as an example of a method for activating the spare word line, the spare word line can be physically connected to the address decoder 240, for example, using an electronic fuse.

[0083] The order in which operations S130 and S140 are executed is not limited to this, and operations S130 and S140 can be executed in parallel or in reverse order.

[0084] refer to Figure 7 , Figure 6 Operation S120 may include operation S121 and operation S122.

[0085] The operation of detecting weak memory cells included in the memory cell array 220 can be performed (S121). For example, weak memory cells in the memory cell array 220 can be detected by the test device 100. The test device 100 can store information about the location of the weak memory cells in the meta-region 223 of the memory cell array 220.

[0086] An operation (S122) can be performed to determine word lines that include at least the reference number of weak memory cells as weak word lines. For example, Figure 1The test device 100 can detect word lines as weak word lines, including at least a reference number of weak memory cells connected to each word line. The reference number can be set by the test device 100 and can be changed according to the characteristics of the memory device 200. The test device 100 can store information including the location of the weak word lines in the meta-region 223.

[0087] refer to Figure 8 Implementation examples may include: Figure 6 Additional steps following operation S140. For example, operations S150 and S160 can be performed.

[0088] An operation (S150) can be performed to store the cell operation mode of each of the plurality of memory cells in the meta region 223. According to an embodiment, the repair controller 210 can set the cell operation mode of each of the plurality of memory cells on a word line basis and store the set cell operation mode information in the meta region 223 of the memory cell array 220. The cell operation mode information can be changed due to a repair operation performed by the repair controller 210.

[0089] Operations can be performed in response to commands based on the storage unit operation mode (S160). According to an embodiment, the repair controller 210 can perform several operations based on the unit operation mode as a response to commands received from outside the memory device 200.

[0090] According to an embodiment, when control logic 250 receives a write command and the address of the memory cell corresponding to the write command, control logic 250 can determine the cell operation mode of the word line connected to the memory cell at the received address. When the word line connected to the memory cell at the received address is determined to be a weak word line, the cell operation mode of the memory cell can be changed, and control logic 250 can generate several control signals to cause the memory cell to perform a write operation in the changed cell operation mode. When the word line connected to the memory cell at the received address is determined to be an active spare word line, control logic 250 can generate several control signals to access the word line. For example, control logic 250 can generate a signal to redirect a signal from a previously weak word line to an active spare word line.

[0091] For example, operation S150 can be performed in the memory device 200 in a state prior to the packaging process, while operation S160 can be performed in the memory device after the packaging process (e.g., ...). Figure 9 Executed in (500) of the memory device. For example, when the memory device 500 is packaged and connected to the memory controller (e.g., Figure 9 When the memory device 500 receives a command from the memory controller 400 and executes operation S160, the memory device 500 can receive a command from the memory controller 400 and execute operation S160.

[0092] According to the embodiments, the repair operation can be performed together with the test operation in the memory device 200 in a wafer state or die state (e.g., semiconductor die) before the packaging process.

[0093] Furthermore, although no weak memory cells are detected during the initial testing of memory device 200, normal memory cells may degrade and become weak memory cells during chip operation after memory device 200 is packaged. In this case, a post-package repair operation can be performed, thus repairing the weak memory cells. For example, memory device 500 can replace or supplement weak memory cells with redundant memory cells in the packaged state.

[0094] The following will describe the situation where a repair operation according to the embodiment is performed in the memory device 500 after packaging.

[0095] Figure 9 This is a block diagram of a storage system 2000 according to an example embodiment.

[0096] Figure 9 The storage system 2000 can correspond to the following embodiments, wherein Figure 1 The memory device 200 of the test system 1000 is connected to the memory controller 400, which is in a packaged state after the memory device 200 has completed the test operation. Therefore, references can be omitted. Figures 1 to 8 Any redundant descriptions given.

[0097] refer to Figure 9 The storage system 2000 may include a memory controller 400 and a memory device 500. The memory device 500 may include a non-volatile memory device and is implemented as a memory chip. The memory device 500 may include a memory cell array 510.

[0098] In some embodiments, the storage system 2000 may be implemented as internal memory embedded in an electronic device. For example, the storage system 2000 may include an embedded universal flash memory (UFS) device, an embedded multimedia card (eMMC), or a solid-state drive (SSD). In some embodiments, the storage system 2000 may be implemented as external memory attached to and removable from an electronic device. For example, the storage system 2000 may include a UFS memory card, a compact flash (CF) card, a secure digital card (SD) card, a micro SD card, a mini SD card, an extreme digital (xD) card, or a memory stick.

[0099] The memory device 500 may include a memory cell array 510, and corresponds to the above reference. Figure 1 and Figure 2 The memory device 200 described. The memory cell array 510 may include multiple word lines to which multiple memory cells are connected, and the multiple word lines may include normal word lines 511 and spare word lines 512.

[0100] In response to a read / write request from the host, the memory controller 400 can control the memory device 500 to read or write data DATA stored in the memory device 500. Specifically, the memory controller 400 can control write, read, and erase operations on the memory device 500 by providing the memory device 500 with commands CMD, address ADDR, and control signals CTRL. Furthermore, the data DATA to be written and the data DATA to be read can be sent and received between the memory controller 400 and the memory device 500.

[0101] The memory controller 400 may include a repair controller 410 and a meta-region 420.

[0102] The repair controller 410 can control the operation of the memory device 500 to detect at least one weak memory cell included in the memory cell array 510 of the memory device 500. Furthermore, according to an embodiment, the repair controller 410 can perform the repair operation described above on the detected weak memory cell.

[0103] The repair controller 410 can control at least one spare word line to supplement or replace the weak word line connected to the detected weak memory cell. For example, the repair controller 410 can change the cell operation mode of the weak word line connected to the detected weak memory cell. Furthermore, at least one spare word line can be activated, and the cell operation mode of at least one spare word line can be set. The repair controller 410 can send a cell operation mode control signal CTRL_CM to the memory device 500 to change or set the cell operation mode of each word line.

[0104] The repair controller 410 can store information required to perform repair operations and information required to control the memory device 500 based on the repair results in the meta-region 420. For example, weak memory cell information can be stored in the meta-region 420 to perform repair operations, and cell operation mode information generated or changed based on the repair results can also be stored in the meta-region 420. Multiple pieces of information stored in the meta-region 420 can be changed due to the operation of the memory controller 400.

[0105] For example, the repair controller 410 can generate a command CMD, an address ADDR, a control signal CTRL, and a unit operation mode control signal CTRL_CM in response to a read / write request received from the host, based on information stored in the meta region 420.

[0106] According to the embodiment, a repair operation can be performed on the memory device 500 at the wafer level, and therefore weak memory cells can be repaired even after the memory device 500 has been packaged. Furthermore, because the weak word lines including the weak memory cells are not discarded and can be utilized, the capacity of the memory device 500 can be ensured.

[0107] Figure 10 This is a block diagram of a memory controller 400 according to an example embodiment.

[0108] Let's refer to each other. Figure 9 and Figure 10 The memory controller 400 may include a host interface 430, random access memory (RAM) 440, flash translation layer (FTL) 450, processor 460, buffer memory 470 and memory interface 480.

[0109] Host interface 430 can send packets to and receive packets from the host. Packets sent from the host to host interface 430 may include commands and / or data to be written to memory device 500. Packets sent from host interface 430 to the host may include responses to commands and / or data read from memory device 500.

[0110] The memory interface 480 can send data to be written to the memory device 500 or receive data read from the memory device 500. The memory interface 480 can be configured to conform to standard protocols such as Toggle or Open NAND Flash Interface (ONFI). The memory interface 480 can control the signals used to drive the memory device 500 and access the memory device 500 via the control of the processor 460. The memory interface 480 can send the cell operation mode control signal CTRL_CM generated by the repair controller 410 and / or commands generated based on cell operation mode information to the memory device 500.

[0111] RAM 440 may include a repair controller 410. The repair controller 410 may send a command to the memory device 500 in response to a request received from the host interface 430. The repair controller 410 may receive a response from the memory device 500, which includes information indicating whether the operation of the memory device 500 in response to the command was successful or failed.

[0112] The repair controller 410 can detect weak memory cells included in the memory cell array 510 based on the received response. Furthermore, the weak memory cell information corresponding to the detection result can be stored in the buffer memory 470. The unit by which the repair controller 410 detects faults in the memory cell array 510 is not limited to the unit of memory cell, but can be, for example, the unit of memory block.

[0113] In addition, the repair controller 410 can perform operations related to... Figures 1 to 8 The repair controller 210 performs the same operation as described above, and its redundant description can be omitted.

[0114] The repair controller 410 can set the cell operation modes of weak word lines and spare word lines included in the memory cell array 510 based on weak memory cell information. For example, before setting the cell operation mode of a spare word line, the repair controller 410 can activate the spare word line to enable access to it. The repair controller 410 can store cell operation mode information for each word line in the buffer memory 470.

[0115] The repair controller 410 can generate a unit operation mode control signal CTRL_CM based on the unit operation mode information to control the word line, and send the unit operation mode control signal CTRL_CM to the memory device 500 through the memory interface 480.

[0116] When the repair controller 410 receives a read / write request from the host via the host interface 430, the repair controller 410 can generate commands, addresses, and control signals to be sent to the memory device 500 based on the cell operation mode information stored in the buffer memory 470. For example, in response to a request received from the host, the repair controller 410 can translate the commands and addresses included in the request based on the cell operation mode information stored in the buffer memory 470, and send the translated commands and addresses to the memory device 500.

[0117] The FTL 450 (Flash Translation Layer) can perform various functions, such as address mapping, wear-leveling, and garbage collection. Address mapping can involve translating logical addresses received from the host into physical addresses used to actually store data in memory device 500. Wear-leveling can include techniques to prevent excessive degradation of specific blocks by allowing all blocks of memory device 500 to be used evenly. As an example, wear-leveling can be implemented using firmware techniques that balance the erase counts of physical blocks. Garbage collection can include techniques to ensure available capacity in memory device 500 by erasing existing blocks after copying valid data from existing blocks to new blocks.

[0118] The FTL 450 can perform address mapping operations based on cell operation mode information. For example, when a spare word line is activated due to a repair operation, a new logical address can be assigned to the activated spare word line. The FTL 450 can map the logical address of the activated spare word line to a physical address and enable access to the memory cells connected to the spare word line.

[0119] The processor 460 can execute various programs stored in the RAM 440 and control all operations of the storage system 2000. For example, the processor 460 can execute programs included in the repair controller 410.

[0120] The buffer memory 470 can temporarily store data received from the host via the host interface 430 or data received from the memory device 500.

[0121] The buffer memory 470 may include a meta-region 420 that includes information about weak memory cells detected by the repair controller 410 and cell operation mode information generated as a result of the repair operation. The information stored in the meta-region 420 may be updated or changed by the repair controller 410.

[0122] Meta-region 420 can correspond to Figure 2 Meta region 223, and meta region 420 may include the information included in meta region 223, and also include the logical address of the memory cell and the physical address of the corresponding memory cell.

[0123] The buffer memory 470 can be implemented as a volatile memory, such as dynamic RAM (DRAM), static DRAM (SDRAM), double data rate (DDR) SDRAM, low power DDR (LPDDR) and / or graphics RAM (GRAM); or a non-volatile memory, such as ferroelectric RAM (FRAM), resistive RAM (ReRAM), spin-transfer torque magnetic RAM (STT-MRAM) and / or phase-change RAM (PRAM).

[0124] also, Figure 10 An example is shown in which the detection and repair of defective word lines according to one embodiment is performed by software, but the embodiment is not necessarily limited to this. As an example, in Figure 10 In the illustrated embodiment, at least some of the operations performed by executing software loaded in RAM440 can be performed by hardware-implemented circuitry.

[0125] Figure 11 This is a diagram of the meta-region based on an example embodiment. Figure 12 This is a table used to explain the weak memory cell information according to the example embodiment. Figure 13 This is a table used to explain the unit operation mode information according to the example embodiment.

[0126] refer to Figure 11 Meta-region 420 may include weak memory cell information 421 and cell operation mode information 422. Referring below... Figure 9 describe Figures 11 to 13 , Figure 9 Assume that the memory cell array 510 of the memory device 500 includes multiple normal word lines (e.g., first normal word lines NWL1 to sixth normal word lines NWL6) and multiple spare word lines (e.g., first spare word lines SWL1 to third spare word lines SWL3), such as Figure 4A As shown.

[0127] refer to Figure 12 Table 421a shows weak memory cell information 421 when all memory cells in a plurality of memory cells are normal, and Table 421b shows weak memory cell information 421 that changes when a weak memory cell is detected.

[0128] In response to a read / write request from the host, the memory controller 400 can control the memory device 500 by sending a command to the memory device 500, causing the memory device 500 to perform a write operation, a read operation, or an erase operation. Subsequently, the repair controller 410 can determine whether the memory device 500 successfully performed the operation in response to the command. For example, the repair controller 410 can determine whether the memory device 500 successfully performed a write operation or an erase operation in response to a write command or an erase command. The repair controller 410 can determine whether the memory cell is normal or defective based on the success or failure of the operation. In this embodiment, a method by which the repair controller 410 determines whether a memory cell is defective based on the success or failure of a write or erase operation on the memory cell has been described. However, the method by which the repair controller 410 determines whether a memory cell is defective is not limited to this. Furthermore, the range of detected faults does not need to be so limited.

[0129] Before the repair controller 410 performs the repair operation, the weak memory cell information 421 can be the same as that shown in the first table 421a. For example, the memory cells at the intersections between the first normal word line NWL1 to the sixth normal word line NWL6 and the first bit line BL1 to the fourth bit line BL4 can all be normal. Although Figure 12The illustration shows a case where the first table 421a does not include the status of memory cells connected to the first spare word line SWL1 through the third spare word line SWL3, but the inventive concept is not necessarily limited to this. In another case, for example, the first table 421a may include information indicating that the memory cells connected to the first spare word line SWL1 through the third spare word line SWL3 are functioning normally.

[0130] The repair controller 410 can update the weak memory cell information 421 shown in the second table 421b based on the location information of the weak memory cells. For example, the second table 421b may include information indicating that the memory cell at the intersection between the first normal word line NWL1 and the fourth bit line BL4, the memory cell at the intersection between the third normal word line NWL3 and the first bit line BL1, the memory cell at the intersection between the third normal word line NWL3 and the fourth bit line BL4, and the memory cell at the intersection between the fifth normal word line NWL5 and the second bit line BL2 are weak memory cells.

[0131] Furthermore, the repair controller 410 can determine the period for updating the weak memory cell information 421. For example, whenever the repair controller 410 receives information indicating the success or failure of an operation performed in response to a command, the repair controller 410 can send a command to the memory device 500 and update the weak memory cell information 421.

[0132] The repair controller 410 can detect weak word lines among multiple normal word lines based on the second table 421b. As an example, a word line comprising at least a reference number of weak memory cells can be identified as a weak word line. For instance, when the reference number is 2, a third normal word line NWL3 comprising two weak memory cells can be identified as a weak word line. The meta-region 420 may also include weak word line information. Furthermore, the method for determining weak word lines based on the weak memory cell information 421 is not limited to this.

[0133] refer to Figure 13 The cell operation mode information 422 may include the logical address of the memory cell, and the physical address and cell operation mode corresponding to that logical address. The following description assumes that cell operation modes are set and changed on a word-line basis, but the unit for setting cell operation modes is not limited to this. For example, the cell operation mode information 422 may include the physical addresses of the first normal word lines NWL1 to the sixth normal word lines NWL6, and their corresponding logical addresses and operation modes, and also includes the physical addresses of the first spare word lines SWL1 to the third spare word lines SWL3, and their corresponding logical addresses and operation modes.

[0134] Table 422a of the third table can correspond to Figure 12The first table 421a, and the cell operation mode information 422 indicating the case where multiple memory cells are normal.

[0135] Table 422a may include the logical addresses LAN1 to LAN6 of the first normal word lines NWL1 to the sixth normal word lines NWL6, and the physical addresses PAN1 to PAN6 of the first normal word lines NWL1 to the sixth normal word lines NWL6 corresponding to the logical addresses LAN1 to LAN6. Furthermore, Table 422a may include the unit operation modes of the first normal word lines NWL1 to the sixth normal word lines NWL6.

[0136] In this scenario, the spare word lines may not be activated, and access to the spare word lines by the memory controller 400 may be blocked. However, the third table 422a may still include the physical addresses PAS1 to PAS3 of the first spare word lines SWL1 to the third spare word lines SWL3.

[0137] When multiple memory cells connected to normal word lines are all functioning normally, the operating mode of memory cells connected to the first normal word line NWL1 through the sixth normal word line NWL6 may have been maintained in a specific cell operating mode. Although Figure 13 The illustration shows a state in which memory cells connected to the first normal word line NWL1 to the sixth normal word line NWL6 are all set to TLC mode, but the inventive concept is not limited to this, and all memory cells may not be in the same operating mode.

[0138] Table 422b can correspond to Figure 12 The second table 421b indicates the unit operation mode information 422 after the repair controller 410 performs the repair operation. Due to the repair operation, the unit operation mode of the weak word line can be changed, and the unit operation mode of the spare word line can be newly set by activating the spare word line.

[0139] For example, when the third normal word line NWL3 is detected as a weak word line, the cell operation mode of the third normal word line NWL3 can be changed from TLC mode to SLC mode. To compensate for the reduction in storage capacity caused by this operation, the first spare word line SWL1 can be activated and set to MLC mode. Table 422b may include the logical address LAS1 corresponding to the physical address PAS1 of the first spare word line SWL1.

[0140] Figure 14 This is an operation based on the example embodiment. Figure 9 A flowchart of the method for the memory controller 400.

[0141] Let's refer to each other. Figure 9 and Figure 14It can perform operations such as receiving read / write requests from the host (S210). For example, the memory controller 400 can access the host interface (e.g., Figure 10 430) receives read / write requests from the host.

[0142] The operation of sending commands to the memory device 500 can be performed (S220). For example, the memory controller 400 can send write, read, and erase commands to the memory device 500.

[0143] Weak word lines can be detected based on the success or failure of an operation performed in response to a command (S230). For example, the repair controller 410 can receive information from the memory device 500 indicating the success or failure of an operation performed in response to a command sent to the memory device 500 in operation S220. The repair controller 410 can detect weak memory cells based on the failure of the operation, and detect weak word lines based on weak memory cell information (see...). Figure 11 (421 in the text). For example, if the repair controller 410 detects at least a reference number of weak memory cells connected to a word line, the repair controller 410 can identify the word line as a weak word line.

[0144] The operation of setting a memory cell connected to a weak word line to a first operating mode can be performed (S240). For example, the repair controller 410 can set the cell operating mode of a memory cell connected to a weak word line to the first operating mode. The first operating mode may be different from the cell operating mode of a normal word line. For example, when the cell operating mode of a normal word line is TLC mode, the first operating mode may be SLC mode, but it is not limited to this.

[0145] An operation (S250) can be performed to set the memory cell connected to the spare word line to a second operating mode. For example, the repair controller 410 can activate the spare word line to compensate for the loss of memory capacity caused by the change in the cell operating mode of the weak word line. Activation of the spare word line may include a series of operations that allow access to the memory cell connected to the spare word line. For example, activation of the spare word line may include assigning a logical address to the memory cell connected to the spare word line, writing data to the memory cell, and mapping the assigned logical address to the physical address of the memory cell.

[0146] For example, the repair controller 410 can set the cell operation mode of the memory cell connected to the active spare word line to a second operation mode. The second operation mode may be different from the cell operation mode and / or the first operation mode of the normal word line. For example, when the cell operation mode of the normal word line is TLC mode and the first operation mode is SLC mode, the second operation mode may be MLC mode, but is not limited to this.

[0147] Furthermore, despite Figure 14 An example is shown in which operation S250 is performed after operation S240, but the order in which operations S240 and S250 are performed is not limited to this. Operations S240 and S250 can be performed in parallel, for example, or in reverse order.

[0148] Figure 15 This is an operation based on the example embodiment. Figure 9 A flowchart of the method for the memory controller 400.

[0149] According to an embodiment, Figure 15 Multiple operations can correspond to Figure 14 Operations S210 to S230 can be omitted, and the steps from... Figure 14 Redundant description.

[0150] refer to Figure 9 and Figure 15 It can perform operations that receive read / write requests from the host (S310).

[0151] The memory device 500 can perform operations such as sending write commands or erasing commands (S320).

[0152] Memory cells where write or erase operations have failed can be detected as weak memory cells (S330). For example, memory cells where write or erase operations have failed at least a reference number of times can be detected as weak memory cells.

[0153] For example, memory cells that have failed in a read operation in response to a read command can also be detected as weak memory cells. It can be determined that memory cells that have failed in a read operation have lower reliability than memory cells that have failed in a write or erase operation. Therefore, in this embodiment, according to this embodiment, memory cells that have failed in a read operation can be excluded from the scope of the repair operation.

[0154] An operation (S340) can be performed to determine whether there are word lines containing at least a reference number of weak memory cells. For example, the repair controller 410 can determine the reference number used to detect weak word lines.

[0155] When a word line containing at least a reference number of weak memory cells exists in operation S340, the word line can be detected as a weak word line (S350).

[0156] If there is no word line in operation S340 that includes at least the number of weak memory cells as referenced, operation S310 can be executed again.

[0157] Figure 15One scenario is illustrated where a weak memory cell and a weak word line are detected each time a command is sent to memory device 500. However, the timing of performing the operations of detecting weak memory cells and / or detecting weak word lines is not limited to this.

[0158] Figure 16 This is a flowchart of a method for operating a memory controller according to an example embodiment.

[0159] According to an embodiment, Figure 16 It can correspond to Figure 14 Operations S240 and S250.

[0160] refer to Figure 9 and Figure 16 The operation (S410) can be performed to determine the word line in which existing data stored in a memory cell connected to a weak word line will be stored. For example, step S410 can describe a process that allows data stored on a weak word line to be transferred to a new word line.

[0161] According to an embodiment, the cell operation mode of a word line detected as a weak word line can be changed, and the word line can then operate in the changed cell operation mode. For this purpose, an operation can be performed to transfer existing data stored in a memory cell connected to the weak word line to another memory cell.

[0162] Therefore, according to the embodiment, the repair controller 410 can determine the new memory cell where existing data stored in the memory cell connected to the weak word line will be stored, and / or the new word line connected to the memory cell storing the existing data. This word line can be a spare word line or a normal word line other than the weak word line. To store the existing data in the spare word line, operations such as assigning a logical address to the spare word line by activating it and setting the cell operation mode of the spare word line can be performed as described above.

[0163] Existing data can be stored in memory cells connected to the defined word lines, and existing data stored in memory cells connected to weak word lines can be erased (S420). For example, the repair controller 410 can send a repair copy command to the memory device 500.

[0164] The repair copy command can refer to a command used to control the movement of data in the memory device 500. For example, the repair controller 410 can provide the memory device 500 with information about weak word lines storing existing data and information about word lines where existing data will be stored, along with the repair copy command.

[0165] Furthermore, by sending a repair copy command to the memory device 500, the repair controller 410 can copy existing data to the memory cell connected to the word line determined in operation S410, and erase existing data from the memory cell connected to the weak word line.

[0166] For example, in order to put all memory cells connected to the weak word line into an erase state, the repair controller 410 can prevent access to the weak word line so that no new data is written or stored data is read.

[0167] The operation of determining which spare word line to be activated can be performed (S430). For example, the repair controller 410 can determine the spare word line to be activated and store the location information of the activated spare word line in the meta area 420. In addition, the repair controller 410 can determine the cell operation mode of the spare word line and store the determined cell operation mode in the meta area 420.

[0168] The operation of sending unit operation mode control signals for setting the unit operation mode of weak word lines and the unit operation mode of spare word lines to memory device 500 can be performed (S440). For example, repair controller 410 can send unit operation mode control signals including the unit operation mode of the weak word line change, the position information of the activated spare word line, and the unit operation mode of the spare word line to memory device 500. Therefore, memory device 500 can contain all the necessary information to redirect data to non-weak cells.

[0169] Furthermore, in response to a request received from the host, the repair controller 410 may not send a unit operation mode control signal to the memory device 500 to change the unit operation mode of the word line, but instead convert the command to be sent to the memory device 500. For example, the repair controller 410 may convert the command, address, and data to be sent to the memory device 500 based on the unit operation mode information 422. In this case, operation S440 can be omitted. After the spare word line is activated, the operation of the memory device 500 can be performed through the conversion operation of the repair controller 410.

[0170] Figure 17 This is a block diagram of a storage system 3000 according to an example embodiment.

[0171] refer to Figure 17 The storage system 3000 may include a memory controller 600 and a memory device 700. Figure 17 It can correspond to Figure 9 Modified embodiments, and references may be omitted. Figure 9 Redundant description.

[0172] The memory device 700 may include a memory cell array 710, and corresponds to the above reference. Figure 1 , Figure 2 and Figure 9 The memory devices 200 and 500 are described. The memory cell array 710 may include a meta-region 720. The meta-region 720 may include memory cells in the memory cell array 710 connected to normal word lines or memory cells connected to spare word lines.

[0173] The memory controller 600 may include a repair controller 610. The repair controller 610 may control the operation of the memory device 700 to detect at least one weak memory cell included in the memory cell array 710 included in the memory device 700. Repair operations according to an embodiment may be performed on the detected weak memory cell.

[0174] The repair controller 610 can control at least one spare word line to supplement or replace the weak word line connected to the detected weak memory cell. For example, the repair controller 610 can change the cell operation mode of the weak word line connected to the detected weak memory cell. Furthermore, at least one spare word line can be activated, and the cell operation mode of that spare word line can be set. The repair controller 610 can send a cell operation mode control signal CTRL_CM to the memory device 700 to change or set the cell operation mode of each word line.

[0175] The repair controller 610 can store the information required to perform the repair operation and the information required to control the memory device 700 based on the repair results in the meta-region 720 of the memory cell array 710. For example, the meta-region 720 may include weak memory cell information and cell operation mode information generated based on the repair results.

[0176] For example, the repair controller 610 can detect weak memory cells and store location information about the weak memory cells in the meta-region 720. Furthermore, the repair controller 610 can generate weak word line information based on the stored location information about the weak memory cells and store the weak word line information in the meta-region 720.

[0177] The repair controller 610 can determine the unit operation mode of the weak word line, the number and location of the spare word lines, and the unit operation mode of at least one spare word line based on the weak word line information. The repair controller 610 can store the unit operation mode of the weak word line, the number and location of the spare word lines, and the unit operation mode of at least one spare word line in the meta-region 720.

[0178] Figure 18 This is a block diagram of an SSD system 4000 according to an example embodiment.

[0179] refer to Figure 18 The SSD system 4000 may include a host 800 and an SSD 900. The SSD 900 can send signals to and receive signals from the host 800 via a signal connector SGL, and receive power via a power connector PWR. The SSD 900 may include an SSD controller 910, an auxiliary power device 920, and multiple non-volatile memory devices (e.g., a first non-volatile memory device 930 to a third non-volatile memory device 950).

[0180] The SSD controller 910 can control the first non-volatile memory device 930 to the third non-volatile memory device 950 in response to signals received from the host 800. For example, the SSD controller 910 and the first non-volatile memory device 930 to the third non-volatile memory device 950 can respectively correspond to references. Figures 9 to 17 The memory controller 400 or 600 and three non-volatile memory devices 200 or 500 are described herein.

[0181] Auxiliary power device 920 can be connected to host 800 via power connector PWR. Auxiliary power device 920 can receive power from host 800 and be charged. When the power supply from host 800 is unstable or intermittent, auxiliary power device 920 can provide power to SSD system 4000. For example, auxiliary power device 920 can be located inside or outside SSD 900. For example, auxiliary power device 920 can be located on the motherboard of SSD system 4000 and provide auxiliary power to SSD 900.

[0182] The first non-volatile memory device 930 to the third non-volatile memory device 950 can be used as storage media for the SSD 900. The first non-volatile memory device 930 to the third non-volatile memory device 950 can be connected to the SSD controller 910 via multiple channels Ch1 to Chn. At least one non-volatile memory can be connected to each of channels Ch1 to Chn. The first non-volatile memory device 930 to the third non-volatile memory device 950 connected to each of channels Ch1 to Chn can be connected to the same data bus.

[0183] The SSD controller 910 may include a repair controller according to the embodiments described above. The repair controller may be implemented in hardware, software, or a combination thereof.

[0184] The repair controller can detect weak word lines included in each of the first to third non-volatile memory devices 930 to 950 as described above, and change the cell operation mode of the memory cells connected to the weak word lines. Furthermore, spare word lines can be activated, and the cell operation mode of the spare word lines can be set, thus enabling write, read, and erase operations to be performed on the memory cells connected to the spare word lines.

[0185] For example, information generated as a result of the operation of the repair controller can be temporarily stored in the SSD controller 910, or stored in a non-volatile manner in each of the first non-volatile memory devices 930 to the third non-volatile memory devices 950.

[0186] Weak word lines and spare word lines can be in different non-volatile memory devices. For example, weak word lines can appear in the first non-volatile memory device 930, and spare word lines of the second non-volatile memory device 940 can be selected and activated to repair weak word lines.

[0187] As described above, the repair operation according to this disclosure allows the use of weak word lines. Therefore, the storage capacity of the memory device according to this disclosure can be ensured by accessing spare word lines.

[0188] Although the inventive concept has been shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A memory device, comprising: A memory cell array comprising multiple normal word lines and at least one spare word line; and The repair controller is configured to set memory cells connected to at least one weak word line in the normal word lines to a first operating mode, and is also configured to set memory cells connected to at least one spare word line to a second operating mode. in, At least one weak word line was detected based on the test results. During the testing process, memory cells connected to multiple normal word lines are configured to write (n+m) bits of data in a third operating mode. The first operating mode is configured to write n bits of data to memory cells connected to at least one weak word line. The second operating mode is configured to write m bits of data to memory cells connected to at least one spare word line. Both n and m are natural numbers greater than or equal to 1, and m is greater than n.

2. The memory device according to claim 1, wherein, The at least one weak word line includes multiple weak memory cells. The number of weak memory cells included in each of the at least one weak word line is greater than or equal to the reference number.

3. The memory device according to claim 1, wherein, The memory cell array includes a meta-region configured to store metadata. The repair controller stores the unit operation mode of the at least one weak word line and the unit operation mode of the at least one spare word line in the meta area.

4. The memory device according to claim 3, wherein, The memory device receives commands from the memory controller and, in response to the commands, performs operations based on the cell operation modes stored in the meta-region.

5. The memory device according to claim 1, wherein, The first operating mode is the single-level cell (SLC) mode. The second operating mode is the Multi-Level Cell (MLC) mode, and The third operating mode is the three-level cell TLC mode.

6. A memory controller connected to a memory device comprising a plurality of normal word lines and at least one spare word line, wherein, The memory controller is configured to: Send commands to the memory device. If the operation performed in response to the command fails, at least one of the normal word lines is detected as a weak word line. Set the memory cell connected to the weak word line to the first operating mode, and The memory cell connected to the at least one spare word line is set to a second operating mode, wherein the memory cell connected to the plurality of normal word lines is set to a third operating mode configured to write (n+m) bits of data, and wherein the first operating mode is configured to write n bits of data to the memory cell connected to the weak word line, the second operating mode is configured to write m bits of data to the memory cell connected to the at least one spare word line, and each of n and m is a natural number greater than or equal to 1, and m is greater than n.

7. The memory controller of claim 6 further includes a buffer memory, the buffer memory including logical addresses, physical addresses and operating mode information of memory cells connected to the weak word line, and also including logical addresses, physical addresses and operating mode information of memory cells connected to the at least one spare word line.

8. The memory controller according to claim 7, wherein, The memory controller is configured to send a repair copy command to the memory device and to store existing data, which is stored in a memory cell connected to the weak word line, a memory cell connected to the normal word line, and a memory cell connected to the at least one spare word line.

9. The memory controller according to claim 8, wherein, The memory controller is configured to receive the existing data from the memory device in response to the repair copy command, the existing data being stored in a memory cell connected to the weak word line, and is also configured to temporarily store the existing data in the buffer memory and send the existing data to the memory device.

10. The memory controller according to claim 7, wherein, The memory controller is configured to generate logical addresses for memory cells connected to the at least one spare word line and to map the logical addresses to physical addresses for memory cells connected to the at least one spare word line.

11. The memory controller according to claim 7, wherein, The memory controller is configured to send a cell operation mode control signal to the memory device, the cell operation mode control signal including operation mode information of the memory cell connected to the weak word line and operation mode information of the memory cell connected to the at least one spare word line.

12. The memory controller according to claim 7, wherein, The memory controller is configured to translate commands and addresses in response to a request received from a host, based on the operating mode information of the memory cells connected to the weak word line and the operating mode information of the memory cells connected to the at least one spare word line, and to send the translated commands and translated addresses to the memory device.

13. The memory controller according to claim 6, wherein, The memory controller is configured to detect a normal word line comprising at least a reference number of weak memory cells as a weak word line based on the number of weak memory cells in each normal word line included in the normal word line.

14. The memory controller according to claim 13, wherein, The commands include write commands or erase commands.

15. A method of operating a storage device, the storage device comprising a memory device and a memory controller, the memory device including a plurality of normal word lines and at least one spare word line, the method comprising: At least one of the normal character lines is detected as a weak character line; The operating mode of the memory cell connected to the weak word line is set to the first operating mode, and the operating mode of the memory cell connected to the at least one spare word line is set to the second operating mode, wherein... A memory cell configured to operate in a first mode is configured to store a first number of bits, and a memory cell configured to operate in a second mode is configured to store a second number of bits, which is greater than the first number of bits. Receive write requests from the host; and Based on the configured operating mode, data is written to at least one of the memory cells connected to a weak word line and the memory cells connected to at least one spare word line. The memory cells connected to the plurality of normal word lines are configured to write (n+m) bits of data in a third operating mode, wherein the first operating mode is configured to write n bits of data to the memory cells connected to the weak word lines, the second operating mode is configured to write m bits of data to the memory cells connected to the at least one spare word line, and each of n and m is a natural number greater than or equal to 1, and m is greater than n.

16. The method according to claim 15, wherein, Detecting at least one of the normal word lines as a weak word line includes detecting a word line comprising at least a reference number of weak memory cells as the weak word line, wherein the weak memory cells are memory cells in which write or erase operations have failed in connection with the normal word line.

17. The method according to claim 15, wherein, Setting the operating mode of the memory cell connected to the spare word line to the second operating mode includes storing the first operating mode information and the second operating mode information in at least one of the buffer memory of the memory controller and the meta region of the memory device.

18. The method according to claim 15, wherein, The data writing includes writing the data to a memory cell connected to the weak word line in Single-Level Cell (SLC) mode, or writing the data to a memory cell connected to the spare word line in Multi-Level Cell (MLC) mode.

Images