Semiconductor memory device

Abstract

A semiconductor storage device of an embodiment of the present application includes a laminate (SK), a columnar body, a conductive member (SL), a plate-shaped portion (ST2), and a division portion (IP). In the laminate (SK), a plurality of conductive layers (WL) and a plurality of insulating layers (OL) are alternately laminated, and a step portion (SR) is formed at an end portion in a first direction by the conductive layer (WL). The columnar body penetrates the laminate (SK), and a memory cell is formed at a portion facing the conductive layer (WL). The conductive member (SL) is electrically connected to the columnar body below the laminate (SK), and extends to a region (PA) in a side direction of the laminate (SK) beyond the step portion (SR) in the first direction. The plate-shaped portion (ST2) extends in a lamination direction of the laminate (SK) and reaches the conductive member (SL) within the region (PA), and extends in a second direction intersecting the first direction. The division portion (IP) is disposed in the conductive member (SL) on a side of the step portion (SR) farther than the plate-shaped portion (ST2), partially divides the conductive member (SL), and contains an insulating material.

Description

[0001] [Related Applications]

[0002] This application claims priority to Japanese Patent Application No. 2020-217402, filed on December 25, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device. Background Technology

[0004] In semiconductor devices such as semiconductor memory devices, three-dimensional structures are employed to increase storage capacity. To further increase storage capacity, the total thickness of the thin films formed on substrates such as semiconductor wafers is further increased. In this case, due to differences in coefficients of thermal expansion between the substrate and various thin films, for example, the stress generated in the films increases, raising concerns about film peeling. Summary of the Invention

[0005] One embodiment provides a semiconductor memory device capable of reducing thin-film peeling.

[0006] According to one embodiment, a semiconductor memory device is provided. The semiconductor memory device includes a stacked body, a pillar-shaped body, a conductive member, a plate-shaped portion, and a segmentation portion. In the stacked body, a plurality of conductive layers and a plurality of insulating layers are alternately stacked layer by layer, and a step portion formed by the conductive layers is formed at the end in a first direction. The pillar-shaped body extends through the stacked body and forms a memory cell at a portion facing at least one of the plurality of conductive layers. The conductive member is electrically connected to the pillar-shaped body below the stacked body and extends along the first direction beyond the step portion to a region on the lower side of the stacked body. The plate-shaped portion extends in the region on the side of the stacked body along the stacking direction of the stacked body and reaches the conductive member, and extends along a second direction intersecting the stacking direction and the first direction. The segmentation portion is disposed within the conductive member further along the step portion side than the plate-shaped portion, partially dividing the conductive member, and includes an insulating material. Attached Figure Description

[0007] Figure 1 This is a partial top view of the semiconductor memory device according to the embodiment.

[0008] Figure 2 It is along Figure 1 A cross-sectional view of line L1-L1.

[0009] Figure 3 It is along Figure 1 A cross-sectional view of line L2-L2.

[0010] Figure 4This is a partial top view showing the top shape of the segment in the semiconductor memory device according to the embodiment.

[0011] Figures 5A to 5C This is a partial cross-sectional view illustrating a method for forming a cell array region of a semiconductor memory device according to an embodiment.

[0012] Figures 6A to 6C It continues Figures 5A to 5C A partial cross-sectional view of the method for forming the cell array region of the semiconductor memory device according to the following embodiment will be described.

[0013] Figures 7A to 7F This is a partial cross-sectional view illustrating the method for forming the segment of a semiconductor memory device according to an embodiment.

[0014] Figure 8 This is a partial cross-sectional view of a comparative example semiconductor memory device.

[0015] Figures 9A to 9C This is a partial cross-sectional view showing a variation of the segment of a semiconductor memory device according to an embodiment.

[0016] Figure 10A , Figure 10B This is a partial cross-sectional view showing a variation of the segment of a semiconductor memory device according to an embodiment.

[0017] Figures 11A to 11C This is a partial top view showing an example of a variation of the segment of a semiconductor memory device according to an embodiment. Detailed Implementation

[0018] Hereinafter, non-limiting exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In all the drawings, the same or corresponding reference numerals are used to denote the same or corresponding components or parts, and repeated descriptions are omitted. Furthermore, the drawings are not intended to show relative comparisons between components or parts, or between the thicknesses of various layers; therefore, the specific thickness or dimensions can be appropriately determined by the operator by referring to the following non-limiting embodiments.

[0019] Figure 1 This is a partial top view of the semiconductor memory device according to the embodiment. Figure 2 It is along Figure 1 A sectional view of line L1-L1. Figure 3 It is along Figure 1 A cross-sectional view along line L2-L2. The semiconductor memory device 1 of this embodiment has a generally rectangular substrate formed of a semiconductor such as silicon, a peripheral circuit section formed on the substrate (described below), and a memory element section formed on the peripheral circuit section.

[0020] Reference Figure 1The semiconductor memory device 1 has a cell array region CA and a stepped region SA in the memory element section. Multiple memory pillars MP are disposed in the cell array region CA, arranged in a grid pattern in the xy plane of the figure, and extending along the z direction of the figure. The stepped region SA includes stepped sections SR, which have multiple steps (described below). Furthermore, an upper wiring layer including upper wiring and plugs is disposed above the cell array region CA and the stepped region SA, but... Figure 1 The illustration is omitted in the text. Furthermore, the region between the stepped region SA and the end 1Y of the semiconductor memory device 1 is sometimes referred to as the peripheral region PA.

[0021] Furthermore, the semiconductor memory device 1 includes multiple first plate-shaped portions ST1 that divide the cell array region CA and the stepped region SA into multiple blocks BLK. Each first plate-shaped portion ST1 extends through the cell array region CA and the stepped region SA in the x-direction and terminates in the peripheral region PA. Additionally, the first plate-shaped portion ST1 extends in the z-direction shown in the figure and terminates in the source line SL described below. Furthermore, the semiconductor memory device 1 has a second plate-shaped portion ST2 in its peripheral region PA. The second plate-shaped portion ST2 has a plate-like shape extending in both the y-direction and the z-direction. Furthermore, a segment IP extending in the y-direction, substantially parallel to the second plate-shaped portion ST2, is provided on the side closer to the stepped region SA than the second plate-shaped portion ST2. The segment IP is formed in the source line SL as described below.

[0022] Reference Figure 2 A transistor Tr, separated by the component separation section STI, is formed on the surface of the substrate S. A first interlayer insulating film IL1, for example made of an insulating material such as silicon oxide, is formed on the transistor Tr and the substrate S. Within the first interlayer insulating film IL1, a via Vg and a wiring ML, connected to the gate electrode of the transistor Tr, are provided. These transistors Tr, via Vg, wiring ML, and the first interlayer insulating film IL1 constitute the peripheral circuit section PER that controls the memory cell described below.

[0023] An insulating film BSL is disposed on top of the first interlayer insulating film IL1. The insulating film BSL can be formed of an insulating material such as silicon oxide. Here, since the insulating film BSL is formed of the same insulating material as the first interlayer insulating film IL1, the insulating film BSL and the first interlayer insulating film IL1 can be considered as a single insulating portion. This insulating portion serves as a base layer, and a storage element portion is disposed on top of it. Specifically, a source line SL is formed on the insulating film BSL. The source line SL has a first conductive layer ECL1, a second conductive layer ECL2, and a third conductive layer ECL3, which are sequentially stacked. The first conductive layer ECL1, the second conductive layer ECL2, and the third conductive layer ECL3 are formed, for example, of conductive polycrystalline silicon with impurities such as arsenic or antimony added.

[0024] A stacked body SK is formed on the source line SL. In the stacked body SK, multiple insulating layers OL and multiple conductive layers WL are alternately stacked layer by layer. The insulating layers OL are formed of an insulating material, such as silicon oxide, and the conductive layers WL are formed of a metal, such as tungsten or molybdenum.

[0025] As shown in the figure, the memory pillar MP penetrates the stacked layer SK, the third conductive layer ECL3, and the second conductive layer ECL2 along the z-direction (the stacking direction of the stacked layer SK), and terminates within the first conductive layer ECL1. The memory pillar MP has a generally cylindrical shape with a base, and includes a core layer COR, a channel layer CHN, and a memory film MEM formed concentrically from the center outwards. Here, the core layer COR can be formed, for example, from silicon oxide, and the channel layer CHN can be formed, for example, from conductive polycrystalline silicon or amorphous silicon. Furthermore, as... Figure 2 As shown, the memory film MEM has a tunnel insulating layer TN, a charge accumulation layer CT, and a barrier insulating layer BK formed sequentially along a direction from the center of the memory pillar MP outward. The tunnel insulating layer TN and the barrier insulating layer BK may be formed, for example, by silicon oxide, and the charge accumulation layer CT may be formed, for example, by silicon nitride.

[0026] In the stacked matrix SK, a memory cell MC is formed at the portion of the conductive layer WL facing the memory film MEM of the memory pillar MP. In this case, the conductive layer WL functions as a word line. Specifically, the portions of the uppermost and lowermost conductive layers WL facing the memory pillar MP function as selection transistors. That is, the uppermost conductive layer WL in the stacked matrix SK corresponds to the drain-side selection gate line, and the lowermost conductive layer WL corresponds to the source-side selection gate line. Alternatively, a conductive polysilicon layer can be used as the source-side selection gate line.

[0027] Furthermore, in the memory cylinder MP, the memory film MEM is not disposed within the area corresponding to the lower and upper surfaces of the second conductive layer ECL2 of the source line SL. Therefore, within this area, the channel layer CHN constitutes the outer surface of the memory cylinder MP. Moreover, the channel layer CHN is in contact with the second conductive layer ECL2. Thus, the channel layer CHN is electrically connected to the source line SL. That is, the source line SL as a whole functions as the source for the memory cell MC formed in the memory cylinder MP. Since the channel layer CHN contacts the second conductive layer ECL2 with its outer peripheral surface, their contact area can be increased, thereby reducing the contact resistance.

[0028] An insulating film SO is formed on the stacked matrix SK and the memory pillar MP. A plug PG, which is connected to the channel layer CHN of the memory pillar MP, is embedded in the insulating film SO. In addition, the plug PG is connected to the upper wiring (not shown), and the upper wiring is connected to the through contact (not shown) that runs through the stacked matrix SK and is connected to the peripheral circuit section PER.

[0029] The first plate-shaped portion ST1 extends from the upper surface of the laminate SK through the laminate SK and the third conductive layer ECL3, and terminates within the second conductive layer ECL2. For example, silicon oxide is embedded into the following slits that extend through the laminate SK, etc. (refer to...) Figure 6C The first plate-shaped portion ST1 is formed by embedding a slit GP1. Alternatively, a metal such as tungsten or molybdenum may be embedded therein instead of silicon oxide. In this case, the first plate-shaped portion ST1 functions as a source line contact that is electrically connected to the source line SL. Furthermore, in this case, before embedding the metal into the slit, a pad layer made of an insulating material such as silicon oxide is formed on the inner wall of the slit.

[0030] Figure 3 It is along Figure 1 The cross-sectional view along line L2-L2 illustrates the stepped region SA and its underlying structure. A peripheral circuit section PER is also located below the stepped region SA, but it differs from the peripheral circuit section PER below the unit array region CA. Figure 2 They have the same composition, therefore, in Figure 3 The illustration is omitted.

[0031] The stepped portion SR has multiple stepped STPs. In this embodiment, each stepped STP is composed of a set of conductive layers WL and insulating layers OL. A second interlayer insulating film IL2 is formed above the stepped portion SR. The second interlayer insulating film IL2 is formed of the same insulating material (e.g., silicon oxide) as the insulating material of the insulating layer OL. Therefore, the insulating layer OL and the second interlayer insulating film IL2 are substantially integrated. Each conductive layer WL extends from the cell array region CA to the stepped region SA in the x-direction. The higher the conductive layer WL, that is, the further away from the source line SL, the shorter its extension length. Thus, the conductive layer WL becomes the substantial step surface (tread surface) TRR of the stepped STP. Furthermore, the end of the lowest conductive layer WL in the x-direction corresponds to the end of the laminate SK in the x-direction. In this embodiment, the end of the laminate SK in the x-direction separates the stepped region SA from the surrounding region PA. Furthermore, from the viewpoint of stress relief described below, the second plate-shaped portion ST2 is disposed within 5 μm of the x-direction end of the laminate SK along the x-direction, and more preferably disposed within 1 μm of the x-direction end of the laminate SK.

[0032] A contact CC, connecting the conductive layer WL to the stepped surface TRR, is formed by the through insulating film SO and the second interlayer insulating film IL2. The contact CC can be formed of a metal such as tungsten or molybdenum. The contact CC is connected to the surrounding circuit section PER via upper wiring (not shown) and the through contact. Figure 2 The peripheral circuit section (PER) connects to the memory cell (MC) via the conductive layer (WL) which serves as the word line. Figure 2 A specified voltage is applied. Furthermore, the contact CC can also be connected to the conductive layer WL, which serves as the step surface of the step portion, after the step portion is provided within the unit array region CA. In this case, the contact CC of the step portion SR can be omitted, thus the step portion SR can be considered a so-called dummy step portion.

[0033] Furthermore, below the stepped section SR and the second interlayer insulating film IL2, the third conductive layer ECL3 of the source line SL extends from the cell array region CA, and an insulating layer IN is disposed below it. The insulating layer IN is in contact with the second conductive layer ECL2 at a designated position between the stepped region SA and the cell array region CA. That is, in the cell array region CA, the second conductive layer ECL2 is disposed below the third conductive layer ECL3, and on the other hand, in the stepped region SA, the insulating layer IN is disposed below the third conductive layer ECL3.

[0034] Below the insulating layer IN, the first conductive layer ECL1 of the source line SL extends from the cell array region CA. Furthermore, the second plate-shaped portion ST2, which penetrates the second interlayer insulating film IL2, the third conductive layer ECL3, and the insulating layer IN, terminates within the first conductive layer ECL1. In this embodiment, the slit is formed in the same step as the slit for forming the first plate-shaped portion ST1, and insulating material is embedded in the slit to form the second plate-shaped portion ST2, as described below. The second plate-shaped portion ST2 and the slit for forming the second plate-shaped portion ST2 function to mitigate stress that may occur in the cell array region CA, the stepped region SA, and the peripheral region PA.

[0035] Furthermore, a break portion IP is provided in the first conductive layer ECL1 to partially break the first conductive layer ECL1. The break portion IP can be formed using the same material as the insulating material constituting the insulating layer IN. Figure 4 This is a partial top view showing the top shape of the break section IP, specifically, a partial top view of the first conductive layer ECL1. For convenience, the position of the first plate-shaped portion ST1 is indicated by a dashed line. As shown in the figure, in this embodiment, the break section IP extends approximately parallel to the second plate-shaped portion ST2 in the peripheral region PA along the y-direction and terminates within the first conductive layer ECL1. That is, the break section IP does not completely break the first conductive layer ECL1. In other words, the first conductive layer ECL1 is connected to both sides of the break section IP along the x-direction through the region outside the y-direction end of the break section IP, thus achieving electrical conduction on both sides of the break section IP.

[0036] The following is for reference Figures 5A to 5C and Figures 6A to 6C The method for forming the cell array region CA is explained. Figures 5A to 5C and Figures 6A to 6C This is a partial sectional view illustrating the formation method of the cell array region CA according to each major step, equivalent to... Figure 2 The partial cross-sectional view shown. Furthermore, prior to this formation method, for example, a peripheral circuit section (PER) as described above is formed on a semiconductor wafer such as a silicon wafer. Figure 2 An insulating film BSL is formed on the interlayer insulating film IL1 of the peripheral circuit section PER.

[0037] Reference Figure 5AA first conductive layer ECL1, a silicon oxide film Ox1, a sacrificial film SC, a silicon oxide film Ox2, and a third conductive layer ECL3 are sequentially formed on the insulating film BSL. Here, the sacrificial film SC can be formed of silicon nitride. Furthermore, a multilayer stack TSK is formed on the third conductive layer ECL3, with multiple insulating layers OL and multiple silicon nitride layers SN alternately stacked layer by layer. Moreover, the multilayer stack SK described above is formed by replacing the silicon nitride layers SN of the multilayer stack TSK with conductive layers WL. The insulating layer OL is the same in both the multilayer stack SK and the multilayer stack TSK.

[0038] Next, as Figure 5B As shown, multiple memory pillars (MP) are formed in the through-layer stack TSK (four in the illustrated example). Specifically, memory pillars MP are formed by forming memory holes in the first conductive layer ECL1 of the through-layer stack TSK, terminating at the source line SL, and then sequentially forming a memory film MEM, a channel layer CHN, and a core layer COR on the inner surface of the memory holes. Then, as... Figure 5C As shown, slits GP1 are formed on both sides of the four memory pillars MP. These slits GP1 are then embedded with insulating material to become the first plate-shaped portion ST1. However, before that, it is used to replace the silicon oxide film Ox1, the sacrificial film SC, and the silicon oxide film Ox2 with the second conductive layer ECL2, and further to replace the silicon nitride layer SN in the stack TSK with the conductive layer WL.

[0039] A padding layer LL is formed on the inner surface and bottom surface of the slit GP1. The padding layer LL is formed to protect the insulating layer OL and the silicon nitride layer SN within the stack TSK during the removal of the sacrificial film SC and the silicon oxide films Ox1 and Ox2. Polysilicon can be used as a material for the padding layer LL. After the padding layer LL formed on the bottom surface of the slit GP1 is removed by anisotropic etching, the sacrificial film SC is exposed on the bottom surface of the slit GP1. Subsequently, after the sacrificial film SC and the silicon oxide films Ox1 and Ox2 are sequentially removed through the slit GP1, as shown... Figure 6A As shown, space S1 is formed. Additionally, simultaneously with the formation of space S1, the memory film MEM of the memory pillar MP is removed, exposing the channel layer CHN on the side of the memory pillar MP. Then, as... Figure 6B As shown, conductive polysilicon is embedded into space S1 through slit GP1, thereby forming the second conductive layer ECL2. Thus, the source line SL is electrically connected to the channel layer CHN of the memory pillar MP.

[0040] Subsequently, after removing the padding layer LL within the slit GP1, the insulating layer OL and the silicon nitride layer SN are exposed on the inner surface of the slit GP1. Then, the silicon nitride layer SN within the stack TSK is etched away through the slit GP1. A conductive material, such as tungsten or molybdenum, is embedded in the space created by removing the silicon nitride layer SN to form the conductive layer WL, which serves as the word line. Figure 6C This yields the laminate SK. Subsequently, an insulating material (e.g., silicon oxide) is embedded into the slit GP1, and an insulating film SO with plugs PG is formed on the laminate SK, thus obtaining the structure of the cell array region CA. Figure 2 ).

[0041] Furthermore, the space created by removing the silicon nitride layer SN through the slit GP1 is defined by two adjacent insulating layers OL, but an aluminum oxide film as a protective layer can also be formed on the exposed surfaces of these insulating layers OL through the slit GP1.

[0042] Next, refer to Figures 7A to 7F The break point IP of the first conductive layer ECL1 ( Figure 3 The formation method of ) will be explained. Figures 7A to 7F This is a partial cross-sectional view illustrating the method of forming the segment IP. Furthermore, for ease of explanation, the structure below the insulating film BSL has been omitted.

[0043] Reference Figure 7A A silicon oxide film Ox1 is formed on the first conductive layer ECL1 on the insulating film BSL, and a silicon nitride film HMO is formed on it as an etching mask (hard mask). The first conductive layer ECL1 and the silicon oxide film Ox1 extend from the cell array region CA beyond the stepped region SA to the peripheral region PA. That is, the first conductive layer ECL1 and the silicon oxide film Ox1 are formed both in the cell array region CA and in the stepped region SA and the peripheral region PA. Figure 5A Before the sacrificial film SC shown, a silicon nitride film HM0 is formed on top of a silicon oxide film Ox1.

[0044] Next, as Figure 7B As shown, an opening OP1 is formed on the silicon nitride film HM0 through photolithography and etching steps to obtain a hard mask HM. Then, an opening OP2 is formed using a plasma etching method on the hard mask HM, such as reactive ion etching (RIE). Opening OP2 penetrates the silicon oxide film Ox1 and the first conductive layer ECL1, terminating within the insulating film BSL. Opening OP2 is intended to serve as an opening for the breakout IP, such as... Figure 4 As shown, it extends along the y-direction.

[0045] Reference Figure 7CAn insulating film TSO is formed on the hard mask HM. The insulating film TSO is formed of an insulating material, such as silicon oxide, and this insulating material is embedded in the opening OP2. Next, the insulating film TSO and the hard mask HM are removed by plasma etching. At this point, as... Figure 7B As shown, insulating material remains in the opening OP2 of the first conductive layer ECL1, thereby obtaining the break portion IP.

[0046] Then, as Figure 7E As shown, an insulating layer IN, such as silicon oxide, is formed on a silicon oxide film Ox1. Here, before forming the insulating layer IN, as... Figure 5A As shown, a sacrificial film SC is formed on a silicon oxide film Ox1. This sacrificial film SC is formed not only in the cell array region CA, but also in the stepped region SA and the peripheral region PA. Therefore, after removing the sacrificial film SC in the stepped region SA and the peripheral region PA by photolithography and etching steps, an insulating layer IN is formed on the silicon oxide film Ox1. Then, a silicon oxide film Ox2 is formed on the insulating layer IN. At this point, the insulating layer IN and the silicon oxide film Ox2 are essentially integrated, also formed on the sacrificial film SC in the cell array region CA. The insulating layer IN and the silicon oxide film Ox2 in these cell array regions CA can remain intact on the sacrificial film SC, or they can be thinned by, for example, chemical mechanical polishing (CMP). Subsequently, a third conductive layer ECL3 is formed on the silicon oxide film Ox2 (on the insulating layer IN, which is essentially integrated with the silicon oxide films Ox1 and Ox2 in the stepped region SA and the peripheral region PA).

[0047] Subsequently, a stacked structure TSK is formed on the third conductive layer ECL, with multiple insulating layers OL and multiple silicon nitride layers SN stacked alternately layer by layer. This stacked structure TSK is continuous with the stacked structure TSK in the cell array region CA described above (Fig. 5A). That is, the stacked structure TSK is formed across the cell array region CA and the step region SA. Then, a resist mask with an opening at the location where the step portion SR should be formed is provided on the upper surface of the stacked structure TSK, and steps such as etching, refinement of the resist mask, and another etching are performed, thereby achieving the desired effect. Figure 7F As shown, a temporary stepped section TSR is formed at the end of the laminate TSK.

[0048] Subsequently, a silicon oxide film is deposited, for example, to cover the temporary stepped section TSR. Then, the silicon oxide film is planarized using, for example, CMP, to obtain the second interlayer insulating film IL2. Next, a slit GP2 is formed through photolithography and etching steps. The slit GP2 penetrates the second interlayer insulating film IL2, the third conductive layer ECL3, and the insulating layer IN, and terminates within the first conductive layer ECL1. The slit GP2 is provided to form the second plate-like portion ST2, as... Figure 4 As shown, it extends along the y-direction.

[0049] In addition, slit GP2 can be combined with slit GP1 ( Figure 5C They form simultaneously. Here, for example... Figure 7F As shown, the slit GP2 extends into the first conductive layer ECL1 and terminates within it. In contrast, Figure 5C The slit GP1 terminates at the upper surface of the sacrificial film SC and does not reach the first conductive layer ECL1. Slit GP1 is formed by etching the stack TSK, which consists of the insulating layer OL and the silicon nitride layer SN. On the other hand, slit GP2 is mainly formed by etching the second interlayer insulating film IL2, which is formed of silicon oxide. Therefore, slit GP2 is formed at a faster etching rate than slit GP1. As a result, the length (depth) of slit GP2 in the z-direction is larger.

[0050] Subsequently, through the slit GP1, Figure 7F In the stack shown, the silicon nitride layer SN of the TSK is replaced with a conductive layer WL, and the temporary step section TSR becomes the step section SR. Figure 3 (Referring to) Figure 6C This replacement is performed in the described steps. Additionally, the slit GP2 is embedded with an insulating material such as silicon oxide, thereby forming the second plate-like portion ST2. For example, silicon oxide can be embedded into the slit GP2 using plasma chemical deposition (CVD). Subsequently, an insulating film SO is formed on the interlayer insulating film IL2, and after forming junctions CC that connect to the various surfaces TRR of the stepped portion SR, a... Figure 3 The structure shown.

[0051] Furthermore, when forming the second plate-shaped portion ST2 using the CVD method, silicon oxide is deposited on the inner and bottom surfaces of the slit GP2, with increased thickness on the inner surfaces, and they bond together at the center of the slit GP2. It is thus embedded into the slit GP2 to form the second plate-shaped portion ST2. Therefore, a seam along the z-direction remains in the center of the second plate-shaped portion ST2. The presence of the second plate-shaped portion ST2 can be detected through this seam.

[0052] Furthermore, as explained above, when the upper and lower insulating layers OL exposed in the space created by removing the silicon nitride layer SN form an aluminum oxide film as a protective layer, the aluminum oxide film can be formed not only on the slit GP1, but also on the inner surface of the slit GP2 used to form the second plate-shaped portion ST2. These inner surface aluminum oxide films are removed after the conductive material is embedded in the space described above, but may remain on the inner surface of the slit GP2. In this case, the outline of the second plate-shaped portion ST2, also formed of silicon oxide, can be defined within the second interlayer insulating film IL2 formed of silicon oxide by the remaining aluminum oxide. That is, the presence of the second plate-shaped portion ST2 within the second interlayer insulating film IL2 can also be determined by the remaining aluminum oxide.

[0053] Next, the effects achieved by the semiconductor memory device 1 of this embodiment will be explained with reference to a comparative example. Figure 8 This is a partial cross-sectional view of a comparative example semiconductor memory device, corresponding to semiconductor memory device 1 of the embodiment. Figure 7F The figure shows a cross-sectional view. As shown, in the comparative example semiconductor memory device, no breakpoint IP is provided, and a first conductive layer ECL1 is continuously formed on the insulating film BSL. Apart from this aspect, the comparative example semiconductor memory device has the same configuration as the semiconductor memory device 1 of the embodiment.

[0054] In this configuration, if a high-temperature step such as annealing is performed after the formation of the slit GP2 for forming the second plate-shaped portion ST2, there is a risk that the first conductive layer ECL1 will peel off from the insulating film BSL. As can be seen from the description so far, the semiconductor memory device at this time has a peripheral circuit portion PER on the substrate S. Figure 2 A laminate TSK, consisting of an insulating layer OL and a silicon nitride layer SN, is formed on the substrate S, with an insulating film BSL and a source line SL (including an insulating layer IN) as separators. That is, many layers of various materials are formed on the substrate S, resulting in a relatively thick total thickness. In this case, if processing is performed at a high temperature, for example, exceeding 800°C, relatively large stresses, such as those caused by differences in the thermal expansion coefficients of the materials, will act on the substrate S and the other layers. Thus, it is considered that under stress, cracks may occur, for example, from the bottom of the slit GP2 used in the second plate-shaped portion ST2 to the first conductive layer ECL1. These cracks may propagate to the interface between the first conductive layer ECL1 and the insulating film BSL, posing a risk of peeling off the PE between them.

[0055] On the other hand, in the semiconductor memory device 1 of this embodiment, a break portion IP is provided in the first conductive layer ECL1. Even if the first conductive layer ECL1 below the slit GP2 cracks due to stress, the break portion IP can prevent peeling from propagating to the stepped region SA. In particular, in this embodiment, the break portion IP is formed of the same insulating material (e.g., silicon oxide) as the insulating film BSL, so the break portion IP and the insulating film BSL can be bonded together with a strong adhesion. Therefore, peeling between the first conductive layer ECL1 and the insulating film BSL can be effectively suppressed.

[0056] Furthermore, the interruption portion IP does not completely interrupt the first conductive layer ECL1; the first conductive layer ECL1 remains electrically continuous on both sides of the interruption portion IP along the x-direction. If the first conductive layer ECL1 were completely interrupted by the interruption portion IP, for example, the portion of the first conductive layer ECL1 closer to the end of the interruption portion IP would be isolated and electrically floating. Thus, in processes such as plasma processing during the manufacturing of the semiconductor memory device 1, there is a risk of arcing in this portion. However, as described above, in the semiconductor memory device 1 of this embodiment, the first conductive layer ECL1 remains electrically continuous on both sides of the interruption portion IP along the x-direction, and the first conductive layer ECL1 can be grounded through other circuit elements; therefore, the generation of arcing can be suppressed.

[0057] Next, refer to Figures 9A to 9C and Figures 10A-10B Explain the variations. Figures 9A to 9C and Figures 10A-10B This is a partial sectional view showing an example of changes in the segmented section.

[0058] (Variation Example 1)

[0059] Reference Figure 9A A break portion IP1 is provided in the first conductive layer ECL1, and a break portion IP2 is provided in the third conductive layer ECL3. In this case, the break portions IP1 and IP2 can have the same top view shape, and the width (length in the x-direction) of one side can be greater than the width of the other side. In addition, both break portions IP1 and IP2 can be formed of the same insulating material as the insulating layer IN. In this case, even if peeling occurs between the first conductive layer ECL1 and the insulating layer BSL below the slit GP2 of the second plate-shaped portion ST2, the break portion IP1 can be used to suppress the propagation of peeling. In addition, when the break portions IP1 and IP2 have the same planar shape, after the third conductive layer ECL3 is formed, not only can an opening as the break portion IP1 be formed in the first conductive layer ECL1 through a photoresist mask (equivalent to...) Figure 7BThe opening OP2 can be formed in the third conductive layer ECL3, and the opening for the break IP2 can be formed in the third conductive layer ECL3. Therefore, the number of steps can be reduced compared to the case where the break IP is formed only in the first conductive layer ECL1.

[0060] (Variation Example 2)

[0061] Reference Figure 9B The first conductive layer ECL1 has a shorter x-direction extension than the third conductive layer ECL3, and its x-direction end is connected to the insulating layer INL. The insulating layer INL can be formed of the same insulating material as the insulating layer IN and the insulating film BSL, such as silicon oxide. Furthermore, a break IP3 is provided in the third conductive layer ECL3, and the second plate-like portion ST2 terminates within the third conductive layer ECL3, further towards its x-direction end. In this case, there is a risk of peeling between the third conductive layer ECL3 and the insulating layer IN, but the peeling process can be suppressed by the break IP3.

[0062] Furthermore, in this variation, the slit GP2 for forming the second plate-shaped portion ST2 can be formed simultaneously with the slit GP1 for forming the first plate-shaped portion ST1. For example, the bottom surface of the slit GP1 can be positioned on the upper surface of the sacrificial film SC by adjusting the etching rate under etching conditions (see reference). Figure 5C Furthermore, the bottom surface of the slit GP2 is located within the third conductive layer ECL3. Additionally, the insulating layer INL can be formed in the following manner: for example, in... Figure 7B In this process, an opening wider than the opening OP1 in the x-direction is set on a hard mask HM. Using this hard mask HM, the first conductive layer ECL1 is removed by etching to form an insulating film TSO. Figure 7C ), and perform back etching on the entire surface.

[0063] (Variation Example 3)

[0064] Figure 9CThe figure illustrates a further variation 3 of variation 2 described above. That is, variation 3 differs from variation 2 in that the second plate-shaped portion ST2 penetrates the third conductive layer ECL3 and terminates within the insulating layer INL; otherwise, they are the same. As described above, the insulating layer IN, the insulating layer INL, and the insulating film BSL are integrally formed using the same insulating material. Therefore, the bottom surface of the slit GP2 used to form the second plate-shaped portion ST2 is less prone to cracking; however, the interface between the third conductive layer ECL3 and the insulating layer IN may peel off. However, as described in this example, a break portion IP3 is provided in the third conductive layer ECL3, thus suppressing the propagation of peeling even if it occurs. Furthermore, the slit GP2 extending into the insulating layer INL can be formed by adjusting the etching rate when it is formed simultaneously with the slit GP1 used for the first plate-shaped portion ST1.

[0065] (Variation Example 4)

[0066] Reference Figure 10A Unlike Variations 2 and 3, in Variation 4, the third conductive layer ECL3 has a shorter extension length in the x-direction, and its x-direction end is separated from the second plate-shaped portion ST2 and connected to the insulating layer INU. The insulating layer INU can be formed of the same insulating material as the insulating layer IN and the second interlayer insulating film IL2, such as silicon oxide. The second plate-shaped portion ST2 penetrates the second interlayer insulating film IL2, the insulating layer INU, and the insulating layer IN, and terminates within the first conductive layer ECL1. The break portion IP is provided in the first conductive layer ECL1. Therefore, it is possible to suppress possible peeling at the interface between the first conductive layer ECL1 and the insulating film BSL. Furthermore, the insulating layer INU can be formed by performing a photolithography step, an etching step, an insulating film deposition step, and a planarization step after forming the third conductive layer ECL3.

[0067] In addition, such as Figure 10B As shown, not only the x-direction end of the third conductive layer ECL3, but also the x-direction end of the first conductive layer ECL1 is separated from the second plate-shaped portion ST. In this case, the second plate-shaped portion ST2 penetrates the second interlayer insulating film IL2, insulating layer INU, insulating layer IN (the second layer), and insulating layer INL, and terminates within the insulating film BSL. In this example, the break portion IP is not formed in either the first conductive layer ECL1 or the third conductive layer ECL3. Here, the slit GP2 (for forming the second plate-shaped portion ST2) is... Figure 7FThe interface between the insulating layer INL and the insulating film BSL appears on the side of the laminate, and there is a possibility that cracks may propagate from this interface. However, the insulating layer INL and the insulating film BSL can be formed using the same insulating material, so they are firmly bonded together, and there is no difference in their coefficients of thermal expansion, thus stress is not easily generated. Therefore, this cracking can be prevented from propagating along the interface between the insulating layer INL and the insulating film BSL towards the laminate SK side.

[0068] Furthermore, the slit GP2 used to form the second plate-shaped portion ST2 can penetrate the insulating film BSL and reach the first interlayer insulating film IL1 of the peripheral circuit portion PER below the insulating film BSL. Therefore, the second plate-shaped portion ST2 can also terminate within the first interlayer insulating film IL1. In other words, the second plate-shaped portion ST2 only needs to connect with the substrate S and the through-hole Vg and wiring ML within the first interlayer insulating film IL1. Figure 2 If the wiring layers are separated, the termination can also occur within either the insulating film BSL or the first interlayer insulating film IL1. That is, these layers can be formed using the same insulating material, so the interface is firmly connected, and there is no difference in the coefficient of thermal expansion, making it less likely to generate interlayer stress. By terminating the second plate-shaped portion ST2 by separating it from the substrate S and wiring layers, which are made of materials different from these layers, the propagation of peeling at the interface can be effectively suppressed.

[0069] Next, refer to Figures 11A to 11C Other variations of the segmented part will be explained. Figures 11A to 11C This is a partial top view showing the segment. That is, the top view shape of the segment in the following variation example is different from the segment IP, etc., described above.

[0070] (Variation Example 5)

[0071] like Figure 11A As shown, the break IP4 in Variation Example 5 is not continuous in the y-direction, but extends intermittently. Even in this case, the break IP4 can suppress possible peeling between the first conductive layer ECL1 and the insulating film BSL, which serves as its base layer.

[0072] (Variation Example 6)

[0073] like Figure 11B As shown, the break portion IP5 in Variation 6 has the same top view shape as the break portion IP4 in Variation 5 and is configured in two columns along the x-direction. Furthermore, the two columns of break portions IP5 are staggered from each other in the y-direction between the columns. Therefore, the break portion IP5 can more effectively suppress possible peeling between the first conductive layer ECL1 and the insulating film BSL, which serves as its substrate layer.

[0074] In addition, such as Figure 11CAs shown, the second plate-like portion ST2 can be arranged along the x-direction and formed into 2 columns, or into 3 or 4 or more columns. Furthermore, Figure 11C The diagram shows segment IP4, but it is also possible to provide two columns of second plate-like portions ST2, and any one of segments IP, IP1-IP3, and IP5. Furthermore, the top view shapes of segments IP2 and IP3 can be the same as those of segment IP4, and segments IP2 and IP3 can be arranged in two columns along the x-direction. In other words, the top view shapes of segments IP, IP1-IP3, and IP5 can extend intermittently like those of segment IP4, rather than being continuous in the y-direction. Alternatively, the two columns of intermittently extending segments IP, IP1-IP3 can be staggered in the y-direction, similar to segment IP5.

[0075] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A semiconductor memory device comprising: The laminate consists of multiple conductive layers and multiple insulating layers stacked alternately layer by layer, and a stepped portion formed by the conductive layers is formed at the end in the first direction. A columnar body extending through the stacked body, and having a memory cell formed at a portion opposite to at least one of the plurality of conductive layers; A conductive component is electrically connected to the column below the laminate and extends along the first direction beyond the stepped portion to the region of the lower side of the laminate. A plate-like portion extends along the lamination direction of the laminate in a region lateral to the laminate and reaches the conductive component, and extends along a second direction intersecting the lamination direction and the first direction; and The dividing portion, disposed within the conductive member further from the stepped portion than the plate-shaped portion, partially divides the conductive member and includes an insulating material; and The conductive component has: Part 1 is electrically connected to the columnar body; and Part 2 extends from Part 1 along the first direction toward the stepped portion side; The second part has: The first layer is electrically connected to the first part; and The third layer, separated by an insulating second layer, is disposed above the first layer and is electrically connected to the first part.

2. The semiconductor memory device of claim 1, wherein the plate-like portion extending along the stacking direction terminates within the first layer. The segment is located in the first layer.

3. The semiconductor memory device of claim 1, wherein the plate-like portion extending along the stacking direction terminates within the third layer. The segment is located in the third layer.

4. The semiconductor memory device according to claim 1, wherein the break portion is disposed on the first layer and the third layer.

5. The semiconductor memory device of claim 1, wherein the first layer has a shorter extension length in the first direction than the third layer has a shorter extension length in the first direction. The plate-shaped portion extending along the lamination direction extends beyond the first layer and reaches the portion of the third layer extending along the first direction. The segment is located in the third layer.

6. The semiconductor memory device according to claim 5, wherein the plate-like portion terminates within an insulating layer disposed below the third layer.

7. The semiconductor memory device of claim 6, wherein the insulating layer disposed below the third layer comprises the same insulating material as the insulating film disposed below the first layer.

8. The semiconductor memory device of claim 1, wherein the extension length of the third layer in the first direction is shorter than the extension length of the first layer in the first direction. The end of the third layer in the first direction is separated from the plate-shaped portion. The segment is located in the first layer.

9. The semiconductor memory device according to claim 1, wherein the break extends intermittently along the second direction.

10. The semiconductor memory device of claim 1, wherein the segment extends intermittently along the second direction and is arranged in two columns along the first direction, the two columns of segments being staggered from each other in the second direction between the columns.

11. The semiconductor memory device according to claim 1, wherein the plate-like portions are arranged along the first direction and in two columns.

12. The semiconductor memory device of claim 1, wherein the plate-like portion is disposed within 5 μm of the end portion of the stacked body in the first direction.

13. The semiconductor memory device of claim 1, wherein the break portion comprises the same insulating material as the insulating film disposed beneath the conductive member.

14. The semiconductor memory device of claim 13, further comprising a wiring layer that separates the insulating film disposed below the conductive component.

15. A semiconductor memory device comprising: The first insulating portion, which serves as the base layer, includes a wiring layer; A laminate comprising a plurality of conductive layers and a plurality of insulating layers stacked alternately layer by layer, disposed above the first insulating portion, and having a stepped portion formed by the conductive layers at the end in the first direction; A columnar body extending through the stacked body, and having a memory cell formed at a portion opposite to at least one of the plurality of conductive layers; The plate-shaped portion extends along the lamination direction of the laminate and a second direction intersecting the lamination direction and the first direction in the region on the side of the laminate in the first direction, and reaches into the first insulating portion in a manner separate from the substrate disposed below the first insulating portion and the wiring layer. and A conductive component is electrically connected to the columnar body below the laminate and extends along the first direction in a manner separate from the plate-like portion; and The conductive component has: Part 1 is electrically connected to the columnar body; and Part 2 extends from Part 1 along the first direction toward the stepped portion side; The second part has: The first layer is electrically connected to the first part; and The third layer, separated by an insulating second layer, is disposed above the first layer and is electrically connected to the first part.

16. The semiconductor memory device of claim 15, wherein the plate-like portion extends through a lateral insulating layer extending from an end of the first layer in the first direction toward the side of the stacked body in the first direction, and terminates within the first insulating portion.

17. The semiconductor memory device of claim 16, wherein the lateral insulating layer and the upper portion of the first insulator on which the conductive member is disposed comprise the same insulating material.

18. The semiconductor memory device of claim 15, wherein the plate-like portion is disposed within 5 μm of an end portion of the stack along the first direction.

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