Transistor, gate structure in transistor and forming method of gate structure

Abstract

A transistor, a gate structure in a transistor, and a method of forming a gate structure, in some embodiments, a method of forming a gate structure includes forming a plurality of nanostructures over a substrate, etching the nanostructures to form first recesses, forming source / drain regions in the first recesses, removing first ones of the nanostructures, leaving second ones of the nanostructures, depositing a gate dielectric layer over and around the second ones of the nanostructures, performing an aluminum treatment on the gate dielectric layer, depositing a first conductive material over and around the gate dielectric layer, performing a fluorine treatment on the first conductive material, and depositing a second conductive material over and around the first conductive material.

Description

Technical Field

[0001] This disclosure relates to a transistor, a gate structure in the transistor, and a method for forming the gate structure. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit components and elements on the substrate.

[0003] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. However, as the minimum feature size is reduced, additional problems arise that need to be addressed. Summary of the Invention

[0004] According to some embodiments of this disclosure, a method of forming a gate structure includes: forming a plurality of nanostructures over a substrate; etching the nanostructures to form a first groove; forming source / drain regions in the first groove; removing the first nanostructures from the nanostructures, thereby leaving a second nanostructure from the nanostructures; depositing a gate dielectric layer over and around the second nanostructures; performing an aluminum treatment on the gate dielectric layer; depositing a first conductive material over and around the gate dielectric layer; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material.

[0005] According to some embodiments disclosed herein, a gate structure includes: a first nanostructure extending between a source region and a drain region; a second nanostructure above the first nanostructure; a gate dielectric layer above and around the first nanostructure and the second nanostructure; an aluminum residue above the gate dielectric layer; a work function metal (WFM) layer above the gate dielectric layer and the aluminum residue, the WFM layer comprising fluorine, a first portion of the WFM layer disposed around the first nanostructure, and a second portion of the WFM layer disposed around the second nanostructure; and a conductive layer disposed above the WFM layer, a first portion of the conductive layer disposed around the first nanostructure, and a second portion of the conductive layer disposed around the second nanostructure.

[0006] According to some embodiments of this disclosure, a transistor includes: a first dielectric material disposed over a first nanostructure; a first metal residue disposed over the first dielectric material; a first conductive material disposed over the first dielectric material; a second conductive material disposed over the first conductive material; a third conductive material disposed over the second conductive material, the third conductive material having the same composition as the first conductive material; a second metal residue disposed over the third conductive material, the second metal residue having the same composition as the first metal residue; a second dielectric material disposed over the second metal residue, the second dielectric material having the same composition as the first dielectric material; and a second nanostructure disposed over the second dielectric material. Attached Figure Description

[0007] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the following detailed description. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0008] Figure 1 The illustration shows an example of a nanostructure field-effect transistor (nano-FET) in a three-dimensional view according to some embodiments;

[0009] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6A , Figure 6B , Figure 7A , Figure 7B , Figure 8A , Figure 8B , Figure 9A , Figure 9B , Figure 10A , Figure 10B , Figure 11A , Figure 11B , Figure 11C , Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 13A , Figure 13B , Figure 13C , Figure 14A , Figure 14B , Figure 15A , Figure 15B , Figure 16A , Figure 16B , Figure 17A , Figure 17B , Figure 18A , Figure 18B , Figure 19A , Figure 19B , Figure 20A , Figure 20B , Figure 21A , Figure 21B , Figure 22A , Figure 22B , Figure 23A , Figure 23B , Figure 23C , Figure 23D , Figure 24A , Figure 24B , Figure 25A , Figure 25B , Figure 25C , Figure 26A , Figure 26B , Figure 26C , Figure 27A , Figure 27B and Figure 27C A cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments;

[0010] Figure 28A , Figure 28B and Figure 28C A cross-sectional view of a nanoFET according to some embodiments;

[0011] Figure 29A , Figure 29B , Figure 29C , Figure 29D and Figure 29E This is a cross-sectional view of a nanoFET according to some embodiments.

[0012] [Symbol Explanation]

[0013] 20: Divider

[0014] 50:Substrate

[0015] 50I: area

[0016] 50N: N-type region

[0017] 50P: P-type area

[0018] 51: First semiconductor layer

[0019] 51A: First semiconductor layer

[0020] 51B: First semiconductor layer

[0021] 51C: First semiconductor layer

[0022] 52: First Nanostructure

[0023] 52A: First Nanostructure

[0024] 52B: First Nanostructure

[0025] 52C: First Nanostructure

[0026] 53: Second semiconductor layer

[0027] 53A: Second semiconductor layer

[0028] 53B: Second semiconductor layer

[0029] 53C: Second semiconductor layer

[0030] 54: Second Nanostructure

[0031] 54A: Second Nanostructure

[0032] 54B: Second Nanostructure

[0033] 54C: Second Nanostructure

[0034] 55: Nanostructures

[0035] 64: Multi-layer stacking

[0036] 66: Fins

[0037] 68: Shallow Trench Isolation Zone (STI)

[0038] 70: Dummy Dielectric Layer

[0039] 71: Dummy gate dielectric layer

[0040] 72: Dummy Gate Layer / Dummy Gate

[0041] 74: Masking layer

[0042] 76: Dummy gate

[0043] 78: Mask

[0044] 80: First spacer layer

[0045] 81: First spacer

[0046] 82: Second spacer layer

[0047] 83: Second spacer

[0048] 86: First Groove

[0049] 88: Side wall groove

[0050] 90: First internal spacer

[0051] 92: Epitaxial Source / Drain Region

[0052] 92A: First semiconductor material layer

[0053] 92B: Second semiconductor material layer

[0054] 92C: Third semiconductor material layer

[0055] 94: Contact Etching Termination Layer (CESL)

[0056] 96: Interlayer Dielectric (ILD)

[0057] 98: Second groove

[0058] 100: Gate dielectric layer

[0059] 101: First gate dielectric layer / interface layer

[0060] 102: Gate electrode

[0061] 103: Second gate dielectric layer

[0062] 104: Gate Mask

[0063] 105: First conductive material

[0064] 106: Interlayer Dielectric (ILD)

[0065] 107: Second conductive material

[0066] 107A: Part 1 / Conductive Materials

[0067] 107B: Part 2 / Conductive Materials

[0068] 107S: Interface

[0069] 108: Third Groove

[0070] 109: Aluminum Treatment

[0071] 110: Silicide region

[0072] 111: First residue of aluminum

[0073] 112: Contact

[0074] 113: Fluorine Treatment

[0075] 114: Contact

[0076] 115: Second residue of metal

[0077] 117: Adhesive layer

[0078] 119: Underlying filler metal

[0079] 121: Conductive materials

[0080] 123: Barrier Layer

[0081] 125: Filler metal

[0082] 127: Gate electrode

[0083] 130: Opening

[0084] A-A': Cross section

[0085] B-B': Cross section

[0086] C-C': Cross section Detailed Implementation

[0087] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0088] Additionally, spatial relative terms, such as “below,” “under,” “lower,” “above,” “upper,” and similar terms, may be used herein for ease of description to describe the relationship between one element or feature as illustrated in the figures and another element or feature(s). Spatial relative terms are intended to cover different orientations of the device in its use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0089] Various embodiments provide gate stacks having an aluminum-treated gate dielectric layer (e.g., a high-k gate dielectric layer) and a fluorine-treated work function metal (WFM) layer. For example, the aluminum treatment may include performing an aluminum immersion on the gate dielectric layer. After depositing the WFM layer, the fluorine treatment may include performing a fluorine immersion on the WFM layer, which may also allow fluorine to diffuse into the underlying gate dielectric layer (e.g., a high-k gate dielectric layer). Without aluminum treatment, the fluorine in the WFM layer will tend to ionize from the WFM layer before the formation of subsequent layers. However, the aluminum deposited during the aluminum treatment absorbs the fluorine from the fluorine treatment to improve the retention of fluorine in the WFM layer. Furthermore, this absorption improves some of the fluorine's movement or diffusion into the gate dielectric layer. Therefore, the flat-band voltage (V0) of the resulting transistor... FB The band edge of the metal towards the WFM layer can be increased, which can reduce the threshold voltage of the resulting transistor and improve device performance.

[0090] Figure 1 The illustration shows an example of a nanoFET (e.g., a nanowire FET, a nanosheet FET, a nanostructure FET, or the like) in a three-dimensional view according to some embodiments. The nanoFET includes a nanostructure 55 (e.g., a nanosheet, a nanowire, or the like) above fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 55 acts as a channel region of the nanoFET. The nanostructure 55 may include p-type nanostructures, n-type nanostructures, or combinations thereof. Isolation regions 68 are disposed between adjacent fins 66, which may protrude above and from between adjacent isolation regions 68. Although isolation regions 68 are described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may refer solely to a semiconductor substrate or to a combination of a semiconductor substrate and an isolation region. Additionally, although the bottom portion of the fins 66 is illustrated as a separate continuous material from the substrate 50, the fins 66 and / or the bottom portion of the substrate 50 may comprise a single material or multiple materials. In this case, fin 66 refers to the portion extending between adjacent isolation regions 68.

[0091] The gate dielectric layer 100 is above the top surface of the fin 66 and extends along the top, sidewalls, and bottom surface of the nanostructure 55. The gate electrode 102 is above the gate dielectric layer 100. Epitaxial source / drain regions 92 are disposed on the fin 66 on the opposite sides of the gate dielectric layer 100 and the gate electrode 102.

[0092] Figure 1Further illustrations show reference cross sections used in subsequent figures. Cross section A-A' is along the longitudinal axis of the gate electrode 102 and in the direction of current flow, for example, perpendicular to the epitaxial source / drain region 92 of the nanoFET. Cross section B-B' is perpendicular to cross section A-A' and parallel to the longitudinal axis of the fin 66 of the nanoFET, and in the direction of current flow, for example, between the epitaxial source / drain regions 92 of the nanoFET. Cross section C-C' is parallel to cross section A-A' and extends through the epitaxial source / drain region of the nanoFET. For clarity, these reference cross sections are referred to in subsequent figures.

[0093] Some embodiments discussed herein are described in the context of nanoFETs formed using a post-gate process. In other embodiments, a pre-gate process may be used. Furthermore, some embodiments are contemplated for use in planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0094] Figures 2 to 29C This is a cross-sectional view of an intermediate stage in the fabrication of a nanoFET according to some embodiments. Figures 2 to 5 , Figure 6A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A , Figure 20A , Figure 21A , Figure 22A , Figure 23A , Figure 24A , Figure 25A , Figure 26A , Figure 27A , Figure 28A and Figure 29A The illustration is in Figure 1 The reference cross section A-A' is shown in the diagram. Figure 6B , Figure 7B , Figure 8B , Figure 9B , Figure 10B , Figure 11B , Figure 11C , Figure 12B , Figure 12D , Figure 13B , Figure 14B , Figure 15B , Figure 16B , Figure 17B , Figure 18B , Figure 19B , Figure 20B , Figure 21B , Figure 22B , Figure 23B , Figure 24B , Figure 25B , Figure 26B , Figure 27B , Figure 28B and Figure 29B The illustration is in Figure 1 The reference cross section B-B' is shown in the diagram. Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13C , Figure 25C , Figure 26C , Figure 27C , Figure 28C and Figure 29E The illustration is in Figure 1 The reference cross section C-C' is shown in the diagram.

[0095] exist Figure 2 In this embodiment, a substrate 50 is disposed. The substrate 50 may be a semiconductor substrate, such as a bulk substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., using p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Specifically, the SOI substrate is a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include: silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium phosphide, and / or gallium arsenide phosphide; or combinations thereof.

[0096] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor (e.g., an n-type nanoFET); and the p-type region 50P can be used to form a p-type device, such as a PMOS transistor (e.g., a p-type nanoFET). The n-type region 50N can be physically separated from the p-type region 50P (as illustrated by separator 20), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are illustrated, any number of n-type regions 50N and p-type regions 50P can be provided. In some embodiments, one or more well and / or anti-punch-through (APT) layers can be formed in the substrate 50 via one or more suitable placement steps.

[0097] In addition, Figure 2 In this embodiment, a multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 51A to 51C (collectively referred to as first semiconductor layers 51) and second semiconductor layers 53A to 53C (collectively referred to as second semiconductor layers 53). For illustrative purposes and as discussed in more detail below, the second semiconductor layers 53 are removed, and the first semiconductor layers 51 are patterned to form a channel region for a nanoFET in the p-type region 50P. Furthermore, the first semiconductor layers 51 are removed, and the second semiconductor layers 53 are patterned to form a channel region for a nanoFET in the n-type region 50N. However, in some embodiments, the first semiconductor layers 51 may be removed, and the second semiconductor layers 53 may be patterned to form a channel region for a nanoFET in the n-type region 50N, and the second semiconductor layers 53 may be removed, and the first semiconductor layers 51 may be patterned to form a channel region for a nanoFET in the p-type region 50P.

[0098] In yet another embodiment, the first semiconductor layer 51 may be removed, and the second semiconductor layer 53 may be patterned to form channel regions of a nanoFET in both the n-type region 50N and the p-type region 50P. In other embodiments, the second semiconductor layer 53 may be removed, and the first semiconductor layer 51 may be patterned to form channel regions of a nanoFET in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or the like) and be formed simultaneously. For example, Figure 27A , Figure 27B and Figure 28C The diagram illustrates a structure resulting from an embodiment of this type, where the channel regions of both the p-type region 50P and the n-type region 50N contain silicon.

[0099] For illustrative purposes, the multilayer stack 64 is illustrated as three layers including each of a first semiconductor layer 51 and a second semiconductor layer 53. In some embodiments, the multilayer stack 64 may include any number of first semiconductor layers 51 and second semiconductor layers 53. Each of the layers of the multilayer stack 64 may be epitaxially grown using processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. In various embodiments, the first semiconductor layer 51 may be formed of a first semiconductor material suitable for a p-type nanoFET, such as silicon germanium or the like, and the second semiconductor layer 53 may be formed of a second semiconductor material suitable for an n-type nanoFET, such as silicon, silicon carbide, or the like. For illustrative purposes, the multilayer stack 64 is illustrated as having a bottom semiconductor layer suitable for a p-type nanoFET. In some embodiments, the multilayer stack 64 may be formed such that the bottom layer is a semiconductor layer suitable for an n-type nanoFET.

[0100] The first and second semiconductor materials can be materials with high etch selectivity relative to each other. Therefore, the first semiconductor layer 51 of the first semiconductor material can be removed without significantly removing the second semiconductor layer 53 of the second semiconductor material in the n-type region 50N, thereby allowing the second semiconductor layer 53 to be patterned to form the channel region of the n-type nanoFET. Similarly, the second semiconductor layer 53 of the second semiconductor material can be removed without significantly removing the first semiconductor layer 51 of the first semiconductor material in the p-type region 50P, thereby allowing the first semiconductor layer 51 to be patterned to form the channel region of the p-type nanoFET. In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously and have the same material composition, such as silicon, silicon germanium, or the like. For example, Figure 28A , Figure 28B and Figure 28C The diagram illustrates a structure resulting from an embodiment of this type, where the channel regions of both the p-type region 50P and the n-type region 50N contain silicon.

[0101] See now Figure 3According to some embodiments, fins 66 are formed in substrate 50, and nanostructures 55 are formed in multilayer stack 64. In some embodiments, nanostructures 55 and fins 66 may be formed in multilayer stack 64 and substrate 50 respectively by etching trenches in multilayer stack 64 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar or combinations thereof. Etching may be anisotropic. The nanostructures 55 formed by etching multilayer stack 64 may further define first nanostructures 52A to 52C (collectively referred to as first nanostructures 52) from first semiconductor layer 51, and second nanostructures 54A to 54C (collectively referred to as second nanostructures 54) from second semiconductor layer 53. First nanostructures 52 and second nanostructures 54 may be further collectively referred to as nanostructure 55.

[0102] The fins 66 and nanostructures 55 can be patterned using any suitable method. For example, the fins 66 and nanostructures 55 can be patterned using one or more optical lithography processes, including dual patterning or multiple patterning processes. Specifically, dual patterning or multiple patterning processes combine optical lithography and self-alignment processes to allow patterns to be generated that have, for example, smaller spacing compared to patterns otherwise obtainable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 66.

[0103] Figure 3 For illustrative purposes, the fins 66 in the n-type region 50N and p-type region 50P are shown to have substantially equal widths. In some embodiments, the width of the fins 66 in the n-type region 50N may be larger or smaller than that of the fins 66 in the p-type region 50P. Additionally, although each of the fins 66 and nanostructures 55 is illustrated to always have a consistent width, in other embodiments, the fins 66 and / or nanostructures 55 may have tapered sidewalls, such that the width of each of the fins 66 and / or nanostructures 55 continuously increases in the direction toward the substrate 50. In such embodiments, each of the nanostructures 55 may have a different width and be trapezoidal in shape.

[0104] exist Figure 4In this embodiment, a shallow trench isolation (STI) region 68 is formed adjacent to the fin 66. The STI region 68 can be formed by depositing an insulating material over the substrate 50, fin 66, and nanostructure 55, and between adjacent fins 66. The insulating material can be an oxide, nitride, or combination thereof, such as silicon oxide, and can be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or combinations thereof. Other insulating materials formed by any acceptable process can be used. In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In this embodiment, the insulating material is formed such that excess insulating material covers the nanostructure 55. Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of the substrate 50, fin 66, and nanostructure 55. Subsequently, filling materials such as those discussed above can be formed on top of the lining.

[0105] The removal process is then applied to the insulating material to remove excess insulating material over the nanostructure 55. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etching back, a combination thereof, or the like, may be used. The planarization process exposes the nanostructure 55 such that the top surfaces of the nanostructure 55 and the insulating material are flush after the planarization process is completed.

[0106] The insulating material is then recessed to form STI regions 68. The insulating material is recessed such that the upper portions of the fins 66 in regions 50N and 50P protrude from between adjacent STI regions 68. Additionally, the top surface of the STI region 68 may have a flat surface, a raised surface, a recessed surface (such as a dish shape), or a combination thereof, as illustrated. The top surface of the STI region 68 may be formed as flat, raised, and / or recessed by appropriate etching. The STI region 68 may use acceptable etching processes, such as selective process recessing for the insulating material (e.g., etching the insulating material at a faster rate compared to the materials of the fins 66 and nanostructures 55). For example, oxide removal using, for instance, diluted hydrofluoric (dHF) acid may be used.

[0107] The above text is about Figures 2 to 4The described process is only one example of how the fins 66 and nanostructures 55 can be formed. In some embodiments, the fins 66 and / or nanostructures 55 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed above the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or nanostructures 55. The epitaxial structures can comprise alternating semiconductor materials discussed above, such as a first semiconductor material and a second semiconductor material. In some embodiments where the epitaxial structure is epitaxially grown, the epitaxial growth material can be doped in situ during growth, which can eliminate previous and / or subsequent implantations, although in-situ and implantation doping can be used together.

[0108] Additionally, for illustrative purposes only, the first semiconductor layer 51 (and the resulting first nanostructure 52) and the second semiconductor layer 53 (and the resulting second nanostructure 54) are illustrated and discussed herein as containing the same material in the p-type region 50P and the n-type region 50N. Therefore, in some embodiments, one or both of the first semiconductor layer 51 and the second semiconductor layer 53 may be made of different materials or formed in different orders in the p-type region 50P and the n-type region 50N.

[0109] In addition, Figure 4 In this embodiment, appropriate wells (not shown separately) may be formed in fins 66, nanostructures 55, and / or STI regions 68. In embodiments with different well types, different implantation steps for n-type regions 50N and p-type regions 50P may be achieved using photoresist or other masks (not shown separately). For example, photoresist may be formed over fins 66 and STI regions 68 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist may be formed using spin-coating techniques and may be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type regions 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into n-type regions 50N. n-type impurities may be implanted in the regions up to approximately 10 13 atoms / cm 3 To about 10 14 atoms / cm 3 The concentration of phosphorus, arsenic, antimony, or similar substances is within a certain range. After application, the photoresist is removed, for example, by an acceptable ashing process.

[0110] Before or after implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 66, nanostructures 55, and STI regions 68 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin coating techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist acts as a mask to substantially prevent p-type impurities from implanting into the p-type region 50P. P-type impurities can be implanted in the region up to approximately 10 13 atoms / cm 3 To about 10 14 atoms / cm 3 The concentration of boron, boron fluoride, indium, or the like is within a certain range. After application, the photoresist can be removed, for example, by an acceptable ashing process.

[0111] Following the implantation of the n-type region 50N and the p-type region 50P, annealing may be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins may be doped in situ during growth, which may eliminate implantation, although in-situ and implantation-doping may be used together.

[0112] exist Figure 5In this configuration, a dummy dielectric layer 70 is formed on the fin 66 and / or nanostructure 55. The dummy dielectric layer 70 may be, for example, silicon oxide, silicon nitride, combinations thereof, or similar materials, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a masking layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be deposited over the dummy dielectric layer 70 and then planarized, for example, by CMP. The masking layer 74 may be deposited over the dummy gate layer 72. The dummy gate layer 72 may be a conductive or non-conductive material and may be selected from the group consisting of: amorphous silicon, polycrystalline silicon, polycrystalline silicon-germanium, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), CVD, sputtering deposition, or other techniques for depositing the selected material. The dummy gate layer 72 can be made of other materials with high etch selectivity for etching the self-isolated region. The mask layer 74 can include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 72 and a single mask layer 74 are formed over the n-type region 50N and the p-type region 50P. Note that, for illustrative purposes only, the dummy dielectric layer 70 is shown covering only the fin 66 and the nanostructure 55. In some embodiments, the dummy dielectric layer 70 can be deposited such that the dummy dielectric layer 70 covers the STI region 68, such that the dummy dielectric layer 70 extends between the dummy gate layer 72 and the STI region 68.

[0113] Figures 6A to 15B The illustration shows various additional steps in the apparatus used to manufacture the embodiment. Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 12C , Figure 13A , Figure 13C , Figure 14A and Figure 15A The illustration shows the features in area 50N or area 50P. Figure 6A and Figure 6B In the middle, mask layer 74 (see Figure 5The mask 78 can be patterned using acceptable photolithography and etching techniques. The pattern of the mask 78 can then be transferred to the dummy gate layer 72 and the dummy dielectric layer 70 to form the dummy gate 76 and the dummy gate dielectric layer 71, respectively. The dummy gate 76 covers the respective channel regions of the fin 66. The pattern of the mask 78 can be used to physically separate each of the dummy gates 76 from its adjacent dummy gate 76. The dummy gate 76 may also have a longitudinal direction that is generally perpendicular to the longitudinal direction of the respective fin 66.

[0114] exist Figure 7A and Figure 7B In the figure, the first spacer layer 80 and the second spacer layer 82 are respectively formed on the part shown in the figure. Figure 6A and Figure 6B Above the structure in the middle. The first spacer layer 80 and the second spacer layer 82 will then be patterned to act as spacers for forming self-aligned source / drain regions. Figure 7A and Figure 7B In this configuration, a first spacer layer 80 is formed on the top surface of the STI region 68; the top surface and sidewalls of the fin 66, nanostructure 55, and mask 78; and the sidewalls of the dummy gate 76 and the dummy gate dielectric layer 71. A second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 can be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like using techniques such as thermal oxidation, or deposited by CVD, ALD, or the like. The second spacer layer 82 can be formed from a material with a different etch rate than the material of the first spacer layer 80, such as silicon oxide, silicon nitride, oxide oxynitride, or the like, and can be deposited by CVD, ALD, or the like.

[0115] After the formation of the first spacer layer 80 and before the formation of the second spacer layer 82, the implantation of lightly doped source / drain (LDD) regions (not illustrated separately) can be performed. In embodiments with different device types, similar to the above... Figure 4 As described in the previous section, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and an appropriate type of impurity (e.g., p-type) may be implanted into the exposed fins 66 and nanostructures 55 in the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and an appropriate type of impurity (e.g., n-type) may be implanted into the exposed fins 66 and nanostructures 55 in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed above, and the p-type impurity can be any of the p-type impurities discussed above. The lightly doped source / drain regions may have a depth of approximately 1 × 10⁻⁶. 15 atoms / cm 3 To approximately 1×1019 atoms / cm 3 The concentration of impurities within a certain range. Annealing can be used to repair implantation damage and reactivate implanted impurities.

[0116] exist Figure 8A and Figure 8B In this process, the first spacer layer 80 and the second spacer layer 82 are etched to form the first spacer 81 and the second spacer 83. As will be discussed in more detail below, during subsequent processing, the first spacer 81 and the second spacer 83 are used to self-align the subsequently formed source and drain regions and protect the sidewalls of the fin 66 and / or nanostructure 55. The first spacer layer 80 and the second spacer layer 82 can be etched using suitable etching processes, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), combinations of each, or similar. In some embodiments, the material of the second spacer layer 82 has a different etching rate than the material of the first spacer layer 80, such that the first spacer layer 80 can act as an etch stop layer when patterning the second spacer layer 82, and that the second spacer layer 82 can act as a mask when patterning the first spacer layer 80. For example, the second spacer layer 82 can be etched using an anisotropic etching process, wherein the first spacer layer 80 acts as an etch stop layer, and the remaining portion of the second spacer layer 82 forms the second spacer 83, such as... Figure 8A As illustrated in the diagram. Subsequently, the second spacer 83 acts as a mask while the exposed portion of the first spacer layer 80 is etched, thereby forming the first spacer 81, as shown in the diagram. Figure 8A As shown in the diagram.

[0117] like Figure 8A As illustrated, the first spacer 81 and the second spacer 83 are disposed on the sidewalls of the fin 66 and / or the nanostructure 55. Figure 8B As illustrated, in some embodiments, the second spacer layer 82 may be removed over the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric layer 71, and the first spacer 81 is disposed on the sidewalls of the mask 78, dummy gate 76, and dummy dielectric layer 60. In other embodiments, a portion of the second spacer layer 82 may be retained over the first spacer layer 80 adjacent to the mask 78, dummy gate 76, and dummy gate dielectric layer 71.

[0118] Please note that the above disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different sequences of steps can be used (e.g., the first spacer 81 can be patterned before the deposition of the second spacer 82), additional spacers can be formed and removed, and / or the like. Furthermore, n-type and p-type devices can be formed using different structures and steps.

[0119] exist Figure 9A and Figure 9B In some embodiments, a first groove 86 is formed in the fin 66, the nanostructure 55, and the substrate 50. Epitaxial source / drain regions are subsequently formed in the first groove 86. The first groove 86 may extend through the first nanostructure 52 and the second nanostructure 54 and extend into the substrate 50. Figure 9A As illustrated, the top surface of the STI region 68 may be flush with the bottom surface of the first groove 86. In various embodiments, the fin 66 may be etched such that the bottom surface of the first groove 86 is positioned below the top surface of the STI region 68; or similarly. The first groove 86 may be formed by etching the fin 66, nanostructure 55, and substrate 50 using an anisotropic etching process, such as RIE, NBE, or similar. The first spacer 81, the second spacer 83, and the mask 78 mask portions of the fin 66, nanostructure 55, and substrate 50 during the etching process used to form the first groove 86. A single etching process or multiple etching processes may be used to etch each layer of the nanostructure 55 and / or the fin 66. A timed etching process may be used to stop etching the first groove 86 after it has reached a desired depth.

[0120] exist Figure 10A and Figure 10B In this process, portions of the sidewalls of several layers of a multilayer stack 64 (e.g., a first nanostructure 52) formed of a first semiconductor material, exposed through a first groove 86, are etched to form sidewall grooves 88 in an n-type region 50N, and portions of the sidewalls of several layers of a multilayer stack 64 (e.g., a second nanostructure 54) formed of a second semiconductor material, exposed through the first groove 86, are etched to form sidewall grooves 88 in a p-type region 50P. Although the sidewalls of the first nanostructure 52 and the second nanostructure 54 in the sidewall grooves 88 are... Figure 10BThe diagram shows a straight sidewall, but the sidewalls can be recessed or raised. The sidewalls can be etched using isotropic etching processes, such as wet etching or similar methods. The p-type region 50P can be protected with a mask (not shown), and an etchant selective for the first semiconductor material is used to etch the first nanostructure 52, such that the second nanostructure 54 and the substrate 50 remain relatively unetched compared to the first nanostructure 52 in the n-type region 50N. Similarly, the n-type region 50N can be protected with a mask (not shown), and an etchant selective for the second semiconductor material is used to etch the second nanostructure 54, such that the first nanostructure 52 and the substrate 50 remain relatively unetched compared to the second nanostructure 54 in the p-type region 50P. In embodiments where the first nanostructure 52 comprises, for example, SiGe and the second nanostructure 54 comprises, for example, Si or SiC, a dry etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like can be used to etch the sidewalls of the first nanostructure 52 in the n-type region 50N, and a dry etching process using hydrogen fluoride, another fluorine gas, or the like can be used to etch the sidewalls of the second nanostructure 54 in the p-type region 50P.

[0121] exist Figures 11A to 11C In the middle, a first internal spacer 90 is formed in a sidewall groove 88. The first internal spacer 90 can be formed by depositing an internal spacer layer (not shown separately) on the sidewall groove 88. Figure 10A and Figure 10B The structure is formed above the gate structure. The first internal spacer 90 serves as an isolation feature between the subsequently formed source / drain regions and the gate structure. As will be discussed in more detail below, the source / drain regions will be formed in the first recess 86, and the first nanostructure 52 in the n-type region 50N and the second nanostructure 54 in the p-type region 50P will be replaced by the corresponding gate structures.

[0122] The internal spacer layer can be deposited using conformal deposition processes such as CVD, ALD, or similar methods. The internal spacer layer may comprise materials such as silicon nitride or silicon oxynitride, although any suitable material with a low dielectric constant (low-k) having a k value less than about 3.5 can be used. The internal spacer layer can then be anisotropically etched to form a first internal spacer 90. Although the outer sidewalls of the first internal spacer 90 are illustrated to be flush with the sidewalls of the second nanostructure 54 in the n-type region 50N and the sidewalls of the first nanostructure 52 in the p-type region 50P, the outer sidewalls of the first internal spacer 90 may extend beyond or be recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0123] Furthermore, although the outer sidewall of the first internal spacer 90 is in Figure 11B The diagram shows a straight line, but the outer sidewall of the first internal spacer 90 can be recessed or convex. As an example, Figure 11C The following embodiment is illustrated: the sidewalls of the first nanostructure 52 are recessed, the outer sidewalls of the first internal spacer 90 are recessed, and the first internal spacer is recessed from the sidewall of the second nanostructure 54 in the n-type region 50N. Another embodiment is illustrated: the sidewalls of the second nanostructure 54 are recessed, the outer sidewalls of the first internal spacer 90 are recessed, and the first internal spacer is recessed from the sidewall of the first nanostructure 52 in the p-type region 50P. The internal spacer layer can be etched using anisotropic etching processes, such as RIE, NBE, or similar methods. The first internal spacer 90 can be prevented from being affected by subsequent etching processes, such as etching processes used to form the gate structure (as described below regarding...). Figures 12A to 12C The damage to the epitaxial source / drain region (92) discussed.

[0124] exist Figures 12A to 12C In this process, an epitaxial source / drain region 92 is formed in the first groove 86. In some embodiments, stress can be applied to the source / drain region 92 to the second nanostructure 54 in the n-type region 50N and the first nanostructure 52 in the p-type region 50P, thereby improving performance. Figure 12B As illustrated, epitaxial source / drain regions 92 are formed in a first recess 86 such that each dummy gate 76 is disposed between adjacent pairs of epitaxial source / drain regions 92. In some embodiments, a first spacer 81 is used to separate the epitaxial source / drain regions 92 from the dummy gate 72, and a first internal spacer 90 is used to separate the epitaxial source / drain regions 92 from the nanostructure 55 by an appropriate lateral distance, such that the epitaxial source / drain regions 92 are not short-circuited to the gate subsequently formed in the resulting nanoFET.

[0125] The epitaxial source / drain region 92 (e.g., an NMOS region) in the n-type region 50N can be formed by shielding the p-type region 50P (e.g., a PMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the n-type region 50N. The epitaxial source / drain region 92 can comprise any acceptable material suitable for an n-type nanoFET. For example, if the second nanostructure 54 is silicon, the epitaxial source / drain region 92 can comprise a material to which tensile stress is applied to the second nanostructure 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain region 92 may have a surface raised from the respective upper surface of the nanostructure 55 and may have facets.

[0126] The epitaxial source / drain region 92 (e.g., a PMOS region) in the p-type region 50P can be formed by shielding the n-type region 50N (e.g., an NMOS region). The epitaxial source / drain region 92 is then epitaxially grown in a first recess 86 in the p-type region 50P. The epitaxial source / drain region 92 can comprise any acceptable material suitable for a p-type nanoFET. For example, if the first nanostructure 52 is silicon-germanium, the epitaxial source / drain region 92 can comprise a material to which compressive stress is applied to the first nanostructure 52, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The epitaxial source / drain region 92 can also have surfaces raised from individual surfaces of the multilayer stack 64 and can have facets.

[0127] Similar to the previously discussed process of forming lightly doped source / drain regions followed by annealing, the epitaxial source / drain regions 92, the first nanostructure 52, the second nanostructure 54, and / or the substrate 50 can be implanted with dopants to form the source / drain regions. The source / drain regions can have a density of approximately 1 × 10⁻⁶. 19 atoms / cm 3 With approximately 1×10 21 atoms / cm 3 The impurity concentrations between these parameters. The n-type and / or p-type impurities in the source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be in-situ doped during growth.

[0128] As a result of the epitaxial process used to form the epitaxial source / drain regions 92 in the n-type region 50N and the p-type region 50P, the upper surface of the epitaxial source / drain regions 92 has facets that extend laterally outward beyond the sidewalls of the nanostructure 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same NSFET to merge, such as by... Figure 12A As illustrated. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated after the epitaxial process is completed, such as through... Figure 12C As shown in the illustration. Figure 12A and Figure 12C In one embodiment, the first spacer 81 may be formed to the top surface of the STI region 68, thereby blocking epitaxial growth. In some other embodiments, the first spacer 81 may cover several portions of the sidewalls of the nanostructure 55, thereby further blocking epitaxial growth. In some other embodiments, the spacer etching used to form the first spacer 81 may be adjusted to remove spacer material to allow the epitaxial growth region to extend to the surface of the STI region 68.

[0129] The epitaxial source / drain region 92 may comprise one or more semiconductor material layers. For example, the epitaxial source / drain region 92 may comprise a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used in the epitaxial source / drain region 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed of different semiconductor materials and may be doped to different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a dopant concentration lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C. In an embodiment where the epitaxial source / drain region 92 comprises three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0130] Figure 12D The following embodiment is illustrated: the sidewalls of the first nanostructure 52 in the n-type region 50N and the sidewalls of the second nanostructure 54 in the p-type region 50P are recessed; the outer sidewall of the first internal spacer 90 is recessed; and the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54 and the first nanostructure 52, respectively. Figure 12D As illustrated, the epitaxial source / drain region 92 can be formed in contact with the first internal spacer 90 and can extend across the sidewalls of the second nanostructure 54 in the n-type region 50N and the sidewalls of the first nanostructure 52 in the p-type region 50P. Alternatively, in embodiments where the first internal spacer 90 is recessed from the sidewalls of the second nanostructure 54 and / or the first nanostructure 52, the epitaxial source / drain region 92 can be formed between the second nanostructure 54 and / or the first nanostructure 52, respectively.

[0131] exist Figures 13A to 13C In the diagram, the first interlayer dielectric (ILD) 96 is deposited on the substrate. Figure 6A , Figure 12B and Figure 12A Above the structure in the middle ( Figures 7A to 12D The manufacturing process remains unchanged. Figure 6A(Cross-section shown in the figure). The first ILD 96 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain region 92, the mask 78, and the first spacer 81. The CESL 94 may comprise a dielectric material having an etch rate different from that of the material covering the first ILD 96, such as silicon nitride, silicon oxide, silicon oxynitride, or the like.

[0132] exist Figures 14A to 14B In this process, a planarization process, such as CMP, can be performed to align the top surface of the first ILD 96 with the top surface of the dummy gate 76 or the mask 78. The planarization process may also remove the mask 78 on the dummy gate 76 and several portions of the first spacer 81 along the sidewalls of the mask 78. After the planarization process, the top surfaces of the dummy gate 76, the first spacer 81, and the first ILD 96 are flush within the process variation. Therefore, the top surface of the dummy gate 72 is exposed via the first ILD 96. In some embodiments, the mask 78 may be maintained while the planarization process aligns the top surface of the first ILD 96 with the top surfaces of the mask 78 and the first spacer 81.

[0133] exist Figure 15A and Figure 15BIn this process, the dummy gate 72 and the mask 78 (if present) are removed in one or more etching steps, resulting in the formation of a second trench 98. Several portions of the dummy dielectric layer 60 in the second trench 98 may also be removed. In some embodiments, the dummy gate 72 and the dummy dielectric layer 60 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 at a rate faster than the first ILD 96 or the first spacer 81. Each second trench 98 exposes and / or covers several portions of the nanostructure 55, which serve as channel regions for subsequent completion of the nanoFET. The portions of the nanostructure 55 serving as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 may be used as an etch stop layer as the dummy gate 72 is etched. The dummy dielectric layer 60 may then be removed after the removal of the dummy gate 72.

[0134] exist Figure 16A and Figure 16B In order to form opening 130, the second nanostructure 54 in the p-type region 50P can be removed by forming a mask (not shown) over the n-type region 50N and performing an isotropic etching process such as wet etching or similar using an etchant selective for the material of the second nanostructure 54, while the first nanostructure 52, substrate 50, and STI region 68 remain relatively unetched relative to the second nanostructure 54. In embodiments where the second nanostructure 54 comprises, for example, SiGe and the first nanostructure 52 comprises, for example, Si or SiC, hydrogen fluoride, another fluorine gas, or the like can be used to remove the second nanostructure 54 in the p-type region 50P. After the removal process, opening 130 includes region 50I between each of the first nanostructures 52.

[0135] In other embodiments, the channel regions in the n-type region 50N and the p-type region 50P can be formed simultaneously, for example, by removing the first nanostructure 52 from both the n-type region 50N and the p-type region 50P, or by removing the second nanostructure 54 from both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions of the n-type nanoFET and the p-type nanoFET can have the same material composition, such as silicon, silicon germanium, or the like. For example, Figure 28A , Figure 28B and Figure 28C The diagram illustrates a structure resulting from such an embodiment: the channel regions in both the p-type region 50P and the n-type region 50N are provided by a second nanostructure 54 and contain silicon.

[0136] exist Figures 17A to 24BIn some embodiments, the gate dielectric layer 100 and the gate electrode 102 are formed as replacement gate structures for use in the second recess 98. The gate dielectric layer 100 (e.g., a high-k gate dielectric layer) and the gate electrode 102 (e.g., a WFM layer) are treated with aluminum and fluorine, respectively. Due to the aluminum immersion and fluorine immersion discussed in more detail below, the flat-band voltage (V) of the resulting transistor is... FB The band edge of the metal towards the WFM layer can be increased, which can reduce the threshold voltage of the resulting transistor and improve device performance.

[0137] The formation of the gate dielectric layer in the n-type region 50N and the p-type region 50P can occur simultaneously, such that the gate dielectric layer in each region is formed of the same material, and the formation of the gate electrode can occur simultaneously, such that the gate electrode in each region is formed of the same material. In some embodiments, the gate dielectric layer in each region can be formed by a unique process, such that the gate dielectric layer can be of different materials and / or have a different number of layers, and / or the gate electrode in each region can be formed by a unique process, such that the gate electrode can be of different materials and / or have a different number of layers. Various masking steps can be used to mask and expose appropriate regions when using unique processes. In the following description, the gate electrode of the n-type region 50N and the gate electrode of the p-type region 50P are formed separately.

[0138] Figures 17A to 23D The diagram shows that a gate dielectric layer 100 and a gate electrode 102 are formed in a p-type region 50P, and an n-type region 50N is at least shielded while the gate electrode 102 is formed in the p-type region 50P.

[0139] exist Figure 17A and Figure 17B In this configuration, gate dielectric layer 100 is conformally deposited in a second recess 98 within a p-type region 50P. Gate dielectric layer 100 comprises one or more dielectric layers, such as oxides, metal oxides, the like, or combinations thereof. For example, in some embodiments, gate dielectric layer 100 may comprise a first gate dielectric layer 101 (e.g., comprising silicon oxide or the like) and a second gate dielectric layer 103 (e.g., comprising metal oxide or the like) above the first gate dielectric layer 101. In some embodiments, the second gate dielectric layer 103 comprises a high-k dielectric material, and in these embodiments, the second gate dielectric layer 103 may have a k value greater than about 7.0, and may comprise metal oxides, or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. In some embodiments, the first gate dielectric layer 101 may be referred to as an interface layer, and the second gate dielectric layer 103 may be referred to as a high-k gate dielectric layer. In some embodiments, the formation of the gate dielectric layer 100, such as the formation of the second gate dielectric layer 103, may include forming pores in the material. For example, the pores may be micropores in the oxide before or after deposition that are not sufficiently dense.

[0140] The structure of the gate dielectric layer 100 may be the same or different in the n-type region 50N and the p-type region 50P. For example, the n-type region 50N may be shielded or exposed, while the gate dielectric layer 100 is formed in the p-type region 50P. In embodiments where the n-type region 50N is exposed, the gate dielectric layer 100 may also be formed in the n-type region 50N. Methods for forming the gate dielectric layer 100 may include molecular-beam deposition (MBD), ALD, PECVD, and the like.

[0141] Figures 18A to 23D A portion of the illustrated gate electrode 102 (e.g., a first conductive material 105) is formed over the gate dielectric layer 100 using pre-deposition and post-deposition treatments. This combination of treatments is used to tune the first conductive material 105 and improve the reliability of the functional device.

[0142] exist Figure 18A and Figure 18B In this process, an aluminum treatment 109 (e.g., a pre-deposition treatment for the gate electrode 102) is applied to the second gate dielectric layer 103. In some embodiments, the aluminum treatment 109 is a deposition process (e.g., ALD process, CVD process, or similar) that allows an aluminum-containing precursor to flow to form a first aluminum residue 111 over the surface of the second gate dielectric layer 103. The first residue 111 is used to pass through a first conductive material 105 (see...). Figure 19A and Figure 19B Subsequent fluorine treatment (see) Figure 20A and Figure 20B The first residue 111 is generally retained at the surface of the gate dielectric layer 100, such that aluminum is absorbed or partially oxidized by the molecules of the gate dielectric layer 100 (e.g., the second gate dielectric layer 103). The aluminum in the first residue 111 can subsequently absorb fluorine by non-oxidation or only partial oxidation.

[0143] In some embodiments, the aluminum-containing precursor applied during aluminum treatment 109 may be triethylaluminum (TEA) (Al2(C2H5)6), trimethylaluminum (TMA) (Al(CH3)6), combinations thereof, or similar. Aluminum treatment 109 may be performed at a temperature ranging from about 250°C to about 550°C and for a duration ranging from about 0.5 seconds to about 5 minutes or from about 15 seconds to about 30 seconds. Temperatures above 550°C and / or durations longer than 5 minutes may cause aluminum to diffuse into the second gate dielectric layer 103 and oxidize within it. Temperatures below 250°C and / or durations less than 0.5 seconds may cause insufficient amounts of aluminum (e.g., insufficient amounts below residue 111) to subsequently absorb fluorine via the first conductive material 105 and into the second gate dielectric layer 103.

[0144] By performing aluminum treatment 109 in the manner described above to avoid triggering a reduction-oxidation reaction (or to minimize this reaction), aluminum treatment 109 does not deposit a continuous film on the gate dielectric layer 100. However, discrete pits of the first aluminum residue 111 may be formed on the top surface of the second gate dielectric layer 103. Each pit of the first residue 111 may be disconnected from other pits of the first residue 111, and no continuous film is formed on the gate dielectric layer 100. The first residue 111 may be formed on the exposed surface of the gate dielectric layer 100 (e.g., the second gate dielectric layer 103), including in regions 50I between the first nanostructures 52. In some embodiments where the second gate dielectric layer 103 contains a high-k dielectric, such as HfO2, the ratio of aluminum to hafnium in region 50I may be less than 0.1, such as in the range of about 0.005 to about 0.1, or less than 0.005.

[0145] exist Figure 19A and Figure 19B In this process, a first conductive material 105 is conformally deposited over the gate dielectric layer 100 and the first residue 111 in the p-type region 50P. In some embodiments, the first conductive material 105 is a p-type WFM containing titanium nitride, tantalum nitride, titanium silicon nitride (TiSiN), or the like. The first conductive material 105 can be deposited by CVD, ALD, PECVD, PVD, or the like. In some embodiments, the first conductive material 105 is deposited in situ using aluminum treatment 109. Therefore, the same deposition tool can be used for two processes without the need for transfer between different tools or chambers. The advantage of the in-situ and rapid deposition of the first conductive material 105 is that the presence of the first conductive material 105 prevents or greatly reduces oxidation (or other oxidation) of the aluminum in the first residue 111 using the gate dielectric layer 100 (e.g., the second gate dielectric layer 103).

[0146] The first conductive material 105 may be deposited to surround each of the first nanostructures 52. The first conductive material 105 may only partially fill region 50I. Therefore, after the deposition of the first conductive material 105, the opening 130 may remain in region 50I between the first nanostructures 52. The first conductive material 105 has an absorption of aluminum using the first residue, which helps to prevent aluminum from diffusing into the second gate dielectric layer 103. Therefore, the second gate dielectric layer 103 is used to prevent the first residue from oxidizing or further oxidizing. Furthermore, after the formation of the first conductive material 105, the pores (e.g., micropores) formed in the gate dielectric layer 103 during the deposition of the second gate dielectric layer 103 remain unfilled and free of aluminum. Therefore, the first residue 111 remains in the aluminum break pits in the region between the second gate dielectric layer 103 and the first conductive material 105.

[0147] exist Figure 20A and Figure 20B In this process, a fluorine treatment 113 is applied to a first conductive material 105. In some embodiments, the fluorine treatment 113 is a deposition process (e.g., ALD process, CVD process, or similar) that causes a fluorine-containing precursor to flow over the surface of the first conductive material 105. In some embodiments, the fluorine-containing precursor may be WF. x NF x TiF x TaF x HfF x Or similar, where x is an integer in the range of 1 to 6. For example, in some embodiments, the fluorine-containing precursor may be WF6 and / or NF3. When the fluorine-containing precursor reaches the first conductive material 105, some of the fluorine diffuses through the first conductive material 105. The first residue 111 improves this diffusion by drawing fluorine towards the interface between the first conductive material 105, the first residue 111, and the gate dielectric layer 100 (e.g., the second gate dielectric layer 103). Some of the fluorine will further diffuse into the gate dielectric layer 100. As discussed above, because the aluminum of the first residue 111 is prevented from reaching the pores in the second gate dielectric layer 103, the fluorine is able to diffuse across the first residue 111 and fill some of those pores in the second gate dielectric layer 103.

[0148] Fluorine treatment 113 can be performed at temperatures ranging from about 250°C to about 475°C. It has been observed that when the temperature of fluorine treatment 113 is below 250°C, the fluorine-containing precursor does not properly ionize the first conductive material 105 and / or its underlying layer, affecting the desired change between the two. It has been observed that when the temperature of fluorine treatment 113 is above 475°C, the amount of fluorine ionized from the fluorine-containing precursor may be too large to be precisely controlled. In some embodiments, fluorine treatment 113 can be performed for a duration ranging from about 1 second to about 15 minutes, such as a duration of about 30 seconds. It has been observed that when the duration of fluorine treatment 113 is less than 1 second, the treatment process may not be sufficient to tune the threshold voltage of the resulting transistor. It has been observed that when the duration of fluorine treatment 113 is greater than 15 minutes, excessive fluorine may be introduced into the device, resulting in capacitance equivalent thickness (CET) penalties (e.g., regrowth of interface layer 101).

[0149] Applying both the aluminum treatment 109 and the fluorine treatment 113 as described above can cause the first conductive material 105 to contain about 10.8% to about 13% or more of fluorine, such as fluorine concentrations in the range of about 5% to about 25%. Furthermore, at the depth of the first residue 111 (e.g., at the interface between the second gate dielectric layer 103 and the first conductive material 105), aluminum may be contained in the range of about 0.3% to about 10%. An aluminum concentration below about 0.3% may be insufficient to absorb enough fluorine into the second gate dielectric layer 103 and retain it in the first conductive material 105, thereby causing the replacement gate structure to receive insufficient voltage tuning. An aluminum concentration above about 10% can cause one or more of the following problems. For example, a high aluminum concentration can create a barrier that prevents fluorine from diffusing or moving across the first residue 111 and into the second gate dielectric layer 103. Furthermore, a high aluminum concentration can further lead to increased aluminum oxidation, for example, in the case of the second gate dielectric layer 103, where some of the aluminum may fill some or most of the pores (e.g., micropores) in the second gate dielectric layer 103, thereby causing CET penalty as described above. Additionally, a high aluminum concentration along the first conductive material 105 can compromise the tuning accuracy of the threshold voltage of the alternative gate structure described herein.

[0150] In some embodiments, to avoid triggering a reduction-oxidation reaction, the fluorination treatment 113 is a deposition process using a single chemical substance (e.g., WF6, NF3, or the like) without any other chemical substance. Therefore, the fluorination treatment 113 does not deposit a continuous film on the first conductive material 105. However, in embodiments where the fluorinated precursor also comprises a metal, discrete pits of the second metal residue 115 may be formed on the top surface of the first conductive material 105. Each pit of the second residue 115 may be disconnected from the other pits of the second residue 115, and no continuous film may be formed on the first conductive material 105. In embodiments where the fluorinated precursor used during the fluorination treatment 113 is WF6, the second precursor 115 may be a tungsten residue formed on the first conductive material 105. The second residue 115 may be formed on the exposed surface of the first conductive material 105, including in regions 50I between the first nanostructures 52. In some embodiments where the second residue 115 is a tungsten residue and the high-k gate dielectric layer 103 comprises HfO2, the tungsten to hafnium ratio in region 50I may be in the range of about 0.001 to about 0.3, or less than 0.1, such as less than 0.001. It has been observed that when the tungsten to hafnium ratio in region 50I is greater than 0.3, the resulting device may not have the desired threshold voltage (e.g., the threshold voltage may be too high).

[0151] In other embodiments where the fluorinated precursor does not contain a metal (e.g., the fluorinated precursor is NF3), the second residue 115 may not form on the first conductive material 105. For example, Figures 29A to 29C The illustration shows an example in which a second residue 115 is not formed and the fluorinated precursor used during fluorine treatment 113 is NF3.

[0152] In some embodiments, the fluorine treatment 113 may further result in fluorine diffusion into the underlying gate dielectric layer 100, such as the high-k gate dielectric layer 103, and the fluorine may be observed in the high-k gate dielectric layer 103 using X-ray photoelectron spectroscopy analysis. For example, in embodiments where the high-k gate dielectric layer 103 comprises hafnium oxide, the fluorine to hafnium ratio in the high-k gate dielectric layer 103 may be in the range of about 0.07 to about 0.4 due to the fluorine treatment 113. It has been observed that when the fluorine to hafnium ratio in the high-k gate dielectric layer 103 is less than 0.07, the amount of fluorine may not be sufficient to tune the threshold voltage of the resulting transistor. It has been observed that when the fluorine to hafnium ratio in the high-k gate dielectric layer 103 is greater than 0.4, excess fluorine may have been introduced into the high-k gate dielectric layer 103, resulting in CET penalty (e.g., regrowth of the interface layer 101). In some embodiments, the amount of fluorine in the high-k gate dielectric layer 103 may be in the range of about 2.5% to about 6%.

[0153] Therefore, as described above, in various embodiments of performing fluorine treatment 113 on the first conductive material 105, fluorine can also diffuse into the lower gate dielectric layer (e.g., a high-k gate dielectric layer). Thus, the V of the resulting transistor... FB By increasing the band edge of the metal towards the WFM layer, the threshold voltage of the resulting device can be reduced, and device performance can be improved. For example, in experimental data, fluorine treatment using WF6 immersion resulted in a 10mV to 30mV shift in the effective work function (EFW) of metal-oxide-semiconductor capacitors (MOSCs) after gas annealing.

[0154] exist Figure 21A and Figure 21B In this process, a second conductive material 107 is conformally deposited on the first conductive material 105 and the second residue 115 (if present). In some embodiments, the second conductive material 107 is a p-type WFM containing titanium nitride, tantalum nitride, tungsten nitride, molybdenum nitride, or the like. The second conductive material 107 can be deposited by CVD, ALD, PECVD, PVD, or the like. Because the second conductive material 107 is deposited after fluorine treatment 113, the second conductive material 107 may be fluorine-free or have a lower fluorine concentration compared to the first conductive material 105.

[0155] The second conductive material 107 may fill the remaining portion of the region 50I between the first nanostructures 52 (e.g., fill the opening 130, see...). Figure 19A and Figure 19B For example, a second conductive material 107 may be deposited on a first conductive material 105 until they are joined and stitched together, and in some embodiments, an interface 107S may be formed by causing a first portion 107A (e.g., conductive material 107A) of the second conductive material 107 to touch a second portion 107B (e.g., conductive material 107B) of the second conductive material 107 in region 50I.

[0156] exist Figure 22A and Figure 22B In this configuration, an adhesive layer 117 is conformally deposited over the second conductive material 107. In some embodiments, the adhesive layer 117 is conformally deposited on the second conductive material 107 in the p-type region 50P. In some embodiments, the adhesive layer 117 comprises titanium nitride, tantalum nitride, or the like. The adhesive layer 117 can be deposited by CVD, ALD, PECVD, PVD, or the like. For example, the adhesive layer 117 may alternatively be referred to as an adhesive layer and improves the adhesion between the second conductive material 107 and the underlying filler metal 119.

[0157] exist Figure 23A , Figure 23B , Figure 23C and Figure 23D In this process, the remaining portion of the gate electrode 102 is deposited to fill the remaining portion of the second recess 98. For example, fill metal 119 may be deposited over the adhesive layer 117. In some embodiments, the fill metal 119 comprises cobalt, ruthenium, aluminum, tungsten, combinations thereof, or the like, and is deposited by CVD, ALD, PECVD, PVD, or the like. The resulting gate electrode 102 is formed as a replacement gate and may include a first residue 111, a first conductive material 105, a second residue 115 (if present), a second conductive material 107, the adhesive layer 117, and the fill metal 119. Figure 23C The diagram follows Figure 23B The top view of line X-X' (e.g., in zone 50I), while Figure 23D The diagram follows Figure 23B A top view of the line Y-Y' (e.g., through one of the first nanostructures 52).

[0158] In the p-type region 50P, the gate dielectric layer 100, the first conductive material 105, the second conductive material 107, the adhesive layer 117, and the filler metal 119 can each be formed on the top surface, sidewalls, and bottom surface of the first nanostructure 52. A first residue 111 (e.g., aluminum) can be formed at the interface between the second gate dielectric layer 103 and the first conductive material 105. A second residue 115 can be formed at the interface between the first conductive material 105 and the second conductive material 107 (including, for example, diffusion of fluorine or one or both), and the metal element of the residue 115 may be different from the metal elements of the first conductive material 105 and / or the second conductive material 107. The gate dielectric layer 100, the first conductive material 105, the residue 115, the second conductive material 107, the adhesive layer 117, and the filler metal 119 can also be deposited on the top surface of the first ILD 96, CESL 94, the first spacer 81, and the STI region 68. After filling the second recess 98, a planarization process, such as CMP, can be performed to remove excess portions of the gate dielectric layer 100, the first conductive material 105, the residue 115, the second conductive material 107, the adhesive layer 117, and the filler metal 119, which are located above the top surface of the first ILD 96. The remaining material of the gate electrode 102 and the gate dielectric layer 100 thus forms the replacement gate structure of the resulting nanoFET. The gate electrode 102 and the gate dielectric layer 100 can be collectively referred to as the "gate structure".

[0159] Figure 24A and Figure 24BThe diagram illustrates a gate stack in an n-type region 50N. Forming a gate stack in the n-type region 50N may include first removing a first nanostructure 52 in the n-type region 50N. The first nanostructure 52 may be removed by forming a mask (not shown) over a p-type region 50P and performing an isotropic etching process such as wet etching or the like using an etchant selective for the material of the first nanostructure 52, while the second nanostructure 54, substrate 50, and STI region 68 remain relatively unetched relative to the first nanostructure 52. In embodiments where the first nanostructures 52A to 52C comprise, for example, SiGe and the second nanostructures 54A to 54C comprise, for example, Si or SiC, tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to remove the first nanostructure 52 in the n-type region 50N.

[0160] A gate stack is then formed above and around the second nanostructure 54 in the n-type region 50N. The gate stack includes a gate dielectric layer 100 and a gate electrode 127. In some embodiments, the gate dielectric layer 100 in the n-type region 50N and the p-type region 50P may be formed simultaneously. Additionally, at least several portions of the gate electrode 127 may be formed in the gate electrode 102 (see [link to documentation]). Figures 23A to 23D The gate electrode 127 may be formed before or after the formation of the p-type region 50P, while at least several portions of the gate electrode 127 are shielded. Therefore, the gate electrode 127 may comprise a different material than the gate electrode 102. For example, the gate electrode 127 may comprise a conductive material 121, a barrier layer 123, and a filler metal 125. The conductive material 121 may be an n-type work function metal (WFM) layer comprising an n-type metal, such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, or the like. The conductive material 121 may be deposited by CVD, ALD, PECVD, PVD, or the like. The barrier layer 123 may comprise titanium nitride, tantalum nitride, tungsten carbide, combinations thereof, or the like, and the barrier layer 123 may further serve as an adhesion layer. The barrier layer 123 may be deposited by CVD, ALD, PECVD, PVD, or the like. The filler metal 125 may comprise cobalt, ruthenium, aluminum, tungsten, combinations thereof, or the like, and is deposited by CVD, ALD, PECVD, PVD, or the like. The filler metal 125 may or may not have the same material composition and is deposited simultaneously with the filler metal 119.

[0161] After filling the second recess 98 in the n-type region 50N, a planarization process, such as CMP, can be performed to remove excess portions of the gate dielectric layer 100 and the gate electrode 127, which are located above the top surface of the first ILD 96. The remaining material of the gate electrode 127 and the gate dielectric layer 100 thus forms the replacement gate structure of the resulting nanoFET in the n-type region 50N. The CMP process for removing excess material from the gate electrode 102 in the p-type region 50P and from the gate electrode 127 in the n-type region 50N can be performed simultaneously or separately.

[0162] exist Figures 25A to 25C In this process, the gate structure (including gate dielectric layer 100, gate electrode 102, and gate electrode 127) is recessed such that a groove is formed directly above the gate structure and between opposing portions of the first spacer 81. A gate mask 104 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, fills the groove, followed by a planarization process to remove excess portions of the dielectric material extending above the first ILD 96. The gate contacts subsequently formed (such as those described below) Figure 27A , Figure 27B and Figure 27C The gate contact 114 penetrates the gate shield 104 to contact the top surface of the recessed gate electrode 102.

[0163] If passed Figures 25A to 25C Further illustration shows that the second ILD 106 is deposited over the first ILD 96 and over the gate mask 104. In some embodiments, the second ILD 106 is a flowable film formed by FCVD. In some embodiments, the second ILD 106 is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable method such as CVD, PECVD, or the like.

[0164] exist Figures 26A to 26CIn this process, the second ILD 106, the first ILD 96, CESL 94, and the gate mask 104 are etched to form a third groove 108, which exposes the surface of the epitaxial source / drain region 92 and / or the gate structure. The third groove 108 can be formed by etching using anisotropic etching processes, such as RIE, NBE, or the like. In some embodiments, the third groove 108 can be etched through the second ILD 106 and the first ILD 96 using a first etching process; it can be etched through the gate mask 104 using a second etching process; and it can then be etched through the CESL 94 using a third etching process. A mask, such as a photoresist, can be formed and patterned over the second ILD 106 to shield several portions of the second ILD 106 from the first and second etching processes. In some embodiments, the etching process may over-etch, and thus the third groove 108 extends into the epitaxial source / drain region 92 and / or gate structure, and the bottom of the third groove 108 may be flush with (e.g., at the same level, or at the same distance from the substrate) or lower than these top surfaces (e.g., closer to the substrate). Although Figure 26B The third groove 108 in the figure exposes the epitaxial source / drain region 92 and / or gate structure in the same cross section. However, in various embodiments, the epitaxial source / drain region 92 and / or gate structure may be exposed in different cross sections, thereby reducing the risk of short-circuiting the subsequently formed contacts.

[0165] After the third groove 108 is formed, a silicide region 110 is formed over the epitaxial source / drain region 92. In some embodiments, the silicide region 110 is formed by first depositing a metal (not shown) capable of reacting with the underlying semiconductor material (e.g., silicon, silicon-germanium, germanium) of the epitaxial source / drain region 92 over the exposed portion of the epitaxial source / drain region 92 to form a silicide or germanide region; then performing a thermal annealing process to form the silicide region 110. Unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide region 110 is referred to as a silicide region, it can also be a germanide region or a silicon-germanium region (e.g., a region containing both silicide and germanide). In an embodiment, the silicide region 110 comprises TiSi and has a thickness ranging from about 2 nm to about 10 nm.

[0166] Next, in Figures 27A to 27CIn this embodiment, contacts 112 and 114 (also referred to as contact plugs) are formed in the third recess 108. Contacts 112 and 114 may each comprise one or more layers, such as a barrier layer, a diffusion layer, and a filler material. For example, in some embodiments, contacts 112 and 114 each include a barrier layer and a conductive material, and are each electrically coupled to an underlying conductive feature (e.g., in the illustrated embodiment, gate electrode 102, gate electrode 127, and / or silicide region 110). Contact 114 is electrically coupled to gate electrodes 102 and 127 and may be referred to as a gate contact, and contact 112 is electrically coupled to silicide region 110 and may be referred to as a source / drain contact. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. Planarization processes such as CMP can be performed to remove excess material from the surface of the second ILD 106.

[0167] Figure 28A , Figure 28B and Figure 28C The figure shows a cross-sectional view of an apparatus according to some other embodiments. Figure 28A The illustration is in Figure 1 The reference cross section A-A' is shown in the diagram. Figure 28B The illustration is in Figure 1 The reference cross section B-B' is shown in the diagram. Figure 28C The illustration is in Figure 1 The reference cross section C-C' is shown in the diagram. Figures 28A to 28C In this context, similar reference numerals indicate elements similar to those formed through similar processes as described in the above embodiments, such as... Figures 27A to 27C The structure. However, in Figures 28A to 28C In this configuration, the channel regions in the n-type region 50N and the p-type region 50P contain the same material. For example, a second nanostructure 54 containing silicon provides the channel region for the p-type nanoFET in the n-type region 50P and the channel region for the n-type nanoFET in the n-type region 50N. Figures 28A to 28C The structure can be formed, for example, by removing the first nanostructure 52 from both the p-type region 50P and the n-type region 50N; depositing a gate dielectric layer 100 and a gate electrode 102 around the second nanostructure 54 in the p-type region 50P; and depositing a gate dielectric layer 100 and a gate electrode 102 around the second nanostructure 54 in the n-type region 50N.

[0168] Figures 29A to 29E The figure shows a cross-sectional view of an apparatus according to some other embodiments. Figure 29A The illustration is in Figure 1 The reference cross section A-A' is shown in the diagram. Figure 29B The illustration is in Figure 1 The reference cross section B-B' is shown in the diagram. Figure 29E The illustration is in Figure 1The reference cross section C-C' is shown in the diagram. Figures 29A to 29E In this context, similar reference numerals indicate elements similar to those formed through similar processes as described in the above embodiments, such as... Figures 27A to 27C The structure. However, in Figures 29A to 29E In this process, the second residue 115 does not form between the first conductive material 105 and the second conductive material 107. For example, when fluorine treatment 113 (see...) Figures 20A to 20B This can be achieved when the fluorinated precursor used during the process does not contain metal. For example, in an embodiment where the fluorinated precursor is NF3, the second residue 115 may not be formed.

[0169] Various embodiments provide gate stacks having an aluminum-treated gate dielectric layer and a fluorine-treated work function metal layer. For example, aluminum treatment may include aluminum immersion in the gate dielectric layer (e.g., a high-k gate dielectric layer), and fluorine treatment may include fluorine immersion in the WFM layer. Thus, fluorine from the fluorine treatment can diffuse into the WFM and into the underlying gate dielectric layer. While fluorine treatment alone (e.g., in the absence of aluminum treatment) would tend to draw fluorine into the WFM and gate dielectric layers to achieve the benefits described herein, aluminum treatment improves the movement and retention of fluorine in these layers. For example, aluminum treatment forms an aluminum residue that is typically retained between the high-k gate dielectric layer and the WFM layer by subsequent processing. The aluminum residue absorbs fluorine from the fluorine treatment via the WFM layer, and some of this fluorine then bypasses the aluminum residue to fill the pores in the high-k gate dielectric layer. The combination of treatments results in the required amount of fluorine in those layers, thereby achieving the following benefits: the flat band voltage of the resulting transistor increases towards the band edge of the metal in the WFM layer, the threshold voltage of the resulting transistor decreases, and the device performance is improved.

[0170] In some embodiments, a method of forming a gate structure includes: forming a plurality of nanostructures over a substrate; etching the nanostructures to form a first groove; forming source / drain regions in the first groove; removing a first nanostructure from the nanostructures, thereby leaving a second nanostructure from the nanostructures; depositing a gate dielectric layer over and around the second nanostructures; performing an aluminum treatment on the gate dielectric layer; depositing a first conductive material over and around the gate dielectric layer; performing a fluorine treatment on the first conductive material; and depositing a second conductive material over and around the first conductive material. In another embodiment, the step of performing the aluminum treatment includes the step of forming an aluminum residue over the gate dielectric layer. In another embodiment, the step of performing the fluorine treatment includes the step of diffusing fluorine into the first conductive material. In another embodiment, the step of performing the fluorine treatment further includes the step of diffusing fluorine into the gate dielectric layer. In another embodiment, the step of performing the fluorine treatment further includes the step of forming a metal residue over the first conductive material. In another embodiment, the first conductive material comprises a p-type work function metal layer. In another embodiment, the step of performing the aluminum treatment includes the step of flowing a precursor comprising triethylaluminum or trimethylaluminum. In another embodiment, the step of performing the fluorine treatment includes the step of flowing a precursor comprising WF... x NF x TiF x TaF x or HfF x The steps of a precursor flow, where x is an integer in the range of 1 to 6.

[0171] In some embodiments, a gate structure includes: a first nanostructure extending between a source region and a drain region; a second nanostructure above the first nanostructure; a gate dielectric layer above and around the first and second nanostructures; an aluminum residue above the gate dielectric layer; a work function metal (WFM) layer above the gate dielectric layer and the aluminum residue, the WFM layer comprising fluorine, a first portion of the WFM layer disposed around the first nanostructure, and a second portion of the WFM layer disposed around the second nanostructure; and a conductive layer disposed above the WFM layer, a first portion of the conductive layer disposed around the first nanostructure, and a second portion of the conductive layer disposed around the second nanostructure. In another embodiment, the gate structure further includes a metal residue directly inserted between the WFM layer and the conductive layer. In another embodiment, each of the WFM layer and the gate dielectric layer comprises fluorine. In another embodiment, the first portion of the conductive layer substantially contacts the second portion of the conductive layer. In another embodiment, the WFM layer is a p-type WFM layer. In another embodiment, the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer. In another embodiment, a region inserted between the second gate dielectric layer and the WFM layer contains aluminum at a concentration ranging from about 0.3% to about 10%.

[0172] In some embodiments, a transistor includes: a first dielectric material disposed over a first nanostructure; a first metal residue disposed over the first dielectric material; a first conductive material disposed over the first dielectric material; a second conductive material disposed over the first conductive material; a third conductive material disposed over the second conductive material, the third conductive material having the same composition as the first conductive material; a second metal residue disposed over the third conductive material, the second metal residue having the same composition as the first metal residue; a second dielectric material disposed over the second metal residue, the second dielectric material having the same composition as the first dielectric material; and a second nanostructure disposed over the second dielectric material. In another embodiment, the transistor further includes a third metal residue interposed between the first conductive material and the second conductive material; and a fourth metal residue interposed between the second conductive material and the third conductive material, the fourth metal residue having the same composition as the third metal residue. In another embodiment, the third metal residue comprises tungsten. In another embodiment, each of the second dielectric material, the first conductive material, the third conductive material, and the third dielectric material comprises fluorine. In another embodiment, the first metal residue comprises aluminum.

[0173] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for forming a gate structure, characterized in that, Includes the following steps: Multiple nanostructures are formed on a substrate; Etch these nanostructures to form the first groove; Source / drain regions are formed in these first grooves; Remove the first nanostructure from these nanostructures, thereby leaving the second nanostructure in these nanostructures; A gate dielectric layer is deposited on top of and around these second nanostructures; Perform an aluminum treatment on the gate dielectric layer, the step of performing the aluminum treatment includes: depositing a discontinuous aluminum film on the gate dielectric layer; A first conductive material is deposited above and around the gate dielectric layer; Performing a fluorine treatment on the first conductive material, the step of performing the fluorine treatment comprising: depositing a discontinuous fluorine film on the first conductive material; and A second conductive material is deposited on top of and around the first conductive material.

2. The method according to claim 1, characterized in that, The step of performing the aluminum treatment includes the following steps: forming an aluminum residue over the gate dielectric layer.

3. The method according to claim 1, characterized in that, The steps of performing the fluorine treatment include the following steps: diffusing fluorine into the first conductive material.

4. The method according to claim 3, characterized in that, The step of performing the fluorine treatment further includes the step of diffusing fluorine into the gate dielectric layer.

5. The method according to claim 3, characterized in that, The step of performing the fluorine treatment further includes the step of forming a metallic residue on the first conductive material.

6. The method according to claim 1, characterized in that, The first conductive material contains a p-type work function metal layer.

7. The method according to claim 1, characterized in that, The steps of performing the aluminum treatment include the following: flowing a precursor containing triethylaluminum or trimethylaluminum.

8. The method according to claim 1, characterized in that, The step of performing this fluorine treatment includes making WF-containing... x NF x TiF x TaF x or HfF x The steps of a precursor flow, where x is an integer in the range of 1 to 6.

9. A gate structure, characterized in that, Include: A first nanostructure extends between a source region and a drain region; A second nanostructure above the first nanostructure; A gate dielectric layer is located above and around the first nanostructure and the second nanostructure; An aluminum residue above the gate dielectric layer, the aluminum residue being discontinuous; A work function metal layer above the gate dielectric layer and the aluminum residue, the work function metal layer comprising fluorine, a first portion of the work function metal layer disposed around the first nanostructure, and a second portion of the work function metal layer disposed around the second nanostructure; and A conductive layer is disposed above the work function metal layer, a first portion of the conductive layer is disposed around the first nanostructure, and a second portion of the conductive layer is disposed around the second nanostructure.

10. The gate structure according to claim 9, characterized in that, It further includes a metal residue that is directly inserted between the work function metal layer and the conductive layer.

11. The gate structure according to claim 10, characterized in that, Each of the work function metal layer and the gate dielectric layer contains fluorine.

12. The gate structure according to claim 9, characterized in that, The first portion of the conductive layer is in contact with the second portion of the conductive layer.

13. The gate structure according to claim 9, characterized in that, The work function metal layer is a p-type work function metal layer.

14. The gate structure according to claim 9, characterized in that, The gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer.

15. The gate structure according to claim 14, characterized in that, A region inserted between the second gate dielectric layer and the work function metal layer contains an aluminum concentration ranging from 0.3% to 10%.

16. A transistor, characterized in that, Include: A first dielectric material, the first dielectric material being disposed on top of a first nanostructure; A first metal residue disposed above the first dielectric material, comprising a discontinuous film formed on the first dielectric material; A first conductive material is disposed on top of the first dielectric material; A second conductive material is disposed on top of the first conductive material; A third conductive material is disposed above the second conductive material, and the third conductive material has the same composition as the first conductive material; A second metal residue disposed above the third conductive material, the second metal residue having the same composition as the first metal residue; A second dielectric material disposed on top of the second metal residue, the second dielectric material having the same composition as the first dielectric material; and A second nanostructure is disposed on top of the second dielectric material.

17. The transistor according to claim 16, characterized in that, Further includes: A third metal residue, the third metal residue being inserted between the first conductive material and the second conductive material; and A fourth metal residue is inserted between the second conductive material and the third conductive material, the fourth metal residue having the same composition as the third metal residue.

18. The transistor according to claim 17, characterized in that, The third metallic residue contains tungsten.

19. The transistor according to claim 16, characterized in that, Each of the second dielectric material, the first conductive material, the third conductive material, and the first dielectric material contains fluorine.

20. The transistor according to claim 16, characterized in that, The first metallic residue contains aluminum.

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