Method of forming a memory node contact structure and semiconductor structure

Abstract

The application provides a forming method of a storage node contact structure and a semiconductor structure. The forming method of the storage node contact structure comprises the following steps: providing a substrate, forming a bit line structure on the surface of the substrate, and forming a contact hole between the bit line structures; growing a silicon crystal in the contact hole, adding a doping source during the growing process, and the doping concentration of the doping source at the end of the growing process is greater than the doping concentration at the beginning of the growing process, so as to form a silicon crystal gradient structure of a single crystal silicon to a heavily doped polycrystalline silicon transition in the contact hole. Through the above design, the application can reduce the resistance of the storage node contact structure, improve the process efficiency of the contact, and reduce the production cost.

Description

Technical Field

[0001] This invention relates to the field of semiconductor memory node processing technology, and in particular to a method for forming a memory node contact structure and a semiconductor structure. Background Technology

[0002] In current mainstream DRAM array structures, heavily doped polysilicon is typically used as the material for the active regions connecting memory nodes. With the continuous miniaturization of feature sizes, smaller apertures place higher demands on the resistivity of the materials used in the memory node contact structures. Epitaxial growth of monocrystalline silicon offers significant advantages over polysilicon in terms of both bulk resistivity and interface contact resistance. However, due to issues such as low growth rates and difficulty in controlling uniformity, the method of obtaining monocrystalline silicon through epitaxial growth is currently difficult to apply to the contact structures of memory nodes in array regions. Summary of the Invention

[0003] A primary objective of this invention is to overcome at least one of the deficiencies of the prior art and to provide a method for forming a memory node contact structure that can improve the process efficiency of the contact structure while reducing the resistance of the contact structure.

[0004] Another major objective of this invention is to overcome at least one of the defects of the prior art and provide a semiconductor structure with low resistance of the storage node contact structure and high contact process efficiency.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] According to one aspect of the present invention, a method for forming a storage node contact structure is provided; wherein, the method comprises the following steps:

[0007] A substrate is provided, wherein bit line structures are formed on the surface of the substrate, and contact holes are formed between the bit line structures;

[0008] Silicon crystals are grown in the contact holes using an epitaxial growth process. During the growth process, doping sources are added, and the doping concentration of the doping sources at the end of the growth is greater than the doping concentration at the beginning of the growth, so as to form a silicon crystal gradient structure in the contact holes that transitions from monocrystalline silicon to heavily doped polycrystalline silicon.

[0009] According to one embodiment of the present invention, the growth process of the silicon crystal includes multiple growth stages, and the doping concentration of the dopant source gradually increases in the multiple growth stages.

[0010] According to one embodiment of the invention, the doping concentration of the dopant source is constant in any of the growth stages.

[0011] According to one embodiment of the present invention, the growth process of the silicon crystal sequentially includes a first growth stage, a second growth stage and a third growth stage, wherein the doping concentration of the dopant source in the first growth stage is a constant first concentration, the doping concentration of the dopant source in the second growth stage is a constant second concentration, and the doping concentration of the dopant source in the third growth stage is a constant third concentration; wherein the first concentration is less than the second concentration, and the second concentration is less than the third concentration.

[0012] According to one embodiment of the present invention, the doping source comprises phosphorus, and the first concentration is 7E+20 / cm. 3 ~8E+20 / cm 3 The second concentration is 8.5E+20 / cm. 3 ~9.5E+20 / cm 3 The third concentration is 1E+21 / cm. 3 ~1.1E+21 / cm 3 .

[0013] According to one embodiment of the present invention, the first concentration is 7.5E+20 / cm³. 3 ; and / or, the second concentration is 9E+20 / cm 3 ; and / or, the third concentration is 1.05E+21 / cm³. 3 .

[0014] According to one embodiment of the present invention, the doping concentration of the dopant source gradually increases during the growth process.

[0015] According to one embodiment of the present invention, before growing the silicon crystal, a groove is formed at the bottom of the contact hole corresponding to the active region, the axial direction of the groove opening having an angle greater than 0° and less than 90° with the vertical direction; wherein, when growing the silicon crystal, it starts from the groove, and during the growth process, the growth rate of the silicon crystal along a first direction and a second direction is controlled, such that at the beginning of growth, the growth rate of the silicon crystal along the first direction is greater than the growth rate along the second direction, and at the end of growth, the growth rate of the silicon crystal along the first direction is equal to the growth rate along the second direction, thereby forming gaps between the silicon crystal and the sidewalls of the bit line structure on both sides along the second direction; wherein, the first direction is the axial direction of the groove opening, and the second direction is perpendicular to the first direction in the vertical plane.

[0016] According to one embodiment of the present invention, during the growth of the silicon crystal, the growth rate of the silicon crystal along the first direction and along the second direction is controlled by adding an inhibitor and controlling the content of the inhibitor. The content of the added inhibitor is negatively correlated with the nucleation rate of the epitaxial growth of the silicon crystal. The content of the added inhibitor at the end of the growth is less than the content added at the beginning of the growth.

[0017] According to one embodiment of the present invention, the amount of the inhibitor added at the end of growth is 0.

[0018] According to one embodiment of the present invention, the growth process of the silicon crystal includes multiple growth stages, and the amount of the inhibitor added in the multiple growth stages gradually decreases.

[0019] According to one embodiment of the present invention, the growth process of the silicon crystal sequentially includes a first growth stage, a second growth stage and a third growth stage, wherein the amount of inhibitor added in the first growth stage is a constant first amount, the amount of inhibitor added in the second growth stage is a gradually decreasing range, and the amount of inhibitor added in the third growth stage is a constant third amount; wherein the first amount is greater than or equal to the upper limit of the range, and the lower limit of the range is greater than or equal to the third amount.

[0020] According to one embodiment of the present invention, the inhibitor comprises hydrochloric acid, and the amount of the inhibitor added is characterized by the flow rate of the hydrochloric acid; wherein, the first amount is 175 sccm to 185 sccm, the upper limit of the amount range is 130 sccm to 140 sccm, the lower limit of the amount range is 85 sccm to 95 sccm, and the third amount is 40 sccm to 50 sccm.

[0021] According to one embodiment of the present invention, the first content is 180 sccm; and / or, the upper limit of the content range is 135 sccm, and the lower limit of the content range is 90 sccm; and / or, the third content is 45 sccm.

[0022] According to another aspect of the present invention, a semiconductor structure is provided; wherein the semiconductor structure includes a substrate, a bit line structure is formed on the surface of the substrate, a contact hole is formed between each bit line structure, and a silicon crystal gradient structure transitioning from single-crystal silicon to heavily doped polycrystalline silicon is formed in the contact hole.

[0023] According to one embodiment of the present invention, the silicon crystal gradient structure is used as a storage node contact structure.

[0024] According to one embodiment of the present invention, the silicon crystal gradient structure includes a first region, a second region, and a third region, wherein the first region is monocrystalline silicon, the second region is polycrystalline silicon, and the doping concentration of the first region is 7E+20 / cm². 3 ~8E+20 / cm 3 The doping concentration in the second region is 8.5E+20 / cm. 3 ~9.5E+20 / cm 3 The doping concentration of the third region is 1E+21 / cm. 3 ~1.1E+21 / cm 3 .

[0025] As can be seen from the above technical solutions, the advantages and positive effects of the method for forming the memory node contact structure and the semiconductor structure proposed in this invention are as follows:

[0026] This invention introduces a doping source during silicon crystal growth and controls the doping concentration at the end of growth to be lower than the initial doping concentration, thereby forming a gradient silicon crystal structure within the contact holes that transitions from monocrystalline silicon to heavily doped polycrystalline silicon. Through this design, the invention can reduce the resistance of the memory node contact structure while improving contact process efficiency and reducing production costs. Attached Figure Description

[0027] Various objects, features, and advantages of the invention will become more apparent from the following detailed description of preferred embodiments of the invention, taken in conjunction with the accompanying drawings. The drawings are merely illustrative of the invention and are not necessarily drawn to scale. In the drawings, the same reference numerals always denote the same or similar parts. Wherein:

[0028] Figures 1 to 4 This is a schematic diagram of the semiconductor structure under each step of a method for forming a memory node contact structure according to an exemplary embodiment;

[0029] Figure 5 It is through Figures 1 to 4 A schematic diagram of the semiconductor structure after processing by the method for forming the memory node contact structure is shown;

[0030] Figures 6 to 9 This is a schematic diagram of the semiconductor structure under each step of a method for forming a memory node contact structure according to another exemplary embodiment;

[0031] Figure 10 It is through Figures 6 to 9 A schematic diagram of the semiconductor structure after processing by the method for forming the memory node contact structure is shown;

[0032] Figure 11This is a schematic diagram of a semiconductor structure under a step of a method for forming a memory node contact structure according to yet another exemplary embodiment.

[0033] The annotations in the attached figures are explained as follows:

[0034] 100. Substrate;

[0035] 110. Active region;

[0036] 111. Groove;

[0037] 200. Bitline structure;

[0038] 210. Metallic layer;

[0039] 300. Contact hole;

[0040] 400. Silicon crystal;

[0041] 410. Gap;

[0042] α. Angle;

[0043] X. First direction;

[0044] Y. Second direction;

[0045] I. First Region;

[0046] II. Second Region;

[0047] III. Third Region. Specific Implementation

[0048] Typical embodiments embodying the features and advantages of the present invention will be described in detail in the following description. It should be understood that the present invention can have various variations in different embodiments without departing from the scope of the present invention, and the description and drawings therein are for illustrative purposes only and not intended to limit the present invention.

[0049] In the following description of various exemplary embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate by way of example different exemplary structures, systems, and steps that can implement various aspects of the invention. It should be understood that other specific embodiments of the components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the invention. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe various exemplary features and elements of the invention, these terms are used herein for convenience only, such as the orientation according to the examples shown in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the invention.

[0050] Example 1 of the method for forming the contact structure of storage nodes

[0051] See Figures 1 to 4 The diagrams illustrate, respectively, the structural schematics of the semiconductor structure under each step of the method for forming the memory node contact structure proposed in this invention. In this exemplary embodiment, the method for forming the memory node contact structure proposed in this invention is described using a memory node applied to a DRAM device as an example. It will be readily understood by those skilled in the art that various modifications, additions, substitutions, deletions, or other changes may be made to the specific embodiments described below to apply the relevant designs of this invention to other types of semiconductor structures or other processes; these changes are still within the scope of the principles of the method for forming the memory node contact structure proposed in this invention.

[0052] In this embodiment, the method for forming the storage node contact structure proposed in this invention includes the following steps:

[0053] A substrate 100 is provided, and a bit line structure 200 is formed on the surface of the substrate 100. Contact holes 300 are formed between the bit line structures 200.

[0054] A silicon crystal 400 is grown within a contact hole 300 using an epitaxial growth process. During the growth process, a doping source is added, and the doping concentration of the doping source at the end of the growth is greater than the doping concentration at the beginning of the growth, so as to form a gradient structure of silicon crystal 400 that transitions from monocrystalline silicon to heavily doped polycrystalline silicon within the contact hole 300.

[0055] Through the above design, the present invention can reduce the resistance of the memory node contact structure while improving the contact process efficiency and reducing production costs.

[0056] Based on the above exemplary description of the design concept of the method for forming the storage node contact structure proposed in this invention, the following will be combined with Figures 1 to 4 The structural states of the semiconductor structure at each step in this embodiment are described.

[0057] like Figure 1 As shown, this diagram represents a schematic representation of a semiconductor structure in the step of "providing substrate 100". In this step, the semiconductor structure includes substrate 100, bit line structures 200, and contact holes 300. Specifically, an active region 110 is formed in substrate 100, bit line structures 200 are formed on the surface of substrate 100, and contact holes 300 are formed between adjacent bit line structures 200.

[0058] Optionally, such as Figures 2 to 4As shown, in this embodiment, the growth process of the silicon crystal 400 can include multiple growth stages. Based on this, the doping concentration of the dopant source in these growth stages can gradually increase. Here, "gradually increasing" can be understood as follows: regardless of whether the doping concentration of the dopant source is a constant or changing value in any growth stage, the minimum doping concentration of the dopant source in one growth stage is greater than or equal to the maximum doping concentration in the previous growth stage, and less than or equal to the minimum doping concentration in the subsequent growth stage. In other embodiments, the growth process of the silicon crystal 400 can also be a single growth stage, in which case the doping concentration of the dopant source in that growth stage can gradually increase.

[0059] Furthermore, such as Figures 2 to 4 As shown, the growth process based on silicon crystal 400 includes a multi-stage growth process design. In this embodiment, the doping concentration of the dopant source in any growth stage can be constant. Furthermore, the doping concentration of the dopant source in any growth stage is greater than the doping concentration of the previous growth stage and less than the doping concentration of the subsequent growth stage.

[0060] It should be noted that in other embodiments, regardless of whether the growth process of the silicon crystal 400 includes multiple growth stages, the doping concentration of the dopant source during the growth process can be designed to gradually increase. That is, during the growth process of the silicon crystal 400, the doping concentration perpendicular to the growth point at any given moment is greater than the doping concentration at the previous moment, and this is not limited to this embodiment.

[0061] Furthermore, such as Figures 2 to 4 As shown, based on a process design where the doping concentration of the dopant source is constant in each growth stage of the silicon crystal 400, in this embodiment, the growth process of the silicon crystal 400 can sequentially include a first growth stage, a second growth stage, and a third growth stage. The doping concentration of the dopant source in the first growth stage is constant at a first concentration, the doping concentration in the second growth stage is constant at a second concentration, and the doping concentration in the third growth stage is constant at a third concentration. Furthermore, the first concentration is less than the second concentration, and the second concentration is less than the third concentration.

[0062] like Figure 2The diagram illustrates a representative schematic of a semiconductor structure during the "first growth stage of silicon crystal 400". In this step, the semiconductor structure includes a substrate 100, a bit line structure 200, contact holes 300, and a first region I of silicon crystal 400 grown in the first growth stage. Specifically, the silicon crystal 400 in the first region I grows within the contact holes 300, growing upwards from the bottom of the holes. During the first growth stage, the doping source can be initially turned off to promote the formation of an undoped single-crystal epitaxial growth layer, ensuring the stability of the single-crystal silicon epitaxial growth. Subsequently, the doping source can be turned on, and the doping concentration perpendicular to the doping point can be controlled to remain constant at a first concentration to form doped single-crystal silicon. Furthermore, the doping concentration of the interface single-crystal silicon is increased through diffusion from the doping source, thereby obtaining a first region I with low resistance (including bulk resistance and interface resistance).

[0063] Furthermore, for the first growth stage of silicon crystal 400, taking phosphorus (P) as an example, the first concentration can be 7E+20 / cm³. 3 ~8E+20 / cm 3 A constant value, for example, 7E+20 / cm 3 7.5E+20 / cm 3 8E+20 / cm 3 In other embodiments, the first concentration of the dopant source in the first growth stage may also be less than 7E+20 / cm². 3 Or it may be greater than 8E+20 / cm 3 For example, 6.9E+20 / cm 3 8.2E+20 / cm 3 Examples of such examples are not limited to this embodiment.

[0064] like Figure 3 The diagram illustrates a representative schematic of a semiconductor structure during the "second growth stage of silicon crystal 400". In this step, the semiconductor structure includes a substrate 100, a bit line structure 200, a contact hole 300, and a first region I and a second region II of the silicon crystal 400 grown in the first and second growth stages. Specifically, the silicon crystal 400 in the second region II is grown within the contact hole 300 and grows upwards from the top of the first region I.

[0065] Furthermore, for the second growth stage of silicon crystal 400, taking phosphorus as an example, the second concentration can be 8.5E+20 / cm³. 3 ~9.5E+20 / cm 3 A constant value, for example, 8.5E+20 / cm 3 9E+20 / cm 3 9.5E+20 / cm 3In other embodiments, the second concentration of the dopant source in the second growth stage may also be less than 8.5E+20 / cm². 3 Or it may be greater than 9.5E+20 / cm 3 For example, 8.4E+20 / cm 3 9.7E+20 / cm 3 Examples of such examples are not limited to this embodiment.

[0066] like Figure 4 The diagram illustrates a representative semiconductor structure during the third growth stage of silicon crystal 400. In this stage, the semiconductor structure includes a substrate 100, bit line structures 200, contact holes 300, and first regions I, second regions II, and third regions III of the silicon crystal 400 grown in the first, second, and third growth stages. Specifically, the silicon crystal 400 in third region III grows within the contact holes 300 and grows upwards from the top of second region II. During the third growth stage, due to the continued increase in the doping concentration of the doping source, the silicon crystal 400 gradually forms heavily doped polycrystalline silicon in third region III, improving the growth rate and growth uniformity.

[0067] Furthermore, for the third growth stage of silicon crystal 400, taking phosphorus as an example of a doping source, the third concentration can be 1E+21 / cm². 3 ~1.1E+21 / cm 3 A constant value, for example, 1E+21 / cm 3 1.05E+21 / cm 3 1.1E+21 / cm 3 In other embodiments, the third concentration of the dopant source in the third growth stage may also be less than 1E+21 / cm. 3 Or it may be greater than 1.1E+21 / cm 3 For example, 0.99E+21 / cm 3 1.12E+21 / cm 3 Examples of such examples are not limited to this embodiment.

[0068] Furthermore, the growth process based on silicon crystal 400 includes a three-stage growth process design. Taking phosphorus (P) as the doping source as an example, the first concentration can be 7.5E+20 / cm³. 3 The second concentration can be 9E+20 / cm 3 The third concentration can be 1.05E+21 / cm. 3 .

[0069] Example 2 of the method for forming the contact structure of storage nodes

[0070] Based on the above detailed description of an exemplary embodiment of the method for forming the storage node contact structure proposed in this invention, the following will be combined with... Figures 6 to 9 Another exemplary embodiment of the method for forming the storage node contact structure proposed in this invention will be described.

[0071] See Figures 6 to 9 The diagrams illustrate, respectively, the structural schematics of the semiconductor structure under each step of the method for forming the memory node contact structure proposed in this invention. In this exemplary embodiment, the method for forming the memory node contact structure proposed in this invention is substantially the same as the process design of the first embodiment described above. The main differences between this embodiment and the first embodiment described above will be explained below.

[0072] like Figures 6 to 9 As shown, in this embodiment, before growing the silicon crystal 400, a groove 111 is formed at the bottom of the contact hole 300 corresponding to the active region 110. The axial direction of the groove 111 has an angle α greater than 0° and less than 90° with the vertical direction. Based on this, when growing the silicon crystal 400, an epitaxial growth process is used, starting from the groove 111. During the growth process, the growth rate of the silicon crystal 400 along the first direction X and the second direction Y is controlled, so that at the beginning of the growth, the growth rate of the silicon crystal 400 along the first direction X is greater than the growth rate along the second direction Y, and at the end of the growth, the growth rate of the silicon crystal 400 along the first direction X is equal to the growth rate along the second direction Y, thereby forming a gap 410 between the silicon crystal 400 and the sidewalls of the bit line structure 200 on both sides along the second direction Y. Wherein, the first direction X is the axial direction of the groove 111, and the second direction Y is perpendicular to the first direction X in the vertical plane. Through the above design, the present invention can reduce the resistance of the memory node contact structure while reducing the parasitic capacitance between the memory node contact structure and the bit line structure.

[0073] like Figure 6 As shown, this diagram represents a typical semiconductor structure in the "forming groove 111" step. In this step, the semiconductor structure includes a substrate 100, bit line structures 200, and contact holes 300. Specifically, an active region 110 is formed in the substrate 100, bit line structures 200 are formed on the surface of the substrate 100, contact holes 300 are formed between adjacent bit line structures 200, and a groove 111 is formed on the bottom of the contact hole 300 corresponding to the active region 110.

[0074] Optionally, in this embodiment, during the growth of the silicon crystal 400, the growth rate of the silicon crystal 400 along the first direction X and the second direction Y can be controlled by adding an inhibitor and controlling the inhibitor content. The amount of inhibitor added is negatively correlated with the epitaxial growth nucleation rate of the silicon crystal 400. Furthermore, the amount of inhibitor added at the end of growth is less than the amount added at the beginning of growth.

[0075] Optionally, such as Figures 7 to 9 As shown, in this embodiment, the growth process of the silicon crystal 400 can include multiple growth stages. Based on this, the amount of inhibitor added in these growth stages can be gradually decreased. Here, "gradually decreased" can be understood as follows: regardless of whether the amount of inhibitor added in any growth stage is a constant or a changing value, the minimum amount of inhibitor added in one growth stage is greater than or equal to the maximum amount added in the previous growth stage, and less than or equal to the minimum amount added in the subsequent growth stage. In other embodiments, the growth process of the silicon crystal 400 can also be a single growth stage, in which case the amount of inhibitor added in that growth stage can be gradually decreased.

[0076] Furthermore, in this embodiment, during the growth of the silicon crystal 400, the amount of inhibitor added at the end of the growth can be 0 or not. In other words, during the growth of the silicon crystal 400, the amount of inhibitor added at the beginning of the growth can be gradually reduced to 0, or gradually reduced to another amount.

[0077] Furthermore, such as Figures 7 to 9 As shown, the growth process of silicon crystal 400 includes a process design with multiple growth stages. In this embodiment, the growth process of silicon crystal 400 may sequentially include a first growth stage, a second growth stage, and a third growth stage. The amount of inhibitor added in the first growth stage is constant at a first content, the amount of inhibitor added in the second growth stage is a gradually decreasing content range, and the amount of inhibitor added in the third growth stage is constant at a third content. The first content is greater than or equal to the upper limit of the content range, and the lower limit of the content range is greater than or equal to the third content. In other embodiments, the inhibitor may also be a gradually decreasing content range in the first or second growth stage, and is not limited to this embodiment.

[0078] like Figure 7The diagram illustrates a representative schematic of a semiconductor structure during the "first growth stage of silicon crystal 400". In this step, the semiconductor structure includes a substrate 100, bit line structures 200, contact holes 300, and a first region I of silicon crystal 400 grown in the first growth stage. Specifically, the silicon crystal 400 in the first region I grows within the contact holes 300 and originates from grooves 111. During the growth of the silicon crystal 400 in the first region I, due to the addition of a high amount of inhibitor, the growth rate of the silicon crystal 400 along the first direction X is greater than its growth rate along the second direction Y, thereby creating gaps 410 between the silicon crystal 400 and the bit line structures 200 on both sides along the first direction X.

[0079] Furthermore, for the first growth stage of silicon crystal 400, taking hydrochloric acid (HCl) as an example as an inhibitor, and using the flow rate of hydrochloric acid to characterize the amount of inhibitor added, the first flow rate (i.e., the first content) can be a constant value of 175 sccm to 185 sccm, such as 175 sccm, 180 sccm, 185 sccm, etc. In other embodiments, the first flow rate of hydrochloric acid in the first growth stage can also be less than 175 sccm or greater than 185 sccm, such as 174 sccm, 187 sccm, etc., and is not limited to this embodiment.

[0080] like Figure 8 The diagram illustrates a representative schematic of a semiconductor structure during the "second growth stage of silicon crystal 400". In this step, the semiconductor structure includes a substrate 100, a bit line structure 200, contact holes 300, and a first region I and a second region II of the silicon crystal 400 grown in the first and second growth stages. Specifically, the silicon crystal 400 in the second region II grows within the contact holes 300 and grows upwards from the top of the first region I. During the growth of the silicon crystal 400 in the second region II, the decreasing amount of inhibitor gradually makes the growth rate of the silicon crystal 400 along the first direction X nearly equal to its growth rate along the second direction Y.

[0081] Furthermore, for the second growth stage of silicon crystal 400, taking hydrochloric acid as an example where the inhibitor is included, and using the flow rate of hydrochloric acid to characterize the amount of inhibitor added, the upper limit of the flow rate range (i.e., the content range) can be 130 sccm to 140 sccm, for example, 130 sccm, 135 sccm, 140 sccm, etc., and the lower limit of the flow rate range can be 85 sccm to 95 sccm, for example, 85 sccm, 90 sccm, 95 sccm, etc. In other embodiments, the upper limit of the flow rate range of hydrochloric acid in the second growth stage can also be less than 130 sccm or greater than 140 sccm, for example, 129 sccm, 142 sccm, etc., and the lower limit of the flow rate range of hydrochloric acid in the second growth stage can also be less than 85 sccm or greater than 95 sccm, for example, 84 sccm, 97 sccm, etc., and is not limited to this embodiment.

[0082] like Figure 9 The diagram illustrates a representative schematic of a semiconductor structure during the "third growth stage of silicon crystal 400". In this step, the semiconductor structure includes a substrate 100, a bit line structure 200, a contact hole 300, and first regions I, second regions II, and third regions III of the silicon crystal 400 grown in the first, second, and third growth stages. Specifically, the silicon crystal 400 in third region III grows within the contact hole 300 and grows upwards from the top of second region II. During the growth of silicon crystal 400 in third region III, due to the low content of inhibitor added, the growth rate of silicon crystal 400 along the first direction X is equal to its growth rate along the second direction Y.

[0083] Furthermore, regarding the third growth stage of silicon crystal 400, taking hydrochloric acid as an example where the inhibitor is included, and using the flow rate of hydrochloric acid to characterize the amount of inhibitor added, the third flow rate (i.e., the third content) can be a constant value of 40 sccm to 50 sccm, such as 40 sccm, 45 sccm, 50 sccm, etc. In other embodiments, the third flow rate of hydrochloric acid in the third growth stage can also be less than 40 sccm or greater than 50 sccm, such as 38 sccm, 51 sccm, etc., and is not limited to this embodiment. In other embodiments, the flow rate of hydrochloric acid in the third growth stage can also be a gradually decreasing flow rate range, or a flow rate range that gradually decreases to 0, or even 0.

[0084] Furthermore, taking hydrochloric acid as an example of an inhibitor, and using the flow rate of hydrochloric acid to characterize the amount of inhibitor added, the first flow rate of hydrochloric acid (i.e., the first content) can be 180 sccm, the flow rate range of hydrochloric acid (i.e., the content range) can be 90 sccm to 135 sccm, and the third flow rate of hydrochloric acid (i.e., the third content) can be 45 sccm.

[0085] Optionally, such as Figures 6 to 9 As shown, in this embodiment, the angle α between the axial direction (i.e., the first direction X) of the groove 111 and the vertical direction can be 30° to 60°, such as 30°, 45°, 50°, 60°, etc. In other embodiments, the angle α between the axial direction of the groove 111 and the vertical direction can be less than 30° or greater than 60°, such as 29°, 61°, etc., and is not limited to this embodiment.

[0086] Furthermore, by adjusting the opening shape of the groove 111, such as the axial direction of the groove, and simultaneously controlling the amount of inhibitor added, the morphology of the gap 410 formed between the silicon crystal 400 and the bit line structure 200 can be adjusted. Based on this, such as... Figures 6 to 9 As shown, in this embodiment, the height of the gap 410 can be higher than or equal to the height of the metal layer 210 (e.g., tungsten, W) in the bit line structure 200.

[0087] It should be noted that, as Figures 6 to 9 As shown, in this embodiment, the three growth stages in the silicon crystal 400 growth process can correspond to the three growth stages in the silicon crystal 400 growth process in the first embodiment. Based on this, the process design for different inhibitor addition contents in the three growth stages in this embodiment can also correspond to the process design for different doping concentrations of the dopant source in the three growth stages in the first embodiment. In other words, in this embodiment, the trend of inhibitor addition content can be positively correlated with the trend of doping concentration of the dopant source. However, throughout the entire growth process of the silicon crystal 400, the nodes of inhibitor addition content change are not limited to completely coinciding with the nodes of doping concentration change of the dopant source.

[0088] It should be understood that in various embodiments conforming to the design concept of the memory node contact structure proposed in this invention, the growth process of the silicon crystal 400 may include other numbers of growth stages, or it may be a single, integrated process. In any case, the design of variations in the doping concentration of the dopant source is unaffected by variations in the amount of inhibitor added, and the amount of inhibitor added may remain unchanged.

[0089] Example 3 of the method for forming the contact structure of storage nodes

[0090] Based on the detailed description of the two exemplary embodiments of the method for forming the storage node contact structure proposed in this invention, the following will be combined with... Figure 11 Another exemplary embodiment of the method for forming the storage node contact structure proposed in this invention will be described.

[0091] See Figure 11This example illustrates a schematic diagram of a semiconductor structure under one step of the method for forming a memory node contact structure proposed in this invention. In this exemplary embodiment, the method for forming a memory node contact structure proposed in this invention is substantially the same as the process design of the second embodiment described above. The main differences between this embodiment and the second embodiment described above will be explained below.

[0092] like Figure 11 As shown, in this embodiment, the angle α between the axial direction (i.e., the first direction X) of the groove 111 opening and the vertical direction is larger than the angle α in the second embodiment. Based on this, the height angle of the gap 410 formed by the silicon crystal 400 growing from the groove 111 is lower than the height of the gap 410 in the second embodiment. Therefore, by adjusting the opening shape of the groove 111, such as the axial direction of the groove opening, the morphology of the gap 410 formed between the silicon crystal 400 and the bit line structure 200 can be adjusted.

[0093] It should be noted that the methods for forming the storage node contact structure shown in the accompanying drawings and described in this specification are merely a few examples of many methods capable of employing the principles of the present invention. It should be clearly understood that the principles of the present invention are by no means limited to any detail or step of the methods for forming the storage node contact structure shown in the accompanying drawings or described in this specification.

[0094] Based on the detailed description of several exemplary embodiments of the method for forming the storage node contact structure proposed in this invention, the following will be combined with... Figure 5 or Figure 10 An exemplary embodiment of the semiconductor structure proposed in this invention will be described.

[0095] like Figure 5 or Figure 10 As shown, in this embodiment, the semiconductor structure proposed in this invention includes a substrate 100, a bit line structure 200 formed on the surface of the substrate 100, contact holes 300 formed between the bit line structures 200, and a silicon crystal gradient structure transitioning from single-crystal silicon to heavily doped polycrystalline silicon formed within the contact holes 300. Through the above design, this invention can meet the industry requirements for the resistance of the contact structure in the active region 110, and while reducing the resistance of the contact structure in the memory node, improve the contact process efficiency and reduce production costs.

[0096] Optionally, in this embodiment, the silicon crystal gradient structure described above can be used as a storage node contact structure.

[0097] Optionally, in this embodiment, the aforementioned silicon crystal gradient structure may include a first region I, a second region II, and a third region III. Specifically, the first region I may be monocrystalline silicon, the second region II may be a transition from monocrystalline silicon to polycrystalline silicon, and the third region III may be polycrystalline silicon (e.g., heavily doped polycrystalline silicon). Based on this, the doping concentration of the first region I may be 7E+20 / cm³. 3 ~8E+20 / cm 3 The doping concentration in region II can be 8.5E+20 / cm². 3 ~9.5E+20 / cm 3 The doping concentration in region III can be 1E+21 / cm. 3 ~1.1E+21 / cm 3 .

[0098] It should be noted that the semiconductor structures shown in the accompanying drawings and described in this specification are merely a few examples among many semiconductor structures from which the principles of the invention can be employed. It should be clearly understood that the principles of the invention are by no means limited to any detail or structure of the semiconductor structures shown in the accompanying drawings or described in this specification.

[0099] In summary, this invention introduces a doping source during silicon crystal growth and controls the doping concentration at the end of growth to be lower than the initial doping concentration, thereby forming a gradient silicon crystal structure transitioning from monocrystalline silicon to heavily doped polycrystalline silicon within the contact holes. Through this design, this invention can reduce the resistance of the memory node contact structure while improving contact process efficiency and reducing production costs.

[0100] The foregoing has described in detail, and / or illustrated, exemplary embodiments of the method for forming the memory node contact structure and the semiconductor structure proposed in this invention. However, the embodiments of this invention are not limited to the specific embodiments described herein; rather, components and / or steps of each embodiment may be used independently and separately from other components and / or steps described herein. Each component and / or step of one embodiment may also be used in combination with other components and / or steps of other embodiments. In describing the elements / components / etc. described and / or illustrated herein, the terms “a,” “an,” and “the above” are used to indicate the presence of one or more elements / components / etc. The terms “comprising,” “including,” and “having” are used to indicate an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to those listed. Furthermore, the terms “first” and “second” in the claims and specification are used only as illustrative marks and are not intended to limit the numerical scope of the subject matter.

[0101] Although the method for forming the memory node contact structure and the semiconductor structure proposed in this invention have been described according to different specific embodiments, those skilled in the art will recognize that modifications can be made to the implementation of this invention within the spirit and scope of the claims.

Claims

1. A method for forming a storage node contact structure, characterized in that, Includes the following steps: A substrate is provided, wherein bit line structures are formed on the surface of the substrate, and contact holes are formed between the bit line structures; A groove is formed at the bottom of the contact hole corresponding to the active area, and the axial direction of the groove opening has an angle greater than 0° and less than 90° with the vertical direction; Silicon crystals are grown in the contact holes using an epitaxial growth process. During the growth process, a doping source is added, and the doping concentration of the doping source at the end of the growth is greater than the doping concentration at the beginning of the growth, so as to form a silicon crystal gradient structure in the contact holes that transitions from monocrystalline silicon to heavily doped polycrystalline silicon. The silicon crystal gradient structure forms gaps with the sidewalls of the bit line structure on both sides.

2. The method for forming the storage node contact structure according to claim 1, characterized in that, The growth process of the silicon crystal includes multiple growth stages, and the doping concentration of the dopant source gradually increases in the multiple growth stages.

3. The method for forming the storage node contact structure according to claim 2, characterized in that, The doping concentration of the dopant source remains constant in any of the growth stages.

4. The method for forming the storage node contact structure according to claim 3, characterized in that, The growth process of the silicon crystal sequentially includes a first growth stage, a second growth stage, and a third growth stage. The doping concentration of the dopant source in the first growth stage is a constant first concentration, the doping concentration of the dopant source in the second growth stage is a constant second concentration, and the doping concentration of the dopant source in the third growth stage is a constant third concentration; wherein, the first concentration is less than the second concentration, and the second concentration is less than the third concentration.

5. The method for forming the storage node contact structure according to claim 4, characterized in that, The doping source contains phosphorus, and the first concentration is 7E+20 / cm³. 3 ~8E+20 / cm 3 The second concentration is 8.5E+20 / cm. 3 ~9.5E+20 / cm 3 The third concentration is 1E+21 / cm. 3 ~1.1E+21 / cm 3 .

6. The method for forming the storage node contact structure according to claim 5, characterized in that, The first concentration was 7.5E+20 / cm. 3 ; and / or, the second concentration is 9E+20 / cm 3 ; and / or, the third concentration is 1.05E+21 / cm³. 3 .

7. The method for forming the storage node contact structure according to claim 1, characterized in that, The doping concentration of the dopant source gradually increases during the growth process.

8. The method for forming a storage node contact structure according to any one of claims 1 to 7, characterized in that, When growing the silicon crystal, it starts from the groove. During the growth process, the growth rate of the silicon crystal along the first direction and the second direction is controlled so that at the beginning of the growth, the growth rate of the silicon crystal along the first direction is greater than the growth rate along the second direction, and at the end of the growth, the growth rate of the silicon crystal along the first direction is equal to the growth rate along the second direction, thereby forming gaps between the silicon crystal and the sidewalls of the bit line structure on both sides along the second direction; wherein, the first direction is the axial direction of the groove opening, and the second direction is perpendicular to the first direction in the vertical plane.

9. The method for forming a storage node contact structure according to claim 8, characterized in that, During the growth of the silicon crystal, the growth rate of the silicon crystal along the first direction and the second direction is controlled by adding inhibitors and controlling the content of the inhibitors. The content of the added inhibitors is negatively correlated with the nucleation rate of the epitaxial growth of the silicon crystal. The content of the added inhibitors at the end of the growth is less than the content added at the beginning of the growth.

10. The method for forming a storage node contact structure according to claim 9, characterized in that, The amount of the inhibitor added at the end of the growth period is 0.

11. The method for forming a storage node contact structure according to claim 9, characterized in that, The growth process of the silicon crystal includes multiple growth stages, and the amount of the inhibitor added in each of the multiple growth stages gradually decreases.

12. The method for forming a storage node contact structure according to claim 11, characterized in that, The growth process of the silicon crystal sequentially includes a first growth stage, a second growth stage, and a third growth stage. The amount of inhibitor added in the first growth stage is constant at a first content, the amount of inhibitor added in the second growth stage is a gradually decreasing content range, and the amount of inhibitor added in the third growth stage is constant at a third content. Wherein, the first content is greater than or equal to the upper limit of the content range, and the lower limit of the content range is greater than or equal to the third content.

13. The method for forming a storage node contact structure according to claim 12, characterized in that, The inhibitor contains hydrochloric acid, and the amount of the inhibitor added is characterized by the flow rate of the hydrochloric acid; wherein, the first content is 175 sccm to 185 sccm, the upper limit of the content range is 130 sccm to 140 sccm, the lower limit of the content range is 85 sccm to 95 sccm, and the third content is 40 sccm to 50 sccm.

14. The method for forming a storage node contact structure according to claim 13, characterized in that, The first content is 180 sccm; and / or, the upper limit of the content range is 135 sccm, and the lower limit of the content range is 90 sccm; and / or, the third content is 45 sccm.

15. A semiconductor structure, characterized in that, The semiconductor structure includes a substrate, on the surface of which bit line structures are formed. Contact holes are formed between each bit line structure. A groove is formed at the bottom of the contact hole corresponding to the active region. The axial direction of the groove opening has an angle greater than 0° and less than 90° with the vertical direction. A silicon crystal gradient structure transitioning from single-crystal silicon to heavily doped polycrystalline silicon is formed inside the contact hole. The silicon crystal gradient structure forms gaps with the sidewalls of the bit line structures on both sides.

16. The semiconductor structure according to claim 15, characterized in that, The silicon crystal gradient structure is used as the contact structure for the storage node.

17. The semiconductor structure according to claim 15, characterized in that, The silicon crystal gradient structure includes a first region, a second region, and a third region. The first region is monocrystalline silicon, the second region is polycrystalline silicon, and the doping concentration of the first region is 7E+20 / cm². 3 ~8E+20 / cm 3 The doping concentration in the second region is 8.5E+20 / cm. 3 ~9.5E+20 / cm 3 The doping concentration of the third region is 1E+21 / cm. 3 ~1.1E+21 / cm 3 .

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