Method of manufacturing a semiconductor structure, semiconductor structure and semiconductor memory

Abstract

Embodiments of the present disclosure provide a preparation method of a semiconductor structure, a semiconductor structure and a semiconductor memory. The preparation method comprises: providing a substrate; performing a patterning process on the substrate to form a substrate layer and a plurality of silicon pillars; forming an oxide layer on a surface of the substrate layer between the plurality of silicon pillars; forming an isolation structure above the oxide layer, a gap being formed between an upper portion of the isolation structure and the silicon pillars; forming a first conductive layer in the gap; removing part of the isolation structure to retain the isolation structure below the first conductive layer to form an isolation layer; and forming a dielectric layer and a second conductive layer on the isolation layer, the oxide layer, the first conductive layer and a surface of the silicon pillars.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor memory. Background Technology

[0002] Capacitors are the components in Dynamic Random Access Memory (DRAM) used to store data. The data value of each memory cell is determined by the charge carried by its capacitor. However, as the integration density of DRAM increases, the size and area of ​​these capacitors decrease relatively. Summary of the Invention

[0003] The technical solution disclosed herein is implemented as follows:

[0004] In a first aspect, embodiments of this disclosure provide a method for fabricating a semiconductor structure, comprising:

[0005] Provide substrate;

[0006] The substrate is patterned to form a substrate layer and multiple silicon pillars;

[0007] An oxide layer is formed on the surface of the substrate layer between the plurality of silicon pillars;

[0008] An isolation structure is formed above the oxide layer, and a gap is formed between the upper part of the isolation structure and the silicon pillar;

[0009] A first conductive layer is formed in the gap;

[0010] Remove part of the isolation structure, retain the isolation structure below the first conductive layer, to form an isolation layer;

[0011] A dielectric layer and a second conductive layer are formed on the surfaces of the isolation layer, the oxide layer, the first conductive layer, and the silicon pillar.

[0012] In some embodiments, the patterning process of the substrate to form a substrate layer and a plurality of silicon pillars includes:

[0013] A first mask layer is formed over the substrate; wherein the first mask layer has a first pattern extending along a first direction;

[0014] Using the first mask layer as a mask, the first pattern is transferred to a portion of the substrate;

[0015] A second mask layer is formed over the substrate; wherein the second mask layer has a second pattern extending along a second direction;

[0016] Using the second mask layer as a mask, the second pattern is transferred to a portion of the substrate to form the substrate layer and the plurality of silicon pillars.

[0017] In some embodiments, the patterning process of the substrate to form a substrate layer and a plurality of silicon pillars includes:

[0018] A third mask layer is formed above the substrate; the third mask layer includes a plurality of sub-masks arranged in an array, and the third mask layer has a third pattern, which is composed of a first pattern extending along a first direction and a second pattern extending along a second direction;

[0019] Using the third mask layer as a mask, the third pattern is transferred to a portion of the substrate to form the substrate layer and the plurality of silicon pillars.

[0020] In some embodiments, forming an oxide layer on the substrate surface between the plurality of silicon pillars includes:

[0021] An initial oxide layer is formed on the surface of the plurality of silicon pillars and on the surface of the substrate layer between the plurality of silicon pillars;

[0022] The initial oxide layer located on the surface of the plurality of silicon pillars is removed, and the remaining initial oxide layer forms the oxide layer.

[0023] In some embodiments, forming an isolation structure over the oxide layer includes:

[0024] A first isolation structure is formed on the surface of the oxide layer;

[0025] A second isolation structure is formed above the first isolation structure, and a gap is formed between the second isolation structure and the silicon pillar. The first isolation structure and the second isolation structure constitute the isolation structure.

[0026] In some embodiments, forming a first isolation structure on the surface of the oxide layer includes:

[0027] An initial first isolation structure is formed on the surface of the oxide layer and each of the silicon pillars;

[0028] The initial first isolation structure is partially removed, and the initial first isolation structure remaining on the surface of the oxide layer forms the first isolation structure.

[0029] In some embodiments, forming a second isolation structure above the first isolation structure includes:

[0030] A sacrificial layer is formed on the surface of the silicon pillar;

[0031] An initial second isolation structure is formed on the surface of the sacrificial layer and above the first isolation structure;

[0032] Remove the initial second isolation structure located above the plane containing the top surface of the sacrificial layer, and retain the initial second isolation structure to form the second isolation structure;

[0033] The sacrificial layer is removed to form the gap between the isolation structure and the silicon pillar.

[0034] In some embodiments, removing a portion of the isolation structure includes:

[0035] Remove the second isolation structure and the first isolation structure located below the second isolation structure, while retaining the first isolation structure below the first conductive layer.

[0036] In some embodiments, the sacrificial layer is formed by thermal oxidation.

[0037] In some embodiments, forming a first conductive layer in the gap includes:

[0038] An initial first conductive layer is formed in the gap, on the top surface of the plurality of silicon pillars and the isolation structure;

[0039] The initial first conductive layer located above the plane containing the top surface of the silicon pillar is removed, and the remaining initial first conductive layer forms the first conductive layer.

[0040] In some embodiments, the method further includes, during the removal of the initial first conductive layer located above the plane containing the top surface of the silicon pillar:

[0041] Remove the isolation structure located above the plane containing the top surface of the silicon pillar.

[0042] In some embodiments, forming a dielectric layer and a second conductive layer on the surfaces of the isolation layer, the oxide layer, the first conductive layer, and the silicon pillar includes:

[0043] The dielectric layer is formed on the surfaces of the isolation layer, the oxide layer, the first conductive layer, and the silicon pillar;

[0044] The second conductive layer is formed on the surface of the dielectric layer.

[0045] In some embodiments, the second conductive layer completely fills the gaps in the dielectric layer.

[0046] In some embodiments, the first isolation structure and the second isolation structure are made of the same material.

[0047] In some embodiments, the bottom of the isolation structure completely covers the oxide layer.

[0048] In some embodiments, the bottom side of the isolation structure is in direct contact with the adjacent silicon pillar.

[0049] In some embodiments, the first conductive layer is used to form the lower electrode of the semiconductor structure, and the second conductive layer is used to form the upper electrode of the semiconductor structure.

[0050] In some embodiments, the plurality of silicon pillars are arranged in an array.

[0051] Secondly, embodiments of this disclosure provide a semiconductor structure prepared by the preparation method described in the first aspect.

[0052] Thirdly, embodiments of this disclosure provide a semiconductor memory, including the semiconductor structure described in the second aspect.

[0053] This disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method involves providing a substrate; patterning the substrate to form a substrate layer and multiple silicon pillars; forming an oxide layer on the surface of the substrate layer between the silicon pillars; forming an isolation structure above the oxide layer, with a gap between the upper part of the isolation structure and the silicon pillars; forming a first conductive layer in the gap; removing part of the isolation structure, retaining the isolation structure below the first conductive layer, to form an isolation layer; and forming a dielectric layer and a second conductive layer on the surfaces of the isolation layer, oxide layer, first conductive layer, and silicon pillars. Thus, in fabricating the semiconductor structure, by forming a gap between the silicon pillars and the isolation structure, forming the first conductive layer in the gap, then removing part of the isolation structure to obtain the isolation layer, and further forming the dielectric layer and the second conductive layer, this fabrication method is simple, easy to implement, and can save on the manufacturing cost of the semiconductor structure. Attached Figure Description

[0054] Figure 1 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0055] Figure 2 This is a schematic diagram of the structure of a substrate provided in an embodiment of the present disclosure;

[0056] Figure 3 This is a schematic diagram of the structure obtained after forming a substrate layer and silicon pillars according to an embodiment of the present disclosure;

[0057] Figure 4 This is a schematic diagram of the structure obtained after forming the first mask layer according to an embodiment of the present disclosure;

[0058] Figure 5This is a schematic diagram of a structure obtained after transferring a first pattern, as provided in an embodiment of the present disclosure;

[0059] Figure 6 This is a schematic diagram of the structure obtained after forming the second mask layer according to an embodiment of the present disclosure;

[0060] Figure 7 This is a schematic diagram of the structure obtained after forming the third mask layer according to an embodiment of the present disclosure;

[0061] Figure 8 This is a schematic diagram of the structure obtained after forming an initial oxide layer, provided by an embodiment of the present disclosure;

[0062] Figure 9 This is a schematic diagram of the structure obtained after forming an oxide layer, provided by an embodiment of the present disclosure;

[0063] Figure 10 This is a schematic diagram of a structure obtained after forming an initial first isolation structure, as provided in an embodiment of the present disclosure;

[0064] Figure 11 This is a schematic diagram of a structure obtained after forming a first isolation structure, provided by an embodiment of the present disclosure;

[0065] Figure 12 This is a schematic diagram of a structure obtained after forming a sacrificial layer, provided by an embodiment of the present disclosure;

[0066] Figure 13 This is a schematic diagram of a structure obtained after forming an initial second isolation structure, as provided in an embodiment of this disclosure;

[0067] Figure 14 This is a schematic diagram of a structure obtained after forming a second isolation structure, provided by an embodiment of the present disclosure;

[0068] Figure 15 This is a schematic diagram of the structure obtained after removing the sacrificial layer, provided in an embodiment of the present disclosure;

[0069] Figure 16 This is a schematic diagram of a structure obtained after forming an initial first conductive layer, as provided in an embodiment of the present disclosure.

[0070] Figure 17 This is a schematic diagram of a structure obtained after forming a first conductive layer, provided by an embodiment of the present disclosure;

[0071] Figure 18 This is a schematic diagram of the structure obtained after forming an isolation layer, provided by an embodiment of the present disclosure;

[0072] Figure 19 This is a schematic diagram of the structure obtained after forming a dielectric layer according to an embodiment of the present disclosure;

[0073] Figure 20 This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of the present disclosure;

[0074] Figure 21 This disclosure provides a simplified schematic diagram of a semiconductor structure formation process.

[0075] Figure 22 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0076] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of the relevant disclosure and not intended to limit it. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0077] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure.

[0078] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0079] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0080] As the integration density of dynamic random access memory (DRAM) increases, the size and area of ​​capacitors in DRAM also decrease relatively. For example, as the semiconductor industry moves towards higher device density and higher performance, three-dimensional (3D) semiconductor devices, such as 3D memory, have been developed. With the development of 3D semiconductor devices, there is a need to develop capacitors for these devices. However, the fabrication process for capacitors in 3D memory is complex and costly, often failing to meet practical requirements.

[0081] Based on this, the present disclosure provides a method for fabricating a semiconductor structure. The basic idea of ​​this method is as follows: providing a substrate; patterning the substrate to form a substrate layer and multiple silicon pillars; forming an oxide layer on the surface of the substrate layer between the multiple silicon pillars; forming an isolation structure above the oxide layer, with a gap between the upper part of the isolation structure and the silicon pillars; forming a first conductive layer in the gap; removing part of the isolation structure, retaining the isolation structure below the first conductive layer to form an isolation layer; and forming a dielectric layer and a second conductive layer on the surfaces of the isolation layer, oxide layer, first conductive layer, and silicon pillars. Thus, in fabricating the semiconductor structure, by forming a gap between the silicon pillars and the isolation structure, forming the first conductive layer in the gap, then removing part of the isolation structure to obtain the isolation layer, and further forming the dielectric layer and the second conductive layer, this fabrication method has a simple process, is easy to implement, and can improve manufacturing yield.

[0082] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0083] Before proceeding with the detailed description, it should be noted that in the following description of the embodiments, the correspondence between the reference numerals used in the drawings and the components in the semiconductor structure is as follows:

[0084] 10: Substrate; 11: Substrate layer; 12: Silicon pillar; 131: First mask layer; 1311: First trench; 132: Second mask layer; 1321: Second trench; 133: Intermediate structure; 134: Submask; 141: Initial oxide layer; 14: Oxide layer; 151: Initial first isolation structure; 15: First isolation structure; 16: Sacrificial layer; 171: Initial second isolation structure; 17: Second isolation structure; 181: Initial first conductive layer; 18: First conductive layer; 19: Isolation layer; 20: Dielectric layer; 21: Second conductive layer.

[0085] In one embodiment of this disclosure, see [link to embodiment]. Figure 1 This illustrates a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 1 As shown, the method includes:

[0086] S101, Provide substrate.

[0087] It should be noted that the method for fabricating a semiconductor structure provided in this disclosure can be a capacitor, which can be applied to semiconductor devices with 3D structures (e.g., 3D DRAM structures). This method can be applied to a transistor-on-the-capacitor (TOC) architecture to form the capacitor within that architecture.

[0088] See Figure 2The diagram shows a schematic structural diagram of a substrate 10 provided in an embodiment of the present disclosure. (a) and (b) are cross-sectional views, and (c) is a top view; (a) is a cross-sectional view along the AA' direction in (c), and (b) is a cross-sectional view along the BB' direction in (c).

[0089] It should also be noted that the substrate 10 can be a silicon substrate or other suitable substrate materials such as silicon, germanium, or silicon-germanium compounds, for example, doped or undoped single-crystal silicon substrates, polycrystalline silicon substrates, etc., and there is no specific limitation thereto. In the embodiments of this disclosure, a silicon substrate is used as an example for description.

[0090] S102. Pattern the substrate to form a substrate layer and multiple silicon pillars.

[0091] It should be noted that the substrate 10 is patterned, dividing it into two parts: a substrate layer 11 and a plurality of silicon pillars 12. The upper part of the substrate 10 is patterned to form a plurality of silicon pillars 12, while the lower part of the substrate 10 is not patterned and forms the substrate layer 11.

[0092] See Figure 3 The diagram shows a schematic diagram of the structure obtained after forming a substrate layer 11 and a silicon pillar 12 according to an embodiment of the present disclosure; wherein (a) and (b) are cross-sectional views, and (c) is a top view; (a) is a cross-sectional view in the AA' direction in (c), and (b) is a cross-sectional view in the BB' direction in (c).

[0093] That is, (a) is a cross-sectional view showing the silicon pillars 12 formed in the first direction, and (b) is a cross-sectional view showing the portion where adjacent silicon pillars 12 are not formed in the first direction. Additionally, with Figure 3 Similarly, in the accompanying figures involved in the subsequent steps, (a) in the figures are all cross-sectional views in the AA' direction, (b) in the figures are all cross-sectional views in the BB' direction, and (c) in the figures are all top views, which will not be described again later.

[0094] like Figure 3 As shown, after patterning the substrate 10, the upper part of the substrate 10 is partially removed to form multiple silicon pillars 12, and the substrate 10 remaining below the multiple silicon pillars 12 forms a substrate layer 11. Figure 3 As shown in (a), a gap is formed between adjacent silicon pillars 12 in the AA' direction; as Figure 3 As shown in (b), there is no silicon pillar 12 above the substrate layer 11 in the BB' direction; Figure 3 As shown in (c) in the top view, multiple silicon pillars 12 are formed in this structure.

[0095] The thickness of the substrate layer 11 and the height of the silicon pillar 12 can be set according to the specific requirements of the actual process level, and this embodiment does not impose specific limitations on them.

[0096] In some embodiments, the silicon pillars 12 are arranged in an array.

[0097] It should be noted that multiple silicon pillars 12 can be arranged in a regular array. For example... Figure 3 As shown, multiple silicon pillars 12 are regularly arranged in a first direction and a second direction, with an angle of 90° between the first direction and the second direction, which can form silicon pillars 12 with a square cross-section; in addition, the angle between the first direction and the second direction can also be other angles, such as 60°, which can form silicon pillars 12 with a rhomboid or other shapes.

[0098] Since the multiple silicon pillars 12 formed are arranged in a regular array, the processing method for patterning the substrate can be relatively simple and easy to implement.

[0099] In one possible implementation of patterning the substrate 10 to form a substrate layer 11 and a plurality of silicon pillars 12, the patterning process may include:

[0100] A first mask layer 131 is formed above the substrate 10; wherein the first mask layer 131 has a first pattern extending along a first direction;

[0101] Using the first mask layer 131 as a mask, the first pattern is transferred to a portion of the substrate 10;

[0102] A second mask layer 132 is formed above the substrate 10; wherein the second mask layer 132 has a second pattern extending along a second direction;

[0103] Using the second mask layer 132 as a mask, the second pattern is transferred to a portion of the substrate 10 to form the substrate layer 10 and a plurality of silicon pillars 12.

[0104] It should be noted that when patterning the substrate 10, the substrate 10 can be patterned twice to form multiple silicon pillars 12. Specifically, firstly, the first pattern is transferred to the substrate 10 to obtain a substrate 10 with the first pattern, and then the second pattern is transferred to the substrate 10 that already has the first pattern. The first and second patterns divide the substrate 10 into multiple silicon pillars 12, and the unpatterned substrate 10 is retained to form the substrate layer 11.

[0105] See Figure 4 This illustrates a schematic diagram of the structure obtained after forming the first mask layer 131, as provided in an embodiment of this disclosure. Figure 4As shown in (c), the first mask layer 13 has a first pattern extending along a first direction; as Figure 4 As shown in (a), a mask material is formed above the substrate 10 in the AA' direction; as Figure 4 As shown in (b), no mask material is formed above the substrate 10 in the BB' direction.

[0106] The first pattern is transferred to the substrate 10, a plurality of first trenches 1311 are formed in the substrate 10, and the first mask layer 131 is removed. See also Figure 5 This illustrates a schematic diagram of the structure obtained after transferring a first pattern, as provided in an embodiment of this disclosure. Figure 4 and Figure 5 As shown, the portion of the substrate 10 where the first pattern is transferred using the first mask layer 131 as a mask is the portion used to form the plurality of silicon pillars 12. Here, a certain height of the portion of the substrate 10 not covered by the mask material can be removed by etching (ETCH) to form a plurality of first trenches 1311 in the substrate 10. After the first pattern is transferred to the substrate 10, the first mask layer 131 is removed.

[0107] like Figure 5 As shown in (a), the height of the substrate 10 remains constant in the AA' direction, or may be slightly reduced due to partial loss during the removal of the first mask layer 131; as Figure 5 As shown in (b) in the figure, the upper part of the substrate 10 is removed in the BB' direction, and the height is significantly reduced.

[0108] In addition, such as Figure 5 As shown in (c), in order to distinguish the removed and unremoved portions in the substrate 10, the substrate 10 with the first trench 1311 is shown with an unfilled pattern. However, it can be understood that although the filling pattern is not shown, this portion is made of the same material as the rest.

[0109] After the first pattern is transferred to substrate 10, a second pattern is formed on top of substrate 10. See also Figure 6 This illustrates a schematic diagram of the structure obtained after forming the second mask layer 132, as provided in an embodiment of this disclosure. Figure 5 and 6 As shown, when forming the second mask layer 132, an intermediate structure 133 can be formed in the first trench 1311 first, or the height of the intermediate structure 133 can be higher than the height of the first trench 1311, completely filling the first trench 1311 and covering the substrate 10.

[0110] by Figure 6For example, the intermediate structure 133 fills the first trench 1311. Then, a second mask layer 132 is formed over the intermediate structure 133 and the substrate 10, the second mask layer 132 having a second pattern extending along a second direction. Figure 6 In the first direction, the angle between the second direction and the first direction is 90°. In actual production, this angle can also be set to other angles according to actual needs. This embodiment does not limit the angle.

[0111] like Figure 6 As shown in (a), in the AA' direction, a second mask layer 132 is formed above the substrate 10; as Figure 6 As shown in (b), in the BB' direction, the second mask layer 132 is formed above the intermediate structure 133.

[0112] Using the second mask layer 132 as a mask, the second pattern is transferred to the substrate 10 and the intermediate structure 133, and then the second mask layer 132 and the intermediate structure 133 are removed; wherein the transfer depth of the second pattern is the same as the transfer depth of the first pattern. In this way, the substrate layer 11 and a plurality of silicon pillars 12 are formed.

[0113] like Figure 3 As shown, the transfer of the second pattern forms a second trench 1321 in the substrate 10, and the first trench 1311 and the second trench 1321 together form the gap between the silicon pillars 12.

[0114] It should be noted that the intermediate structure 133 can be a material that is easier to etch and remove than the substrate 10, thereby ensuring that the intermediate structure 133 can be completely removed.

[0115] In another possible implementation of patterning the substrate 10 to form a substrate layer 11 and a plurality of silicon pillars 12, the patterning process may include:

[0116] A third mask layer is formed above the substrate 10; the third mask layer includes a plurality of sub-masks 134 arranged in an array, and the third mask layer has a third pattern, which is composed of a first pattern extending along a first direction and a second pattern extending along a second direction;

[0117] Using the third mask layer as a mask, the third pattern is transferred to a portion of the substrate 10 to form a substrate layer 11 and a plurality of silicon pillars 12.

[0118] It should be noted that, in this embodiment of the present disclosure, the substrate 10 can also be patterned only once to obtain a plurality of silicon pillars 12. First, a third mask layer is formed above the substrate 10. The third mask layer has a third pattern, which is composed of a first pattern and a second pattern. The first pattern extends along a first direction, and the second pattern extends along a second direction. The angle between the first direction and the second direction can be 90° or other angles, and this embodiment of the present disclosure does not specifically limit this. Transferring the third pattern to the substrate 10 yields the substrate layer 10 and the plurality of silicon pillars 12.

[0119] See Figure 7 This illustration shows a schematic diagram of the structure obtained after forming a third mask layer, according to an embodiment of this disclosure. Figure 7 In, such as Figure 7 As shown in (c), the third mask layer consists of multiple sub-masks 134, which can be arranged in a regular array. The angle between the first direction and the second direction is 90°. The position of each sub-mask 134 is the position where each silicon pillar 12 is subsequently formed. Figure 7 As shown in (a), a plurality of sub-masks 134 are formed above the substrate 10 in the AA' direction; as Figure 7 As shown in (b), no submask 134 is formed above the substrate 10 in the BB' direction.

[0120] Using the third mask layer as a mask, the third pattern is transferred to a certain height on the substrate 10, thereby dividing the substrate 10 into an upper part and a lower part. Multiple silicon pillars 12 are formed in the upper part, and a substrate layer 11 is formed in the lower part. The structure after forming the substrate layer 11 and the multiple silicon pillars 12 is as follows: Figure 3 As shown.

[0121] It should also be noted that, such as Figure 3 As shown, when the substrate 10 is patterned, the surface of the substrate layer 11 between the silicon pillars 12 can be formed into an arc shape as shown in the figure.

[0122] It should also be noted that the first mask layer 131, the second mask layer 132, and the third mask layer can all be formed by deposition. The material of the mask layer can be photoresist, etc. The mask layer can be a single layer or a composite mask material can be selected according to the actual situation. When performing steps such as pattern transfer and mask layer removal, the process used can be etching. This disclosure does not specifically limit this aspect.

[0123] S103, An oxide layer is formed on the surface of the substrate layer between multiple silicon pillars.

[0124] It should be noted that after patterning, the substrate 10 is divided into multiple silicon pillars 12 at the top and a substrate layer 11 at the bottom, and then an oxide layer 14 is formed on the surface of the substrate layer 11 between the multiple silicon pillars 12.

[0125] In some embodiments, forming an oxide layer 14 on the surface of the substrate layer 11 between the plurality of silicon pillars 12 may include:

[0126] An initial oxide layer 141 is formed on the surface of the plurality of silicon pillars 12 and on the surface of the substrate layer 11 between the plurality of silicon pillars 12;

[0127] The initial oxide layer 141 located on the surface of the plurality of silicon pillars 12 is removed, and the remaining initial oxide layer 141 forms oxide layer 14.

[0128] It should be noted that during the formation of oxide layer 14, the initial oxide layer 141 is formed first. See [link / reference] Figure 8 This illustrates a schematic diagram of the structure obtained after forming an initial oxide layer 141, as provided in an embodiment of this disclosure. Figure 8 As shown, an initial oxide layer 141 is formed on the surface of a plurality of silicon pillars 12 (in Figure 8 In the process, the surface of the silicon pillar 12 includes the top surface and four side surfaces of the silicon pillar 12, as well as the surface of the substrate layer 11 between the plurality of silicon pillars 12. An initial oxide layer 141 covers the top surface and four side surfaces of the silicon pillar 12.

[0129] like Figure 8 As shown in (a), it can be seen that in the AA' direction, the initial oxide layer 141 is formed on the surface of the substrate layer 11 and the surface of the silicon pillar 12; as Figure 8 As shown in (b) above, it can be seen that there are no silicon pillars in the BB' direction, and the initial oxide layer 141 is formed on the surface of the substrate layer 11; as Figure 8 As shown in (c) in the top view, the initial oxide layer 141 completely covers the substrate layer 11 and the plurality of silicon pillars 12. In order to show the location of the silicon pillars 12, the outline of the initial oxide layer 141 formed on the top surface of the silicon pillars 12 is shown in (c) with a box.

[0130] It should be noted that the material of the initial oxide layer 141 can be an oxide. In this embodiment, the material of the initial oxide layer 141 can be silicon oxide. The initial oxide layer 141 can be formed by deposition, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0131] A portion of the initial oxide layer 141 is removed, and the remaining initial oxide layer 141 forms oxide layer 14. See also Figure 9 This illustrates a schematic diagram of the structure obtained after forming an oxide layer 14, as provided in an embodiment of this disclosure. Figure 8 and Figure 9As shown, the initial oxide layer 141 on the top and side surfaces of each silicon pillar 12 is removed, leaving only the initial oxide layer 141 formed on the surface of the substrate layer 11. The retained initial oxide layer 141 forms the oxide layer 14. The method for removing the initial oxide layer 141 can be etching.

[0132] S104. An isolation structure is formed above the oxide layer, and a gap is formed between the upper part of the isolation structure and the silicon pillar.

[0133] It should be noted that an isolation structure is formed above the oxide layer 14, and a gap is formed between the upper part of the isolation structure and the silicon pillar 12. That is, a "ring of gap" is formed between the isolation structure and the four sides of each silicon pillar.

[0134] In some embodiments, an isolation structure is formed over the oxide layer 14, including:

[0135] A first isolation structure 15 is formed on the surface of the oxide layer 14;

[0136] A second isolation structure 17 is formed above the first isolation structure 15, and a gap is formed between the second isolation structure 17 and the silicon pillar 12. The first isolation structure 15 and the second isolation structure 17 constitute an isolation structure.

[0137] It should be noted that the isolation structure can be composed of a first isolation structure 15 and a second isolation structure 17. When forming the isolation structure, the first isolation structure 15 is first formed on the surface of the oxide layer 14, and then the second isolation structure 17 is formed above the first isolation structure 15. The second isolation structure 17 is formed between the plurality of silicon pillars 12, and a gap is formed between the second isolation structure 17 and the silicon pillars 12. That is, the gap between the isolation structure and the silicon pillars 12 refers to the gap between the second isolation structure 17 and the silicon pillars 12.

[0138] Furthermore, regarding the first isolation structure 15, in some embodiments, the first isolation structure 15 is formed on the surface of the oxide layer 14, including:

[0139] An initial first isolation structure 151 is formed on the surface of the oxide layer 14 and each silicon pillar 12;

[0140] Part of the initial first isolation structure 151 is removed, and the initial first isolation structure 151 remaining on the surface of the oxide layer 14 forms the first isolation structure 15.

[0141] It should be noted that when forming the first isolation structure 15, the initial first isolation structure 151 is formed first. See [link / reference needed]. Figure 10 This illustration shows a schematic diagram of the structure obtained after forming an initial first isolation structure 151, as provided in an embodiment of this disclosure. Figure 10As shown, an initial first isolation structure 151 is formed on the oxide layer 14 and the surface of each silicon pillar 12. The initial first isolation structure 151 covers the top surface and four sides of the silicon pillar 12.

[0142] like Figure 10 As shown in (a), it can be seen that in the AA' direction, the initial first isolation structure 151 is formed on the surface of the oxide layer 14 and the silicon pillar 12; as Figure 10 As shown in (b) above, it can be seen that in the BB' direction, the initial first isolation structure 151 is formed on the surface of the oxide layer 14; as Figure 10 As shown in (c) in the top view, the initial first isolation structure 151 completely covers the oxide layer 14 and the plurality of silicon pillars 12. In order to show the location of the silicon pillars 12, the outline of the initial first isolation structure 151 formed on the top surface of the silicon pillars 12 is shown in (c) with a box.

[0143] It should be noted that the material of the initial first isolation structure 151 can be silicon nitride, and the method of forming the initial first isolation structure 151 can be deposition, such as CVD, PVD, etc.

[0144] The initial first isolation structure 151 is partially removed, and the remaining initial first isolation structure 151 forms the first isolation structure 15.

[0145] See Figure 11 This illustrates a schematic diagram of the structure obtained after forming the first isolation structure 15, as provided in an embodiment of this disclosure. Figure 10 and Figure 11 As shown, the initial isolation structure 151 located on the top surface of each silicon pillar 12 and a portion of the initial first isolation structure 151 located on the side surface of each silicon pillar 12 are removed, leaving only the initial first isolation structure 151 formed on the surface of the oxide layer 14. The retained initial first isolation structure 151 forms the first isolation structure 15. That is, the first isolation structure 15 completely covers the oxide layer 14, and the first isolation structure 15 is in direct contact with the adjacent silicon pillar 12.

[0146] The method for removing the initial first isolation structure 15 can be etching.

[0147] In some embodiments, the second isolation structure 17 is formed above the first isolation structure 15, including:

[0148] A sacrificial layer 16 is formed on the surface of the silicon pillar 12;

[0149] An initial second isolation structure 171 is formed on the surface of the sacrificial layer 16 and above the first isolation structure 15;

[0150] Remove the initial second isolation structure 171 located above the plane where the top surface of the sacrificial layer 16 is located, and the remaining initial second isolation structure 171 forms the second isolation structure 17;

[0151] Remove the sacrificial layer 16 to form a gap between the isolation structure and the silicon pillar 12.

[0152] It should be noted that, during the formation of the second isolation structure 17, a sacrificial layer 16 is first formed on the surface of the plurality of silicon pillars 12. See [link / reference] Figure 12 This illustrates a schematic diagram of the structure obtained after forming a sacrificial layer 16, as provided in an embodiment of this disclosure. Figure 12 As shown, the sacrificial layer 16 is formed on the surface of each silicon pillar 12, specifically on the top surface and four sides of each silicon pillar 12. That is, the sacrificial layer 16 is only formed on the surface of the silicon pillar 12, and will cover the portion of the surface of the first isolation structure 15 adjacent to the contact portion of the silicon pillar, but will not be formed on all surfaces of the first isolation structure 15.

[0153] like Figure 12 As shown in (a) above, it can be seen that in the AA' direction, the sacrificial layer 16 forms the top and side surfaces of the silicon pillar 12; as Figure 10 As shown in (b), it can be seen that there is no silicon pillar 12 in the BB' direction, and the sacrificial layer 16 is not formed on the surface of the first isolation structure 15 (except for the portion of the surface adjacent to the contact position with the silicon pillar 12). Therefore, the sacrificial layer 16 is not visible in the BB' direction; Figure 12 As shown in (c) in the top view, the sacrificial layer 16 completely covers the plurality of silicon pillars 12, and the gaps between the sacrificial layers 16 expose the first isolation structure 15.

[0154] It should be noted that the material of the sacrificial layer 16 can be an oxide, such as silicon oxide. In some embodiments, the sacrificial layer 16 can also be formed by thermal oxidation.

[0155] It should be noted that the sacrificial layer 16 and the oxide layer 14 can be made of the same material, such as silicon oxide. Therefore, they are represented by the same pattern in the accompanying drawings. When forming the sacrificial layer 16 in this step, a thermal oxidation process can be used. This allows direct oxidation of the surface of the silicon pillar 12 to form silicon oxide, resulting in the sacrificial layer 16, without the need for complex processing, thus simplifying the process. In contrast, if a deposition method is used to form the sacrificial layer, the sacrificial layer will also cover the surface of the first isolation structure 15, requiring the removal of this portion of the sacrificial layer, which complicates the process.

[0156] After the sacrificial layer 16 is formed, the initial second isolation structure 171 continues to be formed. See also Figure 13This illustrates a schematic diagram of the structure obtained after forming an initial second isolation structure 171, as provided in an embodiment of this disclosure. Figure 13 As shown, an initial second isolation structure 171 is formed on the surface of the sacrificial layer 16 and above the first isolation structure 15. Figure 13 In the first isolation structure 171, the initial second isolation structure 171 completely covers the sacrificial layer 16 and the first isolation structure 15, and fills the gap between the sacrificial layer 16.

[0157] like Figure 13 As shown in (a), it can be seen that in the AA' direction, the initial second isolation structure 171 is formed on the surfaces of the sacrificial layer 16 and the first isolation structure 15; as Figure 10 As shown in (b) above, it can be seen that in the BB' direction, the initial second isolation structure 171 is completely formed above the first isolation structure 15; Figure 12 As shown in (c) in the top view, the initial second isolation structure 171 completely covers the sacrificial layer 16 and the first isolation structure 15.

[0158] It should be noted that the initial second isolation structure 171 and the first isolation structure 15 can be made of the same material, such as silicon nitride. Therefore, in Figure 13 Both are shown with the same fill, but a line segment is added at the boundary for easy distinction. It is understood that in actual production, since the first isolation structure 15 and the initial second isolation structure 171 are made of the same material, there is generally no obvious boundary between them. The initial second isolation structure 171 can be formed by deposition, such as CVD, PVD, etc.

[0159] After the initial second isolation structure 171 is formed, the initial second isolation structure 171 located above the plane containing the top surface of the sacrificial layer 16 is removed, and the remaining initial second isolation structure 171 forms the second isolation structure 17. See also Figure 14 It shows a schematic diagram of the structure obtained after forming the second isolation structure 17 according to an embodiment of the present disclosure.

[0160] like Figure 14 As shown in (a) above, it can be seen that in the AA' direction, the top surface of the second isolation structure 17 is flush with the top surface of the sacrificial layer 16; as shown in (a) below. Figure 12 As shown in (b) above, it can be seen that in the BB' direction, the second isolation structure 17 is completely formed above the first isolation structure 15; Figure 12 As shown in (c), in the top view direction, the sacrificial layer 16 covers the surface of the silicon pillar 12, so the silicon pillar 12 is not visible in the top view, only the second isolation structure 17 in the gap between the sacrificial layer 16 and the sacrificial layer 16 can be seen.

[0161] It should be noted that, as Figure 14As shown, the first isolation structure 15 and the second isolation structure 17 together constitute the isolation structure. The first isolation structure 15 is formed on the surface of the oxide layer 14 and completely covers the oxide layer 14; the first isolation structure 15 is the bottom of the isolation structure. That is, the bottom of the isolation structure completely covers the oxide layer 14.

[0162] Furthermore, the side surface of the first isolation structure 14 is in direct contact with the side surface of the adjacent silicon pillar 12. That is, the bottom side surface of the isolation structure is in direct contact with the adjacent silicon pillar 12.

[0163] In this way, the ground side of the isolation structure is in direct contact with the adjacent silicon pillar 12, thereby insulating the silicon pillar 12 from other components in the structure and preventing leakage.

[0164] Removing the sacrificial layer 16 creates the gap between the isolation structure and the silicon pillar 12. See also Figure 15 This illustrates a schematic diagram of the structure obtained after removing the sacrificial layer 16, as provided in an embodiment of this disclosure. Figure 14 and Figure 15 As shown, the first isolation structure 15 and the second isolation structure 17 together form an isolation structure. The sacrificial layer 16 is completely removed, and the original location of the sacrificial layer 16 forms the gap between the isolation structure and the silicon pillar 12. Figure 15 The arrow in (a) points to this. The method for removing the sacrificial layer 16 can be etching.

[0165] like Figure 15 As shown in (a), a gap is formed between the isolation structure and the silicon pillar 12 in the AA' direction; as Figure 15 As shown in (b), there are no silicon pillars 12 in the BB' direction, and the BB' direction is not a cross-section forming an interstitial gap. Therefore, no interstitial gap can be seen in the BB' direction; only the isolation structure above the oxide layer 14 can be seen. Figure 15 As shown in (c) in the top view, silicon pillar 12, first isolation structure 15 and second isolation structure 17 can be seen, wherein the gap between the second isolation structure 17 and silicon pillar 12 exposes the first isolation structure 15.

[0166] Thus, in this embodiment of the present disclosure, a gap is formed between the isolation structure and the silicon pillar 12 by first forming the sacrificial layer 16 and then removing the sacrificial layer 16. This gap is used for the subsequent formation of the first conductive layer 18. Moreover, an isolation structure for insulating isolation has already been formed below the gap. This method is simple to implement and has low cost.

[0167] S105, A first conductive layer 18 is formed in the gap.

[0168] It should be noted that after a gap is formed between the isolation structure and the silicon pillar 12, a first conductive layer 18 is formed in the gap. This first conductive layer is used to form the lower electrode of the semiconductor structure.

[0169] In some embodiments, a first conductive layer 18 is formed in the gap, including:

[0170] An initial first conductive layer 181 is formed in the gaps, on the top surface of the multiple silicon pillars 12 and the isolation structure;

[0171] The initial first conductive layer 181 located above the plane containing the top surface of the silicon pillar 12 is removed, and the remaining initial first conductive layer 181 forms the first conductive layer 18.

[0172] It should be noted that, during the formation of the first conductive layer 18, an initial first conductive layer 181 is formed first. See [link / reference] Figure 16 This illustrates a schematic diagram of the structure obtained after forming an initial first conductive layer 181, as provided in an embodiment of this disclosure. Figure 16 As shown, an initial first conductive layer 181 is formed in the gap between the isolation structure and the silicon pillar 12, and is also formed on the top surface of the isolation structure and each silicon pillar 12. That is, the initial first conductive layer 181 completely fills the gap between the isolation structure and each silicon pillar 12 and covers the top surface of the isolation structure and each silicon pillar 12.

[0173] like Figure 16 As shown in (a), it can be seen that in the AA' direction, the initial first conductive layer 181 completely fills the gap between the isolation structure and the silicon pillar 12, and the initial first conductive layer 181 is also formed above the top surface of the isolation structure and the silicon pillar 12; as Figure 16 As shown in (b) above, it can be seen that in the BB' direction, the initial first conductive layer 181 covers the isolation structure; as Figure 15 As shown in (c), since the initial first isolation structure completely covers the top surface of the isolation structure and each silicon pillar 12, only the initial first isolation structure 181 can be seen in the top view direction.

[0174] The material of the initial first conductive layer 181 can be titanium nitride, and the method of forming the initial first conductive layer 181 can be deposition, such as CVD, PVD, etc.

[0175] The initial first conductive layer 181 is partially removed to obtain the first conductive layer 18. See also Figure 17 This illustrates a schematic diagram of the structure obtained after forming the first conductive layer 18, as provided in an embodiment of this disclosure. Figure 16 and Figure 17As shown, the initial first conductive layer 181 located above the plane where the top surface of the silicon pillar 12 is located is removed, and the initial first conductive layer 181 remaining in the gap between the isolation structure and the silicon pillar 12 forms the first conductive layer 18.

[0176] It should be noted that when removing the initial first conductive layer 181 located above the top surface of the silicon pillar 12, etching or chemical mechanical polishing (CMP) can be used. When CMP is used, the portion of the second isolation structure 17 above the top surface of the silicon pillar 12 will also be removed simultaneously.

[0177] Therefore, in some embodiments, when removing the initial first conductive layer 181 located above the plane containing the top surface of the silicon pillar 12, the method may further include:

[0178] Remove the isolation structure located above the plane containing the top surface of silicon pillar 12.

[0179] It should be noted that, as Figure 16 and Figure 17 As shown, the initial first conductive layer 181 and part of the isolation structure (the second isolation structure 17 above the plane where the top surface of the silicon pillar 12 is located) above the plane are both removed.

[0180] In this way, by removing the initial first conductive layer 181 and the isolation structure on the plane above the top surface of the silicon pillar 12 simultaneously through CMP, the process steps can be simplified and the cost reduced.

[0181] like Figure 17 As shown in (a) above, it can be seen that in the AA' direction, the top surfaces of the isolation structure (mainly referring to the second isolation structure 17), the first conductive layer 18, and the silicon pillar 12 are flush; as Figure 17 As shown in (b) above, it can be seen that silicon pillar 12 is absent in the BB' direction, and the partially removed isolation structure can be observed; as Figure 15 As shown in (c) in the top view, it can be seen that the first conductive layer 18 surrounds the silicon pillar 12, and the remaining area is an isolation structure. The isolation structure that can be seen in the top view is the second isolation structure 17.

[0182] S106. Remove part of the isolation structure, retain the isolation structure below the first conductive layer, and form an isolation layer.

[0183] It should be noted that after the first conductive layer 18 is formed, the isolation structure is partially removed, leaving only the isolation structure below the first conductive layer 18. The retained isolation structure forms the isolation layer 19.

[0184] In some embodiments, removing a portion of the isolation structure includes:

[0185] Remove the second isolation structure 17 and the first isolation structure 15 located below the second isolation structure 17, while retaining the first isolation structure 15 below the first conductive layer 18.

[0186] It should be noted that, see Figure 18 This illustrates a schematic diagram of the structure obtained after forming an isolation layer 19, as provided in an embodiment of this disclosure. Figure 17 and 18 As shown, the second isolation structure 17 and the first isolation structure 15 located below the second isolation structure 17 are removed, and the first isolation structure 15 remaining below the first conductive layer 18 forms the isolation layer 19.

[0187] like Figure 18 As shown in (a), in the AA' direction, both the second isolation structure 17 and the first isolation structure 15 located below the second isolation structure 17 are removed, while the first isolation structure 15 located below the first conductive layer 18 is retained, forming the isolation layer 19; as Figure 17 As shown in (b), there are no silicon pillars 12 in the BB' direction, and all isolation structures in this direction have been removed. Therefore, only the substrate layer 11 and the oxide layer 14 can be seen in the BB' direction; Figure 15 As shown in (c) in the top view, the first conductive layer 18 can be seen surrounding the silicon pillar 12, and the remaining area is an oxide layer 14 exposed by the gaps between the first conductive layers 18.

[0188] It is understood that below the first conductive layer 18, the isolation layer 19 also surrounds the silicon pillar 12. That is, on the side of each silicon pillar 12, the lower part of the side is formed with an isolation layer 19 surrounding the silicon pillar 12, and the isolation layer 19 directly contacts the lower part of the side surrounding the silicon pillar 12; the upper part of the side is formed with the first conductive layer 18 surrounding the silicon pillar 12, and the conductive layer 18 also directly contacts the upper part of the side surrounding the silicon pillar 12. In this way, the isolation layer 19 insulates the first conductive layer 18 from the substrate, that is, it insulates the lower electrode from the substrate, which can prevent leakage.

[0189] It should also be noted that in this embodiment, the first isolation structure 15 and the second isolation structure are made of the same material 17. Since the first isolation structure 15 and the second isolation structure 17 are made of the same material, when removing the isolation structure, for example by etching, the same etching selectivity can be selected to remove the second isolation structure 17 and the first isolation structure 15 located below the second isolation structure 17 in one go. This eliminates the need for multiple etching processes and additional adjustment of etching parameters, simplifying the process and saving costs.

[0190] S107, a dielectric layer 20 and a second conductive layer 21 are formed on the surfaces of the isolation layer 19, the oxide layer 14, the first conductive layer 18 and the silicon pillar 12.

[0191] It should be noted that after the isolation layer 19 is formed, a dielectric layer 20 and a second conductive layer 21 are further formed.

[0192] In some embodiments, a dielectric layer 20 and a second conductive layer 21 are formed on the surfaces of the isolation layer 19, the oxide layer 14, the first conductive layer 18, and the silicon pillar 12, including:

[0193] A dielectric layer 20 is formed on the surface of the isolation layer 19, the oxide layer 14, the first conductive layer 18, and the silicon pillar 12;

[0194] A second conductive layer 21 is formed on the surface of the dielectric layer 20.

[0195] It should be noted that, see Figure 19 This illustrates a schematic diagram of the structure obtained after forming a dielectric layer 20, as provided in an embodiment of this disclosure. Figure 19 As shown, dielectric layer 20 is formed on the surface of isolation layer 19, oxide layer 14 and each silicon pillar 12.

[0196] like Figure 19 As shown in (a) in the diagram, in the AA' direction, the dielectric layer 21 is formed on the surface of the oxide layer 14, the first conductive layer 18, and each silicon pillar 12; as Figure 18 As shown in (b), there are no silicon pillars 12 in the BB' direction; therefore, in the BB' direction, the dielectric layer 20 is formed on the surface of the oxide layer 14; as Figure 18 As shown in (c) in the top view, since the dielectric layer 20 completely covers the isolation layer 19, oxide layer 14, first conductive layer 18 and silicon pillar 12, only the dielectric layer 20 can be seen. In (c), in order to distinguish the dielectric layers 20 formed on different surfaces, the dielectric layer 20 covering the top surface of the silicon pillar 12 and the first conductive layer 18 is shown in a box.

[0197] The dielectric layer 20 can be made of a high dielectric constant (High K) material, such as hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, hafnium silicon oxide, hafnium nitride, etc. The dielectric layer 20 can be formed by deposition, such as CVD, PVD, etc.

[0198] After forming the dielectric layer 20, a second conductive layer 21 is formed on the surface of the dielectric layer 20. See also Figure 20 This illustrates a schematic diagram of the composition of a semiconductor structure 100 provided in an embodiment of this disclosure. For example... Figure 20 As shown, the second conductive layer 21 is formed on the surface of the dielectric layer 20.

[0199] like Figure 20 As shown in (a), in the AA' direction, the second conductive layer 20 is formed on the surface of the dielectric layer 20; as Figure 18 As shown in (b), in the BB' direction, since there is no silicon pillar 12 in this direction, only the second conductive layer 21 can be seen above the dielectric layer 20 in the BB' direction; Figure 18 As shown in (c) in the top view, the dielectric layer can be seen to completely cover the second conductive layer 21 of the dielectric layer 20.

[0200] Furthermore, the second conductive layer 21 and the first conductive layer 18 can be made of the same material, such as titanium nitride. Therefore, in Figure 20 Both are shown with the same filling. Furthermore, the second conductive layer 21 can be formed by deposition, such as CVD, PVD, etc.

[0201] like Figure 20 As shown, the second conductive layer 21 completely fills the gaps in the dielectric layer 20.

[0202] It should be noted that, specifically as follows Figure 20 As shown in (b), the second conductive layer 21 completely fills the gaps between the dielectric layers 20.

[0203] The second conductive layer 21 is used to form the upper electrode.

[0204] It should be noted that the semiconductor structure 100 can be a capacitor, wherein the first conductive layer 18 is used to form the lower electrode of the capacitor, the second conductive layer 21 is used to form the upper electrode of the capacitor, and the dielectric layer 20 is the dielectric layer between the upper electrode and the lower electrode.

[0205] For comparison, see Figure 21 This illustration shows a simplified process diagram for forming a semiconductor structure according to an embodiment of the present disclosure, which differs from the aforementioned methods for forming semiconductor structures. Figure 21 As shown, in this method, after forming the oxide layer 14, titanium nitride layers 182 are formed on the sides of multiple silicon pillars 12 by selective atomic layer deposition (Selective Atomic layer deposition, Selective ALD). Then, the portion of the bottom of the titanium nitride layer 182 that contacts the oxide layer 14 is removed, and then the isolation layer 19 and other parts are formed. This method is difficult to implement and has a high cost.

[0206] In contrast, the method involves providing a substrate; patterning the substrate to form a substrate layer and multiple silicon pillars; forming an oxide layer on the surface of the substrate layer between the silicon pillars; forming an isolation structure above the oxide layer, with a gap between the upper part of the isolation structure and the silicon pillars; forming a first conductive layer in the gap; removing part of the isolation structure, retaining the isolation structure below the first conductive layer to form an isolation layer; and forming a dielectric layer and a second conductive layer on the surfaces of the isolation layer, oxide layer, first conductive layer, and silicon pillars. In this way, when fabricating a semiconductor structure, by forming a gap between the silicon pillars and the isolation structure, forming the first conductive layer in the gap, then removing part of the isolation structure to obtain the isolation layer, and further forming the dielectric layer and the second conductive layer, this fabrication method is simple, easy to implement, and can save on the manufacturing cost of semiconductor structures. In actual production, the process is also easier to implement.

[0207] Based on the aforementioned methods for fabricating semiconductor structures, this disclosure also provides a semiconductor structure prepared by any of the methods described in the foregoing embodiments. For example, see... Figure 20 It shows a schematic diagram of the composition structure of a semiconductor structure 100 provided in an embodiment of the present disclosure.

[0208] In some embodiments, the semiconductor structure 100 includes a capacitor, wherein the upper electrode of the capacitor is a first conductive layer 18 and the lower electrode of the capacitor is a second conductive layer 20.

[0209] Since the semiconductor structure 100 is prepared by the semiconductor structure preparation method described in the foregoing embodiments, the preparation cost of the semiconductor structure 100 is low, and the semiconductor structure 100 can be applied to 3D memory with higher integration, which is beneficial to the integration of memory.

[0210] In another embodiment of this disclosure, see [reference needed]. Figure 22 This illustrates a schematic diagram of the structural composition of a semiconductor memory 200 provided in an embodiment of this disclosure. For example... Figure 22 As shown, the semiconductor memory 200 includes the semiconductor structure 100 described in the foregoing embodiments.

[0211] In some embodiments, the semiconductor memory 200 may be 3D DRAM.

[0212] Since the semiconductor memory 200 includes the semiconductor structure 100 provided in the aforementioned embodiments, it is possible to obtain a semiconductor memory with higher integration and precision, which is beneficial to the integration of semiconductor memories.

[0213] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0214] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0215] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0216] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0217] The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

[0218] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0219] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: Provide substrate; The substrate is patterned to form a substrate layer and multiple silicon pillars; An oxide layer is formed on the surface of the substrate layer between the plurality of silicon pillars; An isolation structure is formed above the oxide layer, and a gap is formed between the upper part of the isolation structure and the silicon pillar; A first conductive layer is formed in the gap; Remove part of the isolation structure, retain the isolation structure below the first conductive layer, to form an isolation layer; A dielectric layer and a second conductive layer are formed on the surfaces of the isolation layer, the oxide layer, the first conductive layer, and the silicon pillar.

2. The method according to claim 1, characterized in that, The step of patterning the substrate to form a substrate layer and multiple silicon pillars includes: A first mask layer is formed over the substrate; wherein the first mask layer has a first pattern extending along a first direction; Using the first mask layer as a mask, the first pattern is transferred to a portion of the substrate; A second mask layer is formed over the substrate; wherein the second mask layer has a second pattern extending along a second direction; Using the second mask layer as a mask, the second pattern is transferred to a portion of the substrate to form the substrate layer and the plurality of silicon pillars.

3. The method according to claim 1, characterized in that, The step of patterning the substrate to form a substrate layer and multiple silicon pillars includes: A third mask layer is formed above the substrate; the third mask layer includes a plurality of sub-masks arranged in an array, and the third mask layer has a third pattern, which is composed of a first pattern extending along a first direction and a second pattern extending along a second direction; Using the third mask layer as a mask, the third pattern is transferred to a portion of the substrate to form the substrate layer and the plurality of silicon pillars.

4. The method according to claim 1, characterized in that, The formation of an oxide layer on the substrate surface between the plurality of silicon pillars includes: An initial oxide layer is formed on the surface of the plurality of silicon pillars and on the surface of the substrate layer between the plurality of silicon pillars; The initial oxide layer located on the surface of the plurality of silicon pillars is removed, and the remaining initial oxide layer forms the oxide layer.

5. The method according to claim 1, characterized in that, The formation of an isolation structure above the oxide layer includes: A first isolation structure is formed on the surface of the oxide layer; A second isolation structure is formed above the first isolation structure, and a gap is formed between the second isolation structure and the silicon pillar. The first isolation structure and the second isolation structure constitute the isolation structure.

6. The method according to claim 5, characterized in that, The formation of a first isolation structure on the surface of the oxide layer includes: An initial first isolation structure is formed on the surface of the oxide layer and each of the silicon pillars; The initial first isolation structure is partially removed, and the initial first isolation structure remaining on the surface of the oxide layer forms the first isolation structure.

7. The method according to claim 5, characterized in that, The formation of a second isolation structure above the first isolation structure includes: A sacrificial layer is formed on the surface of the silicon pillar; An initial second isolation structure is formed on the surface of the sacrificial layer and above the first isolation structure; Remove the initial second isolation structure located above the plane containing the top surface of the sacrificial layer, and retain the initial second isolation structure to form the second isolation structure; The sacrificial layer is removed to form the gap between the isolation structure and the silicon pillar.

8. The method according to claim 5, characterized in that, The removal of a portion of the isolation structure includes: Remove the second isolation structure and the first isolation structure located below the second isolation structure, while retaining the first isolation structure below the first conductive layer.

9. The method according to claim 7, characterized in that, The sacrificial layer is formed by thermal oxidation.

10. The method according to claim 1, characterized in that, The formation of a first conductive layer in the gap includes: An initial first conductive layer is formed in the gap, on the top surface of the plurality of silicon pillars and the isolation structure; The initial first conductive layer located above the plane containing the top surface of the silicon pillar is removed, and the remaining initial first conductive layer forms the first conductive layer.

11. The method according to claim 10, characterized in that, The method further includes, during the removal of the initial first conductive layer located above the plane containing the top surface of the silicon pillar: Remove the isolation structure located above the plane containing the top surface of the silicon pillar.

12. The method according to claim 1, characterized in that, The method of forming a dielectric layer and a second conductive layer on the surfaces of the isolation layer, the oxide layer, the first conductive layer, and the silicon pillar includes: The dielectric layer is formed on the surfaces of the isolation layer, the oxide layer, the first conductive layer, and the silicon pillar; The second conductive layer is formed on the surface of the dielectric layer.

13. The method according to claim 12, characterized in that, The second conductive layer completely fills the gaps in the dielectric layer.

14. The method according to any one of claims 5 to 9, characterized in that, The first isolation structure and the second isolation structure are made of the same material.

15. The method according to any one of claims 1 to 13, characterized in that, The bottom of the isolation structure is completely covered by the oxide layer.

16. The method according to any one of claims 1 to 13, characterized in that, The bottom side of the isolation structure is in direct contact with the adjacent silicon pillar.

17. The method according to any one of claims 1 to 13, characterized in that, The first conductive layer is used to form the lower electrode of the semiconductor structure, and the second conductive layer is used to form the upper electrode of the semiconductor structure.

18. The method according to any one of claims 1 to 13, characterized in that, The multiple silicon pillars are arranged in an array.

19. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the preparation method according to any one of claims 1 to 18.

20. A semiconductor memory, characterized in that, Including the semiconductor structure as described in claim 19.

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