A semiconductor device and a method of fabricating the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate; at least one material layer on one side of the substrate, wherein the at least one material layer comprises N material layers, N is an integer and N>=1; and a patterned structure is arranged in at least the Nth material layer. By arranging the patterned structure in at least the Nth material layer, the adhesion between the packaging layer and the material layer is increased, a sufficient number of stress locking steps are provided on the surface of the semiconductor device to eliminate the damage of the thermal mechanical stress to the surface of the chip, and the reliability of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] Radio frequency and power electronic devices based on third-generation semiconductor materials are finding increasingly widespread applications due to their superior performance. The expanding range of applications is also placing increasingly higher demands on device performance. As power requirements increase in applications, chip area, especially for third-generation semiconductor devices based on silicon substrates, will increase significantly. To reduce costs, many products are now using die-cast plastic packaging.

[0003] However, due to the significant difference in thermal expansion coefficients between the molding compound and third-generation semiconductor materials and their substrates, the die-cast plastic can exert enormous mechanical stress on the semiconductor chip surface under the thermal stress of external temperature changes, potentially causing damage. Separation of the die-cast plastic from the chip surface can lead to the mechanical stress being concentrated in areas where stress is hindered, rather than being distributed across the chip surface. This increases the likelihood of localized displacement of the device and material breakage during manufacturing. Therefore, it is necessary to take measures to reduce such damage and improve the overall reliability of the product. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a semiconductor device and a method for fabricating the same, so as to provide a semiconductor device with high reliability, which can effectively solve the problem of semiconductor devices being damaged by the huge mechanical stress applied to the surface of semiconductor chips by die-cast plastic.

[0005] In a first aspect, embodiments of the present invention provide a semiconductor device, comprising:

[0006] Substrate;

[0007] At least one material layer located on one side of the substrate, the at least one material layer comprising N material layers, where N≥1 and N is an integer;

[0008] At least the Nth material layer has a patterned structure.

[0009] Secondly, embodiments of the present invention also provide a method for fabricating a semiconductor device, used to fabricate the semiconductor device described in the first aspect of the present invention; the fabrication method includes:

[0010] Provide substrate;

[0011] At least one material layer is prepared on one side of the substrate, the at least one material layer comprising N material layers, where N≥1 and N is an integer;

[0012] Patterned structures are prepared in at least the Nth material layer.

[0013] The semiconductor device and its fabrication method provided in this invention provide a patterned structure in at least the outermost material layer, thereby increasing the adhesion between the encapsulation layer and the material layer, providing a sufficient number of stress-locking steps on the surface of the semiconductor device to eliminate the damage to the semiconductor device surface caused by thermomechanical stress, and improving the reliability of the semiconductor device. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0015] Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line A-A';

[0016] Figure 3 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0017] Figure 4 yes Figure 3 A schematic diagram of the cross-sectional structure of the provided semiconductor device along section line B-B';

[0018] Figure 5 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0019] Figure 6 yes Figure 5 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line C-C';

[0020] Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0021] Figure 8 yes Figure 7 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line D-D';

[0022] Figure 9 yes Figure 3 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line B-B';

[0023] Figure 10 yes Figure 3 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line B-B';

[0024] Figure 11 yes Figure 3 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line B-B'; Figure 12 yes Figure 5 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line C-C';

[0025] Figure 13 yes Figure 5 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line C-C';

[0026] Figure 14 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0027] Figure 15 yes Figure 14 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line E-E';

[0028] Figure 16 This is a schematic diagram of a metal patterned structure provided in an embodiment of the present invention;

[0029] Figure 17 This is a schematic diagram of another metal patterned structure provided in an embodiment of the present invention;

[0030] Figure 18 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention;

[0031] Figure 19 yes Figure 18 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line F-F';

[0032] Figure 20 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention;

[0033] Figure 21 This is a schematic flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0034] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention and not the entire structure.

[0035] Figure 1 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 2 yes Figure 1 The provided schematic diagram shows the cross-sectional structure of the semiconductor device along section line A-A', as shown below. Figure 1 and Figure 2As shown, the semiconductor device 10 provided in this embodiment of the invention includes a substrate 11; at least one material layer 12 located on one side of the substrate 11, the at least one material layer 12 includes N material layers, N≥1 and N is an integer; at least the Nth material layer is provided with a patterned structure 13.

[0036] For example, Figure 2 The following description will be based on an example where at least one material layer 12 includes a first material layer 121 and a second material layer 122, and a patterned structure 13 is provided only on the second material layer 122. Figure 1 and Figure 2 As shown, by providing a patterned structure 13 on the second material layer 122, the exposed surface area of ​​the second material layer 122 can be increased. When the encapsulation layer is formed on the second material layer 122, the contact area between the second material layer 122 and the encapsulation layer can be increased. At the same time, a sufficient number of stress-locking steps can be provided on the surface of the semiconductor device to eliminate the damage to the surface of the semiconductor device caused by thermomechanical stress. This not only eliminates the damage caused by stress in the parallel direction on the surface of the semiconductor device, but also prevents the damage caused by stress applied to the surface of the semiconductor device in the vertical direction, thereby improving the reliability of the semiconductor device.

[0037] Furthermore, the substrate 11 may be formed from one of the following materials: silicon, sapphire, silicon carbide, gallium arsenide, diamond, gallium nitride, etc., or it may be other materials suitable for growing gallium nitride or directly forming the active part of the device. This embodiment of the invention does not limit this.

[0038] The material layer 12 can be a metallic material layer or a non-metallic material layer. The embodiments of the present invention will describe different material layers in detail in the subsequent embodiment section.

[0039] It should be noted that the patterned structure 13 can be a recessed patterned structure, such as... Figure 2 As shown, the patterned structure can also be a raised patterned structure, or it can include both a recessed patterned structure and a raised patterned structure simultaneously. This embodiment of the invention does not limit the specific features in this regard. Figure 2 The explanation will focus on patterned structure 13 as a recessed patterned structure. Furthermore, when patterned structure 13 is a recessed patterned structure, the recessed patterned structure can penetrate the film layer it resides in (e.g., Figure 2 As shown in the figure, it may also not penetrate the film layer in which it is located (not shown in the figure), and the embodiments of the present invention do not limit this.

[0040] It should also be noted that, in order to ensure adhesion between the semiconductor device surface and the packaging layer, the distance between adjacent patterned structures can be reasonably set. For example, the interval between adjacent patterned structures can be greater than or equal to 1 μm. Simultaneously, the distance between the patterned structure and the edge of the semiconductor device should be greater than or equal to 1 μm, ensuring both increased adhesion between the semiconductor device surface and the packaging layer and a stable mechanical structure at their contact surface. Furthermore, the patterned structure described in this embodiment of the invention comprises at least two independent structures.

[0041] Based on the above embodiments, Figure 3 This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention. Figure 4 yes Figure 3 The provided schematic diagram shows the cross-sectional structure of the semiconductor device along section line B-B'. Figure 5 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 6 yes Figure 5 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line C-C'. Figure 7 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 8 yes Figure 7 A schematic diagram of the cross-sectional structure of the provided semiconductor device along the section line D-D'. Figure 9 yes Figure 3 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line B-B'. Figure μ0 is... Figure 3 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line B-B'; combined with Figures 3-10 As shown, the semiconductor device 10 provided in this embodiment of the invention includes a working region a and a non-working region b, with the non-working region b surrounding the working region a; at least one material layer 12 includes at least one metal layer 14 located in the working region a and at least one dielectric layer 15 located in the non-working region b; the at least one metal layer 14 includes N1 metal layers, where N1 ≥ 1 and N1 is an integer; the at least one dielectric layer 15 includes N2 dielectric layers, where N2 ≥ 1 and N2 is an integer; at least the N1th metal layer is provided with a first patterned structure 131, and / or at least the N2th dielectric layer is provided with a second patterned structure 132.

[0042] For example, Figure 3 and Figure 4 Taking the N1th metal layer having a first patterned structure 131 as an example, as follows... Figure 3 and Figure 4As shown, a first patterned structure 131 is provided in the N1 metal layer, thereby increasing the adhesion between the encapsulation layer and the surface of the working area a of the semiconductor device 10, and providing a sufficient number of stress-locking steps on the surface of the working area a of the semiconductor device 10 to eliminate the damage to the surface of the working area a of the semiconductor device 10 caused by thermomechanical stress.

[0043] It should be noted that, Figure 3 and Figure 4 Let's take working area a, which includes a metal layer, as an example for illustration.

[0044] Figure 5 and Figure 6 Taking the N2 dielectric layer having a second patterned structure 132 as an example, as follows... Figure 5 and Figure 6 As shown, a second patterned structure 132 is provided in the N2 dielectric layer 15a, thereby increasing the adhesion between the encapsulation layer and the surface of the non-working area b of the semiconductor device 10, and providing a sufficient number of stress-locking steps on the surface of the non-working area b of the semiconductor device 10 to eliminate the damage to the surface of the non-working area b of the semiconductor device 10 caused by thermomechanical stress.

[0045] Optionally, the dielectric layer 15 can be silicon nitride, silicon oxide, silicon oxynitride, or other dielectric materials. The specific material of the dielectric layer 15 is not limited in the embodiments of the present invention.

[0046] It should be noted that, Figure 5 and Figure 6 The following explanation uses a non-working area b, which includes a dielectric layer, as an example.

[0047] Figure 7 and Figure 8 The following explanation will be based on an example where a first patterned structure 131 is provided in the N1st metal layer and a second patterned structure 132 is provided in the N2nd dielectric layer. Figure 7 and Figure 8 As shown, a first patterned structure 131 is provided in the N1 metal layer and a second patterned structure 132 is provided in the N2 dielectric layer. This increases the adhesion between the encapsulation layer and the surfaces of the working area a and the non-working area b of the semiconductor device 10, and provides a sufficient number of stress-locking steps on both the working area a and the non-working area b of the semiconductor device 10 to eliminate the damage to the surfaces of the working area a and the non-working area b of the semiconductor device 10 caused by thermomechanical stress.

[0048] It should be noted that, Figure 7 and Figure 8 The following is an example of working area a consisting of a metal layer and non-working area b consisting of a dielectric layer.

[0049] It should also be noted that N represents the number of material layers, N1 represents the number of metal layers, and N2 represents the number of dielectric layers. Here, N, N1, and N2 are used to characterize the number of layers, rather than limiting the number of material, metal, and dielectric layers. N1 and N can be the same or different, and N2 and N can be the same or different.

[0050] It should also be noted that each metal layer mentioned in this article refers to a single metal layer or a metal stack formed by directly stacking metal layers of different materials in the process flow. Similarly, each dielectric layer mentioned in this article refers to a single dielectric layer or a dielectric stack formed by directly stacking dielectric layers of different materials in the process flow.

[0051] It should also be noted that, in the embodiments of the present invention, the working area can refer to the working area of ​​a semiconductor device, such as the area where signals are generated or where signal transmission occurs; the non-working area can refer to the non-working area of ​​a semiconductor device, where no signals are generated and no signal transmission occurs.

[0052] Optional, continue to refer to Figure 3 , Figure 4 , Figure 7 and Figure 8 As shown, the working area a may include an active area a1 and a passive area a2 located around the active area a1. The metal layer 14 may include electrodes and / or electrode connection structures located in the working area a, and at least one electrode and / or electrode connection structure is provided with a first patterned structure 131.

[0053] For details, please refer to [link / reference]. Figure 3 , Figure 4 , Figure 7 and Figure 8 As shown, the metal layer 14 may include a source 141, a gate 142, and a drain 143 located in the working region a, and may also include a gate connection structure 144 located in the passive region a2. A first patterned structure 131 is provided in at least one of the source 141, gate 142, drain 143, and gate connection structure 144. Furthermore, since the linewidth of the gate 142 in the actual semiconductor structure is relatively small, the first patterned structure 131 can be provided in at least one of the source 141, drain 143, and gate connection structure 144. This ensures that the design of the first patterned structure 131 will not cause an open circuit in the source 141, drain 143, or gate connection structure 144, thus not affecting normal signal transmission and ensuring the normal operation of the semiconductor device 10. Figure 3 , Figure 4 , Figure 7 and Figure 8The following descriptions are based on the example of a first patterned structure 131 provided in the gate 141, drain 143 and gate connection structure 144.

[0054] It should be noted that, Figures 3-8 The semiconductor devices shown in the following figures are illustrated using field-effect devices as an example only. Therefore, the metal layer 14 may include a source 141, a gate 142, and a drain 143 located within the working region a. However, the semiconductor devices in this embodiment of the invention can be other semiconductor devices besides field-effect devices, such as IGBTs. This embodiment of the invention does not limit the specific type of semiconductor device; it only uses field-effect devices as an example for illustration, and is not a limitation.

[0055] Based on the above embodiments, and considering the actual structure of semiconductor devices, the working area of ​​a semiconductor device generally includes at least two metal layers, and the non-working area of ​​a semiconductor device includes at least two dielectric layers. The following description will be based on the example of the working area including at least two metal layers and the non-working area including at least two dielectric layers.

[0056] First, we will explain how to set the first patterned structure in the at least two metal layers of the work area.

[0057] Figure 9 yes Figure 3 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line B-B'. Figure 10 yes Figure 3 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line B-B'. Figure 11 yes Figure 3 The provided schematic diagram shows another cross-sectional structure of the semiconductor device along section line B-B', combined with... Figure 3 , Figure 9 , Figure 10 and Figure 11 As shown, at least one metal layer 14 includes a first metal layer 14b near the substrate, an N1 metal layer 14a located on the side of the first metal layer 14b away from the substrate 11, and a j-th metal layer located between the first metal layer and the N1 metal layer, where N1≥2 and N1 is an integer, 0≤j≤N1, and j is an integer; at least the N1 metal layer 14a is provided with a first patterned structure 131; and when at least two metal layers from the first metal layer 14b to the N1 metal layer 14a are provided with the first patterned structure 131, the first patterned structures 131 in different metal layers overlap at least partially along the first direction, and the first direction is perpendicular to the plane where the substrate 11 is located.

[0058] For example, Figure 9 , Figure 10 and Figure 11The examples all use at least one metal layer 14, including a first metal layer 14b and a second metal layer 14a, as an example, where N1 = 2 and j = 0. Figure 9 The following explanation will be based on the example of setting the first patterned structure 131 only in the N1st metal layer 14a. Figure 10 and Figure 11 The following explanation will be based on the example of having a first patterned structure 131 in both the first metal layer 14b and the N1th metal layer 14a. Figure 10 The first metal layer 14b and the second metal layer 14a are electrically connected. Figure 11 The first metal layer 14b and the second metal layer 14a are not connected.

[0059] First, let's take the example of setting the first patterned structure 131 only in the N1 metal layer 14a.

[0060] like Figure 9 As shown, specifically, the source 141 may include a first source metal layer 141b and an N1th source metal layer 141a sequentially located on one side of the substrate 11. The first source metal layer 141b may be an ohmic contact layer in contact with the substrate 11, and the N1th source metal layer 141a may be a source signal transmission layer. By providing a first patterned structure 131 in the N1th source metal layer 141a, the adhesion between the surface of the working area a and the packaging layer can be increased. A sufficient number of stress-locking steps are provided on the surface of the working area a to eliminate the damage of thermomechanical stress to the chip surface and improve the reliability of the semiconductor device.

[0061] Meanwhile, the drain 143 may include a first drain metal layer 143b and an N1 drain metal layer 143a sequentially located on one side of the substrate 11. The first drain metal layer 143b may be an ohmic contact layer in contact with the substrate 11, and the N1 drain metal layer 143a may be a drain signal transmission layer. By setting a first patterned structure 131 in the N1 drain metal layer 143a, the adhesion between the working area a surface and the packaging layer 14 can be increased. A sufficient number of stress-locking steps are provided on the working area a surface to eliminate the damage of thermomechanical stress to the chip surface and improve the reliability of the semiconductor device.

[0062] The following explanation will take the example of setting a first patterned structure 131 in both the first metal layer 14b and the N1 metal layer 14a.

[0063] like Figure 10 and Figure 11As shown, specifically, the source 141 may include a first source metal layer 141b and an N1th source metal layer 141a sequentially located on one side of the substrate 11. The first source metal layer 141b may be an ohmic contact layer in contact with the substrate 11, and the N1th source metal layer 141a may be a source signal transmission layer. Both the first source metal layer 141b and the N1th source metal layer 141a are provided with a first patterned structure 131. Along the direction perpendicular to the plane where the substrate 11 is located, the first patterned structures 131 in the first source metal layer 141b and the N1th source metal layer 141a overlap at least partially. This can further increase the adhesion between the surface of the working area a and the packaging layer, provide more stress-locking steps on the surface of the working area a to eliminate the damage of thermomechanical stress to the chip surface, and further improve the reliability of the semiconductor device.

[0064] Meanwhile, the drain 143 may include a first drain metal layer 143b and an N1 drain metal layer 143a sequentially located on one side of the substrate 11. The first drain metal layer 143b may be an ohmic contact layer in contact with the substrate 11, and the N1 drain metal layer 143a may be a drain signal transmission layer. Both the first drain metal layer 143b and the N1 drain metal layer 143a are provided with a first patterned structure 131. Along the direction perpendicular to the plane where the substrate 11 is located, the first patterned structures 131 in the first drain metal layer 143b and the N1 drain metal layer 143a overlap at least partially. This can further increase the adhesion between the surface of the working area a and the packaging layer, provide more stress-locking steps on the surface of the working area a to eliminate the damage of thermomechanical stress to the chip surface, and further improve the reliability of the semiconductor device.

[0065] The above describes in detail the arrangement of the first patterned structure 131 using two feasible implementation methods as examples. The specific arrangement of the first patterned structure 131 in this embodiment of the invention is not limited. The first patterned structure can be arranged only in the N1st metal layer 14a, improving the reliability of the semiconductor device while ensuring a simple arrangement of the first patterned structure; alternatively, the first patterned structure can be arranged in each of the multiple metal layers, including the N1st metal layer 14a, further improving the reliability of the semiconductor device.

[0066] It should also be noted that a dielectric layer is typically placed above the top metal layer, i.e., the N1th metal layer. Figure 9 , Figure 10 and Figure 11 To clearly show the first patterned structure 131, the dielectric layer above the N1th metal layer is omitted and is not shown.

[0067] Continue to refer to Figure 3 and Figure 7As shown, the first patterned structure 131 includes a strip groove structure, wherein the extension direction of the long side of the strip groove structure is parallel to the current direction in the metal layer 14.

[0068] For example, in order not to reduce the conductivity of the metal layer 14, the first patterned structure 131 can be configured as a strip-shaped groove structure, and the extension direction of the long side of the strip-shaped groove structure is parallel to the current direction in the metal layer 14. For example, for the first patterned structure 131 disposed in the source 141 and drain 143, the extension direction of its long side can be the same as the X direction shown in the figure, ensuring that the conductivity of the source 141 and drain 143 is not reduced; for the first patterned structure 131 disposed in the gate connection structure 144, the extension direction of its long side can be the same as the Y direction shown in the figure, ensuring that the conductivity of the gate connection structure 144 is not reduced.

[0069] Further reference Figure 3 As shown, to ensure adhesion between the working area surface and the encapsulation layer, the size of the strip groove structure and the distance between two adjacent strip groove structures can be reasonably set. For example, the extension width of the strip groove structure in the Y direction can be set to be greater than or equal to 1 μm, and the distance between two adjacent strip groove structures in both the X and Y directions can be greater than or equal to 2 μm. This ensures increased adhesion between the working area surface and the encapsulation layer while ensuring no significant impact on the conductivity of the metal lines.

[0070] In summary, the above embodiments have described how to set a first patterned structure in the at least two metal layers of the working area. Next, we will describe how to set a second patterned structure in the dielectric layer of the non-working area, which includes at least two dielectric layers.

[0071] Optionally, the second patterned structure 132 may include a recessed patterned structure 1321 or a raised patterned structure 1322. Here, the recessed patterned structure 1321 will be described first.

[0072] Figure 12 yes Figure 5 A schematic diagram of another cross-sectional structure of the provided semiconductor device along section line C-C'. Figure 13 yes Figure 5 The provided schematic diagram shows another cross-sectional structure of the semiconductor device along section line C-C', combined with... Figure 5 , Figure 12 and Figure 13As shown, at least one dielectric layer 15 includes a first dielectric layer 15b near the substrate 11, an N2 dielectric layer 15a on the side of the first dielectric layer 15b away from the substrate 11, and a k-th dielectric layer between the first dielectric layer 15b and the N2 dielectric layer 15a, where N2 ≥ 2 and N2 is an integer, 0 ≤ k ≤ N2, and k is an integer; at least the N2 dielectric layer 15a is provided with a second patterned structure 132; or, at least two dielectric layers are provided with a second patterned structure 132, and the at least two dielectric layers include the N2 dielectric layer 15a, the N2-1 dielectric layer to the k-th dielectric layer stacked sequentially, where 1 ≤ k ≤ N2-1.

[0073] First, we will take the example of setting the second patterned structure 132 only in the N2 dielectric layer 15a as an example.

[0074] like Figure 12 As shown, at least one metal layer includes a first metal layer 14b and an N1 metal layer 14a sequentially located on one side of the substrate 11. Correspondingly, a first dielectric layer 15b is located between the first metal layer 14b and the substrate 11, a second dielectric layer 15c is located between the first metal layer 14b and the N1 metal layer 14a, and an N2 dielectric layer 15a is located on the side of the N1 metal layer 14a away from the substrate 11. The recessed patterned structure 1321 is provided only in the N2 dielectric layer 15a to ensure increased adhesion between the surface of the non-working area b and the packaging layer. A sufficient number of stress-locking steps are provided on the surface of the non-working area b to eliminate thermomechanical stress damage to the chip surface, thereby improving the reliability of the semiconductor device.

[0075] The following explanation will take the example of setting a second patterned structure 132 in both the second dielectric layer 15c and the N2 dielectric layer 15a.

[0076] like Figure 13 As shown, at least one metal layer includes a first metal layer 14b and an N1 metal layer 14a sequentially located on one side of the substrate 11. Correspondingly, a first dielectric layer 15b is located between the first metal layer 14b and the substrate 11, a second dielectric layer 15c is located between the first metal layer 14b and the N1 metal layer 14a, and an N2 dielectric layer 15a is located on the side of the N1 metal layer 14a away from the substrate 11. Recessed patterned structures 1321 are provided in both the second dielectric layer 15c and the N2 dielectric layer 15a, which can further increase the adhesion between the surface of the non-working area b and the encapsulation layer.

[0077] It should be noted that continued reference is necessary. Figure 5As shown, to ensure adhesion between the working area surface and the encapsulation layer, the size of the recessed patterned structure and the distance between two adjacent recessed patterned structures can be reasonably set. For example, the extension width of the recessed patterned structure can be set to be greater than or equal to 1 μm, the distance between two adjacent strip groove structures in the X or Y direction can be greater than or equal to 1 μm, the ratio between the total area of ​​the recessed patterned structure in the non-working area and the total area of ​​the non-working area is greater than or equal to 5%, and the distance between the recessed patterned structure and the edge of the metal structure semiconductor device in the working area is greater than or equal to 1 μm. This ensures increased adhesion between the working area surface and the encapsulation layer while maintaining a stable mechanical structure at the contact surface.

[0078] The above describes in detail the setting method of the recessed patterned structure using two feasible implementation methods as examples. The specific setting method of the recessed patterned structure in this embodiment of the invention is not limited. The recessed patterned structure can be set only in the N2 dielectric layer 15a to improve the reliability of the semiconductor device while ensuring a simple setting method; alternatively, the recessed patterned structure can be set in multiple dielectric layers, including the N2 dielectric layer 15a, and stacked sequentially with the N2 dielectric layer 15a, such as... Figure 12 As shown, this further improves the reliability of semiconductor devices. Furthermore, the shape of the recessed patterned structure can be stripe, square, cross, network, or other shapes; this invention does not limit the shape of the recessed patterned structure.

[0079] It is important to note that when recessed patterned structures are provided in multiple dielectric layers, including the N2nd dielectric layer 15a, these layers are stacked sequentially, i.e., the N2nd dielectric layer, the N2-1th dielectric layer, ..., up to the kth dielectric layer, where 1 ≤ k ≤ N2-1. Furthermore, the recessed patterned structures in these multiple dielectric layers, including the N2nd dielectric layer 15a, are formed in a single masking process, ensuring a simple fabrication process. Alternatively, the recessed patterned structures in these multiple dielectric layers, including the N2nd dielectric layer 15a, can be formed through multiple processes, for example, simultaneously with the via fabrication steps in the dielectric layer of the working area a. This achieves the recessed patterned structure in the non-working area without adding additional process steps.

[0080] It should also be noted that the above embodiments are only illustrated by setting a recessed patterned structure in one or more dielectric layers including the N2 dielectric layer 15a. It can be understood that for non-planarization processes, the second patterned structure of the N2 dielectric layer (surface) can also be achieved by cutting grooves in the dielectric layer below the N2 dielectric layer.

[0081] Next, the raised patterned structure 1322 will be explained.

[0082] Figure 14 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 15 yes Figure 14 The provided schematic diagram shows the cross-sectional structure of the semiconductor device along the section line E-E', combined with... Figure 14 and Figure 15 As shown, at least one dielectric layer 15 includes a first dielectric layer 15b near the substrate 11, a second dielectric layer 15a on the side of the first dielectric layer 15b away from the substrate 11, and a third dielectric layer k between the first dielectric layer and the second dielectric layer, where N2 ≥ 2 and N2 is an integer, 0 ≤ k ≤ N2, and k is an integer; the semiconductor device 10 also includes at least one metal patterned structure 16 located in the non-working area b, the at least one metal patterned structure 16 being located between the first dielectric layer 15b and the second dielectric layer 15a, and the at least one metal patterned structure 16 forming a raised patterned structure 1322 on the surface of the second dielectric layer 15a away from the substrate 11.

[0083] For example, Figure 14 and Figure 15 Taking at least one dielectric layer 15 comprising a first dielectric layer 15b and a second dielectric layer 15c located between the first dielectric layer 15b and the N2nd dielectric layer 15a as an example, where N2 = 3 and k = 2. Figure 15 The following description will be based on an example of at least one layer of metal patterned structure 16, which includes one layer of metal patterned structure 16 and is located between the second dielectric layer 15c and the N2 dielectric layer 15a.

[0084] like Figure 15 As shown, a metal patterned structure 16 is provided between the second dielectric layer 15c and the N2 dielectric layer 15a. The at least one metal patterned structure 16 forms a raised patterned structure 1322 on the surface of the N2 dielectric layer 15a away from the substrate 11. This ensures that the adhesion between the surface of the non-working area b and the packaging layer can be increased, and a sufficient number of stress-locking steps are provided on the surface of the non-working area b to eliminate the damage of thermomechanical stress to the chip surface and improve the reliability of the semiconductor device.

[0085] Based on the above embodiments, continue to refer to Figure 15 As shown, at least one metal layer 14 includes a first metal layer 14b near the substrate 11, an N1 metal layer 14a on the side of the first metal layer away from the substrate 11, and a j-th metal layer between the first metal layer 14b and the N1 metal layer, where N1 ≥ 2 and N1 is an integer, 0 ≤ j ≤ N1, and j is an integer.

[0086] For example, Figure 15Taking at least one metal layer 14, including a first metal layer 14b and a second metal layer 14a, as an example, where N1 = 2 and j = 0. The N1th to nth metal layers, stacked sequentially, include portions located in the non-working area b. The N1th to jth metal layers, stacked sequentially in the non-working area b, contain a metal patterned structure 16. That is, the metal patterned structure 16 in the non-working area b is disposed in the same layer as the electrode or electrode connection structure in the working area a. Figure 15 As shown. Figure 15 The following description takes the example of a metal patterned structure 16 being arranged in the same layer as the second metal layer 14a (141a and 143a).

[0087] Furthermore, when at least one layer of metal patterned structure 16 includes only one layer of metal patterned structure 16, the metal patterned structure 16 can be set in the same layer as the second metal layer 14a. This ensures that the raised patterned structure 1322 formed on the surface of the N2 dielectric layer 15a away from the substrate 11 is obvious, which is beneficial to increase the adhesion between the surface of the non-working area b and the packaging layer, and provides a sufficient number of stress-locking steps on the surface of the non-working area b to eliminate the damage of thermomechanical stress to the chip surface and improve the reliability of the semiconductor device.

[0088] Based on the above embodiments, continue to refer to Figure 15 As shown, the metal patterned structure 16 includes a first edge 161 near the working area a; along the direction from the non-working area b to the working area a (X direction as shown in the figure), the minimum distance between the first edge 161 and the metal layer disposed in the same layer as the metal patterned structure 16 and located in the working area a is L, where L≥1μm.

[0089] For example, Figure 15 The following explanation uses the first edge 161 of the metal patterned structure 16 with the gate connection structure 144 and the drain 143 as examples. By reasonably setting the distance L between the first edge 161 of the metal patterned structure 16 and the metal layer disposed in the same layer as the metal patterned structure 16 and located in the working area a, L≥1μm, it can be ensured that the metal patterned structure 16 disposed in the non-working area b will not affect the working area a, will not affect the electrical performance of the semiconductor device 10, and ensures the normal operation of the semiconductor device.

[0090] It should be noted that continued reference is necessary. Figure 14As shown, to ensure adhesion between the working area surface and the encapsulation layer, the size of the raised patterned structure and the distance between two adjacent raised patterned structures can be reasonably set. For example, the extension width of the raised patterned structure can be set to be greater than or equal to 0.3 μm, the distance between two adjacent strip groove structures in the X or Y direction can be greater than or equal to 2 μm, and the ratio between the total area of ​​the raised patterned structure in the non-working area and the total area of ​​the non-working area is greater than or equal to 5%. This ensures increased adhesion between the working area surface and the encapsulation layer while maintaining a stable mechanical structure at the contact surface.

[0091] Optional, Figure 16 This is a schematic diagram of a metal patterned structure provided in an embodiment of the present invention. Figure 17 This is a schematic diagram of another metal patterned structure provided in an embodiment of the present invention, combined with... Figure 14 , Figure 16 and Figure 17 As shown, the metal patterned structure 16 provided in this embodiment of the invention may include a cross structure (such as...). Figure 14 As shown), mesh structure (such as) Figure 16 As shown), the strip groove structure (such as...) Figure 17 (As shown), and a square structure. The shape of the metal patterned structure 16 is not limited in this embodiment of the invention; only three feasible structures are described as examples.

[0092] In summary, the above embodiments illustrate how to set a second patterned structure in at least two dielectric layers in a non-working area.

[0093] It should be noted that the above embodiments of the present invention have independently described the technical solutions for setting the first patterned structure in the metal layer of the working area and the second patterned structure in the dielectric layer of the non-working area. It is understood that for the technical solution of setting the first patterned structure in the metal layer of the working area and the second patterned structure in the dielectric layer of the non-working area at the same time, the above solutions for setting the first patterned structure in the metal layer of the working area and the second patterned structure in the dielectric layer of the non-working area can be arbitrarily combined to obtain the technical solution of setting the first patterned structure in the metal layer of the working area and the second patterned structure in the dielectric layer of the non-working area at the same time.

[0094] As one possible implementation method, please refer to [reference]. Figure 12 , Figure 13 and Figure 15As shown, at least one metal layer 14 includes a first metal layer 14b near the substrate 11, an N1 metal layer 14a located on the side of the first metal layer 14b away from the substrate 11, and a j-th metal layer located between the first metal layer 14b and the N1 metal layer 14a, where N1 ≥ 2 and N1 is an integer, 0 ≤ j ≤ N1, and j is an integer; at least one dielectric layer 15 includes a first dielectric layer 15b near the substrate 11, an N2 dielectric layer 15a located on the side of the first dielectric layer 15b away from the substrate 11, and a k-th dielectric layer located between the first dielectric layer 15b and the N2 dielectric layer 15a, where N2 ≥ 2 and N2 is an integer, 0 ≤ k ≤ N2, and k is an integer; the first dielectric layer 15b to the N2 dielectric layer 15a are all disposed in the working area a and the non-working area b; the first dielectric layer 15b is disposed between the substrate 11 and the first metal layer 14b, and the N2 dielectric layer 15a is disposed on the side of the N1 metal layer 14a away from the substrate 11.

[0095] For example, Figure 12 , Figure 15 and Figure 16 The following descriptions are based on examples where at least one metal layer 14 includes a first metal layer 14b and a second metal layer 14a, i.e., N1 = 2, j = 0; and at least one dielectric layer 15 includes a first dielectric layer 15b and a second dielectric layer 15c located between the first dielectric layer 15b and the N2nd dielectric layer 15a, i.e., N2 = 3, k = 2. (Reference) Figure 12 , Figure 15 and Figure 16 As shown, a dielectric layer, namely the first dielectric layer 15b, can generally be disposed between the substrate 11 and the first metal layer 14b. The first dielectric layer 15b can provide a flat base film layer for the first metal layer 14b, and at the same time electrically isolate the first metal layer 14b from the semiconductor surface. At the same time, a dielectric layer, namely the N2 dielectric layer 15a, is disposed above the topmost metal layer, namely the N1st metal layer 14a, for insulating and protecting the topmost metal layer.

[0096] As a feasible implementation method, Figure 18 This is a schematic diagram of another semiconductor device provided in an embodiment of the present invention. Figure 19 yes Figure 18 The provided schematic diagram shows the cross-sectional structure of the semiconductor device along section line F-F', combined with... Figure 18 and Figure 19 As shown, the semiconductor device 10 provided in this embodiment of the invention may further include an encapsulation layer 17 located on the side of the material layer 12 away from the substrate 11; the encapsulation layer 17 covers the material layer 12 and covers the patterned structure 13.

[0097] For example, by providing a patterned structure 13 in at least the Nth material layer, the contact area between the material layer 12 and the encapsulation layer 17 is increased, which helps to increase the adhesion between the surface of the non-working area b and the encapsulation layer. A sufficient number of stress-locking steps are provided on the surface of the non-working area b to eliminate the damage of thermomechanical stress to the chip surface and improve the reliability of the semiconductor device.

[0098] Optionally, the encapsulation layer 17 can be a plastic encapsulation material to encapsulate and protect the semiconductor device 10.

[0099] It should be understood that the embodiments of the present invention increase the adhesion between the packaging layer and the metal layer and / or dielectric layer from the perspective of semiconductor device structure design. The semiconductor devices include, but are not limited to: high-power gallium nitride high electron mobility transistors (HEMTs) operating under high voltage and high current conditions; silicon-on-insulator (SOI) transistors; gallium arsenide (GaAs)-based transistors; and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), and metal-insulator-semiconductor heterojunction field-effect transistors (MESFETs). Transistor (MISHFET) or other field-effect transistors; furthermore, the semiconductor device provided by the present invention can be not only a field-effect transistor, but also other types of semiconductor devices, such as IGBTs. The embodiments of the present invention do not limit the type of semiconductor device.

[0100] Based on the same inventive concept, embodiments of the present invention also provide a method for fabricating a semiconductor device. Figure 20 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of the present invention, as shown below. Figure 20As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention may include:

[0101] S110 provides a substrate.

[0102] For example, the substrate material can be Si, SiC, or sapphire, or other materials suitable for growing gallium nitride or materials from which the active part of the device is directly formed.

[0103] S120. Prepare at least one material layer on one side of the substrate, wherein the at least one material layer comprises N material layers, where N≥1 and N is an integer.

[0104] S130, Prepare a patterned structure in at least the Nth material layer.

[0105] In summary, the semiconductor device fabrication method provided by the embodiments of the present invention, by setting a patterned structure in at least the outermost material layer, ensures increased adhesion between the encapsulation layer and the material layer, and provides a sufficient number of stress-locking steps on the surface of the semiconductor device to eliminate the damage to the semiconductor device surface caused by thermomechanical stress. This not only eliminates the damage caused by stress in the parallel direction on the surface of the semiconductor device, but also prevents the damage caused by stress applied to the surface of the semiconductor device in the vertical direction, thereby improving the reliability of the semiconductor device.

[0106] Optionally, based on the above embodiments, the semiconductor device includes a working area and a non-working area, with the non-working area surrounding the working area; based on this, Figure 21 This is a schematic flowchart of another method for fabricating a semiconductor device provided in an embodiment of the present invention, as shown below. Figure 21 As shown, the method for fabricating a semiconductor device provided in this embodiment of the invention includes:

[0107] S210 provides a substrate.

[0108] S220. At least one metal layer is prepared in the working area, and at least one dielectric layer is prepared in the non-working area. The at least one metal layer includes an N1 metal layer, where N1 ≥ 1 and N1 is an integer; the at least one dielectric layer includes an N2 dielectric layer, where N2 ≥ 1 and N2 is an integer.

[0109] S230, a first patterned structure is prepared in at least the N1 metal layer, and / or a second patterned structure is prepared in at least the N2 dielectric layer.

[0110] Thus, by providing a first patterned structure in at least the topmost metal layer of the working area and / or a second patterned structure in the topmost dielectric layer of the non-working area, the adhesion between the encapsulation layer and the surface of the working and / or non-working areas of the semiconductor device is increased. Sufficient stress-locking steps are provided on both the working and / or non-working areas of the semiconductor device to eliminate the damage to the working and / or non-working areas of the semiconductor device 10 caused by thermomechanical stress. This not only eliminates the damage caused by stress in the parallel direction on the working and / or non-working areas of the semiconductor device, but also prevents damage caused by stress in the vertical direction applied to the working and / or non-working areas of the semiconductor device, thereby improving the reliability of the semiconductor device.

[0111] It should be noted that the semiconductor device provided in the embodiments of the present invention can be an active semiconductor device or a passive semiconductor device, and the embodiments of the present invention do not limit it in this regard.

[0112] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; At least one material layer located on one side of the substrate, the at least one material layer comprising N material layers, where N≥1 and N is an integer; At least the Nth material layer has a patterned structure; wherein the Nth material layer is the outermost material layer on the side of the material layer away from the substrate; the patterned structure includes a recessed patterned structure and / or a raised patterned structure; The semiconductor device further includes an encapsulation layer located on the side of the material layer away from the substrate; The encapsulation layer covers the material layer and also covers the patterned structure; The semiconductor device includes a working region and a non-working region, the non-working region surrounding the working region; The at least one material layer includes at least one metal layer located in the working area and at least one dielectric layer located in the non-working area; At least one metal layer includes N1 metal layers, where N1 ≥ 1 and N1 is an integer; At least one dielectric layer includes N2 dielectric layers, where N2 ≥ 1 and N2 is an integer; At least the N1th metal layer has a first patterned structure, and / or at least the N2th dielectric layer has a second patterned structure; At least one metal layer includes a first metal layer close to the substrate, an N1th metal layer located on the side of the first metal layer away from the substrate, and a jth metal layer located between the first metal layer and the N1th metal layer, where N1≥2 and N1 is an integer, 0≤j≤N1, and j is an integer; The first patterned structure is provided in at least two of the first metal layers to the N1th metal layer, and the first patterned structures in different metal layers overlap at least partially along a first direction, wherein the first direction is perpendicular to the plane of the substrate.

2. The semiconductor device according to claim 1, characterized in that, The working area includes an active area and a passive area surrounding the active area; The metal layer includes electrodes and / or electrode connection structures located within the working area, and at least one of the electrodes and / or the electrode connection structures is provided with the first patterned structure.

3. The semiconductor device according to claim 2, characterized in that, The first patterned structure includes a strip groove structure, wherein the extension direction of the long side of the strip groove structure is parallel to the current direction in the metal layer.

4. The semiconductor device according to claim 1, characterized in that, The second patterned structure includes a recessed patterned structure; At least one dielectric layer includes a first dielectric layer near the substrate, an N2 dielectric layer located on the side of the first dielectric layer away from the substrate, and a k-th dielectric layer located between the first dielectric layer and the N2 dielectric layer, where N2 ≥ 2 and N2 is an integer, 0 ≤ k ≤ N2, and k is an integer; At least the N2 dielectric layer is provided with the second patterned structure; Alternatively, the second patterned structure is provided in at least two dielectric layers, wherein the at least two dielectric layers include the N2th dielectric layer, the N2-1th dielectric layer to the kth dielectric layer stacked sequentially, where 1≤k≤N2-1.

5. The semiconductor device according to claim 1, characterized in that, The second patterned structure includes a raised patterned structure; At least one dielectric layer includes a first dielectric layer near the substrate, an N2 dielectric layer located on the side of the first dielectric layer away from the substrate, and a k-th dielectric layer located between the first dielectric layer and the N2 dielectric layer, where N2 ≥ 2 and N2 is an integer, 0 ≤ k ≤ N2, and k is an integer; The semiconductor device further includes at least one metal patterned structure located in the non-working area, the at least one metal patterned structure being located between the first dielectric layer and the N2 dielectric layer, and the at least one metal patterned structure forming the raised patterned structure on the surface of the N2 dielectric layer away from the substrate.

6. The semiconductor device according to claim 5, characterized in that, At least one metal layer includes a first metal layer close to the substrate, an N1th metal layer located on the side of the first metal layer away from the substrate, and a jth metal layer located between the first metal layer and the N1th metal layer, where N1≥2 and N1 is an integer, 0≤j≤N1, and j is an integer; The j-th to N1-th metal layers stacked sequentially include a portion located in the non-working area, and the j-th to N1-th metal layers stacked sequentially in the non-working area are provided with the metal patterned structure.

7. The semiconductor device according to claim 6, characterized in that, The patterned metal structure includes a first edge near the side of the working area; Along the direction from the non-working area to the working area, the minimum distance between the first edge and the metal layer that is disposed in the same layer as the metal patterned structure and located in the working area is L, where L≥1μm.

8. The semiconductor device according to claim 1, characterized in that, At least one metal layer includes a first metal layer close to the substrate, an N1th metal layer located on the side of the first metal layer away from the substrate, and a jth metal layer located between the first metal layer and the N1th metal layer, where N1≥2 and N1 is an integer, 0≤j≤N1, and j is an integer; At least one dielectric layer includes a first dielectric layer near the substrate, an N2 dielectric layer located on the side of the first dielectric layer away from the substrate, and a k-th dielectric layer located between the first dielectric layer and the N2 dielectric layer, where N2 ≥ 2 and N2 is an integer, 0 ≤ k ≤ N2, and k is an integer; The first dielectric layer to the N2 dielectric layer are all disposed in the working area and the non-working area; The first dielectric layer is disposed between the substrate and the first metal layer, and the N2 dielectric layer is disposed on the side of the N1 metal layer away from the substrate.

9. A method for fabricating a semiconductor device, used to fabricate the semiconductor device according to any one of claims 1-8, characterized in that, The preparation method includes: Provide substrate; At least one material layer is prepared on one side of the substrate, the at least one material layer comprising N material layers, where N≥1 and N is an integer; Patterned structures are prepared in at least the Nth material layer.

10. The preparation method according to claim 9, characterized in that, The semiconductor device includes a working region and a non-working region, the non-working region surrounding the working region; At least one material layer is prepared on one side of the substrate, including: At least one metal layer is prepared in the working area, and at least one dielectric layer is prepared in the non-working area. The at least one metal layer includes N1 metal layers, where N1 ≥ 1 and N1 is an integer; the at least one dielectric layer includes N2 dielectric layers, where N2 ≥ 1 and N2 is an integer. Patterned structures are fabricated in at least the Nth material layer, including: A first patterned structure is prepared in at least the N1 metal layer, and / or a second patterned structure is prepared in at least the N2 dielectric layer.

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