Semiconductor chip including through electrode and semiconductor package including the same

Abstract

A semiconductor chip includes a main body portion having a front surface and a back surface, a plurality of through electrodes penetrating the main body portion and arranged in an array region in a first direction, a plurality of front surface connection electrodes respectively coupled to the through electrodes over the front surface of the main body portion, and a plurality of back surface connection electrodes respectively coupled to the through electrodes over the back surface of the main body portion. The array region includes a central region and edge regions located on both sides of the central region in the first direction. Centers of the front surface connection electrodes and centers of the back surface connection electrodes located in each of the edge regions are disposed at a distance farther from the central region than centers of the corresponding through electrodes.

Description

Technical Field

[0001] Various embodiments of this disclosure relate to semiconductor technology, and more specifically, to a semiconductor chip including a through electrode and a semiconductor package including the semiconductor chip. Background Technology

[0002] As data processing capacity increases, electronic products are becoming smaller. This requires semiconductor chips used in electronic products to be thinner and smaller in overall size. In addition, semiconductor packages with multiple embedded semiconductor chips are being manufactured.

[0003] Semiconductor chips can be interconnected within a package through vias that penetrate the semiconductor chip to provide an electrical connection path. Summary of the Invention

[0004] Some embodiments of this disclosure relate to semiconductor chips including through electrodes and semiconductor packages including semiconductor chips, which can reduce size while minimizing processing defects.

[0005] According to an embodiment of this disclosure, a semiconductor chip includes: a body portion having a front surface and a rear surface; a plurality of through electrodes penetrating the body portion and arranged in an array region along a first direction; a plurality of front surface connecting electrodes respectively connected to the through electrodes above the front surface of the body portion; and a plurality of rear surface connecting electrodes respectively connected to the through electrodes above the rear surface of the body portion. The array region includes a central region and a plurality of edge regions located on both sides of the central region in the first direction. The centers of the front surface connecting electrodes and the centers of the rear surface connecting electrodes located in each edge region are positioned at a distance farther from the central region than the centers of the corresponding through electrodes.

[0006] According to another embodiment of this disclosure, a semiconductor chip includes: a body portion having a front surface and a rear surface; a plurality of through electrodes penetrating the body portion and arranged along a first direction in each of a first array region and a second array region adjacent to each other along the first direction; a plurality of front surface connecting electrodes respectively connected to the through electrodes above the front surface of the body portion; and a plurality of rear surface connecting electrodes respectively connected to the through electrodes above the rear surface of the body portion. Each of the first array region and the second array region includes a central region, and a side edge region and a side edge region are respectively located on both sides of the central region in the first direction. In each of the first array region and the second array region, the center of the front surface connecting electrode and the center of the rear surface connecting electrode located in the side edge region and the side edge region, respectively, are disposed at a distance farther from the central region than the center of the corresponding through electrode.

[0007] According to another embodiment of this disclosure, a semiconductor package includes: a first semiconductor chip including a first body portion having a front surface and a rear surface, a plurality of first through electrodes penetrating the first body portion and disposed in a first direction, and a plurality of first rear surface connection electrodes respectively connected to the first through electrodes above the rear surface of the first body portion; and a second semiconductor chip including a second body portion having a front surface and a rear surface, and a plurality of second front surface connection electrodes located above the front surface of the second body portion. The first rear surface connection electrodes and the second front surface connection electrodes are respectively connected to each other. An array region includes a central region and a plurality of edge regions located on both sides of the central region in a first direction. The centers of the second front surface connection electrodes and the centers of the first rear surface connection electrodes located in each edge region are disposed at a distance farther from the central region than the centers of the corresponding first through electrodes. Attached Figure Description

[0008] Figure 1A This is a cross-sectional view showing a semiconductor chip according to an embodiment of the present disclosure.

[0009] Figure 1B It shows the arrangement of Figure 1A A plan view of the region through the electrode.

[0010] Figure 1C This is a plan view showing another example of a region with through electrodes arranged.

[0011] Figure 2 This is a cross-sectional view showing a stacked semiconductor chip according to an embodiment of the present disclosure.

[0012] Figure 3This is a plan view showing a region in which a semiconductor chip is arranged with through electrodes according to another embodiment of the present disclosure.

[0013] Figure 4 This is a plan view showing a region in which a semiconductor chip is arranged with through electrodes according to another embodiment of the present disclosure.

[0014] Figure 5 This is a plan view showing a region in which a semiconductor chip is arranged with through electrodes according to another embodiment of the present disclosure.

[0015] Figure 6 This is a plan view showing a region in which a semiconductor chip is arranged with through electrodes according to another embodiment of the present disclosure.

[0016] Figure 7 This is a plan view showing a region in which a semiconductor chip is arranged with through electrodes according to another embodiment of the present disclosure.

[0017] Figure 8 This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure.

[0018] Figure 9 This is a cross-sectional view showing a stacked semiconductor chip according to another embodiment of the present disclosure.

[0019] Figure 10 A block diagram illustrating an electronic system employing a memory card including a semiconductor package according to an embodiment is shown.

[0020] Figure 11 A block diagram illustrating another electronic system including a semiconductor package according to an embodiment is shown. Detailed Implementation

[0021] Some embodiments of this disclosure are described in more detail below with reference to the accompanying drawings. However, this disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be accessible to those skilled in the art. Throughout this disclosure, similar reference numerals denote similar components in the various drawings and embodiments.

[0022] The accompanying drawings are not necessarily to scale, and in some cases, the scale may be exaggerated to clearly show the features of the embodiments. When the first layer is referred to as being "on" the second layer or "on" the substrate, it refers not only to the case where the first layer is formed directly on the second layer or the substrate, but also to the case where the third layer exists between the first layer and the second layer or the substrate.

[0023] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0024] Figure 1A This is a cross-sectional view showing a semiconductor chip according to an embodiment of the present disclosure. Figure 1B It shows the arrangement of Figure 1A A plan view of the region through the electrode.

[0025] Reference Figure 1A and Figure 1B The semiconductor chip 100 of this embodiment may include a main body portion 110, a wiring portion 115, a through electrode 120, a front surface connection electrode 130, a bonding layer 140, and a rear surface connection electrode 150.

[0026] The main body portion 110 may be formed of a semiconductor material such as silicon (Si) or germanium (Ge) and may have a front surface 111, a rear surface 112, and side surfaces connecting the front surface 111 and the rear surface 112 to each other. The front surface 111 of the main body portion 110 may refer to an active surface provided with a wiring portion 115 electrically connected to the through electrode 120, and the rear surface 112 of the main body portion 110 may refer to a surface opposite to the front surface 111. In this embodiment of the present disclosure, the front surface 111 is shown to be located below the rear surface 112 in the vertical direction. However, the present disclosure is not limited thereto, and the positions of the front surface 111 and the rear surface 112 may be interchanged.

[0027] The wiring portion 115 may include various circuit / wiring structures. For ease of description, the circuit / wiring structures in the wiring portion 115 are simply shown as lines, but the shape and connection relationships of the circuit / wiring structures may be modified differently. Here, the circuit / wiring structures may be implemented differently depending on the type of semiconductor chip 100. For example, the semiconductor chip 100 may include volatile memory such as dynamic random access memory (DRAM) and static RAM (SRAM), non-volatile memory such as NAND flash memory, resistive RAM (RRAM), phase-change RAM (PRAM), magnetoresistive RAM (MRAM) and ferroelectric RAM (FRAM), logic circuits, etc.

[0028] A through-electrode 120 may be formed in the body portion 110. The through-electrode 120 may have a pillar shape extending vertically from the front surface 111 to the rear surface 112 of the body portion 110 to penetrate the body portion 110. As an example, the through-electrode 120 may be a through-silicon via (TSV). The through-electrode 120 may comprise various conductive materials. As an example, the through-electrode 120 may comprise a metal or a compound of metals such as copper (Cu), tin (Sn), silver (Ag), tungsten (W), nickel (Ni), ruthenium (Ru), and cobalt (Co). Although not shown, a dielectric pad for insulating the through-electrode 120 and the body portion 110 from each other may be inserted between the through-electrode 120 and the body portion 110. Additionally, although not shown, a barrier metal layer may be formed around the sidewalls of the through-electrode 120 to prevent diffusion of the metal forming the through-electrode 120. One end of the through electrode 120 can be connected to the wiring portion 115, and the other end of the through electrode 120 can be connected to the rear surface connection electrode 150. One end of the through electrode 120 can be electrically connected to the front surface connection electrode 130 through the wiring portion 115. Various signals or power supplies for driving the semiconductor chip 100 can be transmitted through the through electrode 120.

[0029] The through electrodes 120 can be arranged with a first spacing P1 in a first direction. Here, the first spacing P1 can refer to the distance between the center of one through electrode 120 and the center of a neighboring through electrode 120. The first spacing P1 can have a substantially constant value, i.e., a fixed value. Additionally, each through electrode 120 can have a first width W1 in the first direction. The first width W1 can have a substantially constant value, i.e., a fixed value. Although each through electrode 120 is shown as having a circular shape in plan view, the planar shape of each through electrode 120 can be modified differently.

[0030] The region where the through electrodes 120 are arranged may be referred to as the array region AR. Here, the array region AR may include a central region CR located at the center and edge regions ER1 and ER2 located on both sides of the central region CR in a first direction. For ease of description, the edge region located on one side (e.g., the left side) in the first direction may be referred to as the one-side edge region ER1, and the edge region located on the other side (e.g., the right side) in the first direction may be referred to as the other-side edge region ER2. In this embodiment, it is shown that three through electrodes 120 are arranged along the first direction in the array region AR, and the three through electrodes 120 are respectively located on the one-side edge region ER1, the central region CR, and the other-side edge region ER2. However, the embodiments of this disclosure are not limited to this, and the number of through electrodes 120 arranged along the first direction in the array region AR may vary, and the number of regions in the array region AR distinguished according to the arrangement of the through electrodes 120 may also vary.

[0031] A front surface connection electrode 130 may be formed above a wiring portion 115 formed above the front surface 111 of the body portion 110. The front surface connection electrode 130 may be electrically connected to the wiring portion 115, and thus electrically connected to one end of the through electrode 120. The front surface connection electrode 130 may comprise a metal or a compound thereof, such as copper (Cu), nickel (Ni), or a combination thereof, and may have a single-layer or multi-layer structure.

[0032] The front surface connection electrode 130 can be configured to overlap and connect with the through electrode 120, respectively. The front surface connection electrode 130 and the through electrode 120 can be connected via wiring portion 115. Therefore, in this embodiment of the present disclosure, three front surface connection electrodes 130 can be arranged in the array region AR along a first direction, and these three front surface connection electrodes 130 can be located in one side edge region ER1, the central region CR, and the other side edge region ER2, respectively. Each front surface connection electrode 130 in the first direction can have a second width W2. The second width W2 can be greater than the first width W1 of the through electrode 120.

[0033] In this configuration, in the first direction, the center of the front surface connecting electrode 130 of the central region CR can substantially coincide with the center of the through electrode 120 of the central region CR. On the other hand, in the first direction, the center of the front surface connecting electrode 130 of each of the side edge regions ER1 and the other side edge region ER2 can be located at a greater distance from the central region CR than the center of the through electrode 120 of each of the side edge regions ER1 and the other side edge region ER2. For example, in the first direction, the center of the front surface connecting electrode 130 of one side edge region ER1 can be located to the left of the center of the through electrode 120 of one side edge region ER1, and the center of the front surface connecting electrode 130 of the other side edge region ER2 can be located to the right of the center of the through electrode 120 of the other side edge region ER2. However, in this configuration, the position of the front surface connecting electrode 130 in each of the side edge regions ER1 and the other side edge region ER2 can be controlled such that the front surface connecting electrode 130 overlaps with the entire end of the through electrode 120. The distance between the center of the through electrode 120 in each of the side edge regions ER1 and ER2 and the center of the front surface connecting electrode 130 can be represented by the numeral D.

[0034] Since the center of each front surface connecting electrode 130 in one side edge region ER1 and the other side edge region ER2 is located at a greater distance from the central region CR than the center of the through electrode 120, the front surface connecting electrodes 130 can be configured to have a second spacing P2 in the first direction that is greater than the first spacing P1. The second spacing P2 can refer to the distance between the center of one front surface connecting electrode 130 and the center of the adjacent front surface connecting electrode 130. The second spacing P2 can have a substantially constant value. Although the respective front surface connecting electrodes 130 are shown as having a circular shape in the plan view, the planar shape of the respective front surface connecting electrodes 130 can vary.

[0035] A bonding layer 140 may be formed over the front surface connection electrode 130. The bonding layer 140 may be provided to bond to, for example, another semiconductor chip or other constituent element (not shown) of the substrate, to connect to the semiconductor chip 100 while facing the front surface 111 of the semiconductor chip 100. For example, when multiple semiconductor chips 100 are stacked in a vertical direction, the bonding layer 140 may perform the function of bonding to the rear surface connection electrode facing itself. This will be referred to... Figure 2 A more detailed description follows. The bonding layer 140 may include solder material having a hemispherical, spherical, or similar shape. However, the spirit and concept of this embodiment are not limited thereto, and the shape and material of the bonding layer 140 may be modified differently.

[0036] A rear surface connection electrode 150 may be formed above the rear surface 112 of the main body portion 110. The rear surface connection electrode 150 may be configured to overlap and connect with the through electrode 120, respectively. The rear surface connection electrode 150 may directly contact the through electrode 120. Unlike the front surface connection electrode 130, the rear surface connection electrode 150 may directly contact the other end of the through electrode 120. The rear surface connection electrode 150 may include a metal such as copper (Cu), nickel (Ni), or a combination thereof, or may include compounds thereof, and may have a single-layer structure or a multi-layer structure.

[0037] Here, the width and arrangement of the rear surface connecting electrode 150 in the first direction can be substantially the same as the width and arrangement of the front surface connecting electrode 130. In other words, in a plan view, the rear surface connecting electrode 150 and the front surface connecting electrode 130 can overlap each other. Therefore, three rear surface connecting electrodes 150 can be arranged in the array region AR along the first direction, and these three rear surface connecting electrodes 150 can be located in one side edge region ER1, the central region CR, and the other side edge region ER2, respectively. Each rear surface connecting electrode 150 in the first direction can have a second width W2. In the first direction, the center of the rear surface connecting electrode 150 in the central region CR can substantially coincide with the center of the through electrode 120 in the central region CR. On the other hand, in the first direction, the center of the rear surface connecting electrode 150 of each of the one side edge region ER1 and the other side edge region ER2 can be located at a greater distance from the central region CR than the center of the through electrode 120 of each of the one side edge region ER1 and the other side edge region ER2. The position of the rear surface connecting electrode 150 in each of the side edge regions ER1 and ER2 can be controlled such that the rear surface connecting electrode 150 overlaps with the entire other end of the through electrode 120. The distance between the center of the through electrode 120 and the center of the rear surface connecting electrode 150 in each of the side edge regions ER1 and ER2 is indicated by the reference numeral D. The rear surface connecting electrode 150 can be configured to have a second spacing P2 in a first direction. Although each rear surface connecting electrode 150 is shown as having a circular shape in the plan view, the planar shape of each rear surface connecting electrode 150 can vary.

[0038] The effects obtained by the above-described semiconductor chip 100 will be described below in comparison with existing technologies.

[0039] When the center and spacing of the front and rear surface connection electrodes are the same as those of the through electrodes, as in the prior art, the spacing of the front and rear surface connection electrodes can be reduced if the spacing of the through electrodes is reduced to the desired level. As a result, sufficient distance cannot be ensured between adjacent front surface connection electrodes and adjacent rear surface connection electrodes. When forming a bonding structure including front surface connection electrodes, rear surface connection electrodes, and a bonding layer between the front and rear surface connection electrodes by stacking multiple semiconductor chips vertically adjacent to each other, voids may occur between the bonding structures because molding material or gap-filling material has difficulty flowing through the narrow gaps between the bonding structures. These voids can lead to process defects, such as bridging between adjacent bonding structures (especially between adjacent bonding layers). On the other hand, when the spacing of the front and rear surface connection electrodes increases along with the spacing of the through electrodes, the space in the semiconductor chip for the through electrodes and connection electrodes can be increased. This can increase the planar dimensions of the semiconductor chip / semiconductor package.

[0040] According to embodiments of this disclosure, by satisfying the requirement to reduce the spacing of the through electrodes 120, the planar dimensions of the semiconductor chip 100 and the semiconductor package including the semiconductor chip 100 can be reduced. Furthermore, when a semiconductor package consisting of multiple stacked semiconductor chips 100 is implemented by increasing the spacing between the front surface connection electrodes 130 and the rear surface connection electrodes 150, process defects such as bridging of bonding layers can be reduced.

[0041] Furthermore, the through electrode 120, the front surface connecting electrode 130, and the rear surface connecting electrode 150 can be arranged not only in the first direction but also in the second direction. In other words, they can be arranged in a matrix in both the first and second directions (see...). Figure 1C ).

[0042] Figure 2 This is a cross-sectional view showing a stacked semiconductor chip according to an embodiment of the present disclosure. Figure 2 This shows two semiconductor chips stacked vertically.

[0043] Reference Figure 2 The second semiconductor chip 200 can be stacked on top of the first semiconductor chip 100.

[0044] The first semiconductor chip 100 can be coupled with the above-mentioned... Figure 1A and Figure 1B The semiconductor chip 100 shown is essentially the same. Therefore, it is used in conjunction with... Figure 1A and Figure 1BThe same reference numerals are used for the first semiconductor chip 100. The first semiconductor chip 100 may include: a first body portion 110 having a front surface 111 and a rear surface 112; a first wiring portion 115 above the front surface 111 of the first body portion 110; a first through electrode 120 penetrating the first body portion 110; a first front surface connecting electrode 130 connected to the first through electrode 120 above the first wiring portion 115 via the first wiring portion 115; a first bonding layer 140 above the first front surface connecting electrode 130; and a first rear surface connecting electrode 150 connected to the first through electrode 120 above the rear surface 112 of the first body portion 110.

[0045] In addition to the shape of the second bonding layer 240, the second semiconductor chip 200 can also be coupled with the above-mentioned... Figure 1A and Figure 1B The semiconductor chip 100 shown is substantially the same. In other words, the second semiconductor chip 200 may include: a second body portion 210 having a front surface 211 and a rear surface 212; a second wiring portion 215 above the front surface 211 of the second body portion 210; a second through electrode 220 penetrating the second body portion 210; a second front surface connection electrode 230 connected to the second through electrode 220 above the second wiring portion 215 via the second wiring portion 215; a second bonding layer 240 above the second front surface connection electrode 230; and a second rear surface connection electrode 250 connected to the second through electrode 220 above the rear surface 212 of the second body portion 210.

[0046] The arrangement and width of the first through electrode 120 and the second through electrode 220 can be substantially the same. Specifically, the centers of the first through electrode 120 and the second through electrode 220 can coincide with each other, and the first through electrode 120 and the second through electrode 220 can be arranged in a first direction with a first spacing P1.

[0047] The arrangement and width of the first front surface connecting electrode 130, the first rear surface connecting electrode 150, the second front surface connecting electrode 230, and the second rear surface connecting electrode 250 can be substantially the same. Specifically, the centers of the first front surface connecting electrode 130, the first rear surface connecting electrode 150, the second front surface connecting electrode 230, and the second rear surface connecting electrode 250 can coincide with each other. The first front surface connecting electrode 130, the first rear surface connecting electrode 150, the second front surface connecting electrode 230, and the second rear surface connecting electrode 250 can be arranged in a first direction at a second spacing P2.

[0048] Here, in the central region CR, the centers of the first front surface connecting electrode 130, the first rear surface connecting electrode 150, the second front surface connecting electrode 230, and the second rear surface connecting electrode 250 may coincide with the centers of the first through electrode 120 and the second through electrode 220. On the other hand, in one side edge region ER1, the centers of the first front surface connecting electrode 130, the first rear surface connecting electrode 150, the second front surface connecting electrode 230, and the second rear surface connecting electrode 250 may be located at a greater distance from the central region CR than the centers of the first through electrode 120 and the second through electrode 220 (e.g., on the left side). Furthermore, in the other side edge region ER2, the centers of the first front surface connecting electrode 130, the first rear surface connecting electrode 150, the second front surface connecting electrode 230, and the second rear surface connecting electrode 250 may be located at a greater distance from the central region CR than the centers of the first through electrode 120 and the second through electrode 220 (e.g., on the right side). Therefore, the second spacing P2 may be greater than the first spacing P1. In each of the side edge regions ER1 and the other side edge regions ER2, the distance between the center of the first front surface connecting electrode 130, the first rear surface connecting electrode 150, the second front surface connecting electrode 230 and the second rear surface connecting electrode 250 and the center of the first through electrode 120 and the second through electrode 220 is indicated by the numeral D.

[0049] The second semiconductor chip 200 may be stacked on top of the first semiconductor chip 100, with its front surface 211 facing the rear surface 112 of the first semiconductor chip 100. More specifically, the second bonding layer 240 of the second semiconductor chip 200 may be bonded to the first rear surface connection electrode 150 of the first semiconductor chip 100 via a bonding process. During the bonding process, the shape of the second bonding layer 240 may differ from the shape of the first bonding layer 140. Therefore, a bonding structure BS formed by the first rear surface connection electrode 150, the second bonding layer 240, and the second front surface connection electrode 230 may be formed between the first semiconductor chip 100 and the second semiconductor chip 200. Multiple bonding structures BS may be arranged in a first direction with a second spacing P2.

[0050] In the aforementioned stacked structure of the first semiconductor chip 100 and the second semiconductor chip 200, the second spacing P2 of the bonding structure BS can be greater than the first spacing P1 of the first through electrode 120 and the second through electrode 220. Therefore, the spacings S1, S2, and S3 between the bonding structures BS can be significantly ensured. More specifically, the spacing S1 between the first rear surface connecting electrodes 150, the spacing S2 between the second bonding layers 240, and the spacing S3 between the second front surface connecting electrodes 230 can be significantly ensured. Therefore, when the space between the first semiconductor chip 100 and the second semiconductor chip 200 is filled with molding material or gap-filling material (see...), the spacing between the first semiconductor chip 100 and the second semiconductor chip 200 can be significantly ensured. Figure 8When filling with 810), the flow of molding material / gap filler material is smoothed. This reduces or prevents the formation of voids between bonded structures (BS) and the occurrence of process defects.

[0051] According to embodiments of this disclosure, as described, two semiconductor chips 100 and 200 are stacked in a vertical direction; however, the concept and spirit of this disclosure are not limited thereto. According to another embodiment of this disclosure, three or more semiconductor chips may be repeatedly stacked in a vertical direction. Therefore, a high-density semiconductor package in which multiple semiconductor chips are stacked in a vertical direction can be realized.

[0052] Furthermore, in the above embodiments of this disclosure, the case where the number of through electrodes, front surface connecting electrodes, and rear surface connecting electrodes arranged in the first direction is three is described; however, this disclosure is not limited to this, and the number may vary. Hereinafter, reference will be made to… Figures 3 to 5 A description is provided. In describing additional embodiments of this disclosure, the focus will be on the differences from the embodiments described above.

[0053] Figure 3 This is a plan view showing a region in which a semiconductor chip is arranged with through electrodes according to another embodiment of the present disclosure.

[0054] Reference Figure 3 In an array region AR comprising a central region CR, a side edge region ER1, and a side edge region ER2, two through electrodes 320 may be arranged with a first spacing P1 in a first direction. The two through electrodes 320 may be located in the side edge region ER1 and the side edge region ER2, respectively. The through electrodes may not be located in the central region CR.

[0055] The front surface connecting electrode 330 and the rear surface connecting electrode 350 may be formed to overlap and connect with the through electrode 320 above the front and rear surfaces of the main body portion (not shown), respectively. For reference, the front surface connecting electrode 330 may be connected to the through electrode 320 above the front surface of the main body portion via a wiring portion, and the rear surface connecting electrode 350 may directly contact the through electrode 320. Therefore, the two front surface connecting electrodes 330 may be located in one side edge region ER1 and the other side edge region ER2, respectively, and the two rear surface connecting electrodes 350 may be located in one side edge region ER1 and the other side edge region ER2, respectively. The front surface connecting electrode 330 and the rear surface connecting electrode 350 may not be located in the central region CR.

[0056] Here, in the first direction, the centers of the front surface connecting electrodes 330 and the rear surface connecting electrodes 350 of one side edge region ER1 and the other side edge region ER2 can be located at a distance farther from the central region CR than the centers of one side edge region ER1 and the other side edge region ER2. For example, in the first direction, the centers of the front surface connecting electrodes 330 and the rear surface connecting electrodes 350 of one side edge region ER1 can be located to the left of the center of the through electrode 320 of one side edge region ER1. The centers of the front surface connecting electrodes 330 and the rear surface connecting electrodes 350 of the other side edge region ER2 can be located to the right of the center of the through electrode 320 of the other side edge region ER2. Therefore, the plurality of front surface connecting electrodes 330 can be arranged to have a second spacing P2 greater than the first spacing P1 in the first direction, and the plurality of rear surface connecting electrodes 350 can be arranged to have a second spacing P2 greater than the first spacing P1 in this direction. The distance between the centers of the front surface connecting electrodes 330 and the rear surface connecting electrodes 350 and the center of the through electrode 320 is indicated by the reference numeral D.

[0057] Figure 4 This is a plan view showing a region in which a semiconductor chip is arranged with through electrodes according to another embodiment of the present disclosure.

[0058] Reference Figure 4 In an array region AR comprising a central region CR, two side edge regions ER11 and ER12, and two other side edge regions ER21 and ER22, four through electrodes 420 may be configured with a first spacing P1 in a first direction. The side edge regions ER11 and ER12 may include a first side edge region ER11 and a second side edge region ER12 arranged sequentially according to their distance from the central region CR. The other side edge regions ER21 and ER22 may include a first other side edge region ER21 and a second other side edge region ER22 arranged sequentially according to their distance from the central region CR. The four through electrodes 420 may be located in the first side edge region ER11, the second side edge region ER12, the first other side edge region ER21, and the second other side edge region ER22, respectively. The through electrodes may not be located in the central region CR.

[0059] The front surface connecting electrode 430 and the rear surface connecting electrode 450 may be formed to overlap and connect with the through electrode 420 on the front and rear surfaces of the main body portion (not shown). Therefore, the four front surface connecting electrodes 430 may be located in the first side edge region ER11, the second side edge region ER12, the first other side edge region ER21, and the second other side edge region ER22, respectively. Additionally, the four rear surface connecting electrodes 450 may be located in the first side edge region ER11, the second side edge region ER12, the first other side edge region ER21, and the second other side edge region ER22, respectively. The front surface connecting electrodes 430 and the rear surface connecting electrodes 450 may not be located in the central region CR.

[0060] In the first direction, the centers of the front surface connecting electrodes 430 and rear surface connecting electrodes 450 of the first side edge region ER11 and the first other side edge region ER21 can be located at a distance farther from the central region CR than the center of the through electrode 420 of the first side edge region ER11 and the first other side edge region ER21. For example, in the first direction, the centers of the front surface connecting electrodes 430 and rear surface connecting electrodes 450 of the first side edge region ER11 can be located to the left of the center of the through electrode 420 of the first side edge region ER11, and the centers of the front surface connecting electrodes 430 and rear surface connecting electrodes 450 of the first other side edge region ER21 can be located to the right of the center of the through electrode 420 of the first other side edge region ER21. The distance between the centers of the front surface connecting electrodes 430 and rear surface connecting electrodes 450 and the center of the through electrode 420 in the first side edge region ER11 and the first other side edge region ER21 can be referred to as the first distance D1.

[0061] Furthermore, in the first direction, the centers of the front surface connecting electrodes 430 and rear surface connecting electrodes 450 of the second side edge region ER12 and the second side edge region ER22 can be located at a distance farther from the central region CR than the center of the through electrode 420 of the second side edge region ER12 and the second side edge region ER22. For example, in the first direction, the centers of the front surface connecting electrodes 430 and rear surface connecting electrodes 450 of the second side edge region ER12 can be located to the left of the center of the through electrode 420 of the second side edge region ER12, and the centers of the front surface connecting electrodes 430 and rear surface connecting electrodes 450 of the second side edge region ER22 can be located to the right of the center of the through electrode 420 of the second side edge region ER22. The distance between the centers of the front surface connecting electrodes 430 and rear surface connecting electrodes 450 and the center of the through electrode 420 in the second side edge region ER12 and the second side edge region ER22 can be referred to as the second distance D2.

[0062] In this case, the second distance D2 can be greater than the first distance D1. In other words, as the distance from the central region CR increases, the distance between the center of the through electrode 420 and the centers of the front surface connecting electrode 430 and the rear surface connecting electrode 450 can increase. Even in this case, the spacing between the front surface connecting electrode 430 and the rear surface connecting electrode 450 can remain substantially constant. In other words, the plurality of front surface connecting electrodes 430 can be arranged with a second spacing P2 in the first direction that is greater than the first spacing P1, and the plurality of rear surface connecting electrodes 450 can be arranged with a second spacing P2 in the first direction that is greater than the first spacing P1.

[0063] Reference Figure 3 and Figure 4 The following describes the case where an even number of through electrodes are arranged in the array region.

[0064] The array region may include a central region and first to Nth edge regions arranged sequentially on both sides of the central region according to their distance from the central region (where N is a natural number of 2 or greater).

[0065] An even number of through electrodes may be located in the first to Nth edge regions on one side of the central region and in the first to Nth edge regions on the other side of the central region, respectively. Through electrodes may not be located in the central region. Additionally, front surface connecting electrodes and rear surface connecting electrodes, which overlap and connect with the even number of through electrodes, may be located in the first to Nth edge regions on one side of the central region and in the first to Nth edge regions on the other side of the central region, respectively.

[0066] In each of the first to Nth edge regions, the centers of the front surface connecting electrode and the rear surface connecting electrode can be located at a greater distance from the central region than the center of the through electrode. In this paper, the distance between the centers of the front surface connecting electrode and the rear surface connecting electrode in the kth edge region (where k is a natural number between 1 and N-1) and the center of the through electrode can be less than the distance between the centers of the front surface connecting electrode and the rear surface connecting electrode in the (k+1)th edge region and the center of the through electrode.

[0067] Even under these conditions, the spacing between the front surface connecting electrode and the rear surface connecting electrode can remain essentially constant and can be greater than the spacing between the through electrodes.

[0068] Figure 5 This is a plan view showing a region in which a semiconductor chip is arranged with through electrodes according to another embodiment of the present disclosure.

[0069] Reference Figure 5In an array region AR comprising a central region CR, two side edge regions ER11 and ER12, and two other side edge regions ER21 and ER22, five through electrodes 520 may be configured to have a first spacing P1 in a first direction. The side edge regions ER11 and ER12 may include a first side edge region ER11 and a second side edge region ER12 arranged sequentially according to their distance from the central region CR. The other side edge regions ER21 and ER22 may include a first other side edge region ER21 and a second other side edge region ER22 arranged sequentially according to their distance from the central region CR. The five through electrodes 520 may be located in the central region CR, the first side edge region ER11, the second side edge region ER12, the first other side edge region ER21, and the second other side edge region ER22, respectively.

[0070] The front surface connecting electrode 530 and the rear surface connecting electrode 550 can be formed to overlap and connect with the through electrode 520 on the front surface connecting electrode and the rear surface connecting electrode of the main body portion (not shown). Therefore, the five front surface connecting electrodes 530 can be located in the central region CR, the first side edge region ER11, the second side edge region ER12, the first other side edge region ER21, and the second other side edge region ER22, respectively, and the five rear surface connecting electrodes 550 can be located in the central region CR, the first side edge region ER11, the second side edge region ER12, the first other side edge region ER21, and the second other side edge region ER22, respectively.

[0071] In the first direction, the centers of the front surface connecting electrode 530 and the rear surface connecting electrode 550 of the central region CR can substantially coincide with the center of the through electrode 520 of the central region CR.

[0072] On the other hand, in the first direction, the centers of the front surface connecting electrode 530 and the rear surface connecting electrode 550 of each of the first side edge region ER11 and the first other side edge region ER21 can be located at a distance farther from the central region than the center of the through electrode 520 of each of the first side edge region ER11 and the first other side edge region ER21. For example, in the first direction, the centers of the front surface connecting electrode 530 and the rear surface connecting electrode 550 of the first side edge region ER11 can be located to the left of the center of the through electrode 520 of the first side edge region ER11, and the centers of the front surface connecting electrode 530 and the rear surface connecting electrode 550 of the first other side edge region ER21 can be located to the right of the center of the through electrode 520 of the first other side edge region ER21. The distance between the center of the front surface connecting electrode 530 and the rear surface connecting electrode 550 and the center of the through electrode 520 in each of the first side edge region ER11 and the first other side edge region ER21 can be referred to as the first distance D1.

[0073] Furthermore, in the first direction, the centers of the front surface connecting electrode 530 and the rear surface connecting electrode 550 of each of the second side edge region ER12 and the second other side edge region ER22 can be located at a distance farther from the central region than the center of the through electrode 520 of each of the second side edge region ER12 and the second other side edge region ER22. For example, in the first direction, the centers of the front surface connecting electrode 530 and the rear surface connecting electrode 550 of the second side edge region ER12 can be located to the left of the center of the through electrode 520 of the second side edge region ER12, and the centers of the front surface connecting electrode 530 and the rear surface connecting electrode 550 of the second other side edge region ER22 can be located to the right of the center of the through electrode 520 of the second other side edge region ER22. The distance between the center of the front surface connecting electrode 530 and the rear surface connecting electrode 550 and the center of the through electrode 520 in each of the second side edge region ER12 and the second other side edge region ER22 can be referred to as the second distance D2.

[0074] In this case, the second distance D2 can be greater than the first distance D1. In other words, as the distance from the central region CR increases, the distance between the center of the through electrode 520 and the centers of the front surface connecting electrode 530 and the rear surface connecting electrode 550 can increase. Even in this case, the spacing between the front surface connecting electrode 530 and the rear surface connecting electrode 550 can remain substantially constant. In other words, the front surface connecting electrode 530 can be arranged with a second spacing P2 in the first direction that is greater than the first spacing P1, and the plurality of rear surface connecting electrodes 550 can be arranged with a second spacing P2 in the first direction that is greater than the first spacing P1.

[0075] Reference Figure 1B and Figure 5 The following describes the case where an odd number of through electrodes are arranged in the array region.

[0076] The array region may include a central region and first to Nth edge regions arranged sequentially on both sides of the central region according to their distance from the central region (where N is a natural number of 2 or greater).

[0077] An odd number of through electrodes may be located in the central region, the first to Nth edge regions on one side of the central region, and the first to Nth edge regions on the other side of the central region, respectively. In addition, front surface connecting electrodes and rear surface connecting electrodes that overlap and connect with the odd number of through electrodes may be located in the central region, the first to Nth edge regions on one side of the central region, and the first to Nth edge regions on the other side of the central region.

[0078] In the central region, the centers of the front and rear surface connecting electrodes can substantially coincide with the center of the through electrode. In each of the first to Nth edge regions, the centers of the front and rear surface connecting electrodes can be located at a greater distance from the central region than the center of the through electrode. In this paper, the distance between the centers of the front and rear surface connecting electrodes and the center of the through electrode in the kth edge region (where k is a natural number between 1 and N-1) can be less than the distance between the centers of the front and rear surface connecting electrodes and the center of the through electrode in the (k+1)th edge region.

[0079] Even under these conditions, the spacing between the front surface connecting electrode and the rear surface connecting electrode can remain essentially constant and can be greater than the spacing between the through electrodes.

[0080] Furthermore, the through electrodes of the above embodiments of this disclosure can be arranged in multiple groups in the first direction. This will be referred to... Figure 6 and Figure 7 Description. In describing embodiments of this disclosure, the focus will be on the differences from the embodiments described above.

[0081] Figure 6 This is a plan view showing a region in which a semiconductor chip is arranged with through electrodes according to another embodiment of the present disclosure. Figure 6 Show a set including Figure 1B The three through electrodes and the two sets located in the first direction.

[0082] Reference Figure 6 It can provide a first array region AR1 and a second array region AR2 arranged adjacent to each other in a first direction. Each of the first array region AR1 and the second array region AR2 may include a central region CR, a side edge region ER1, and a side edge region ER2.

[0083] The through-electrode 620 of the first group G1 can be arranged in the first array region AR1, and the through-electrode 620 of the second group G2 can be arranged in the second array region AR2. The arrangement of the through-electrode 620 of each of the first group G1 and the second group G2 can be... Figure 1B The arrangement of the through electrodes 120 shown is substantially the same. In other words, the three through electrodes 620 in each of the first array region AR1 and the second array region AR2 may be located in the central region CR, one side edge region ER1 and the other side edge region ER2, respectively, to have a first spacing P1 in the first direction.

[0084] On the other hand, the distance P1' between the center of the through electrode 620 in the other edge region ER2 of the first array region AR1 and the center of the through electrode 620 in the one edge region ER1 of the adjacent second array region AR2 can be greater than the first spacing P1. In other words, the spacing of the through electrodes 620 may vary between the first array region AR1 and the second array region AR2.

[0085] The front surface connecting electrode 630 and rear surface connecting electrode 650 of the first group G1 can be arranged in the first array region AR1, and the front surface connecting electrode 630 and rear surface connecting electrode 650 of the second group G2 can be arranged in the second array region AR2. The arrangement of the front surface connecting electrode 630 and rear surface connecting electrode 650 of each of the first group G1 and the second group G2 can be... Figure 1BThe front surface connecting electrodes 130 and rear surface connecting electrodes 150 are arranged substantially the same. In other words, the three front surface connecting electrodes 630 and the three rear surface connecting electrodes 650 can be located in the central region CR, one side edge region ER1, and the other side edge region ER2, respectively, in each of the first array region AR1 and the second array region AR2, and can be configured to have a second spacing P2 in a first direction. Specifically, in each of the first array region AR1 and the second array region AR2, the center of the front surface connecting electrode 630 and the rear surface connecting electrode 650 of each of the one side edge region ER1 and the other side edge region ER2 can be located at a distance farther from the central region CR than the center of the through electrode 620 of each of the one side edge region ER1 and the other side edge region ER2. For example, the center of the front surface connecting electrode 630 and the rear surface connecting electrode 650 of one side edge region ER1 can be located to the left of the center of the through electrode 620 of one side edge region ER1. The centers of the front surface connecting electrode 630 and the rear surface connecting electrode 650 of the other edge region ER2 can be located to the right of the center of the through electrode 620 of the other edge region ER2. The distance between the centers of the front surface connecting electrode 630 and the rear surface connecting electrode 650 and the center of the through electrode 620 can be represented by the reference numeral D.

[0086] Here, the centers of the front surface connecting electrode 630 and the rear surface connecting electrode 650 of the other side edge region ER2 of the first array region AR1 are located to the right of the center of the through electrode 620, while the centers of the front surface connecting electrode 630 and the rear surface connecting electrode 650 of one side edge region ER1 of the second array region AR2 may be located to the left of the center of the through electrode 620. Therefore, there is a possibility that the distance S1' between the front surface connecting electrode 630 and the rear surface connecting electrode 650 of the other side edge region ER2 of the first array region AR1 and the front surface connecting electrode 630 and the rear surface connecting electrode 650 of one side edge region ER1 of the second array region AR2 can be reduced. However, in this embodiment of the present disclosure, as described above, by increasing the distance P1' between the center of the through electrode 620 of the other side edge region ER2 of the first array region AR1 and the center of the through electrode 620 of one side edge region ER1 of the second array region AR2 by increasing the first spacing P1, the reduction of the distance S1' can be prevented. This distance S1' can be substantially the same as the distance S1 between adjacent front surface connecting electrodes 630 and / or adjacent rear surface connecting electrodes 650 in each of the first array region AR1 and the second array region AR2. The spacing between the front surface connecting electrodes 630 and the rear surface connecting electrodes 650 between the first array region AR1 and the second array region AR2 can be maintained substantially the same as the second spacing P2. In other words, the distance between the center of the front surface connecting electrodes 630 and the rear surface connecting electrodes 650 of the other edge region ER2 of the first array region AR1 and the center of the front surface connecting electrodes 630 and the rear surface connecting electrodes 650 of one side edge region ER1 of the second array region AR2 can be substantially the same as the second spacing P2.

[0087] According to the embodiments of this disclosure, all the effects of the above embodiments can be obtained. Furthermore, even if the number of through electrodes 620 arranged in the first direction is large, it is not necessary to adjust the distance between the center of the through electrode 620 and the center of the front surface connecting electrode 630 and the rear surface connecting electrode 650 in multiple steps, which reduces the complexity of the manufacturing process.

[0088] Although not shown, groups of three or more through electrodes, as well as front surface connecting electrodes and rear surface connecting electrodes, may be arranged in the first direction. In this case, the arrangement of the individual groups and the arrangement between these groups may be substantially the same as those described in this figure.

[0089] Figure 7 This is a plan view showing a region in which a semiconductor chip is arranged with through electrodes according to another embodiment of the present disclosure. Figure 7 Show a set including Figure 3 Two through electrodes and two sets located in the first direction.

[0090] Reference Figure 7 The through-electrode 720 of the first group G1 can be arranged in the first array region AR1, and the through-electrode 720 of the second group G2 can be arranged in the second array region AR2. The arrangement of the through-electrode 720 of each of the first group G1 and the second group G2 can be... Figure 3 The arrangement of the through electrodes 320 is substantially the same. In other words, in each of the first array region AR1 and the second array region AR2, the two through electrodes 720 may be located in one side edge region ER1 and the other side edge region ER2 (excluding the central region CR), respectively, and may be arranged to have a first spacing P1 in the first direction.

[0091] On the other hand, the distance P1' between the center of the through electrode 720 of the other edge region ER2 of the first array region AR1 and the center of the through electrode 720 of the one side edge region ER1 of the adjacent second array region AR2 can be greater than the first spacing P1.

[0092] The front surface connecting electrode 730 and rear surface connecting electrode 750 of the first group G1 can be arranged in the first array region AR1, and the front surface connecting electrode 730 and rear surface connecting electrode 750 of the second group G2 can be arranged in the second array region AR2. The arrangement of the front surface connecting electrode 730 and rear surface connecting electrode 750 of each of the first group G1 and the second group G2 can be... Figure 3 The front surface connecting electrodes 330 and rear surface connecting electrodes 350 are arranged substantially the same. In other words, the two front surface connecting electrodes 730 and the two rear surface connecting electrodes 750 in each of the first array region AR1 and the second array region AR2 can be located in one side edge region ER1 and the other side edge region ER2 (excluding the central region CR), and can be arranged to have a second spacing P2 in a first direction. Specifically, in each of the first array region AR1 and the second array region AR2, the center of the front surface connecting electrode 730 and the rear surface connecting electrode 750 in each of the one side edge region ER1 and the other side edge region ER2 can be located at a distance farther from the central region CR than the center of the through electrode 720 in each of the one side edge region ER1 and the other side edge region ER2. For example, the center of the front surface connecting electrode 730 and the rear surface connecting electrode 750 in one side edge region ER1 can be located to the left of the center of the through electrode 720 in one side edge region ER1. The centers of the front surface connecting electrode 730 and the rear surface connecting electrode 750 of the other edge region ER2 can be located to the right of the center of the through electrode 720 of the other edge region ER2. The distance between the centers of the front surface connecting electrode 730 and the rear surface connecting electrode 750 and the center of the through electrode 720 can be represented by the reference numeral D.

[0093] Here, the centers of the front surface connecting electrode 730 and the rear surface connecting electrode 750 of the other side edge region ER2 of the first array region AR1 are located to the right of the center of the through electrode 720, while the centers of the front surface connecting electrode 730 and the rear surface connecting electrode 750 of one side edge region ER1 of the second array region AR2 may be located to the left of the center of the through electrode 720. Therefore, there is a possibility that the distance S1' between the front surface connecting electrode 730 and the rear surface connecting electrode 750 of the other side edge region ER2 of the first array region AR1 and the front surface connecting electrode 730 and the rear surface connecting electrode 750 of one side edge region ER1 of the second array region AR2 may be reduced. However, in this embodiment of the present disclosure, as described above, by increasing the distance P1' between the center of the through electrode 720 of the other side edge region ER2 of the first array region AR1 and the center of the through electrode 720 of one side edge region ER1 of the second array region AR2 beyond the first spacing P1, the reduction of the distance S1' can be prevented. The distance S1' can be substantially the same as the distance S1 between adjacent front surface connecting electrodes 730 and / or adjacent rear surface connecting electrodes 750 in each of the first array region AR1 and the second array region AR2. In other words, the spacing between the front surface connecting electrodes 730 and the rear surface connecting electrodes 750 between the first array region AR1 and the second array region AR2 can be maintained substantially the same as the second spacing P2.

[0094] Although not shown, when Figure 4 or Figure 5 When the multiple through electrodes included are referred to as a group, two or more groups may be arranged in the first direction.

[0095] Figure 8 This is a cross-sectional view showing a semiconductor package according to an embodiment of the present disclosure. The semiconductor package of this embodiment may include a plurality of semiconductor chips stacked in a vertical direction. The semiconductor chips may be substantially the same as those in the semiconductor chips of the above embodiments.

[0096] Reference Figure 8 The semiconductor package according to this embodiment may include a substrate 800 and a plurality of semiconductor chips 100, 200, 300, and 400 stacked on the substrate 800 in a vertical direction. In this embodiment of the present disclosure, a case of four semiconductor chips 100, 200, 300, and 400 stacked is shown; however, the present disclosure is not limited thereto, and the number of semiconductor chips stacked in the vertical direction may be modified differently. For ease of description, the four semiconductor chips 100, 200, 300, and 400 may be referred to as the first semiconductor chip 100, the second semiconductor chip 200, the third semiconductor chip 300, and the fourth semiconductor chip 400, respectively, in order of increasing distance from the substrate 800.

[0097] The substrate 800 may be a layer having circuitry and / or wiring structures to connect the stacked structure of semiconductor chips 100, 200, 300, and 400 to external constituent elements. For example, the substrate 800 may include a substrate such as a printed circuit board (PCB), an insert, a redistribution layer, etc. Alternatively, when the semiconductor chips 100, 200, 300, and 400 are memory chips, the substrate 800 may be a semiconductor chip including logic circuitry that supports the operation of the memory chips (e.g., operations of reading data from or writing data to the memory chips).

[0098] The substrate 800 may include an upper surface on which semiconductor chips 100, 200, 300 and 400 are disposed, and an opposite side of the upper surface and includes an external connection terminal 830 disposed thereon to connect the semiconductor package to the lower surface of an external constituent element.

[0099] Except for the fourth semiconductor chip 400 located on top of the first to fourth semiconductor chips 100, 200, 300 and 400, each of the first to third semiconductor chips 100, 200 and 300 may be implemented substantially identically to one of the semiconductor chips in the above-described embodiments of this disclosure. Since the fourth semiconductor chip 400 is located on top, it may not include through electrodes and rear surface connection electrodes.

[0100] The spaces between the substrate 800 and the first semiconductor chip 100, between the first semiconductor chip 100 and the second semiconductor chip 200, between the second semiconductor chip 200 and the third semiconductor chip 300, and between the third semiconductor chip 300 and the fourth semiconductor chip 400 can be filled with a gap-filling material 810. The gap-filling material 810 can be formed by allowing the bottom filler material to flow into the space based on a capillary phenomenon and then curing it.

[0101] Additionally, the base layer 800 and the first to fourth semiconductor chips 100, 200, 300, and 400 may be surrounded by a molding layer 820. In other words, the molding layer 820 may be formed to cover the first to fourth semiconductor chips 100, 200, 300, and 400 above the upper surface of the base layer 800. The molding layer 820 may include various molding materials such as EMC (epoxy molding compound). As an example, when the gap-filling material 810 is omitted, the molding layer 820 may be formed to fill the spaces between the base layer 800 and the first semiconductor chip 100, between the first semiconductor chip 100 and the second semiconductor chip 200, between the second semiconductor chip 200 and the third semiconductor chip 300, and between the third semiconductor chip 300 and the fourth semiconductor chip 400.

[0102] According to some semiconductor packages consistent with this embodiment, all the advantages described in the above embodiments can be obtained. Specifically, since the spacing between the bonding structures formed by the respective front surface connecting electrodes, the rear surface connecting electrodes, and the bonding layer between them can be formed to be wider than the spacing of the through electrodes, the gap between the bonding structures can be increased. As a result, the formation of voids in the gap filling material 810 or the molding layer 820 between the bonding structures and the process defects caused by the formation of voids can be reduced or prevented.

[0103] Furthermore, the above embodiments of this disclosure describe a case where the front surface connection electrodes and the rear surface connection electrodes of a stacked semiconductor chip are bonded to each other using a bonding layer. However, this disclosure is not limited thereto; the front surface connection electrodes and the rear surface connection electrodes of a stacked semiconductor chip can be directly bonded. This will be referred to below. Figure 9 describe.

[0104] Figure 9 This is a cross-sectional view showing a stacked semiconductor chip according to another embodiment of the present disclosure.

[0105] Reference Figure 9 The second semiconductor chip 1200 can be stacked on top of the first semiconductor chip 1100.

[0106] The first semiconductor chip 1100 may include: a first body portion 1110 having a front surface 1111 and a rear surface 1112; a first wiring portion 1115 above the front surface 1111 of the first body portion 1110; a first through electrode 1120 penetrating the first body portion 1110; a first front surface connection electrode 1130 connected to the first through electrode 1120 above the first wiring portion 1115 via the first wiring portion 1115; a first front surface dielectric layer 1135 filling the space between the first front surface connection electrodes 1130 above the first wiring portion 1115; a first rear surface connection electrode 1150 connected to the first through electrode 1120 above the rear surface 1112 of the first body portion 1110; and a first rear surface dielectric layer 1155 filling the space between the first rear surface connection electrodes 1150 above the rear surface 1112 of the first body portion 1110.

[0107] The second semiconductor chip 1200 may include: a second body portion 1210 having a front surface 1211 and a rear surface 1212; a second wiring portion 1215 above the front surface 1211 of the second body portion 1210; a second through electrode 1220 penetrating the second body portion 1210; a second front surface connection electrode 1230 connected to the second through electrode 1220 above the second wiring portion 1215 via the second wiring portion 1215; a second front surface dielectric layer 1235 filling the space between the second front surface connection electrodes 1230 above the second wiring portion 1215; a second rear surface connection electrode 1250 connected to the second through electrode 1220 above the rear surface 1212 of the second body portion 1210; and a second rear surface dielectric layer 1255 filling the space between the second rear surface connection electrodes 1250 above the rear surface 1212 of the second body portion 1210.

[0108] The arrangement and width of the first through electrode 1120 and the second through electrode 1220 can be substantially the same. Specifically, the centers of the first through electrode 1120 and the second through electrode 1220 can coincide with each other, and the plurality of first through electrodes 1120 and the plurality of second through electrodes 1220 can be arranged to have a first spacing P1 in a first direction.

[0109] The arrangement and width of the first front surface connecting electrode 1130, the first rear surface connecting electrode 1150, the second front surface connecting electrode 1230, and the second rear surface connecting electrode 1250 can be substantially the same. Specifically, the centers of the first front surface connecting electrode 1130, the first rear surface connecting electrode 1150, the second front surface connecting electrode 1230, and the second rear surface connecting electrode 1250 can coincide with each other, and the plurality of first front surface connecting electrodes 1130, the plurality of first rear surface connecting electrodes 1150, the plurality of second front surface connecting electrodes 1230, and the plurality of second rear surface connecting electrodes 1250 can be arranged to have a second spacing P2 in a first direction.

[0110] Here, in the central region CR, the centers of the first front surface connecting electrode 1130, the first rear surface connecting electrode 1150, the second front surface connecting electrode 1230, and the second rear surface connecting electrode 1250 may coincide with the centers of the first through electrode 1120 and the second through electrode 1220. On the other hand, in one side edge region ER1, the centers of the first front surface connecting electrode 1130, the first rear surface connecting electrode 1150, the second front surface connecting electrode 1230, and the second rear surface connecting electrode 1250 may be located at a distance farther from the central region CR than the centers of the first through electrode 1120 and the second through electrode 1220 (e.g., on the left side). Furthermore, in the other side edge region ER2, the first front surface connecting electrode 1130, the first rear surface connecting electrode 1150, the second front surface connecting electrode 1230, and the second rear surface connecting electrode 1250 may be located at a distance farther from the central region CR than the centers of the first through electrode 1120 and the second through electrode 1220 (e.g., on the right side). Therefore, the second spacing P2 can be greater than the first spacing P1. In each of the side edge regions ER1 and ER2, the distance between the center of the first front surface connecting electrode 1130, the first rear surface connecting electrode 1150, the second front surface connecting electrode 1230 and the second rear surface connecting electrode 1250 and the center of the first through electrode 1120 and the second through electrode 1220 is indicated by the numeral D.

[0111] The second semiconductor chip 1200 may be stacked on top of the first semiconductor chip 1100, with its front surface 1211 facing the rear surface 1112 of the first semiconductor chip 1100. Here, the first rear surface connection electrode 1150 may be directly bonded to the second front surface connection electrode 1230, and the first rear surface dielectric layer 1155 may be directly bonded to the second front surface dielectric layer 1235. The first rear surface connection electrode 1150 and the second front surface connection electrode 1230 may be bonded by the interdiffusion of the metals (e.g., copper) forming them. Alternatively, the first rear surface dielectric layer 1155 and the second front surface dielectric layer 1235 may be bonded by a covalent bond formed between the dielectric materials (e.g., silicon oxide or silicon nitride) forming them. Therefore, a hybrid bonding (i.e., metal-to-metal and dielectric-to-dielectric layer bonding) between the first semiconductor chip 1100 and the second semiconductor chip 1200 can be performed in situ.

[0112] According to embodiments of this disclosure, a semiconductor chip including a through electrode and a semiconductor package including the semiconductor chip are provided, which can reduce the size while reducing process defects.

[0113] Figure 10A block diagram illustrating an electronic system including a memory card 7800 employing at least one of the semiconductor packages according to an embodiment is shown. The memory card 7800 includes a memory 7810, such as a non-volatile memory device, and a memory controller 7820. The memory 7810 and the memory controller 7820 are capable of storing or retrieving stored data. At least one of the memory 7810 and the memory controller 7820 may include at least one of the semiconductor packages according to the described embodiment.

[0114] The memory 7810 may include a non-volatile memory device to which the techniques of embodiments of the present disclosure are applied. The memory controller 7820 may control the memory 7810 such that, in response to a read / write request from the host 7830, stored data or stored data can be read.

[0115] Figure 11 A block diagram illustrating an electronic system 8710 including at least one of the semiconductor packages according to the described embodiments is shown. The electronic system 8710 may include a controller 8711, an input / output device 8712, and a memory 8713. The controller 8711, the input / output device 8712, and the memory 8713 may be interconnected via a bus 8715 providing a path for data movement.

[0116] In embodiments, controller 8711 may include one or more microprocessors, digital signal processors, microcontrollers, and / or logic devices capable of performing the same functions as these components. Controller 8711 or memory 8713 may include one or more semiconductor packages according to embodiments of this disclosure. Input / output device 8712 may include at least one selected from keypads, keyboards, display devices, touchscreens, etc. Memory 8713 is a means for storing data. Memory 8713 may store data and / or commands, etc., to be executed by controller 8711.

[0117] The memory 8713 may include volatile memory devices such as DRAM and / or non-volatile memory devices such as flash memory. For example, flash memory may be installed in information processing systems such as mobile terminals or desktop computers. Flash memory may constitute a solid-state drive (SSD). In this case, the electronic system 8710 can stably store large amounts of data in the flash memory system.

[0118] The electronic system 8710 may also include an interface 8714 configured to transmit data to and receive data from a communication network. The interface 8714 may be wired or wireless. For example, the interface 8714 may include an antenna or a wired or wireless transceiver.

[0119] The electronic system 8710 can be implemented as a mobile system, a personal computer, an industrial computer, or a logical system performing various functions. For example, a mobile system can be any of a personal digital assistant (PDA), a portable computer, a tablet computer, a mobile phone, a smartphone, a wireless phone, a laptop computer, a memory card, a digital music system, and an information sending / receiving system.

[0120] If electronic system 8710 represents a device capable of performing wireless communication, then electronic system 8710 can be used in communication systems using technologies such as CDMA (Code Division Multiple Access), GSM (Global System for Mobile Communications), NADC (North American Digital Cellular), E-TDMA (Enhanced Time Division Multiple Access), WCDMA (Wideband Code Division Multiple Access), CDMA2000, LTE (Long Term Evolution), or Wibro (Wireless Broadband Internet).

[0121] Although this disclosure has been described with respect to a limited number of specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made to these embodiments without departing from the spirit and scope of this disclosure as defined in the following claims.

[0122] Cross-references to related applications

[0123] This application claims priority to Korean Patent Application No. 10-2020-0186901, filed on December 30, 2020, the entirety of which is incorporated herein by reference.

Claims

1. A semiconductor chip, the semiconductor chip comprising: The main body has a front surface and a rear surface; Multiple through electrodes, the multiple through electrodes penetrating the main body portion and arranged in an array region along a first direction; Multiple front surface connecting electrodes are respectively connected to the through electrode above the front surface of the main body portion; as well as Multiple rear surface connecting electrodes are respectively connected to the through electrode above the rear surface of the main body portion. The array region includes a central region and edge regions located on both sides of the central region in the first direction. The centers of the front surface connecting electrodes and the rear surface connecting electrodes located in each of the edge regions are positioned at a greater distance from the central region than the centers of the corresponding through electrodes. The center of the front surface connecting electrode coincides with the center of the rear surface connecting electrode in each of the central region and the edge region.

2. The semiconductor chip according to claim 1, wherein, The center of the front surface connecting electrode and the center of the rear surface connecting electrode located in the central region coincide with the center of the corresponding through electrode.

3. The semiconductor chip according to claim 1, wherein, The through electrode is arranged with a first spacing in the first direction. The front surface connecting electrode and the rear surface connecting electrode are arranged to have a second spacing in the first direction, and The second spacing is greater than the first spacing.

4. The semiconductor chip according to claim 1, wherein, The edge regions located on each side of the central region include a first edge region to an Nth edge region arranged sequentially according to their distance from the central region, where N is a natural number of 2 or greater. The distance between the center of the front surface connecting electrode and the center of the rear surface connecting electrode located in the k-th edge region and the center of the corresponding through electrode is less than the distance between the center of the front surface connecting electrode and the center of the rear surface connecting electrode located in the (k+1)-th edge region and the center of the corresponding through electrode, where k is a natural number between 1 and N-1.

5. A semiconductor chip, the semiconductor chip comprising: The main body has a front surface and a rear surface; Multiple through electrodes, the multiple through electrodes penetrating the main body portion and arranged along a first direction in each of a first array region and a second array region adjacent to each other along the first direction; Multiple front surface connecting electrodes are respectively connected to the through electrode above the front surface of the main body portion; as well as Multiple rear surface connecting electrodes are respectively connected to the through electrode above the rear surface of the main body portion. Each of the first array region and the second array region includes a central region, and a side edge region and a other side edge region are respectively located on both sides of the central region in the first direction. In each of the first array region and the second array region, the center of the front surface connecting electrode and the center of the rear surface connecting electrode, located in the one side edge region and the other side edge region respectively, are positioned at a distance farther from the central region than the center of the corresponding through electrode. The center of the front surface connecting electrode coincides with the center of the rear surface connecting electrode in each of the central region, the one side edge region, and the other side edge region.

6. The semiconductor chip according to claim 5, wherein, In each of the first array region and the second array region: The through electrode is arranged with a first spacing in the first direction. The front surface connecting electrode and the rear surface connecting electrode are arranged to have a second spacing in the first direction, and The second spacing is greater than the first spacing.

7. The semiconductor chip according to claim 6, wherein, The other edge region of the first array region and the one edge region of the second array region are adjacent to each other, and The distance between the center of the through electrode in the other edge region of the first array region and the center of the through electrode in the one side edge region of the second array region is greater than the first spacing.

8. The semiconductor chip according to claim 7, wherein, The distance between the center of the front surface connecting electrode and the center of the rear surface connecting electrode in the other edge region of the first array region and the center of the front surface connecting electrode and the center of the rear surface connecting electrode in the other edge region of the second array region is the same as the second spacing.

9. The semiconductor chip according to claim 5, wherein, In each of the first array region and the second array region, the center of the front surface connecting electrode and the center of the rear surface connecting electrode located in the central region coincide with the center of the corresponding through electrode.

10. The semiconductor chip according to claim 5, wherein, Each of the one-sided edge region and the other-sided edge region includes a first edge region to an Nth edge region arranged sequentially according to their distance from the central region, where N is a natural number of 2 or greater. The distance between the center of the front surface connecting electrode and the center of the rear surface connecting electrode located in the k-th edge region and the center of the corresponding through electrode is less than the distance between the center of the front surface connecting electrode and the center of the rear surface connecting electrode located in the (k+1)-th edge region and the center of the corresponding through electrode, where k is a natural number between 1 and N-1.

11. A semiconductor package comprising: A first semiconductor chip includes a first body portion having a front surface and a rear surface, a plurality of first through electrodes penetrating the first body portion and arranged in an array region along a first direction, and a plurality of first rear surface connection electrodes respectively connected to the first through electrodes above the rear surface of the first body portion; and The second semiconductor chip includes a second body portion having a front surface and a rear surface, and a plurality of second front surface connection electrodes located above the front surface of the second body portion. The first rear surface connecting electrode and the second front surface connecting electrode are respectively connected to each other. The array region includes a central region and edge regions located on both sides of the central region in the first direction. Wherein, the centers of the second front surface connecting electrodes and the first rear surface connecting electrodes located in each of the respective edge regions are positioned at a greater distance from the central region than the center of the corresponding first through electrode, and The center of the second front surface connecting electrode coincides with the center of the first rear surface connecting electrode in each of the central region and the edge region.

12. The semiconductor package of claim 11, wherein, The center of the second front surface connecting electrode and the center of the first rear surface connecting electrode located in the central region coincide with the center of the corresponding first through electrode.

13. The semiconductor package of claim 11, wherein, The first through electrode is arranged to have a first spacing in the first direction. The second front surface connecting electrode and the first rear surface connecting electrode are arranged to have a second spacing in the first direction, and The second spacing is greater than the first spacing.

14. The semiconductor package of claim 11, wherein, The edge regions located on each side of the central region include a first edge region to an Nth edge region arranged sequentially according to their distance from the central region, where N is a natural number of 2 or greater. The distance between the center of the second front surface connecting electrode and the center of the first rear surface connecting electrode located in the kth edge region and the center of the corresponding first through electrode is less than the distance between the center of the second front surface connecting electrode and the center of the first rear surface connecting electrode located in the (k+1)th edge region and the center of the corresponding first through electrode, where k is a natural number between 1 and N-1.

15. The semiconductor package of claim 11, further comprising a gap filler material or molding material for filling the space between the first semiconductor chip and the second semiconductor chip.

16. The semiconductor package of claim 11, further comprising a bonding layer that bonds the first rear surface connection electrode and the second front surface connection electrode to each other.

17. The semiconductor package of claim 11, wherein, The first rear surface connecting electrode and the second front surface connecting electrode are directly bonded.

18. The semiconductor package of claim 17, wherein, The first semiconductor chip also includes a first rear surface dielectric layer that fills the space between the first rear surface connection electrodes. The second semiconductor chip further includes a second front surface dielectric layer that fills the space between the second front surface connection electrodes, and The first rear surface dielectric layer and the second front surface dielectric layer are directly bonded together.

19. The semiconductor package of claim 11, wherein, In the first direction, the width of the first through electrode is smaller than both the width of the second front surface connecting electrode and the width of the first rear surface connecting electrode.

20. The semiconductor package of claim 11, wherein, The end of the first rear surface connecting electrode completely overlaps with the end of the first through electrode.

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